#include<stdio.h>
#include<cuda_runtime.h>
#include <stdlib.h>

#define length 10
#define length_thread 256

#define test(a){\
	for(int i =0;i<length;i++){\
		printf("a[%d] = %d \n",i,a[i] );\
	}\
}

#define pr_array(a,start,end){\
	for(int i=start;i<=end;i++){\
		printf("a[%d] = %d\n",i,a[i]);\
	}\
}

//return b_end where the vuela a will be put in the new array
//if a equel a vuale which is in the b array,a will in front of the vuale;
#define insert0(a,b,b_start,b_end){\
	while((b_end-b_start)>1){\
		int point = (b_start+b_end)/2;\
		 if(a<=b[point])b_end = point;\
		 else b_start = point;\
	}\
	b_end += (a>b[b_end])-(a<=b[b_start]);\
}\
//if a equel a vuale which is in the b array,a will in back of the vuale;
#define insert1(a,b,b_start,b_end){\
	while((b_end-b_start)>1){\
		int point = (b_start+b_end)/2;\
		 if(a<b[point])b_end = point;\
		 else b_start = point;\
	}\
	b_end += (a>=b[b_end])-(a<b[b_start]);\
}\


int cmp(const void *a,const void *b)
{
    return *(int *)a-*(int *)b;
}

__global__ void pr(int *a){
	int tid = threadIdx.x;
	__shared__ int a_s[length];
	a_s[tid] = a[tid];
	a[tid] = a_s[tid]*2;
}
					
__global__ void merger_thread(int *a,int len){
	__shared__ int a_s[length_thread];
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	int r1,r2;
	if(tid < len){
		a_s[threadIdx.x] = a[tid];
	}
	r1 = blockDim.x/2;
	int flag = (threadIdx.x>=r1);
	tid = threadIdx.x%r1;
	if((gridDim.x-1) == blockIdx.x)len %= blockDim.x;
	else len = blockDim.x;
	__syncthreads();
	if(threadIdx.x<(len/2)){
		r1 = threadIdx.x*2;
		if(a_s[r1]>a_s[r1+1]){
			r2 = a_s[r1];
			a_s[r1] = a_s[r1+1];
			a_s[r1+1] = r2;
		}
	}
	int loop = 1;
	int x , start , end;
	x = len;
	x = (x/2) + (x%2);
	while(x>1){
		x = (x/2) + (x%2);
		r1 = tid>>loop;
		r1 *= 2;
		start = r1+1-(int)flag;
		r1 += flag;
		end = 1<<loop;
		r1 *= end;
		start *= end;
		r2 = tid % end;
		r1 += r2;
		end += (start-1);
		__syncthreads();
		if(end > len)end = len;
		if(r1 < len){
			r1 = a_s[r1];
			if(flag){
				insert1(r1,a_s,start,end);
			}
			else{
				insert0(r1,a_s,start,end);
			}
			end %= (1<<loop);
			r2 +=end;
			a_s[r2] = r1;
		}
		loop++;
		__syncthreads();
	}
	if(threadIdx.x < len){
		a[threadIdx.x + blockIdx.x * blockDim.x] = a_s[threadIdx.x];
	}
}

int random(int range){
	static int start = 444;
	int d = 233333;
	int k = 33352;
	start = ((start*k)+d)%range;
	return start;
}

int* gen(){
	int *a_h;
	cudaHostAlloc( (void**)&a_h, length* sizeof(int),cudaHostAllocDefault );
	for (int i = 0; i < length; ++i)
	{
		a_h[i] = random(52);
		printf("a_h[%d] = %d \n",i,a_h[i]);
	}
	return a_h;
}

void sort_int(int *a,int len){
	int block_num = len/length_thread;
	if((len%length_thread)!=0)block_num++;
	merger_thread<<<block_num,length_thread>>>(a,len);
}

void msort(void *a,size_t num,size_t size,int ( * comparator ) ( const void *, const void * ) ){
	
}

int main(){
	/* int *a_h = gen();
	test(a_h);
	qsort(a_h,length,sizeof(int),cmp);
	printf("sorted!!!!!!!\n");
	test(a_h);
	a_h[43]=10;
	a_h[42]=10;
	pr_array(a_h,10,100);
	int start = 10,end = 50;
	insert0(10,a_h,start,end);
	printf("end %d\n",end );
	start = 10;
	end=50;
	insert1(10,a_h,start,end);
	printf("end %d\n",end );
	printf("used ipad pro maked\n");	 */
	int *a_h;
	cudaHostAlloc( (void**)&a_h, length* sizeof(int),cudaHostAllocDefault );
	for (int i = 0;i<length;i++) {
    	a_h[i] = length - i;
    	printf("a_h[%d] = %d \n",i,a_h[i]);
	}
	int *a_d;
	cudaMalloc( (void**)&a_d, length*sizeof(int) );
	cudaMemcpy(a_d,a_h, length*sizeof(int),cudaMemcpyHostToDevice);
	sort_int(a_d,length);
	cudaMemcpy(a_h,a_d,length*sizeof(int),cudaMemcpyDeviceToHost);
	for (int i = 0;i<length;i++) {
    	printf("a_h[%d] = %d \n",i,a_h[i]);
	}
}

	.file	"tmpxft_00397bfc_00000000-6_sort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z3cmpPKvS0_
	.type	_Z3cmpPKvS0_, @function
_Z3cmpPKvS0_:
.LFB2027:
	.cfi_startproc
	endbr64
	movl	(%rdi), %eax
	subl	(%rsi), %eax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z3cmpPKvS0_, .-_Z3cmpPKvS0_
	.globl	_Z6randomi
	.type	_Z6randomi, @function
_Z6randomi:
.LFB2028:
	.cfi_startproc
	endbr64
	imull	$33352, _ZZ6randomiE5start(%rip), %eax
	addl	$233333, %eax
	cltd
	idivl	%edi
	movl	%edx, _ZZ6randomiE5start(%rip)
	movl	%edx, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6randomi, .-_Z6randomi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"a_h[%d] = %d \n"
	.text
	.globl	_Z3genv
	.type	_Z3genv, @function
_Z3genv:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edx, %edx
	movl	$40, %esi
	leaq	.LC0(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaHostAlloc@PLT
.L5:
	movq	(%rsp), %rax
	movl	$52, %edi
	leaq	(%rax,%rbx,4), %rsi
	call	_Z6randomi
	movl	%ebx, %edx
	movl	$2, %edi
	incq	%rbx
	movl	%eax, (%rsi)
	movl	%eax, %ecx
	movq	%rbp, %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L5
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z3genv, .-_Z3genv
	.globl	_Z5msortPvmmPFiPKvS1_E
	.type	_Z5msortPvmmPFiPKvS1_E, @function
_Z5msortPvmmPFiPKvS1_E:
.LFB2031:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z5msortPvmmPFiPKvS1_E, .-_Z5msortPvmmPFiPKvS1_E
	.globl	_Z21__device_stub__Z2prPiPi
	.type	_Z21__device_stub__Z2prPiPi, @function
_Z21__device_stub__Z2prPiPi:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z2prPi(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L11:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z21__device_stub__Z2prPiPi, .-_Z21__device_stub__Z2prPiPi
	.globl	_Z2prPi
	.type	_Z2prPi, @function
_Z2prPi:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z21__device_stub__Z2prPiPi
	.cfi_endproc
.LFE2058:
	.size	_Z2prPi, .-_Z2prPi
	.globl	_Z34__device_stub__Z13merger_threadPiiPii
	.type	_Z34__device_stub__Z13merger_threadPiiPii, @function
_Z34__device_stub__Z13merger_threadPiiPii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13merger_threadPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z34__device_stub__Z13merger_threadPiiPii, .-_Z34__device_stub__Z13merger_threadPiiPii
	.globl	_Z13merger_threadPii
	.type	_Z13merger_threadPii, @function
_Z13merger_threadPii:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z13merger_threadPiiPii
	.cfi_endproc
.LFE2060:
	.size	_Z13merger_threadPii, .-_Z13merger_threadPii
	.globl	_Z8sort_intPii
	.type	_Z8sort_intPii, @function
_Z8sort_intPii:
.LFB2030:
	.cfi_startproc
	endbr64
	movl	%esi, %eax
	movl	$256, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	cmpb	$1, %sil
	movl	$16777217, %edx
	movl	$1, %ecx
	sbbl	$-1, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movl	%ebx, %esi
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z34__device_stub__Z13merger_threadPiiPii
.L21:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z8sort_intPii, .-_Z8sort_intPii
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edx, %edx
	movl	$40, %esi
	leaq	.LC0(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebx, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaHostAlloc@PLT
.L28:
	movq	8(%rsp), %rax
	movl	$10, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rsi
	subl	%ebx, %ecx
	movl	$2, %edi
	movl	%ecx, (%rax,%rbx,4)
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L28
	leaq	16(%rsp), %rdi
	movl	$40, %esi
	xorl	%ebx, %ebx
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$10, %esi
	call	_Z8sort_intPii
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$40, %edx
	call	cudaMemcpy@PLT
.L29:
	movq	8(%rsp), %rax
	movl	%ebx, %edx
	movq	%rbp, %rsi
	movl	$2, %edi
	movl	(%rax,%rbx,4), %ecx
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$10, %rbx
	jne	.L29
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z13merger_threadPii"
.LC2:
	.string	"_Z2prPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13merger_threadPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z2prPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.data
	.align 4
	.type	_ZZ6randomiE5start, @object
	.size	_ZZ6randomiE5start, 4
_ZZ6randomiE5start:
	.long	444
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<stdio.h>
#include<hip/hip_runtime.h>
#include <stdlib.h>

#define length 10
#define length_thread 256

#define test(a){\
	for(int i =0;i<length;i++){\
		printf("a[%d] = %d \n",i,a[i] );\
	}\
}

#define pr_array(a,start,end){\
	for(int i=start;i<=end;i++){\
		printf("a[%d] = %d\n",i,a[i]);\
	}\
}

//return b_end where the vuela a will be put in the new array
//if a equel a vuale which is in the b array,a will in front of the vuale;
#define insert0(a,b,b_start,b_end){\
	while((b_end-b_start)>1){\
		int point = (b_start+b_end)/2;\
		 if(a<=b[point])b_end = point;\
		 else b_start = point;\
	}\
	b_end += (a>b[b_end])-(a<=b[b_start]);\
}\
//if a equel a vuale which is in the b array,a will in back of the vuale;
#define insert1(a,b,b_start,b_end){\
	while((b_end-b_start)>1){\
		int point = (b_start+b_end)/2;\
		 if(a<b[point])b_end = point;\
		 else b_start = point;\
	}\
	b_end += (a>=b[b_end])-(a<b[b_start]);\
}\


int cmp(const void *a,const void *b)
{
    return *(int *)a-*(int *)b;
}

__global__ void pr(int *a){
	int tid = threadIdx.x;
	__shared__ int a_s[length];
	a_s[tid] = a[tid];
	a[tid] = a_s[tid]*2;
}
					
__global__ void merger_thread(int *a,int len){
	__shared__ int a_s[length_thread];
	int tid = threadIdx.x + blockIdx.x * blockDim.x;
	int r1,r2;
	if(tid < len){
		a_s[threadIdx.x] = a[tid];
	}
	r1 = blockDim.x/2;
	int flag = (threadIdx.x>=r1);
	tid = threadIdx.x%r1;
	if((gridDim.x-1) == blockIdx.x)len %= blockDim.x;
	else len = blockDim.x;
	__syncthreads();
	if(threadIdx.x<(len/2)){
		r1 = threadIdx.x*2;
		if(a_s[r1]>a_s[r1+1]){
			r2 = a_s[r1];
			a_s[r1] = a_s[r1+1];
			a_s[r1+1] = r2;
		}
	}
	int loop = 1;
	int x , start , end;
	x = len;
	x = (x/2) + (x%2);
	while(x>1){
		x = (x/2) + (x%2);
		r1 = tid>>loop;
		r1 *= 2;
		start = r1+1-(int)flag;
		r1 += flag;
		end = 1<<loop;
		r1 *= end;
		start *= end;
		r2 = tid % end;
		r1 += r2;
		end += (start-1);
		__syncthreads();
		if(end > len)end = len;
		if(r1 < len){
			r1 = a_s[r1];
			if(flag){
				insert1(r1,a_s,start,end);
			}
			else{
				insert0(r1,a_s,start,end);
			}
			end %= (1<<loop);
			r2 +=end;
			a_s[r2] = r1;
		}
		loop++;
		__syncthreads();
	}
	if(threadIdx.x < len){
		a[threadIdx.x + blockIdx.x * blockDim.x] = a_s[threadIdx.x];
	}
}

int random(int range){
	static int start = 444;
	int d = 233333;
	int k = 33352;
	start = ((start*k)+d)%range;
	return start;
}

int* gen(){
	int *a_h;
	hipHostAlloc( (void**)&a_h, length* sizeof(int),hipHostMallocDefault );
	for (int i = 0; i < length; ++i)
	{
		a_h[i] = random(52);
		printf("a_h[%d] = %d \n",i,a_h[i]);
	}
	return a_h;
}

void sort_int(int *a,int len){
	int block_num = len/length_thread;
	if((len%length_thread)!=0)block_num++;
	merger_thread<<<block_num,length_thread>>>(a,len);
}

void msort(void *a,size_t num,size_t size,int ( * comparator ) ( const void *, const void * ) ){
	
}

int main(){
	/* int *a_h = gen();
	test(a_h);
	qsort(a_h,length,sizeof(int),cmp);
	printf("sorted!!!!!!!\n");
	test(a_h);
	a_h[43]=10;
	a_h[42]=10;
	pr_array(a_h,10,100);
	int start = 10,end = 50;
	insert0(10,a_h,start,end);
	printf("end %d\n",end );
	start = 10;
	end=50;
	insert1(10,a_h,start,end);
	printf("end %d\n",end );
	printf("used ipad pro maked\n");	 */
	int *a_h;
	hipHostAlloc( (void**)&a_h, length* sizeof(int),hipHostMallocDefault );
	for (int i = 0;i<length;i++) {
    	a_h[i] = length - i;
    	printf("a_h[%d] = %d \n",i,a_h[i]);
	}
	int *a_d;
	hipMalloc( (void**)&a_d, length*sizeof(int) );
	hipMemcpy(a_d,a_h, length*sizeof(int),hipMemcpyHostToDevice);
	sort_int(a_d,length);
	hipMemcpy(a_h,a_d,length*sizeof(int),hipMemcpyDeviceToHost);
	for (int i = 0;i<length;i++) {
    	printf("a_h[%d] = %d \n",i,a_h[i]);
	}
}

	.text
	.file	"sort.hip"
	.globl	_Z3cmpPKvS0_                    # -- Begin function _Z3cmpPKvS0_
	.type	_Z3cmpPKvS0_,@function
_Z3cmpPKvS0_:                           # @_Z3cmpPKvS0_
	.cfi_startproc
# %bb.0:
	movl	(%rdi), %eax
	subl	(%rsi), %eax
	retq
.Lfunc_end0:
	.size	_Z3cmpPKvS0_, .Lfunc_end0-_Z3cmpPKvS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z17__device_stub__prPi         # -- Begin function _Z17__device_stub__prPi
	.type	_Z17__device_stub__prPi,@function
_Z17__device_stub__prPi:                # @_Z17__device_stub__prPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z2prPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z17__device_stub__prPi, .Lfunc_end1-_Z17__device_stub__prPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__merger_threadPii # -- Begin function _Z28__device_stub__merger_threadPii
	.type	_Z28__device_stub__merger_threadPii,@function
_Z28__device_stub__merger_threadPii:    # @_Z28__device_stub__merger_threadPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13merger_threadPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__merger_threadPii, .Lfunc_end2-_Z28__device_stub__merger_threadPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z6randomi                      # -- Begin function _Z6randomi
	.type	_Z6randomi,@function
_Z6randomi:                             # @_Z6randomi
	.cfi_startproc
# %bb.0:
	imull	$33352, _ZZ6randomiE5start(%rip), %eax # imm = 0x8248
	addl	$233333, %eax                   # imm = 0x38F75
	cltd
	idivl	%edi
	movl	%edx, %eax
	movl	%edx, _ZZ6randomiE5start(%rip)
	retq
.Lfunc_end3:
	.size	_Z6randomi, .Lfunc_end3-_Z6randomi
	.cfi_endproc
                                        # -- End function
	.globl	_Z3genv                         # -- Begin function _Z3genv
	.type	_Z3genv,@function
_Z3genv:                                # @_Z3genv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	xorl	%edx, %edx
	callq	hipHostAlloc
	xorl	%ebx, %ebx
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	imull	$33352, _ZZ6randomiE5start(%rip), %eax # imm = 0x8248
	addl	$233333, %eax                   # imm = 0x38F75
	movslq	%eax, %rdx
	imulq	$1321528399, %rdx, %rax         # imm = 0x4EC4EC4F
	movq	%rax, %rcx
	shrq	$63, %rcx
	sarq	$36, %rax
	addl	%ecx, %eax
	imull	$52, %eax, %eax
	subl	%eax, %edx
	movl	%edx, _ZZ6randomiE5start(%rip)
	movq	8(%rsp), %rax
	movl	%edx, (%rax,%rbx,4)
	movl	$.L.str, %edi
	movl	%ebx, %esi
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB4_1
# %bb.2:
	movq	8(%rsp), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z3genv, .Lfunc_end4-_Z3genv
	.cfi_endproc
                                        # -- End function
	.globl	_Z8sort_intPii                  # -- Begin function _Z8sort_intPii
	.type	_Z8sort_intPii,@function
_Z8sort_intPii:                         # @_Z8sort_intPii
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	leal	255(%rbx), %eax
	testl	%esi, %esi
	cmovnsl	%esi, %eax
	sarl	$8, %eax
	cmpb	$1, %bl
	sbbl	$-1, %eax
	movq	%rdi, %r14
	btsq	$32, %rax
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movq	%rax, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movl	%ebx, %esi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z28__device_stub__merger_threadPii # TAILCALL
.Lfunc_end5:
	.size	_Z8sort_intPii, .Lfunc_end5-_Z8sort_intPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5msortPvmmPFiPKvS1_E          # -- Begin function _Z5msortPvmmPFiPKvS1_E
	.type	_Z5msortPvmmPFiPKvS1_E,@function
_Z5msortPvmmPFiPKvS1_E:                 # @_Z5msortPvmmPFiPKvS1_E
	.cfi_startproc
# %bb.0:
	retq
.Lfunc_end6:
	.size	_Z5msortPvmmPFiPKvS1_E, .Lfunc_end6-_Z5msortPvmmPFiPKvS1_E
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	xorl	%edx, %edx
	callq	hipHostAlloc
	movl	$10, %ebx
	xorl	%r14d, %r14d
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax
	movl	%ebx, (%rax,%r14,4)
	movl	$.L.str, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	decq	%rbx
	jne	.LBB7_1
# %bb.2:
	leaq	16(%rsp), %rbx
	movl	$40, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	8(%rsp), %rsi
	movl	$40, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbx), %rdi
	movl	$10, %esi
	callq	_Z8sort_intPii
	movq	8(%rsp), %rdi
	movq	(%rbx), %rsi
	movl	$40, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB7_3:                                # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax
	movl	(%rax,%rbx,4), %edx
	movl	$.L.str, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$10, %rbx
	jne	.LBB7_3
# %bb.4:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z2prPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13merger_threadPii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z2prPi,@object                 # @_Z2prPi
	.section	.rodata,"a",@progbits
	.globl	_Z2prPi
	.p2align	3, 0x0
_Z2prPi:
	.quad	_Z17__device_stub__prPi
	.size	_Z2prPi, 8

	.type	_Z13merger_threadPii,@object    # @_Z13merger_threadPii
	.globl	_Z13merger_threadPii
	.p2align	3, 0x0
_Z13merger_threadPii:
	.quad	_Z28__device_stub__merger_threadPii
	.size	_Z13merger_threadPii, 8

	.type	_ZZ6randomiE5start,@object      # @_ZZ6randomiE5start
	.data
	.p2align	2, 0x0
_ZZ6randomiE5start:
	.long	444                             # 0x1bc
	.size	_ZZ6randomiE5start, 4

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"a_h[%d] = %d \n"
	.size	.L.str, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z2prPi"
	.size	.L__unnamed_1, 8

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13merger_threadPii"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z17__device_stub__prPi
	.addrsig_sym _Z28__device_stub__merger_threadPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z2prPi
	.addrsig_sym _Z13merger_threadPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z2prPi                 ; -- Begin function _Z2prPi
	.globl	_Z2prPi
	.p2align	8
	.type	_Z2prPi,@function
_Z2prPi:                                ; @_Z2prPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v1, 1, v1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z2prPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 2
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z2prPi, .Lfunc_end0-_Z2prPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 52
; NumSgprs: 2
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 2
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13merger_threadPii    ; -- Begin function _Z13merger_threadPii
	.globl	_Z13merger_threadPii
	.p2align	8
	.type	_Z13merger_threadPii,@function
_Z13merger_threadPii:                   ; @_Z13merger_threadPii
; %bb.0:
	s_clause 0x3
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s5, s[0:1], 0x8
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x10
	v_lshlrev_b32_e32 v4, 2, v0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmpx_gt_i32_e64 s5, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s0, -1
	s_lshr_b32 s0, s4, 1
	s_cmp_lg_u32 s1, s15
	s_cbranch_scc1 .LBB1_4
; %bb.3:
	v_cvt_f32_u32_e32 v2, s4
	s_sub_i32 s6, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_mul_i32 s6, s6, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s1, s6
	s_add_i32 s1, s1, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s1, s5, s1
	s_mul_i32 s1, s1, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s1, s5, s1
	s_sub_i32 s5, s1, s4
	s_cmp_ge_u32 s1, s4
	s_cselect_b32 s1, s5, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s5, s1, s4
	s_cmp_ge_u32 s1, s4
	s_cselect_b32 s4, s5, s1
	s_lshr_b32 s1, s4, 1
	s_branch .LBB1_5
.LBB1_4:
	s_mov_b32 s1, s0
.LBB1_5:
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_u32_e64 s1, v0
	s_cbranch_execz .LBB1_8
; %bb.6:
	v_lshlrev_b32_e32 v5, 3, v0
	ds_load_b64 v[2:3], v5
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v2, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v2
	ds_store_b64 v5, v[6:7]
.LBB1_8:
	s_or_b32 exec_lo, exec_lo, s5
	s_and_b32 s5, s4, 1
	s_mov_b32 s6, 1
	s_add_i32 s5, s1, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s5, 2
	s_cbranch_scc1 .LBB1_25
; %bb.9:                                ; %.lr.ph108
	v_cvt_f32_u32_e32 v2, s0
	v_cvt_f32_u32_e32 v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v5, v3
	v_trunc_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v2, v5
	v_cvt_u32_f32_e32 v3, v3
	v_cmp_ge_f32_e64 vcc_lo, |v5|, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	v_mul_lo_u32 v2, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v0, v2
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, s0, v0
	v_and_b32_e32 v3, 0x7fff, v3
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
.LBB1_10:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_14 Depth 2
                                        ;     Child Loop BB1_20 Depth 2
	s_lshl_b32 s1, 1, s6
	s_delay_alu instid0(VALU_DEP_2)
	v_lshrrev_b32_e32 v9, s6, v3
	s_ashr_i32 s0, s1, 31
	s_mov_b32 s8, exec_lo
	s_add_i32 s7, s1, s0
	s_waitcnt lgkmcnt(0)
	s_xor_b32 s7, s7, s0
	s_barrier
	v_cvt_f32_u32_e32 v6, s7
	s_sub_i32 s0, 0, s7
	buffer_gl0_inv
	v_rcp_iflag_f32_e32 v6, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x4f7ffffe, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v6, v6
	v_mul_lo_u32 v7, s0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v7
	v_add_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v3, v6
	v_mul_lo_u32 v7, v7, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v3, v7
	v_subrev_nc_u32_e32 v8, s7, v7
	v_cmp_le_u32_e64 s0, s7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v7, v8, s0
	v_lshlrev_b32_e32 v8, 1, v9
	v_subrev_nc_u32_e32 v9, s7, v7
	v_cmp_le_u32_e64 s0, s7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v10, v8, v2
	v_cndmask_b32_e64 v7, v7, v9, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v9, v10, s6, v7
	v_cmpx_gt_i32_e64 s4, v9
	s_cbranch_execz .LBB1_24
; %bb.11:                               ;   in Loop: Header=BB1_10 Depth=1
	v_or_b32_e32 v8, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v10, s6, v8
	v_lshlrev_b32_e32 v8, 2, v9
	v_add3_u32 v9, s1, -1, v10
	ds_load_b32 v8, v8
	v_min_i32_e32 v9, s4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v9, v10
	v_cmp_lt_i32_e64 s0, 1, v11
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s9, exec_lo, s1
	s_cbranch_execz .LBB1_17
; %bb.12:                               ; %.preheader95
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB1_16
; %bb.13:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_mov_b32 s11, 0
.LBB1_14:                               ; %.lr.ph
                                        ;   Parent Loop BB1_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v12, 31, v11
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 1, v11
	v_lshlrev_b32_e32 v12, 2, v11
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s1, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v10, v11, s1
	v_cndmask_b32_e64 v9, v11, v9, s1
	v_sub_nc_u32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, 2, v11
	s_or_b32 s11, s1, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_14
; %bb.15:                               ; %Flow
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB1_16:                               ; %Flow114
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b32_e32 v11, 2, v9
	v_lshlrev_b32_e32 v10, 2, v10
	ds_load_b32 v11, v11
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(1)
	v_cmp_gt_i32_e64 s1, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
	s_waitcnt lgkmcnt(0)
	v_cmp_le_i32_e64 s1, v8, v10
                                        ; implicit-def: $vgpr10
	v_subrev_co_ci_u32_e64 v11, s1, 0, v9, s1
                                        ; implicit-def: $vgpr9
.LBB1_17:                               ; %Flow117
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_and_not1_saveexec_b32 s1, s9
	s_cbranch_execz .LBB1_23
; %bb.18:                               ; %.preheader
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB1_22
; %bb.19:                               ; %.lr.ph101.preheader
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_mov_b32 s10, 0
.LBB1_20:                               ; %.lr.ph101
                                        ;   Parent Loop BB1_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v12, 31, v11
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 1, v11
	v_lshlrev_b32_e32 v12, 2, v11
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s0, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v11, v10, s0
	v_cndmask_b32_e64 v9, v9, v11, s0
	v_sub_nc_u32_e32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, 2, v11
	s_or_b32 s10, s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_20
; %bb.21:                               ; %Flow115
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_22:                               ; %Flow116
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	v_lshlrev_b32_e32 v11, 2, v9
	v_lshlrev_b32_e32 v10, 2, v10
	ds_load_b32 v11, v11
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(1)
	v_cmp_ge_i32_e64 s0, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s0, v8, v10
	v_subrev_co_ci_u32_e64 v11, s0, 0, v9, s0
.LBB1_23:                               ; %Flow118
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v11
	v_add_nc_u32_e32 v10, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v9
	v_mul_hi_u32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v6, s7
	v_sub_nc_u32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v10, s7, v6
	v_cmp_le_u32_e64 s0, s7, v6
	v_cndmask_b32_e64 v6, v6, v10, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v10, s7, v6
	v_cmp_le_u32_e64 s0, s7, v6
	v_cndmask_b32_e64 v6, v6, v10, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v6, v6, v9
	v_sub_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v6, v6, v7, 2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v6, v8
.LBB1_24:                               ; %Flow119
                                        ;   in Loop: Header=BB1_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_lshr_b32 s0, s5, 1
	s_and_b32 s1, s5, 1
	s_add_i32 s6, s6, 1
	s_add_i32 s5, s0, s1
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_u32 s5, 1
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_10
.LBB1_25:                               ; %._crit_edge109
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB1_27
; %bb.26:
	ds_load_b32 v3, v4
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
.LBB1_27:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13merger_threadPii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13merger_threadPii, .Lfunc_end1-_Z13merger_threadPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1408
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z2prPi
    .private_segment_fixed_size: 0
    .sgpr_count:     2
    .sgpr_spill_count: 0
    .symbol:         _Z2prPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13merger_threadPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13merger_threadPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
