#include <stdio.h>


template <typename T>
struct SinFunctor
{
    __host__ __device__
    T operator()(const T& x) const {
        return sinf(x);
    }
};


template <typename T>
struct CosFunctor
{
    __host__ __device__
    T operator()(const T& x) const {
        return cosf(x);
    }
};


struct OrderFunctor
{
    const float num_oscilators;

    OrderFunctor(float _num_oscilators) : num_oscilators(_num_oscilators) {}
    __host__ __device__
        float operator()(const float& x, const float& y) const {
            return sqrtf(powf(x, 2)+powf(y, 2))/num_oscilators;
        }
};


__global__ void kernel_heuns(int num_oscilators, int num_couplings, float *phases_new,
  float *phases_old, float *omegas,float *couplings, float dt,  int *indices, int *ptr)
{

    int i_thread = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int index =i_thread; index < num_oscilators*num_couplings; index += stride){

        float findex = (float)index;
        float fnum_oscilators = (float)num_oscilators;
        float fi_section = (findex+1)/fnum_oscilators-1;
        fi_section=ceil(fi_section);
        int i_section = (int)fi_section;
        
        //int i_section = (int)ceil(((float)index+1)/(float)num_oscilators-1);
        int i_node = index - i_section*num_oscilators;

        float coupling = couplings[i_section];
        float phase = phases_old[index];
        float omega = omegas[i_node];

        int i_nei = 0;
        float f = 0;
        float f_tild = 0;
        float phase_tild = 0.;
        for( int i_ptr = ptr[i_node]; i_ptr < ptr[i_node+1]; i_ptr = i_ptr + 1 ) {
            i_nei = indices[i_ptr]+ i_section*num_oscilators;
            f +=  coupling*sinf( phases_old[i_nei]  -phase);

        };
        f = f + omega;

        phase_tild =  phase + dt*f;

        for( int i_ptr = ptr[i_node]; i_ptr < ptr[i_node+1]; i_ptr = i_ptr + 1 ) {
            i_nei = indices[i_ptr]+ i_section*num_oscilators;
            f_tild +=  coupling*sinf( phases_old[i_nei] - phase_tild);
        };
        f_tild = f_tild +  omega;
        phases_new[index] = phase + dt*(f+f_tild)/2.;
    }
}
	.file	"tmpxft_00333205_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_
	.type	_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_, @function
_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 48(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z12kernel_heunsiiPfS_S_S_fPiS0_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_, .-_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_
	.globl	_Z12kernel_heunsiiPfS_S_S_fPiS0_
	.type	_Z12kernel_heunsiiPfS_S_S_fPiS0_, @function
_Z12kernel_heunsiiPfS_S_S_fPiS0_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z12kernel_heunsiiPfS_S_S_fPiS0_iiPfS_S_S_fPiS0_
	.cfi_endproc
.LFE2058:
	.size	_Z12kernel_heunsiiPfS_S_S_fPiS0_, .-_Z12kernel_heunsiiPfS_S_S_fPiS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12kernel_heunsiiPfS_S_S_fPiS0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12kernel_heunsiiPfS_S_S_fPiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>


template <typename T>
struct SinFunctor
{
    __host__ __device__
    T operator()(const T& x) const {
        return sinf(x);
    }
};


template <typename T>
struct CosFunctor
{
    __host__ __device__
    T operator()(const T& x) const {
        return cosf(x);
    }
};


struct OrderFunctor
{
    const float num_oscilators;

    OrderFunctor(float _num_oscilators) : num_oscilators(_num_oscilators) {}
    __host__ __device__
        float operator()(const float& x, const float& y) const {
            return sqrtf(powf(x, 2)+powf(y, 2))/num_oscilators;
        }
};


__global__ void kernel_heuns(int num_oscilators, int num_couplings, float *phases_new,
  float *phases_old, float *omegas,float *couplings, float dt,  int *indices, int *ptr)
{

    int i_thread = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
    for (int index =i_thread; index < num_oscilators*num_couplings; index += stride){

        float findex = (float)index;
        float fnum_oscilators = (float)num_oscilators;
        float fi_section = (findex+1)/fnum_oscilators-1;
        fi_section=ceil(fi_section);
        int i_section = (int)fi_section;
        
        //int i_section = (int)ceil(((float)index+1)/(float)num_oscilators-1);
        int i_node = index - i_section*num_oscilators;

        float coupling = couplings[i_section];
        float phase = phases_old[index];
        float omega = omegas[i_node];

        int i_nei = 0;
        float f = 0;
        float f_tild = 0;
        float phase_tild = 0.;
        for( int i_ptr = ptr[i_node]; i_ptr < ptr[i_node+1]; i_ptr = i_ptr + 1 ) {
            i_nei = indices[i_ptr]+ i_section*num_oscilators;
            f +=  coupling*sinf( phases_old[i_nei]  -phase);

        };
        f = f + omega;

        phase_tild =  phase + dt*f;

        for( int i_ptr = ptr[i_node]; i_ptr < ptr[i_node+1]; i_ptr = i_ptr + 1 ) {
            i_nei = indices[i_ptr]+ i_section*num_oscilators;
            f_tild +=  coupling*sinf( phases_old[i_nei] - phase_tild);
        };
        f_tild = f_tild +  omega;
        phases_new[index] = phase + dt*(f+f_tild)/2.;
    }
}
	.text
	.file	"kernel.hip"
	.globl	_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_ # -- Begin function _Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_
	.type	_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_,@function
_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_: # @_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	4(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12kernel_heunsiiPfS_S_S_fPiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_, .Lfunc_end0-_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12kernel_heunsiiPfS_S_S_fPiS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12kernel_heunsiiPfS_S_S_fPiS0_,@object # @_Z12kernel_heunsiiPfS_S_S_fPiS0_
	.section	.rodata,"a",@progbits
	.globl	_Z12kernel_heunsiiPfS_S_S_fPiS0_
	.p2align	3, 0x0
_Z12kernel_heunsiiPfS_S_S_fPiS0_:
	.quad	_Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_
	.size	_Z12kernel_heunsiiPfS_S_S_fPiS0_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12kernel_heunsiiPfS_S_S_fPiS0_"
	.size	.L__unnamed_1, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__kernel_heunsiiPfS_S_S_fPiS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12kernel_heunsiiPfS_S_S_fPiS0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12kernel_heunsiiPfS_S_S_fPiS0_ ; -- Begin function _Z12kernel_heunsiiPfS_S_S_fPiS0_
	.globl	_Z12kernel_heunsiiPfS_S_S_fPiS0_
	.p2align	8
	.type	_Z12kernel_heunsiiPfS_S_S_fPiS0_,@function
_Z12kernel_heunsiiPfS_S_S_fPiS0_:       ; @_Z12kernel_heunsiiPfS_S_S_fPiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x4c
	s_load_b64 s[16:17], s[0:1], 0x0
	s_add_u32 s2, s0, 64
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s21, s4, 0xffff
	s_mul_i32 s17, s17, s16
	v_mad_u64_u32 v[1:2], null, s15, s21, v[0:1]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s17, v1
	s_cbranch_execz .LBB0_19
; %bb.1:                                ; %.lr.ph95
	s_load_b32 s2, s[2:3], 0x0
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s3, s[0:1], 0x28
	s_load_b128 s[12:15], s[0:1], 0x30
	v_cvt_f32_i32_e32 v0, s16
	v_mov_b32_e32 v3, 0
	s_mov_b32 s18, 0
	s_mov_b32 s19, 0x7fffff
	s_mov_b32 s20, 0xb94c1982
	s_mov_b32 s22, 0x37d75334
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s21, s2, s21
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
	v_cvt_f32_i32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, 1.0, v2
	v_div_scale_f32 v4, null, v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v7, vcc_lo, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v8, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v5
	v_fma_f32 v4, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v6
	v_div_fixup_f32 v2, v4, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, -1.0, v2
	v_ceil_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v6, v2
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_lo_u32 v12, v6, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v8, v1, v12
	v_add_co_u32 v10, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v9, vcc_lo
	v_add_co_u32 v15, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v8
	global_load_b64 v[6:7], v[13:14], off
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v13, v[10:11], off
	global_load_b32 v15, v[15:16], off
	global_load_b32 v14, v[8:9], off
	v_mov_b32_e32 v8, v3
	s_waitcnt vmcnt(3)
	v_cmp_lt_i32_e32 vcc_lo, v6, v7
	v_ashrrev_i32_e32 v9, 31, v6
	s_and_saveexec_b32 s23, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v8, v6
	v_mov_b32_e32 v16, v6
	s_mov_b32 s24, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[8:9]
	v_mov_b32_e32 v8, 0
	v_add_co_u32 v10, s0, s12, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s13, v11, s0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[10:11], off
                                        ; implicit-def: $vgpr19
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s0, s6, v17
	v_add_co_ci_u32_e64 v18, s0, s7, v18, s0
	global_load_b32 v2, v[17:18], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v17, v2, v13
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v18, 0x7fffffff, v17
	v_cmpx_ngt_f32_e64 0x48000000, |v17|
	s_xor_b32 s25, exec_lo, s1
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v27, v18, s19, 0x800000
	v_lshrrev_b32_e32 v24, 23, v18
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v27, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, 0xffffff88, v24
	v_cmp_lt_u32_e64 s0, 63, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v20
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v27, v[2:3]
	v_add_nc_u32_e32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v21
	v_cmp_lt_u32_e64 s1, 31, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[21:22], null, 0xdb629599, v27, v[2:3]
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v28, v28, v26
	v_mov_b32_e32 v2, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v21, v19, s0
	v_cmp_lt_u32_e64 s2, 31, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0xf534ddc0, v27, v[2:3]
	v_mov_b32_e32 v2, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v20, v22, v20, s0
	v_mad_u64_u32 v[23:24], null, 0xfc2757d1, v27, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v20, v19, s1
	v_mov_b32_e32 v2, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0x4e441529, v27, v[2:3]
	v_mov_b32_e32 v2, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[25:26], null, 0xa2f9836e, v27, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v27, v24, v22, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v2, v2, v28
	v_cndmask_b32_e64 v25, v25, v23, s0
	v_cndmask_b32_e64 v24, v26, v24, s0
	v_cndmask_b32_e64 v23, v23, v21, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v26, 32, v2
	v_cndmask_b32_e64 v22, v25, v27, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v24, v25, s1
	v_cndmask_b32_e64 v25, v27, v23, s1
	v_cndmask_b32_e64 v23, v23, v20, s1
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v24, v22, s2
	v_cndmask_b32_e64 v22, v22, v25, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, v25, v23, s2
	v_cndmask_b32_e64 v19, v23, v19, s2
	v_alignbit_b32 v27, v24, v22, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v22, v25, v26
	v_cndmask_b32_e64 v2, v27, v24, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v21, v22, s0
	v_alignbit_b32 v24, v25, v19, v26
	v_bfe_u32 v21, v2, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v2, v20, 30
	v_cndmask_b32_e64 v24, v24, v25, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v23, 0, v21
	v_alignbit_b32 v20, v20, v24, 30
	v_alignbit_b32 v19, v24, v19, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v22, v22, v23
	v_xor_b32_e32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v19, v19, v23
	v_lshrrev_b32_e32 v23, 29, v2
	v_clz_i32_u32_e32 v25, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v23, 31, v23
	v_min_u32_e32 v25, 32, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v26, 0.5, v23
	v_sub_nc_u32_e32 v24, 31, v25
	v_lshlrev_b32_e32 v27, 23, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v22, v20, v24
	v_alignbit_b32 v19, v20, v19, v24
	v_sub_nc_u32_e32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v22, v19, 9
	v_lshrrev_b32_e32 v22, 9, v22
	v_clz_i32_u32_e32 v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v24, 32, v24
	v_sub_nc_u32_e32 v28, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v20, v19, v28
	v_or_b32_e32 v20, v22, v26
	v_add_lshl_u32 v22, v24, v25, 23
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, 0x3fc90fda, v20
	v_sub_nc_u32_e32 v19, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3fc90fda, v20, -v24
	v_add_nc_u32_e32 v19, 0x33000000, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x33a22168, v20
	v_or_b32_e32 v19, v19, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, 0x3fc90fda, v19
	v_lshrrev_b32_e32 v19, 30, v2
	v_dual_add_f32 v2, v24, v22 :: v_dual_add_nc_u32 v19, v21, v19
.LBB0_6:                                ; %Flow138
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s0, s25
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	v_mul_f32_e64 v2, 0x3f22f983, |v17|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v19, v2
	v_fma_f32 v2, 0xbfc90fda, v19, |v17|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xb3a22168, v19
	v_fmac_f32_e32 v2, 0xa7c234c4, v19
	v_cvt_i32_f32_e32 v19, v19
; %bb.8:                                ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v20, v2, v2 :: v_dual_and_b32 v23, 1, v19
	v_xor_b32_e32 v18, v18, v17
	v_add_co_u32 v10, s1, v10, 4
	v_fmaak_f32 v21, s20, v20, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s0, 0, v23
	v_add_co_ci_u32_e64 v11, s1, 0, v11, s1
	v_dual_fmaak_f32 v21, v20, v21, 0xbe2aaa9d :: v_dual_add_nc_u32 v16, 1, v16
	v_dual_fmaak_f32 v22, s22, v20, 0xbab64f3b :: v_dual_lshlrev_b32 v19, 30, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v20, v21
	v_fmaak_f32 v22, v20, v22, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v2, v21 :: v_dual_and_b32 v19, 0x80000000, v19
	v_fmaak_f32 v22, v20, v22, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v20, v22, 1.0
	v_cndmask_b32_e64 v2, v20, v2, s0
	v_cmp_class_f32_e64 s0, v17, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v2, v18, v19, v2
	v_cndmask_b32_e64 v2, 0x7fc00000, v2, s0
	v_cmp_ge_i32_e64 s0, v16, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v15, v2
	s_or_b32 s24, s0, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_4
; %bb.9:                                ; %Flow139
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_10:                               ; %Flow140
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s23
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v10, v14, v8 :: v_dual_mov_b32 v11, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.11:                               ; %.lr.ph90.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v16, s3, v10, v13
	s_mov_b32 s23, 0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
.LBB0_12:                               ; %.lr.ph90
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v2, v[8:9], off
                                        ; implicit-def: $vgpr19
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, v2, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v17, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
	global_load_b32 v2, v[17:18], off
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v17, v2, v16
                                        ; implicit-def: $vgpr2
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v18, 0x7fffffff, v17
	v_cmpx_ngt_f32_e64 0x48000000, |v17|
	s_xor_b32 s24, exec_lo, s1
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v27, v18, s19, 0x800000
	v_lshrrev_b32_e32 v24, 23, v18
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v27, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, 0xffffff88, v24
	v_cmp_lt_u32_e32 vcc_lo, 63, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v20
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v27, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, v26, v25
	v_mov_b32_e32 v2, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v26
	v_mad_u64_u32 v[21:22], null, 0xdb629599, v27, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v28, v28, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v2, v22 :: v_dual_cndmask_b32 v19, v21, v19
	v_cmp_lt_u32_e64 s1, 31, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0xf534ddc0, v27, v[2:3]
	v_mov_b32_e32 v2, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, v22, v20, vcc_lo
	v_mad_u64_u32 v[23:24], null, 0xfc2757d1, v27, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v20, v19, s0
	v_mov_b32_e32 v2, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0x4e441529, v27, v[2:3]
	v_mov_b32_e32 v2, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0xa2f9836e, v27, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v27, v24, v22 :: v_dual_add_nc_u32 v2, v2, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v25, v25, v23 :: v_dual_cndmask_b32 v24, v26, v24
	v_cndmask_b32_e32 v23, v23, v21, vcc_lo
	v_sub_nc_u32_e32 v26, 32, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v25, v27, s0
	v_cndmask_b32_e64 v24, v24, v25, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v27, v23, s0
	v_cndmask_b32_e64 v23, v23, v20, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v24, v24, v22, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v22, v25, s1
	v_cndmask_b32_e64 v25, v25, v23, s1
	v_cndmask_b32_e64 v19, v23, v19, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v24, v22, v26
	v_alignbit_b32 v21, v22, v25, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v27, v24, vcc_lo
	v_cndmask_b32_e32 v20, v21, v22, vcc_lo
	v_alignbit_b32 v24, v25, v19, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v21, v2, 29, 1
	v_alignbit_b32 v22, v2, v20, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v24, v24, v25, vcc_lo
	v_sub_nc_u32_e32 v23, 0, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v20, v24, 30
	v_alignbit_b32 v19, v24, v19, 30
	v_xor_b32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v20, v20, v23
	v_xor_b32_e32 v19, v19, v23
	v_lshrrev_b32_e32 v23, 29, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v25, v22
	v_lshlrev_b32_e32 v23, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v25, 32, v25
	v_or_b32_e32 v26, 0.5, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, 31, v25
	v_lshlrev_b32_e32 v27, 23, v25
	v_alignbit_b32 v22, v22, v20, v24
	v_alignbit_b32 v19, v20, v19, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v27
	v_alignbit_b32 v20, v22, v19, 9
	v_lshrrev_b32_e32 v22, 9, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v24, v20
	v_min_u32_e32 v24, 32, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v28, 31, v24
	v_alignbit_b32 v19, v20, v19, v28
	v_or_b32_e32 v20, v22, v26
	v_add_lshl_u32 v22, v24, v25, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v19, 9, v19
	v_mul_f32_e32 v24, 0x3fc90fda, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v22
	v_fma_f32 v22, 0x3fc90fda, v20, -v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 0x33000000, v19
	v_fmac_f32_e32 v22, 0x33a22168, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v19, v19, v23
	v_fmac_f32_e32 v22, 0x3fc90fda, v19
	v_lshrrev_b32_e32 v19, 30, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v2, v24, v22 :: v_dual_add_nc_u32 v19, v21, v19
.LBB0_14:                               ; %Flow
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_and_not1_saveexec_b32 s0, s24
; %bb.15:                               ;   in Loop: Header=BB0_12 Depth=2
	v_mul_f32_e64 v2, 0x3f22f983, |v17|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v19, v2
	v_fma_f32 v2, 0xbfc90fda, v19, |v17|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xb3a22168, v19
	v_fmac_f32_e32 v2, 0xa7c234c4, v19
	v_cvt_i32_f32_e32 v19, v19
; %bb.16:                               ; %_ZL4sinff.exit80
                                        ;   in Loop: Header=BB0_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v20, v2, v2 :: v_dual_and_b32 v23, 1, v19
	v_xor_b32_e32 v18, v18, v17
	v_add_co_u32 v8, s0, v8, 4
	v_dual_fmaak_f32 v21, s20, v20, 0x3c0881c4 :: v_dual_add_nc_u32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	v_fmaak_f32 v21, v20, v21, 0xbe2aaa9d
	v_dual_fmaak_f32 v22, s22, v20, 0xbab64f3b :: v_dual_lshlrev_b32 v19, 30, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v20, v21
	v_fmaak_f32 v22, v20, v22, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v2, v21 :: v_dual_and_b32 v19, 0x80000000, v19
	v_fmaak_f32 v22, v20, v22, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, v20, v22, 1.0
	v_cndmask_b32_e32 v2, v20, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v17, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v2, v18, v19, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fmac_f32_e32 v11, v15, v2
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_12
; %bb.17:                               ; %Flow136
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_18:                               ; %Flow137
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_add_f32 v2, v14, v11 :: v_dual_add_nc_u32 v1, s21, v1
	v_cvt_f64_f32_e32 v[6:7], v13
	v_add_co_u32 v4, s0, s4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v2, v10, v2
	v_cmp_le_i32_e32 vcc_lo, s17, v1
	v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, s3, v2
	s_or_b32 s18, vcc_lo, s18
	v_cvt_f64_f32_e32 v[8:9], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[8:9], 0.5, v[6:7]
	v_cvt_f32_f64_e32 v2, v[6:7]
	global_store_b32 v[4:5], v2, off
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_2
.LBB0_19:                               ; %Flow142
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12kernel_heunsiiPfS_S_S_fPiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12kernel_heunsiiPfS_S_S_fPiS0_, .Lfunc_end0-_Z12kernel_heunsiiPfS_S_S_fPiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2812
; NumSgprs: 28
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12kernel_heunsiiPfS_S_S_fPiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z12kernel_heunsiiPfS_S_S_fPiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
