#include <stdio.h>
#include <time.h>

// by lectures and "CUDA by Example" book

#define ind(k, i, j, rows, cols) (k * (rows * cols) + i * cols + j)


// device code: matrices sum calculation
__global__ void sum_matrices_kernel(int* mat_stack, int* mat, int rows, int cols, int num) {
    // row and col that correspond to current thread
    // process all elements that correspond to current thread
    for (int i = blockIdx.y * blockDim.y + threadIdx.y;
            i < rows; i += blockDim.y * gridDim.y)
        for (int j = blockIdx.x * blockDim.x + threadIdx.x;
                j < cols; j += blockDim.x * gridDim.x) {
            int mat_ind = ind(0, i, j, rows, cols);
            mat[mat_ind] = 0;
            // iterating over all elements on (i, j) position
            for (int k = 0; k < num; k++) {
                int stack_ind = ind(k, i, j, rows, cols);
                mat[mat_ind] += mat_stack[stack_ind];
            }
        }
}

int* cuda_copy_tens(int* host_tensor, int rows, int cols, int num) {
    int* dev_tensor;
    // size of memory to allocate on device for tensor
    long mem_size = rows * cols * num * sizeof(int);
    // device memory allocation
    cudaMalloc((void**) &dev_tensor, mem_size);
    // copying data from host to device
    cudaMemcpy(dev_tensor, host_tensor, mem_size, cudaMemcpyHostToDevice);
    // returning pointer
    return dev_tensor;
}

// host code: preparation
float sum_matrices_gpu(int* host_mat_stack, int* host_m, int rows, int cols, int num) {
    // Step 1: moving data on device
    int* dev_mat_stack = cuda_copy_tens(host_mat_stack, rows, cols, num);
    int* dev_m = cuda_copy_tens(host_m, rows, cols, 1);
    
    // Step 2
    // grid (of blocks) dimensions
    dim3 grid_dim(128, 128, 1);
    // block (of threads) dimensions
    dim3 block_dim(32, 32, 1);
    // running kernel summation code
    clock_t start = clock();
    sum_matrices_kernel<<<grid_dim, block_dim>>>(dev_mat_stack, dev_m, rows, cols, num);
    cudaDeviceSynchronize();
    clock_t end = clock();
    float time = (float)(end - start) / CLOCKS_PER_SEC;

    // Step 3
    // copying result from device to host matrix
    cudaMemcpy(host_m, dev_m, rows * cols * sizeof(int), cudaMemcpyDeviceToHost);
    // freeing device memory
    cudaFree(dev_mat_stack);
    cudaFree(dev_m);

    return time;
}

float sum_matrices_cpu(int* mat_stack, int* mat, int rows, int cols, int num) {
    clock_t start = clock();
    for (int i = 0; i < rows; i++)
        for (int j = 0; j < cols; j++) {
            int mat_ind = ind(0, i, j, rows, cols);
            mat[mat_ind] = 0;
            for (int k = 0; k < num; k++) {
                int stack_ind = ind(k, i, j, rows, cols);
                mat[mat_ind] += mat_stack[stack_ind];
            }
        }
    clock_t end = clock();
    float time = (float)(end - start) / CLOCKS_PER_SEC;
    return time;
}

// initialize matrix stack
int* init_mat_stack(int* mat_stack, int rows, int cols, int num) {
    for (int k = 0; k < num; k++)
        for (int i = 0; i < rows; i++)
            for (int j = 0; j < cols; j++) {
                int index = ind(k, i, j, rows, cols);
                mat_stack[index] = rand() % 20;
            }
    return mat_stack;
}

// QUESTION #1: why gpu times differ despite elements of each line
// always processing by single thread and number of threads always more
// than number of lines?
// there should be time always equal to process time of single thread?
// possible answer: in case of multiple threads they must wait each other
// in cudaDeviceSynchronize point?
// QUESTION #2: why when we set dim of block equal to 64x64
// then cudaDeviceSynchronize doesn't work?
int main() {
    // matrix count
    int num = 1e6;

    for (int dim = 10; dim > 0; dim--) {
        int rows = dim;
        int cols = dim;

        // first matrix
        int* host_mat_stack = (int*) malloc(rows * cols * num * sizeof(int));
        init_mat_stack(host_mat_stack, rows, cols, num);

        // result matrix
        int* host_m = (int*) malloc(rows * cols * sizeof(int));

        // summation
        int num_measures = 10;
        float gpu_time_mean = 0;
        float cpu_time_mean = 0;
        for (int i = 0; i < num_measures; i++) {
            gpu_time_mean += sum_matrices_gpu(host_mat_stack, host_m, rows, cols, num);
            cpu_time_mean += sum_matrices_cpu(host_mat_stack, host_m, rows, cols, num);
        }
        gpu_time_mean /= num_measures;
        cpu_time_mean /= num_measures;
        printf("Matrix stack params: (%d, %d) x %.0e\n", rows, cols, double(num));
        printf("CPU time mean: %.10f\n", cpu_time_mean);
        printf("GPU time mean: %.10f\n", gpu_time_mean);
        printf("CPU / GPU time: %.10f\n", cpu_time_mean / gpu_time_mean);
        printf("--------------------------\n");
    }

    return 0;
}
	.file	"tmpxft_00379025_00000000-6_speed_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14cuda_copy_tensPiiii
	.type	_Z14cuda_copy_tensPiiii, @function
_Z14cuda_copy_tensPiiii:
.LFB2027:
	.cfi_startproc
	endbr64
	imull	%edx, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	imull	%ecx, %esi
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	movslq	%esi, %rsi
	leaq	0(,%rsi,4), %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L3
	call	__stack_chk_fail@PLT
.L3:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14cuda_copy_tensPiiii, .-_Z14cuda_copy_tensPiiii
	.globl	_Z16sum_matrices_cpuPiS_iii
	.type	_Z16sum_matrices_cpuPiS_iii, @function
_Z16sum_matrices_cpuPiS_iii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r8d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	pushq	%r9
	.cfi_def_cfa_offset 64
	call	clock@PLT
	movl	%ebp, %edx
	xorl	%esi, %esi
	xorl	%edi, %edi
	imull	%ebx, %edx
	movq	%rax, %r12
	movslq	%edx, %rdx
	salq	$2, %rdx
.L7:
	cmpl	%ebp, %edi
	jge	.L11
	movslq	%esi, %rax
	xorl	%ecx, %ecx
	salq	$2, %rax
.L12:
	cmpl	%ebx, %ecx
	jge	.L14
	leaq	0(%r13,%rax), %r10
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
.L8:
	movl	%r9d, (%r14,%rax)
	cmpl	%r15d, %r8d
	jge	.L15
	addl	(%r10), %r9d
	incl	%r8d
	addq	%rdx, %r10
	jmp	.L8
.L15:
	incl	%ecx
	addq	$4, %rax
	jmp	.L12
.L14:
	incl	%edi
	addl	%ebx, %esi
	jmp	.L7
.L11:
	call	clock@PLT
	subq	%r12, %rax
	cvtsi2ssq	%rax, %xmm0
	divss	.LC0(%rip), %xmm0
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z16sum_matrices_cpuPiS_iii, .-_Z16sum_matrices_cpuPiS_iii
	.globl	_Z14init_mat_stackPiiii
	.type	_Z14init_mat_stackPiiii, @function
_Z14init_mat_stackPiiii:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%esi, %r9d
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	imull	%edx, %r9d
	movl	%ecx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	xorl	%esi, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
.L17:
	cmpl	%r14d, %r15d
	jge	.L24
	movl	%esi, %edi
	xorl	%r8d, %r8d
.L21:
	cmpl	%r12d, %r8d
	jge	.L19
	movslq	%edi, %rax
	xorl	%r13d, %r13d
	leaq	0(%rbp,%rax,4), %r10
.L20:
	cmpl	%r13d, %ebx
	jle	.L25
	movl	%esi, 28(%rsp)
	movl	%edi, 24(%rsp)
	movq	%r10, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movl	%r8d, 8(%rsp)
	call	rand@PLT
	movl	$20, %ecx
	movq	16(%rsp), %r10
	movl	28(%rsp), %esi
	cltd
	movl	24(%rsp), %edi
	movl	12(%rsp), %r9d
	idivl	%ecx
	movl	8(%rsp), %r8d
	movl	%edx, (%r10,%r13,4)
	incq	%r13
	jmp	.L20
.L25:
	incl	%r8d
	addl	%ebx, %edi
	jmp	.L21
.L19:
	incl	%r15d
	addl	%r9d, %esi
	jmp	.L17
.L24:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbp, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z14init_mat_stackPiiii, .-_Z14init_mat_stackPiiii
	.globl	_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii
	.type	_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii, @function
_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z19sum_matrices_kernelPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii, .-_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii
	.globl	_Z19sum_matrices_kernelPiS_iii
	.type	_Z19sum_matrices_kernelPiS_iii, @function
_Z19sum_matrices_kernelPiS_iii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii
	.cfi_endproc
.LFE2057:
	.size	_Z19sum_matrices_kernelPiS_iii, .-_Z19sum_matrices_kernelPiS_iii
	.globl	_Z16sum_matrices_gpuPiS_iii
	.type	_Z16sum_matrices_gpuPiS_iii, @function
_Z16sum_matrices_gpuPiS_iii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	movl	%r8d, %ecx
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	movl	%ebp, %edx
	movl	%ebx, %esi
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	call	_Z14cuda_copy_tensPiiii
	movl	$1, %ecx
	movl	%ebp, %edx
	movl	%ebx, %esi
	movq	%r13, %rdi
	movq	%rax, %r12
	call	_Z14cuda_copy_tensPiiii
	movl	$1, 32(%rsp)
	movq	%rax, (%rsp)
	movabsq	$549755814016, %rax
	movq	%rax, 24(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 36(%rsp)
	movl	$1, 44(%rsp)
	call	clock@PLT
	movl	44(%rsp), %ecx
	movl	32(%rsp), %esi
	xorl	%r9d, %r9d
	movq	36(%rsp), %rdx
	movq	24(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %r15
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	(%rsp), %rsi
	movl	%r14d, %r8d
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movq	%r12, %rdi
	call	_Z44__device_stub__Z19sum_matrices_kernelPiS_iiiPiS_iii
.L32:
	call	cudaDeviceSynchronize@PLT
	imull	%ebp, %ebx
	call	clock@PLT
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	subq	%r15, %rax
	movslq	%ebx, %rdx
	cvtsi2ssq	%rax, %xmm0
	divss	.LC0(%rip), %xmm0
	movss	%xmm0, 12(%rsp)
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	%r12, %rdi
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movss	12(%rsp), %xmm0
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z16sum_matrices_gpuPiS_iii, .-_Z16sum_matrices_gpuPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Matrix stack params: (%d, %d) x %.0e\n"
.LC5:
	.string	"CPU time mean: %.10f\n"
.LC6:
	.string	"GPU time mean: %.10f\n"
.LC7:
	.string	"CPU / GPU time: %.10f\n"
.LC8:
	.string	"--------------------------\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	$10, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
.L36:
	movl	%ebx, %ebp
	movl	$10, %r13d
	imull	%ebx, %ebp
	imull	$1000000, %ebp, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movl	$1000000, %ecx
	movl	%ebx, %edx
	movl	%ebx, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	call	_Z14init_mat_stackPiiii
	movslq	%ebp, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	xorps	%xmm1, %xmm1
	movq	%rax, %rbp
	movss	%xmm1, 8(%rsp)
.L35:
	movl	$1000000, %r8d
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	movss	%xmm1, 12(%rsp)
	call	_Z16sum_matrices_gpuPiS_iii
	addss	8(%rsp), %xmm0
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movl	$1000000, %r8d
	movq	%rbp, %rsi
	movq	%r12, %rdi
	movss	%xmm0, 8(%rsp)
	call	_Z16sum_matrices_cpuPiS_iii
	movss	12(%rsp), %xmm1
	addss	%xmm0, %xmm1
	decl	%r13d
	jne	.L35
	movsd	.LC3(%rip), %xmm0
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movb	$1, %al
	divss	.LC2(%rip), %xmm1
	movl	$2, %edi
	movd	%xmm1, %ebp
	leaq	.LC4(%rip), %rsi
	movss	8(%rsp), %xmm2
	divss	.LC2(%rip), %xmm2
	movss	%xmm2, 8(%rsp)
	call	__printf_chk@PLT
	movd	%ebp, %xmm4
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	cvtss2sd	%xmm4, %xmm0
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	8(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	movd	%ebp, %xmm0
	divss	8(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	call	__printf_chk@PLT
	decl	%ebx
	jne	.L36
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z19sum_matrices_kernelPiS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19sum_matrices_kernelPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1232348160
	.align 4
.LC2:
	.long	1092616192
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>

// by lectures and "CUDA by Example" book

#define ind(k, i, j, rows, cols) (k * (rows * cols) + i * cols + j)


// device code: matrices sum calculation
__global__ void sum_matrices_kernel(int* mat_stack, int* mat, int rows, int cols, int num) {
    // row and col that correspond to current thread
    // process all elements that correspond to current thread
    for (int i = blockIdx.y * blockDim.y + threadIdx.y;
            i < rows; i += blockDim.y * gridDim.y)
        for (int j = blockIdx.x * blockDim.x + threadIdx.x;
                j < cols; j += blockDim.x * gridDim.x) {
            int mat_ind = ind(0, i, j, rows, cols);
            mat[mat_ind] = 0;
            // iterating over all elements on (i, j) position
            for (int k = 0; k < num; k++) {
                int stack_ind = ind(k, i, j, rows, cols);
                mat[mat_ind] += mat_stack[stack_ind];
            }
        }
}

int* cuda_copy_tens(int* host_tensor, int rows, int cols, int num) {
    int* dev_tensor;
    // size of memory to allocate on device for tensor
    long mem_size = rows * cols * num * sizeof(int);
    // device memory allocation
    hipMalloc((void**) &dev_tensor, mem_size);
    // copying data from host to device
    hipMemcpy(dev_tensor, host_tensor, mem_size, hipMemcpyHostToDevice);
    // returning pointer
    return dev_tensor;
}

// host code: preparation
float sum_matrices_gpu(int* host_mat_stack, int* host_m, int rows, int cols, int num) {
    // Step 1: moving data on device
    int* dev_mat_stack = cuda_copy_tens(host_mat_stack, rows, cols, num);
    int* dev_m = cuda_copy_tens(host_m, rows, cols, 1);
    
    // Step 2
    // grid (of blocks) dimensions
    dim3 grid_dim(128, 128, 1);
    // block (of threads) dimensions
    dim3 block_dim(32, 32, 1);
    // running kernel summation code
    clock_t start = clock();
    sum_matrices_kernel<<<grid_dim, block_dim>>>(dev_mat_stack, dev_m, rows, cols, num);
    hipDeviceSynchronize();
    clock_t end = clock();
    float time = (float)(end - start) / CLOCKS_PER_SEC;

    // Step 3
    // copying result from device to host matrix
    hipMemcpy(host_m, dev_m, rows * cols * sizeof(int), hipMemcpyDeviceToHost);
    // freeing device memory
    hipFree(dev_mat_stack);
    hipFree(dev_m);

    return time;
}

float sum_matrices_cpu(int* mat_stack, int* mat, int rows, int cols, int num) {
    clock_t start = clock();
    for (int i = 0; i < rows; i++)
        for (int j = 0; j < cols; j++) {
            int mat_ind = ind(0, i, j, rows, cols);
            mat[mat_ind] = 0;
            for (int k = 0; k < num; k++) {
                int stack_ind = ind(k, i, j, rows, cols);
                mat[mat_ind] += mat_stack[stack_ind];
            }
        }
    clock_t end = clock();
    float time = (float)(end - start) / CLOCKS_PER_SEC;
    return time;
}

// initialize matrix stack
int* init_mat_stack(int* mat_stack, int rows, int cols, int num) {
    for (int k = 0; k < num; k++)
        for (int i = 0; i < rows; i++)
            for (int j = 0; j < cols; j++) {
                int index = ind(k, i, j, rows, cols);
                mat_stack[index] = rand() % 20;
            }
    return mat_stack;
}

// QUESTION #1: why gpu times differ despite elements of each line
// always processing by single thread and number of threads always more
// than number of lines?
// there should be time always equal to process time of single thread?
// possible answer: in case of multiple threads they must wait each other
// in cudaDeviceSynchronize point?
// QUESTION #2: why when we set dim of block equal to 64x64
// then cudaDeviceSynchronize doesn't work?
int main() {
    // matrix count
    int num = 1e6;

    for (int dim = 10; dim > 0; dim--) {
        int rows = dim;
        int cols = dim;

        // first matrix
        int* host_mat_stack = (int*) malloc(rows * cols * num * sizeof(int));
        init_mat_stack(host_mat_stack, rows, cols, num);

        // result matrix
        int* host_m = (int*) malloc(rows * cols * sizeof(int));

        // summation
        int num_measures = 10;
        float gpu_time_mean = 0;
        float cpu_time_mean = 0;
        for (int i = 0; i < num_measures; i++) {
            gpu_time_mean += sum_matrices_gpu(host_mat_stack, host_m, rows, cols, num);
            cpu_time_mean += sum_matrices_cpu(host_mat_stack, host_m, rows, cols, num);
        }
        gpu_time_mean /= num_measures;
        cpu_time_mean /= num_measures;
        printf("Matrix stack params: (%d, %d) x %.0e\n", rows, cols, double(num));
        printf("CPU time mean: %.10f\n", cpu_time_mean);
        printf("GPU time mean: %.10f\n", gpu_time_mean);
        printf("CPU / GPU time: %.10f\n", cpu_time_mean / gpu_time_mean);
        printf("--------------------------\n");
    }

    return 0;
}
	.text
	.file	"speed_test.hip"
	.globl	_Z34__device_stub__sum_matrices_kernelPiS_iii # -- Begin function _Z34__device_stub__sum_matrices_kernelPiS_iii
	.type	_Z34__device_stub__sum_matrices_kernelPiS_iii,@function
_Z34__device_stub__sum_matrices_kernelPiS_iii: # @_Z34__device_stub__sum_matrices_kernelPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19sum_matrices_kernelPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__sum_matrices_kernelPiS_iii, .Lfunc_end0-_Z34__device_stub__sum_matrices_kernelPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14cuda_copy_tensPiiii         # -- Begin function _Z14cuda_copy_tensPiiii
	.type	_Z14cuda_copy_tensPiiii,@function
_Z14cuda_copy_tensPiiii:                # @_Z14cuda_copy_tensPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	imull	%edx, %esi
	imull	%ecx, %esi
	movslq	%esi, %r14
	shlq	$2, %r14
	leaq	8(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z14cuda_copy_tensPiiii, .Lfunc_end1-_Z14cuda_copy_tensPiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z16sum_matrices_gpuPiS_iii
.LCPI2_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z16sum_matrices_gpuPiS_iii
	.type	_Z16sum_matrices_gpuPiS_iii,@function
_Z16sum_matrices_gpuPiS_iii:            # @_Z16sum_matrices_gpuPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r12d
	movl	%edx, %r13d
	movq	%rsi, %rbx
	movl	%edx, %esi
	movl	%ecx, %edx
	movl	%r8d, 4(%rsp)                   # 4-byte Spill
	movl	%r8d, %ecx
	callq	_Z14cuda_copy_tensPiiii
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movl	%r12d, %eax
	imull	%r13d, %eax
	movslq	%eax, %r15
	shlq	$2, %r15
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %r14
	callq	clock
	movq	%rax, %rbp
	movabsq	$549755814016, %rdi             # imm = 0x8000000080
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	%r14, %rsi
	movl	%r13d, %edx
	movl	%r12d, %ecx
	movl	4(%rsp), %r8d                   # 4-byte Reload
	callq	_Z34__device_stub__sum_matrices_kernelPiS_iii
.LBB2_2:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%rbp, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI2_0(%rip), %xmm0
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z16sum_matrices_gpuPiS_iii, .Lfunc_end2-_Z16sum_matrices_gpuPiS_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z16sum_matrices_cpuPiS_iii
.LCPI3_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	_Z16sum_matrices_cpuPiS_iii
	.type	_Z16sum_matrices_cpuPiS_iii,@function
_Z16sum_matrices_cpuPiS_iii:            # @_Z16sum_matrices_cpuPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, %r13
	callq	clock
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	testl	%r15d, %r15d
	jle	.LBB3_9
# %bb.1:                                # %.preheader.lr.ph
	movl	%r15d, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%ebp, %ecx
	movl	%ebx, %eax
	imull	%ebp, %r15d
	xorl	%esi, %esi
	xorl	%edi, %edi
	movl	%ebp, 4(%rsp)                   # 4-byte Spill
.LBB3_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
                                        #       Child Loop BB3_6 Depth 3
	testl	%ebp, %ebp
	jle	.LBB3_8
# %bb.3:                                # %.lr.ph34
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	%edi, %r8d
	imull	4(%rsp), %r8d                   # 4-byte Folded Reload
	movl	%esi, %r9d
	xorl	%r10d, %r10d
.LBB3_4:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_6 Depth 3
	leaq	(%r10,%r8), %r11
	movl	$0, (%r12,%r11,4)
	testl	%ebx, %ebx
	jle	.LBB3_7
# %bb.5:                                # %.lr.ph
                                        #   in Loop: Header=BB3_4 Depth=2
	xorl	%r14d, %r14d
	movq	%rax, %rdx
	movl	%r9d, %ebp
.LBB3_6:                                #   Parent Loop BB3_2 Depth=1
                                        #     Parent Loop BB3_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movslq	%ebp, %rbp
	addl	(%r13,%rbp,4), %r14d
	movl	%r14d, (%r12,%r11,4)
	addl	%r15d, %ebp
	decq	%rdx
	jne	.LBB3_6
.LBB3_7:                                # %._crit_edge
                                        #   in Loop: Header=BB3_4 Depth=2
	incq	%r10
	incl	%r9d
	cmpq	%rcx, %r10
	jne	.LBB3_4
.LBB3_8:                                # %._crit_edge35
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%rdi
	movl	4(%rsp), %ebp                   # 4-byte Reload
	addl	%ebp, %esi
	cmpq	16(%rsp), %rdi                  # 8-byte Folded Reload
	jne	.LBB3_2
.LBB3_9:                                # %._crit_edge37
	callq	clock
	subq	8(%rsp), %rax                   # 8-byte Folded Reload
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z16sum_matrices_cpuPiS_iii, .Lfunc_end3-_Z16sum_matrices_cpuPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14init_mat_stackPiiii         # -- Begin function _Z14init_mat_stackPiiii
	.type	_Z14init_mat_stackPiiii,@function
_Z14init_mat_stackPiiii:                # @_Z14init_mat_stackPiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, 16(%rsp)                  # 4-byte Spill
	movq	%rdi, %r14
	movl	%ecx, 24(%rsp)                  # 4-byte Spill
	testl	%ecx, %ecx
	jle	.LBB4_7
# %bb.1:                                # %.preheader21.lr.ph
	movl	%edx, %ebp
	movl	%edx, %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	%edx, %eax
	imull	16(%rsp), %eax                  # 4-byte Folded Reload
	movl	%eax, 20(%rsp)                  # 4-byte Spill
	movl	$0, 12(%rsp)                    # 4-byte Folded Spill
	xorl	%ecx, %ecx
.LBB4_2:                                # %.preheader21
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_4 Depth 2
                                        #       Child Loop BB4_8 Depth 3
	movl	%ecx, 28(%rsp)                  # 4-byte Spill
	cmpl	$0, 16(%rsp)                    # 4-byte Folded Reload
	jle	.LBB4_6
# %bb.3:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB4_2 Depth=1
	xorl	%ebx, %ebx
	movl	12(%rsp), %r13d                 # 4-byte Reload
.LBB4_4:                                # %.preheader
                                        #   Parent Loop BB4_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_8 Depth 3
	movq	32(%rsp), %r12                  # 8-byte Reload
	movl	%r13d, %r15d
	testl	%ebp, %ebp
	jle	.LBB4_5
.LBB4_8:                                #   Parent Loop BB4_2 Depth=1
                                        #     Parent Loop BB4_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$35, %rcx
	addl	%edx, %ecx
	shll	$2, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movslq	%r15d, %r15
	movl	%eax, (%r14,%r15,4)
	incl	%r15d
	decq	%r12
	jne	.LBB4_8
.LBB4_5:                                # %._crit_edge
                                        #   in Loop: Header=BB4_4 Depth=2
	incl	%ebx
	addl	%ebp, %r13d
	cmpl	16(%rsp), %ebx                  # 4-byte Folded Reload
	jne	.LBB4_4
.LBB4_6:                                # %._crit_edge24
                                        #   in Loop: Header=BB4_2 Depth=1
	movl	28(%rsp), %ecx                  # 4-byte Reload
	incl	%ecx
	movl	12(%rsp), %eax                  # 4-byte Reload
	addl	20(%rsp), %eax                  # 4-byte Folded Reload
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	cmpl	24(%rsp), %ecx                  # 4-byte Folded Reload
	jne	.LBB4_2
.LBB4_7:                                # %._crit_edge26
	movq	%r14, %rax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z14init_mat_stackPiiii, .Lfunc_end4-_Z14init_mat_stackPiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI5_0:
	.long	0x41200000                      # float 10
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI5_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$10, %ebx
.LBB5_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_2 Depth 2
	movq	%rbx, %r15
	imulq	%rbx, %r15
	imulq	$4000000, %r15, %rdi            # imm = 0x3D0900
	callq	malloc
	movq	%rax, %r14
	movq	%rax, %rdi
	movl	%ebx, %esi
	movl	%ebx, %edx
	movl	$1000000, %ecx                  # imm = 0xF4240
	callq	_Z14init_mat_stackPiiii
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r15
	xorps	%xmm1, %xmm1
	movl	$10, %ebp
	xorps	%xmm0, %xmm0
	movss	%xmm0, (%rsp)                   # 4-byte Spill
.LBB5_2:                                #   Parent Loop BB5_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	movl	$1000000, %r8d                  # imm = 0xF4240
	callq	_Z16sum_matrices_gpuPiS_iii
	movss	(%rsp), %xmm1                   # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addss	%xmm0, %xmm1
	movss	%xmm1, (%rsp)                   # 4-byte Spill
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	movl	$1000000, %r8d                  # imm = 0xF4240
	callq	_Z16sum_matrices_cpuPiS_iii
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	addss	%xmm0, %xmm1
	decl	%ebp
	jne	.LBB5_2
# %bb.3:                                #   in Loop: Header=BB5_1 Depth=1
	movss	.LCPI5_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	(%rsp), %xmm2                   # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm2
	movss	%xmm2, (%rsp)                   # 4-byte Spill
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movl	$.L.str, %edi
	movl	%ebx, %esi
	movl	%ebx, %edx
	movsd	.LCPI5_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rsp), %xmm0                   # 4-byte Folded Reload
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	(%rsp), %xmm0                   # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
	leaq	-1(%rbx), %rax
	cmpq	$1, %rbx
	movq	%rax, %rbx
	ja	.LBB5_1
# %bb.4:
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19sum_matrices_kernelPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19sum_matrices_kernelPiS_iii,@object # @_Z19sum_matrices_kernelPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z19sum_matrices_kernelPiS_iii
	.p2align	3, 0x0
_Z19sum_matrices_kernelPiS_iii:
	.quad	_Z34__device_stub__sum_matrices_kernelPiS_iii
	.size	_Z19sum_matrices_kernelPiS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Matrix stack params: (%d, %d) x %.0e\n"
	.size	.L.str, 38

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CPU time mean: %.10f\n"
	.size	.L.str.1, 22

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"GPU time mean: %.10f\n"
	.size	.L.str.2, 22

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"CPU / GPU time: %.10f\n"
	.size	.L.str.3, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19sum_matrices_kernelPiS_iii"
	.size	.L__unnamed_1, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"--------------------------"
	.size	.Lstr, 27

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__sum_matrices_kernelPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19sum_matrices_kernelPiS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19sum_matrices_kernelPiS_iii ; -- Begin function _Z19sum_matrices_kernelPiS_iii
	.globl	_Z19sum_matrices_kernelPiS_iii
	.p2align	8
	.type	_Z19sum_matrices_kernelPiS_iii,@function
_Z19sum_matrices_kernelPiS_iii:         ; @_Z19sum_matrices_kernelPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s8, 16
	s_mov_b32 s8, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s7, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_9
; %bb.1:                                ; %.lr.ph43
	s_clause 0x1
	s_load_b32 s15, s[2:3], 0xc
	s_load_b64 s[12:13], s[2:3], 0x0
	s_load_b128 s[8:11], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_mul_lo_u32 v3, s5, v1
	v_mov_b32_e32 v6, 0
	s_mul_i32 s1, s5, s4
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s15, s15, 0xffff
	s_cmp_gt_i32 s6, 0
	s_mul_i32 s14, s14, s15
	s_mul_i32 s7, s13, s7
	v_add_nc_u32_e32 v0, s14, v2
	v_add3_u32 v7, v2, v3, s14
	s_cselect_b32 s3, -1, 0
	s_mul_i32 s12, s12, s15
	s_mul_i32 s13, s7, s5
	v_cmp_gt_i32_e64 s0, s5, v0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_8
; %bb.3:                                ; %.lr.ph39
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_lo_u32 v8, v1, s5
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v0
	s_mov_b32 s15, 0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v10, v8
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s3
	global_store_b32 v[2:3], v6, off
	s_cbranch_vccnz .LBB0_7
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v4, v9
	s_mov_b32 s16, s6
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s16, s16, -1
	s_cmp_eq_u32 s16, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	v_add_nc_u32_e32 v4, s1, v4
	v_add_co_u32 v12, vcc_lo, s8, v12
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	global_load_b32 v5, v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v11, v11, v5
	global_store_b32 v[2:3], v11, off
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v10, s12, v10
	v_add_nc_u32_e32 v9, s12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s5, v10
	s_or_b32 s15, vcc_lo, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_4
.LBB0_8:                                ; %Flow67
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v1, s7, v1
	v_add_nc_u32_e32 v7, s13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
.LBB0_9:                                ; %Flow69
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19sum_matrices_kernelPiS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19sum_matrices_kernelPiS_iii, .Lfunc_end0-_Z19sum_matrices_kernelPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19sum_matrices_kernelPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z19sum_matrices_kernelPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
