//parameters: shiftX,Y, scaleX,Y,  shearX,Y = 6dimensions
//            multiply angle = 7
__global__ void AffineForward(const float* bottom_data,
    const int* bottomSize, const float* affine, const int len, float* top_data) {
    
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bottomSize[0];
    int w = (index / bottomSize[0]) % bottomSize[1];
    int c = (index / bottomSize[0] / bottomSize[1]) % bottomSize[2];
    int n = index / bottomSize[0] / bottomSize[1] / bottomSize[2];

    // get current affine start index
    const float* a = affine + n*7;

    // calc bottom index
    //                    [a0 a1 0] [cos6  sin6 0]             [0cos6-1sin6 0sin6+1cos6 0]
    // [x y 1] = [u v 1] *[a2 a3 0]*[-sin6 cos6 0] = [u v 1] * [2cos6-3sin6 2sin6+3cos6 0]
    //                    [a4 a5 1] [0     0    1]             [4cos6-5sin6 4sin6+5cos6 1]
    float nw = 2.0*((float)w/(float)bottomSize[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bottomSize[0]-0.5); //-1~1

    float w_new = nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6]));
    float h_new = nw*(a[0]*sin(a[6])+a[1]*cos(a[6])) + nh*(a[2]*sin(a[6])+a[3]*cos(a[6])) + (a[4]*sin(a[6])+a[5]*cos(a[6]));
    w_new = (w_new/2.0+0.5)*(float)bottomSize[1];
    h_new = (h_new/2.0+0.5)*(float)bottomSize[0];

    // calc neighbor pixel index, if > size or < size, do
    float v = 0.0;
    for (int x = floor(w_new); x<=ceil(w_new); x++) {
      for (int y = floor(h_new); y<=ceil(h_new); y++) {
        if (x<0 || x>= bottomSize[1] || y < 0 || y >= bottomSize[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y];
        }
        top_data[index] += v * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
      }
    }

}

__global__ void AffineBackward(const float* bottom_data,
    const int* bottomSize, const float* affine, const int len, const float* top_data, const float* top_diff, float* bottom_diff1, float* bottom_diff2) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bottomSize[0];
    int w = (index / bottomSize[0]) % bottomSize[1];
    int c = (index / bottomSize[0] / bottomSize[1]) % bottomSize[2];
    int n = index / bottomSize[0] / bottomSize[1] / bottomSize[2];

    // get current affine start index
    const float* a = affine + n*7;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bottomSize[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bottomSize[0]-0.5); //-1~1

    float w_new = nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6]));
    float h_new = nw*(a[0]*sin(a[6])+a[1]*cos(a[6])) + nh*(a[2]*sin(a[6])+a[3]*cos(a[6])) + (a[4]*sin(a[6])+a[5]*cos(a[6]));
    w_new = (w_new/2.0+0.5)*(float)bottomSize[1];
    h_new = (h_new/2.0+0.5)*(float)bottomSize[0];

    float v = 0.0;
    float dx = 0.0;
    float dy = 0.0;
    for (int x = floor(w_new); x<=ceil(w_new); x++) {
      for (int y = floor(h_new); y<=ceil(h_new); y++) {
        if (x<0 || x>= bottomSize[1] || y < 0 || y >= bottomSize[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y];
        }
        bottom_diff1[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y] += top_diff[index] * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
        dx += v * (1-abs(h_new - (float)y)) * ((float)x > w_new ? 1.0:-1.0 );
        dy += v * (1-abs(w_new - (float)x)) * ((float)y > h_new ? 1.0:-1.0 );
      }
    }
    
    
    atomicAdd((bottom_diff2+n*7)+0, nw *(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+2, nh *(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+4, 1.0*(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+1, nw *(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+3, nh *(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+5, 1.0*(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    float ba6 = (nw*(-a[0]*sin(a[6])-a[1]*cos(a[6])) + nh*(-a[2]*sin(a[6])-a[3]*cos(a[6])) + (-a[4]*sin(a[6])-a[5]*cos(a[6])))*dx*top_diff[index];
    ba6 += (nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6])))*dy*top_diff[index];
    atomicAdd((bottom_diff2+n*7)+6, ba6);
}
	.file	"tmpxft_002358fd_00000000-6_affine7.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.type	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf, @function
_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z13AffineForwardPKfPKiS0_iPf(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf, .-_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.type	_Z13AffineForwardPKfPKiS0_iPf, @function
_Z13AffineForwardPKfPKiS0_iPf:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z13AffineForwardPKfPKiS0_iPfPKfPKiS0_iPf
	.cfi_endproc
.LFE2033:
	.size	_Z13AffineForwardPKfPKiS0_iPf, .-_Z13AffineForwardPKfPKiS0_iPf
	.globl	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.type	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_, @function
_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_, .-_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, @function
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_PKfPKiS0_iS0_S0_PfS3_
	.cfi_endproc
.LFE2035:
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .-_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_"
.LC1:
	.string	"_Z13AffineForwardPKfPKiS0_iPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13AffineForwardPKfPKiS0_iPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
//parameters: shiftX,Y, scaleX,Y,  shearX,Y = 6dimensions
//            multiply angle = 7
__global__ void AffineForward(const float* bottom_data,
    const int* bottomSize, const float* affine, const int len, float* top_data) {
    
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bottomSize[0];
    int w = (index / bottomSize[0]) % bottomSize[1];
    int c = (index / bottomSize[0] / bottomSize[1]) % bottomSize[2];
    int n = index / bottomSize[0] / bottomSize[1] / bottomSize[2];

    // get current affine start index
    const float* a = affine + n*7;

    // calc bottom index
    //                    [a0 a1 0] [cos6  sin6 0]             [0cos6-1sin6 0sin6+1cos6 0]
    // [x y 1] = [u v 1] *[a2 a3 0]*[-sin6 cos6 0] = [u v 1] * [2cos6-3sin6 2sin6+3cos6 0]
    //                    [a4 a5 1] [0     0    1]             [4cos6-5sin6 4sin6+5cos6 1]
    float nw = 2.0*((float)w/(float)bottomSize[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bottomSize[0]-0.5); //-1~1

    float w_new = nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6]));
    float h_new = nw*(a[0]*sin(a[6])+a[1]*cos(a[6])) + nh*(a[2]*sin(a[6])+a[3]*cos(a[6])) + (a[4]*sin(a[6])+a[5]*cos(a[6]));
    w_new = (w_new/2.0+0.5)*(float)bottomSize[1];
    h_new = (h_new/2.0+0.5)*(float)bottomSize[0];

    // calc neighbor pixel index, if > size or < size, do
    float v = 0.0;
    for (int x = floor(w_new); x<=ceil(w_new); x++) {
      for (int y = floor(h_new); y<=ceil(h_new); y++) {
        if (x<0 || x>= bottomSize[1] || y < 0 || y >= bottomSize[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y];
        }
        top_data[index] += v * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
      }
    }

}

__global__ void AffineBackward(const float* bottom_data,
    const int* bottomSize, const float* affine, const int len, const float* top_data, const float* top_diff, float* bottom_diff1, float* bottom_diff2) {
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    if (index >= len) return;

    // get current index, [h,w,c,n]
    int h = index % bottomSize[0];
    int w = (index / bottomSize[0]) % bottomSize[1];
    int c = (index / bottomSize[0] / bottomSize[1]) % bottomSize[2];
    int n = index / bottomSize[0] / bottomSize[1] / bottomSize[2];

    // get current affine start index
    const float* a = affine + n*7;

    // calc bottom index
    //                    [a0 a1 0]
    // [x y 1] = [u v 1] *[a2 a3 0] 
    //                    [a4 a5 1]
    float nw = 2.0*((float)w/(float)bottomSize[1]-0.5); //-1~1
    float nh = 2.0*((float)h/(float)bottomSize[0]-0.5); //-1~1

    float w_new = nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6]));
    float h_new = nw*(a[0]*sin(a[6])+a[1]*cos(a[6])) + nh*(a[2]*sin(a[6])+a[3]*cos(a[6])) + (a[4]*sin(a[6])+a[5]*cos(a[6]));
    w_new = (w_new/2.0+0.5)*(float)bottomSize[1];
    h_new = (h_new/2.0+0.5)*(float)bottomSize[0];

    float v = 0.0;
    float dx = 0.0;
    float dy = 0.0;
    for (int x = floor(w_new); x<=ceil(w_new); x++) {
      for (int y = floor(h_new); y<=ceil(h_new); y++) {
        if (x<0 || x>= bottomSize[1] || y < 0 || y >= bottomSize[0]){
          v = 0.0;
        }else{
          v = bottom_data[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y];
        }
        bottom_diff1[n*bottomSize[2]*bottomSize[1]*bottomSize[0] + c*bottomSize[1]*bottomSize[0] + x*bottomSize[0] + y] += top_diff[index] * (1-abs(w_new - (float)x)) * (1-abs(h_new - (float)y));
        dx += v * (1-abs(h_new - (float)y)) * ((float)x > w_new ? 1.0:-1.0 );
        dy += v * (1-abs(w_new - (float)x)) * ((float)y > h_new ? 1.0:-1.0 );
      }
    }
    
    
    atomicAdd((bottom_diff2+n*7)+0, nw *(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+2, nh *(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+4, 1.0*(cos(a[6])+sin(a[6])) *dx*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+1, nw *(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+3, nh *(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    atomicAdd((bottom_diff2+n*7)+5, 1.0*(cos(a[6])-sin(a[6])) *dy*top_diff[index]);
    float ba6 = (nw*(-a[0]*sin(a[6])-a[1]*cos(a[6])) + nh*(-a[2]*sin(a[6])-a[3]*cos(a[6])) + (-a[4]*sin(a[6])-a[5]*cos(a[6])))*dx*top_diff[index];
    ba6 += (nw*(a[0]*cos(a[6])-a[1]*sin(a[6])) + nh*(a[2]*cos(a[6])-a[3]*sin(a[6])) + (a[4]*cos(a[6])-a[5]*sin(a[6])))*dy*top_diff[index];
    atomicAdd((bottom_diff2+n*7)+6, ba6);
}
	.text
	.file	"affine7.hip"
	.globl	_Z28__device_stub__AffineForwardPKfPKiS0_iPf # -- Begin function _Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.type	_Z28__device_stub__AffineForwardPKfPKiS0_iPf,@function
_Z28__device_stub__AffineForwardPKfPKiS0_iPf: # @_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13AffineForwardPKfPKiS0_iPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__AffineForwardPKfPKiS0_iPf, .Lfunc_end0-_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_ # -- Begin function _Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.type	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@function
_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_: # @_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .Lfunc_end1-_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13AffineForwardPKfPKiS0_iPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13AffineForwardPKfPKiS0_iPf,@object # @_Z13AffineForwardPKfPKiS0_iPf
	.section	.rodata,"a",@progbits
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.p2align	3, 0x0
_Z13AffineForwardPKfPKiS0_iPf:
	.quad	_Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.size	_Z13AffineForwardPKfPKiS0_iPf, 8

	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@object # @_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.p2align	3, 0x0
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_:
	.quad	_Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13AffineForwardPKfPKiS0_iPf"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_"
	.size	.L__unnamed_2, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__AffineForwardPKfPKiS0_iPf
	.addrsig_sym _Z29__device_stub__AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13AffineForwardPKfPKiS0_iPf
	.addrsig_sym _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13AffineForwardPKfPKiS0_iPf ; -- Begin function _Z13AffineForwardPKfPKiS0_iPf
	.globl	_Z13AffineForwardPKfPKiS0_iPf
	.p2align	8
	.type	_Z13AffineForwardPKfPKiS0_iPf,@function
_Z13AffineForwardPKfPKiS0_iPf:          ; @_Z13AffineForwardPKfPKiS0_iPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_59
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[8:9], s[6:7], 0x0
	s_load_b32 s6, s[6:7], 0x8
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s7, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s8, s7
	s_xor_b32 s10, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s11, 0, s10
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s11, v0
	s_ashr_i32 s11, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s9, s11
	s_xor_b32 s12, s12, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, s12
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	v_add_nc_u32_e32 v4, v1, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v0, v0, v3
	v_xor_b32_e32 v4, v4, v2
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s10
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s10, v3
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v3, v3, v6
	v_xor_b32_e32 v6, s7, v2
	s_sub_i32 s7, 0, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s10, v3
	v_cvt_u32_f32_e32 v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_mul_lo_u32 v4, s7, v3
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s10, s6, s7
	v_xor_b32_e32 v0, v0, v6
	s_xor_b32 s10, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v7, s10
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v6
	v_rcp_iflag_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v0
	v_add_nc_u32_e32 v3, v3, v4
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v7, 0x4f7ffffe, v7 :: v_dual_add_nc_u32 v6, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v6, v5
	v_xor_b32_e32 v5, s11, v5
	s_sub_i32 s11, 0, s10
	v_mul_hi_u32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v3, s12
	v_sub_nc_u32_e32 v4, v4, v6
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s12, v4
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s12, v4
	v_cvt_u32_f32_e32 v4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	v_mul_lo_u32 v6, s11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v3, v5
	v_mul_hi_u32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v3, v5
	v_ashrrev_i32_e32 v3, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_add_nc_u32_e32 v7, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v7, v3
	v_xor_b32_e32 v3, s7, v3
	v_mul_hi_u32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v4, s10
	v_sub_nc_u32_e32 v6, v6, v7
	v_add_nc_u32_e32 v7, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v8, s10, v6
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_add_nc_u32_e32 v7, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v3
	v_sub_nc_u32_e32 v6, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v6, 7
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_clause 0x1
	global_load_b32 v8, v[3:4], off offset:24
	global_load_b32 v7, v[3:4], off
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, 0x7fffffff, v8
	v_cmp_ngt_f32_e64 s7, 0x48000000, |v8|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v16, 23, v9
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v22, v9, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v22, 0
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v22, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v14
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v22, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v15
	v_add_nc_u32_e32 v15, 0xffffff88, v16
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v22, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v11, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v17, v13 :: v_dual_cndmask_b32 v10, v14, v10
	v_add_nc_u32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v22, v[11:12]
	v_cmp_lt_u32_e64 s2, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v19
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s2
	v_cndmask_b32_e64 v10, v13, v10, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v22, v[11:12]
	v_add_nc_u32_e32 v15, v21, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v15
	v_mov_b32_e32 v11, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v22, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
	v_cndmask_b32_e32 v12, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v20, v20, v18 :: v_dual_add_nc_u32 v11, v11, v15
	v_dual_cndmask_b32 v19, v21, v19 :: v_dual_cndmask_b32 v18, v18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e64 v15, v20, v12, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v19, v20, s2
	v_cndmask_b32_e64 v12, v12, v18, s2
	v_sub_nc_u32_e32 v19, 32, v11
	v_cndmask_b32_e64 v18, v18, v13, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v15, s3
	v_cndmask_b32_e64 v15, v15, v12, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v18, s3
	v_cndmask_b32_e64 v10, v18, v10, s3
	v_alignbit_b32 v20, v17, v15, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v12, v19
	v_alignbit_b32 v18, v12, v10, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v20, v17, vcc_lo
	v_cndmask_b32_e32 v13, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v18, v12, vcc_lo
	v_bfe_u32 v14, v11, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v11, v13, 30
	v_alignbit_b32 v13, v13, v12, 30
	v_alignbit_b32 v10, v12, v10, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v17, 0, v14
	v_xor_b32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v13, v17
	v_xor_b32_e32 v10, v10, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v18, v15
	v_min_u32_e32 v18, 32, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	v_alignbit_b32 v15, v15, v12, v13
	v_alignbit_b32 v10, v12, v10, v13
	v_lshrrev_b32_e32 v13, 29, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v15, v10, 9
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v17, v12
	v_or_b32_e32 v19, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, 31, v17
	v_alignbit_b32 v10, v12, v10, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v12, v15, v19
	v_add_lshl_u32 v15, v17, v18, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x3fc90fda, v12
	v_sub_nc_u32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3fc90fda, v12, -v17
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v12, v12, 0x33a22168, v15
	v_or_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0x3fc90fda, v10
	v_add_f32_e32 v12, v17, v12
	v_lshrrev_b32_e32 v10, 30, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v13, v14, v10
.LBB0_3:                                ; %Flow246
	s_or_saveexec_b32 s2, s10
	v_mul_f32_e64 v20, 0x3f22f983, |v8|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v10, v20
	v_fma_f32 v11, 0xbfc90fda, v10, |v8|
	v_cvt_i32_f32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v11, v10, 0xb3a22168, v11
	v_fmamk_f32 v12, v10, 0xa7c234c4, v11
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v10, v[3:4], off offset:4
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v11, v9, s2, 0x800000
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v17, v15
	v_add_nc_u32_e32 v15, 0xffffff88, v16
	v_mad_u64_u32 v[21:22], null, 0x3c439041, v11, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v17, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, v19, v15
	v_mad_u64_u32 v[22:23], null, 0xdb629599, v11, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v15
	v_mov_b32_e32 v17, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v14, v22, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[23:24], null, 0xf534ddc0, v11, v[17:18]
	v_add_nc_u32_e32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v15
	v_mov_b32_e32 v17, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0xfc2757d1, v11, v[17:18]
	v_mov_b32_e32 v17, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[25:26], null, 0x4e441529, v11, v[17:18]
	v_mov_b32_e32 v17, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[26:27], null, 0xa2f9836e, v11, v[17:18]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
	v_cndmask_b32_e32 v17, v25, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v26, v24 :: v_dual_add_nc_u32 v11, v11, v15
	v_dual_cndmask_b32 v19, v27, v25 :: v_dual_cndmask_b32 v24, v24, v22
	v_cndmask_b32_e32 v15, v23, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e64 v21, v18, v17, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v19, v18, s2
	v_cndmask_b32_e64 v17, v17, v24, s2
	v_sub_nc_u32_e32 v19, 32, v11
	v_cndmask_b32_e64 v23, v24, v15, s2
	v_cndmask_b32_e64 v14, v15, v14, s2
	v_cndmask_b32_e64 v18, v18, v21, s3
	v_cndmask_b32_e64 v21, v21, v17, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v23, s3
	v_cndmask_b32_e64 v14, v23, v14, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v18, v21, v19
	v_alignbit_b32 v22, v21, v17, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v17, v14, v19
	v_cndmask_b32_e32 v11, v24, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v22, v21, vcc_lo
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v18, v11, 29, 1
	v_alignbit_b32 v21, v11, v15, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v15, v15, v17, 30
	v_alignbit_b32 v14, v17, v14, 30
	v_sub_nc_u32_e32 v22, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v21, v21, v22
	v_xor_b32_e32 v15, v15, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v22
	v_clz_i32_u32_e32 v19, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v17, 31, v19
	v_lshlrev_b32_e32 v24, 23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v21, v15, v17
	v_alignbit_b32 v14, v15, v14, v17
	v_lshrrev_b32_e32 v17, 29, v11
	v_lshrrev_b32_e32 v11, 30, v11
	v_alignbit_b32 v15, v21, v14, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v21, 9, v21
	v_clz_i32_u32_e32 v22, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v23, 0.5, v17
	v_min_u32_e32 v22, 32, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v23, v23, v24
	v_sub_nc_u32_e32 v25, 31, v22
	v_add_lshl_u32 v19, v22, v19, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v15, v14, v25
	v_or_b32_e32 v15, v21, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v21, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v19
	v_fma_f32 v19, 0x3fc90fda, v15, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, v14, v17
	v_add_nc_u32_e32 v17, v18, v11
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v15, v21, v15
.LBB0_7:                                ; %Flow245
	s_and_not1_saveexec_b32 s2, s10
; %bb.8:
	v_rndne_f32_e32 v11, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0xbfc90fda, v11, |v8|
	v_cvt_i32_f32_e32 v17, v11
	v_fmamk_f32 v14, v11, 0xb3a22168, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v11, 0xa7c234c4, v14
; %bb.9:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v11, v[3:4], off offset:8
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr19
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v14, v9, s2, 0x800000
	v_mad_u64_u32 v[18:19], null, 0xfe5163ab, v14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v21, v19
	v_add_nc_u32_e32 v19, 0xffffff88, v16
	v_mad_u64_u32 v[23:24], null, 0x3c439041, v14, v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v19
	v_cndmask_b32_e64 v28, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v21, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v28, v19
	v_mad_u64_u32 v[24:25], null, 0xdb629599, v14, v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v19
	v_mov_b32_e32 v21, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v18, v24, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[25:26], null, 0xf534ddc0, v14, v[21:22]
	v_add_nc_u32_e32 v19, v29, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v19
	v_mov_b32_e32 v21, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, 0xfc2757d1, v14, v[21:22]
	v_mov_b32_e32 v21, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[27:28], null, 0x4e441529, v14, v[21:22]
	v_mov_b32_e32 v21, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, 0xa2f9836e, v14, v[21:22]
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v21, v27, v25 :: v_dual_add_nc_u32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v22, v28, v26 :: v_dual_cndmask_b32 v27, v29, v27
	v_dual_cndmask_b32 v26, v26, v24 :: v_dual_cndmask_b32 v19, v25, v23
	v_sub_nc_u32_e32 v25, 32, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v22, v21, s2
	v_cndmask_b32_e64 v22, v27, v22, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v26, s2
	v_cndmask_b32_e64 v26, v26, v19, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e64 v18, v19, v18, s2
	v_cndmask_b32_e64 v22, v22, v23, s3
	v_cndmask_b32_e64 v23, v23, v21, s3
	v_cndmask_b32_e64 v21, v21, v26, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v26, v18, s3
	v_alignbit_b32 v27, v22, v23, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v23, v21, v25
	v_alignbit_b32 v25, v21, v18, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v27, v22 :: v_dual_cndmask_b32 v19, v24, v23
	v_cndmask_b32_e32 v21, v25, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v22, v14, 29, 1
	v_alignbit_b32 v23, v14, v19, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v19, v19, v21, 30
	v_alignbit_b32 v18, v21, v18, 30
	v_sub_nc_u32_e32 v24, 0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v23, v23, v24
	v_xor_b32_e32 v19, v19, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v24
	v_clz_i32_u32_e32 v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v25, 32, v25
	v_sub_nc_u32_e32 v21, 31, v25
	v_lshlrev_b32_e32 v27, 23, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v23, v19, v21
	v_alignbit_b32 v18, v19, v18, v21
	v_lshrrev_b32_e32 v21, 29, v14
	v_lshrrev_b32_e32 v14, 30, v14
	v_alignbit_b32 v19, v23, v18, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v21, 31, v21
	v_lshrrev_b32_e32 v23, 9, v23
	v_clz_i32_u32_e32 v24, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v26, 0.5, v21
	v_min_u32_e32 v24, 32, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v27
	v_sub_nc_u32_e32 v28, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v19, v18, v28
	v_or_b32_e32 v19, v23, v26
	v_add_lshl_u32 v23, v24, v25, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v18, 9, v18
	v_mul_f32_e32 v24, 0x3fc90fda, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, v18, v23
	v_fma_f32 v23, 0x3fc90fda, v19, -v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v18, 0x33000000, v18
	v_fmamk_f32 v19, v19, 0x33a22168, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v18, v18, v21
	v_add_nc_u32_e32 v21, v22, v14
	v_fmac_f32_e32 v19, 0x3fc90fda, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v19, v24, v19
.LBB0_11:                               ; %Flow244
	s_and_not1_saveexec_b32 s2, s10
; %bb.12:
	v_rndne_f32_e32 v14, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0xbfc90fda, v14, |v8|
	v_cvt_i32_f32_e32 v21, v14
	v_fmamk_f32 v18, v14, 0xb3a22168, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v19, v14, 0xa7c234c4, v18
; %bb.13:                               ; %_ZL3cosf.exit107
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v14, v[3:4], off offset:12
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.14:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v24, 0
	v_and_or_b32 v18, v9, s2, 0x800000
	v_add_nc_u32_e32 v30, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, 0xfe5163ab, v18, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v30
	v_cndmask_b32_e64 v31, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[25:26], null, 0x3c439041, v18, v[23:24]
	v_add_nc_u32_e32 v31, v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v23, v26
	v_cmp_lt_u32_e64 s2, 31, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[26:27], null, 0xdb629599, v18, v[23:24]
	v_cndmask_b32_e64 v32, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v23, v27 :: v_dual_add_nc_u32 v32, v32, v31
	v_cndmask_b32_e32 v22, v26, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v32
	v_mad_u64_u32 v[27:28], null, 0xf534ddc0, v18, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v23, v28
	v_cndmask_b32_e32 v25, v27, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, 0xfc2757d1, v18, v[23:24]
	v_mov_b32_e32 v23, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, 0x4e441529, v18, v[23:24]
	v_mov_b32_e32 v23, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[30:31], null, 0xa2f9836e, v18, v[23:24]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v23, v29, v27 :: v_dual_add_nc_u32 v18, v18, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v24, v30, v28 :: v_dual_cndmask_b32 v29, v31, v29
	v_cndmask_b32_e32 v28, v28, v26, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v27, v24, v23, s2
	v_cndmask_b32_e64 v24, v29, v24, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v28, s2
	v_sub_nc_u32_e32 v29, 32, v18
	v_cndmask_b32_e64 v28, v28, v25, s2
	v_cndmask_b32_e64 v24, v24, v27, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, v27, v23, s3
	v_cndmask_b32_e64 v23, v23, v28, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v30, v24, v27, v29
	v_alignbit_b32 v26, v27, v23, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, v30, v24, vcc_lo
	v_cndmask_b32_e32 v24, v26, v27, vcc_lo
	v_cndmask_b32_e64 v22, v25, v22, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v25, v18, 29, 1
	v_alignbit_b32 v26, v18, v24, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v22, v28, v22, s3
	v_sub_nc_u32_e32 v27, 0, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v28, v23, v22, v29
	v_xor_b32_e32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v28, v23, vcc_lo
	v_clz_i32_u32_e32 v28, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v24, v23, 30
	v_alignbit_b32 v22, v23, v22, 30
	v_min_u32_e32 v28, 32, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v23, v24, v27
	v_xor_b32_e32 v22, v22, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, 31, v28
	v_lshlrev_b32_e32 v30, 23, v28
	v_alignbit_b32 v26, v26, v23, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v23, v22, v24
	v_lshrrev_b32_e32 v24, 29, v18
	v_lshrrev_b32_e32 v18, 30, v18
	v_alignbit_b32 v23, v26, v22, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v24, 31, v24
	v_lshrrev_b32_e32 v26, 9, v26
	v_clz_i32_u32_e32 v27, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v29, 0.5, v24
	v_min_u32_e32 v27, 32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v29, v29, v30
	v_sub_nc_u32_e32 v31, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v23, v22, v31
	v_or_b32_e32 v23, v26, v29
	v_add_lshl_u32 v26, v27, v28, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v22, 9, v22
	v_mul_f32_e32 v27, 0x3fc90fda, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v26
	v_fma_f32 v26, 0x3fc90fda, v23, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v22, 0x33000000, v22
	v_fmamk_f32 v23, v23, 0x33a22168, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v22, v22, v24
	v_fmac_f32_e32 v23, 0x3fc90fda, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v22, v27, v23 :: v_dual_add_nc_u32 v23, v25, v18
.LBB0_15:                               ; %Flow243
	s_and_not1_saveexec_b32 s2, s10
; %bb.16:
	v_rndne_f32_e32 v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0xbfc90fda, v18, |v8|
	v_cvt_i32_f32_e32 v23, v18
	v_fmamk_f32 v22, v18, 0xb3a22168, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v22, v18, 0xa7c234c4, v22
; %bb.17:                               ; %_ZL3sinf.exit115
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v18, v[3:4], off offset:16
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_19
; %bb.18:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v26, 0
	v_and_or_b32 v34, v9, s2, 0x800000
	v_add_nc_u32_e32 v32, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[24:25], null, 0xfe5163ab, v34, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v32
	v_cndmask_b32_e64 v33, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, 0x3c439041, v34, v[25:26]
	v_add_nc_u32_e32 v33, v33, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v25, v28
	v_cmp_lt_u32_e64 s2, 31, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[28:29], null, 0xdb629599, v34, v[25:26]
	v_cndmask_b32_e64 v35, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v24, v28, v24 :: v_dual_add_nc_u32 v35, v35, v33
	v_mov_b32_e32 v25, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v35
	v_mad_u64_u32 v[29:30], null, 0xf534ddc0, v34, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v25, v30
	v_cndmask_b32_e32 v27, v29, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xfc2757d1, v34, v[25:26]
	v_cndmask_b32_e64 v24, v27, v24, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v25, v31
	v_mad_u64_u32 v[31:32], null, 0x4e441529, v34, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v25, v32
	v_mad_u64_u32 v[32:33], null, 0xa2f9836e, v34, v[25:26]
	v_cndmask_b32_e64 v25, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v26, v31, v29 :: v_dual_add_nc_u32 v25, v25, v35
	v_dual_cndmask_b32 v32, v32, v30 :: v_dual_cndmask_b32 v31, v33, v31
	v_cndmask_b32_e32 v30, v30, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	v_cndmask_b32_e64 v29, v32, v26, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v32, s2
	v_cndmask_b32_e64 v26, v26, v30, s2
	v_sub_nc_u32_e32 v32, 32, v25
	v_cndmask_b32_e64 v30, v30, v27, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v29, s3
	v_cndmask_b32_e64 v29, v29, v26, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v26, v30, s3
	v_cndmask_b32_e64 v24, v30, v24, s3
	v_alignbit_b32 v33, v31, v29, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v28, v29, v26, v32
	v_cndmask_b32_e32 v25, v33, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v26, v24, v32
	v_cndmask_b32_e32 v27, v28, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v28, v25, 29, 1
	v_cndmask_b32_e32 v26, v31, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v25, v27, 30
	v_sub_nc_u32_e32 v30, 0, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v27, v26, 30
	v_alignbit_b32 v24, v26, v24, 30
	v_xor_b32_e32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v26, v27, v30
	v_xor_b32_e32 v24, v24, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v31, v29
	v_min_u32_e32 v31, 32, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v27, 31, v31
	v_lshlrev_b32_e32 v33, 23, v31
	v_alignbit_b32 v29, v29, v26, v27
	v_alignbit_b32 v24, v26, v24, v27
	v_lshrrev_b32_e32 v27, 29, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v26, v29, v24, 9
	v_lshlrev_b32_e32 v27, 31, v27
	v_lshrrev_b32_e32 v29, 9, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v30, v26
	v_or_b32_e32 v32, 0.5, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v30, 32, v30
	v_sub_nc_u32_e32 v32, v32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v34, 31, v30
	v_alignbit_b32 v24, v26, v24, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v26, v29, v32
	v_add_lshl_u32 v29, v30, v31, 23
	v_lshrrev_b32_e32 v24, 9, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v30, 0x3fc90fda, v26
	v_sub_nc_u32_e32 v24, v24, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, 0x3fc90fda, v26, -v30
	v_add_nc_u32_e32 v24, 0x33000000, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v26, v26, 0x33a22168, v29
	v_or_b32_e32 v24, v24, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, 0x3fc90fda, v24
	v_lshrrev_b32_e32 v25, 30, v25
	v_dual_add_f32 v24, v30, v26 :: v_dual_add_nc_u32 v25, v28, v25
.LBB0_19:                               ; %Flow242
	s_and_not1_saveexec_b32 s2, s10
; %bb.20:
	v_rndne_f32_e32 v25, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, 0xbfc90fda, v25, |v8|
	v_fmamk_f32 v24, v25, 0xb3a22168, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v24, v25, 0xa7c234c4, v24
	v_cvt_i32_f32_e32 v25, v25
; %bb.21:                               ; %_ZL3cosf.exit121
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v3, v[3:4], off offset:20
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_23
; %bb.22:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v28, 0
	v_and_or_b32 v4, v9, s2, 0x800000
	v_add_nc_u32_e32 v34, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[26:27], null, 0xfe5163ab, v4, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v34
	v_cndmask_b32_e64 v35, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0x3c439041, v4, v[27:28]
	v_add_nc_u32_e32 v35, v35, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v27, v30
	v_cmp_lt_u32_e64 s2, 31, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xdb629599, v4, v[27:28]
	v_cndmask_b32_e64 v36, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v27, v31 :: v_dual_add_nc_u32 v36, v36, v35
	v_cndmask_b32_e32 v26, v30, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v36
	v_mad_u64_u32 v[31:32], null, 0xf534ddc0, v4, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v27, v32
	v_cndmask_b32_e32 v29, v31, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[32:33], null, 0xfc2757d1, v4, v[27:28]
	v_mov_b32_e32 v27, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[33:34], null, 0x4e441529, v4, v[27:28]
	v_mov_b32_e32 v27, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0xa2f9836e, v4, v[27:28]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v27, v33, v31 :: v_dual_add_nc_u32 v4, v4, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v28, v34, v32 :: v_dual_cndmask_b32 v33, v35, v33
	v_cndmask_b32_e32 v32, v32, v30, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v28, v27, s2
	v_cndmask_b32_e64 v28, v33, v28, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v27, v27, v32, s2
	v_sub_nc_u32_e32 v33, 32, v4
	v_cndmask_b32_e64 v32, v32, v29, s2
	v_cndmask_b32_e64 v28, v28, v31, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v31, v31, v27, s3
	v_cndmask_b32_e64 v27, v27, v32, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v34, v28, v31, v33
	v_alignbit_b32 v30, v31, v27, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v34, v28, vcc_lo
	v_cndmask_b32_e32 v28, v30, v31, vcc_lo
	v_cndmask_b32_e64 v26, v29, v26, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v29, v4, 29, 1
	v_alignbit_b32 v30, v4, v28, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v32, v26, s3
	v_sub_nc_u32_e32 v31, 0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v32, v27, v26, v33
	v_xor_b32_e32 v30, v30, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v27, v32, v27, vcc_lo
	v_clz_i32_u32_e32 v32, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v28, v28, v27, 30
	v_alignbit_b32 v26, v27, v26, 30
	v_min_u32_e32 v32, 32, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v27, v28, v31
	v_xor_b32_e32 v26, v26, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v28, 31, v32
	v_lshlrev_b32_e32 v34, 23, v32
	v_alignbit_b32 v30, v30, v27, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v26, v27, v26, v28
	v_lshrrev_b32_e32 v28, 29, v4
	v_alignbit_b32 v27, v30, v26, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v28, 31, v28
	v_lshrrev_b32_e32 v30, 9, v30
	v_clz_i32_u32_e32 v31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v33, 0.5, v28
	v_min_u32_e32 v31, 32, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v33, v33, v34
	v_sub_nc_u32_e32 v35, 31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v26, v27, v26, v35
	v_or_b32_e32 v27, v30, v33
	v_add_lshl_u32 v30, v31, v32, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 9, v26
	v_mul_f32_e32 v31, 0x3fc90fda, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v30
	v_fma_f32 v30, 0x3fc90fda, v27, -v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, 0x33000000, v26
	v_fmamk_f32 v27, v27, 0x33a22168, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v26, v26, v28
	v_fmac_f32_e32 v27, 0x3fc90fda, v26
	v_lshrrev_b32_e32 v26, 30, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v31, v27
	v_add_nc_u32_e32 v28, v29, v26
.LBB0_23:                               ; %Flow241
	s_and_not1_saveexec_b32 s2, s10
; %bb.24:
	v_rndne_f32_e32 v26, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0xbfc90fda, v26, |v8|
	v_cvt_i32_f32_e32 v28, v26
	v_fmamk_f32 v4, v26, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v26, 0xa7c234c4, v4
; %bb.25:                               ; %_ZL3sinf.exit129
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_27
; %bb.26:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v38, v9, s2, 0x800000
	v_mad_u64_u32 v[26:27], null, 0xfe5163ab, v38, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v29, v27
	v_add_nc_u32_e32 v27, 0xffffff88, v16
	v_mad_u64_u32 v[31:32], null, 0x3c439041, v38, v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v27
	v_cndmask_b32_e64 v36, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v29, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v27, v36, v27
	v_mad_u64_u32 v[32:33], null, 0xdb629599, v38, v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v27
	v_mov_b32_e32 v29, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v37, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v26, v32, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[33:34], null, 0xf534ddc0, v38, v[29:30]
	v_add_nc_u32_e32 v27, v37, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v27
	v_mov_b32_e32 v29, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0xfc2757d1, v38, v[29:30]
	v_mov_b32_e32 v29, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[35:36], null, 0x4e441529, v38, v[29:30]
	v_mov_b32_e32 v29, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[36:37], null, 0xa2f9836e, v38, v[29:30]
	v_cndmask_b32_e64 v29, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v30, v35, v33 :: v_dual_add_nc_u32 v27, v29, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v36, v36, v34 :: v_dual_cndmask_b32 v35, v37, v35
	v_dual_cndmask_b32 v34, v34, v32 :: v_dual_cndmask_b32 v29, v33, v31
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v36, v30, s2
	v_cndmask_b32_e64 v33, v35, v36, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v30, v30, v34, s2
	v_sub_nc_u32_e32 v35, 32, v27
	v_cndmask_b32_e64 v34, v34, v29, s2
	v_cndmask_b32_e64 v26, v29, v26, s2
	v_cndmask_b32_e64 v33, v33, v31, s3
	v_cndmask_b32_e64 v31, v31, v30, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v30, v30, v34, s3
	v_cndmask_b32_e64 v26, v34, v26, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v33, v31, v35
	v_alignbit_b32 v32, v31, v30, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v30, v26, v35
	v_cndmask_b32_e32 v27, v36, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v29, v32, v31 :: v_dual_cndmask_b32 v30, v34, v30
	v_bfe_u32 v31, v27, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v27, v29, 30
	v_alignbit_b32 v29, v29, v30, 30
	v_alignbit_b32 v26, v30, v26, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v33, 0, v31
	v_xor_b32_e32 v32, v32, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v29, v29, v33
	v_xor_b32_e32 v26, v26, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v34, v32
	v_min_u32_e32 v34, 32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v30, 31, v34
	v_lshlrev_b32_e32 v36, 23, v34
	v_alignbit_b32 v32, v32, v29, v30
	v_alignbit_b32 v26, v29, v26, v30
	v_lshrrev_b32_e32 v30, 29, v27
	v_lshrrev_b32_e32 v27, 30, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v32, v26, 9
	v_lshlrev_b32_e32 v30, 31, v30
	v_lshrrev_b32_e32 v32, 9, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v27, v31, v27
	v_clz_i32_u32_e32 v33, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v35, 0.5, v30
	v_min_u32_e32 v33, 32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, v35, v36
	v_sub_nc_u32_e32 v37, 31, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v26, v29, v26, v37
	v_or_b32_e32 v29, v32, v35
	v_add_lshl_u32 v32, v33, v34, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 9, v26
	v_mul_f32_e32 v33, 0x3fc90fda, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v32
	v_fma_f32 v32, 0x3fc90fda, v29, -v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, 0x33000000, v26
	v_fmamk_f32 v29, v29, 0x33a22168, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v26, v26, v30
	v_fmac_f32_e32 v29, 0x3fc90fda, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v26, v33, v29
.LBB0_27:                               ; %Flow240
	s_and_not1_saveexec_b32 s2, s10
; %bb.28:
	v_rndne_f32_e32 v27, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, 0xbfc90fda, v27, |v8|
	v_fmamk_f32 v26, v27, 0xb3a22168, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v26, v27, 0xa7c234c4, v26
	v_cvt_i32_f32_e32 v27, v27
; %bb.29:                               ; %_ZL3sinf.exit137
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr29
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_31
; %bb.30:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v31, 0
	v_and_or_b32 v39, v9, s2, 0x800000
	v_add_nc_u32_e32 v37, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0xfe5163ab, v39, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v37
	v_cndmask_b32_e64 v38, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0x3c439041, v39, v[30:31]
	v_add_nc_u32_e32 v38, v38, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v30, v33
	v_cmp_lt_u32_e64 s2, 31, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0xdb629599, v39, v[30:31]
	v_cndmask_b32_e64 v40, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v29, v33, v29 :: v_dual_add_nc_u32 v40, v40, v38
	v_mov_b32_e32 v30, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v40
	v_mad_u64_u32 v[34:35], null, 0xf534ddc0, v39, v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v30, v35
	v_cndmask_b32_e32 v32, v34, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0xfc2757d1, v39, v[30:31]
	v_cndmask_b32_e64 v29, v32, v29, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v30, v36
	v_mad_u64_u32 v[36:37], null, 0x4e441529, v39, v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v30, v37
	v_mad_u64_u32 v[37:38], null, 0xa2f9836e, v39, v[30:31]
	v_cndmask_b32_e64 v30, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v31, v36, v34 :: v_dual_add_nc_u32 v30, v30, v40
	v_dual_cndmask_b32 v37, v37, v35 :: v_dual_cndmask_b32 v36, v38, v36
	v_cndmask_b32_e32 v35, v35, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v30
	v_cndmask_b32_e64 v34, v37, v31, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v36, v37, s2
	v_cndmask_b32_e64 v31, v31, v35, s2
	v_sub_nc_u32_e32 v37, 32, v30
	v_cndmask_b32_e64 v35, v35, v32, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v36, v34, s3
	v_cndmask_b32_e64 v34, v34, v31, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v31, v31, v35, s3
	v_cndmask_b32_e64 v29, v35, v29, s3
	v_alignbit_b32 v38, v36, v34, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v33, v34, v31, v37
	v_cndmask_b32_e32 v30, v38, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v31, v29, v37
	v_cndmask_b32_e32 v32, v33, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v33, v30, 29, 1
	v_cndmask_b32_e32 v31, v36, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v30, v32, 30
	v_sub_nc_u32_e32 v35, 0, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v32, v31, 30
	v_alignbit_b32 v29, v31, v29, 30
	v_xor_b32_e32 v34, v34, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v31, v32, v35
	v_xor_b32_e32 v29, v29, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v36, v34
	v_min_u32_e32 v36, 32, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, 31, v36
	v_lshlrev_b32_e32 v38, 23, v36
	v_alignbit_b32 v34, v34, v31, v32
	v_alignbit_b32 v29, v31, v29, v32
	v_lshrrev_b32_e32 v32, 29, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v31, v34, v29, 9
	v_lshlrev_b32_e32 v32, 31, v32
	v_lshrrev_b32_e32 v34, 9, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v35, v31
	v_or_b32_e32 v37, 0.5, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v35, 32, v35
	v_sub_nc_u32_e32 v37, v37, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v39, 31, v35
	v_alignbit_b32 v29, v31, v29, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v31, v34, v37
	v_add_lshl_u32 v34, v35, v36, 23
	v_lshrrev_b32_e32 v29, 9, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, 0x3fc90fda, v31
	v_sub_nc_u32_e32 v29, v29, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, 0x3fc90fda, v31, -v35
	v_add_nc_u32_e32 v29, 0x33000000, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v31, v31, 0x33a22168, v34
	v_or_b32_e32 v29, v29, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, 0x3fc90fda, v29
	v_lshrrev_b32_e32 v30, 30, v30
	v_dual_add_f32 v29, v35, v31 :: v_dual_add_nc_u32 v30, v33, v30
.LBB0_31:                               ; %Flow239
	s_and_not1_saveexec_b32 s2, s10
; %bb.32:
	v_rndne_f32_e32 v30, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, 0xbfc90fda, v30, |v8|
	v_fmamk_f32 v29, v30, 0xb3a22168, v29
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v29, v30, 0xa7c234c4, v29
	v_cvt_i32_f32_e32 v30, v30
; %bb.33:                               ; %_ZL3cosf.exit143
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr31
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_35
; %bb.34:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v33, 0
	v_and_or_b32 v41, v9, s2, 0x800000
	v_add_nc_u32_e32 v39, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0xfe5163ab, v41, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v39
	v_cndmask_b32_e64 v40, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0x3c439041, v41, v[32:33]
	v_add_nc_u32_e32 v40, v40, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v32, v35
	v_cmp_lt_u32_e64 s2, 31, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0xdb629599, v41, v[32:33]
	v_cndmask_b32_e64 v42, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v31, v35, v31 :: v_dual_add_nc_u32 v42, v42, v40
	v_mov_b32_e32 v32, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v42
	v_mad_u64_u32 v[36:37], null, 0xf534ddc0, v41, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v32, v37
	v_cndmask_b32_e32 v34, v36, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, 0xfc2757d1, v41, v[32:33]
	v_cndmask_b32_e64 v31, v34, v31, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v32, v38
	v_mad_u64_u32 v[38:39], null, 0x4e441529, v41, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v32, v39
	v_mad_u64_u32 v[39:40], null, 0xa2f9836e, v41, v[32:33]
	v_cndmask_b32_e64 v32, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v33, v38, v36 :: v_dual_add_nc_u32 v32, v32, v42
	v_dual_cndmask_b32 v39, v39, v37 :: v_dual_cndmask_b32 v38, v40, v38
	v_cndmask_b32_e32 v37, v37, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v32
	v_cndmask_b32_e64 v36, v39, v33, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v38, v38, v39, s2
	v_cndmask_b32_e64 v33, v33, v37, s2
	v_sub_nc_u32_e32 v39, 32, v32
	v_cndmask_b32_e64 v37, v37, v34, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v38, v38, v36, s3
	v_cndmask_b32_e64 v36, v36, v33, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v33, v33, v37, s3
	v_cndmask_b32_e64 v31, v37, v31, s3
	v_alignbit_b32 v40, v38, v36, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v35, v36, v33, v39
	v_cndmask_b32_e32 v32, v40, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v33, v31, v39
	v_cndmask_b32_e32 v34, v35, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v35, v32, 29, 1
	v_cndmask_b32_e32 v33, v38, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v32, v34, 30
	v_sub_nc_u32_e32 v37, 0, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v34, v33, 30
	v_alignbit_b32 v31, v33, v31, 30
	v_xor_b32_e32 v36, v36, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v33, v34, v37
	v_xor_b32_e32 v31, v31, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v38, v36
	v_min_u32_e32 v38, 32, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, 31, v38
	v_lshlrev_b32_e32 v40, 23, v38
	v_alignbit_b32 v36, v36, v33, v34
	v_alignbit_b32 v31, v33, v31, v34
	v_lshrrev_b32_e32 v34, 29, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v33, v36, v31, 9
	v_lshlrev_b32_e32 v34, 31, v34
	v_lshrrev_b32_e32 v36, 9, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v37, v33
	v_or_b32_e32 v39, 0.5, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v37, 32, v37
	v_sub_nc_u32_e32 v39, v39, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v41, 31, v37
	v_alignbit_b32 v31, v33, v31, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v33, v36, v39
	v_add_lshl_u32 v36, v37, v38, 23
	v_lshrrev_b32_e32 v31, 9, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v37, 0x3fc90fda, v33
	v_sub_nc_u32_e32 v31, v31, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v36, 0x3fc90fda, v33, -v37
	v_add_nc_u32_e32 v31, 0x33000000, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v33, v33, 0x33a22168, v36
	v_or_b32_e32 v31, v31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, 0x3fc90fda, v31
	v_lshrrev_b32_e32 v32, 30, v32
	v_dual_add_f32 v31, v37, v33 :: v_dual_add_nc_u32 v32, v35, v32
.LBB0_35:                               ; %Flow238
	s_and_not1_saveexec_b32 s2, s10
; %bb.36:
	v_rndne_f32_e32 v32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, 0xbfc90fda, v32, |v8|
	v_fmamk_f32 v31, v32, 0xb3a22168, v31
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v31, v32, 0xa7c234c4, v31
	v_cvt_i32_f32_e32 v32, v32
; %bb.37:                               ; %_ZL3sinf.exit151
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr33
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_39
; %bb.38:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v35, 0
	v_and_or_b32 v43, v9, s2, 0x800000
	v_add_nc_u32_e32 v41, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0xfe5163ab, v43, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v41
	v_cndmask_b32_e64 v42, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, 0x3c439041, v43, v[34:35]
	v_add_nc_u32_e32 v42, v42, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v34, v37
	v_cmp_lt_u32_e64 s2, 31, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, 0xdb629599, v43, v[34:35]
	v_cndmask_b32_e64 v44, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v33, v37, v33 :: v_dual_add_nc_u32 v44, v44, v42
	v_mov_b32_e32 v34, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v44
	v_mad_u64_u32 v[38:39], null, 0xf534ddc0, v43, v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v34, v39
	v_cndmask_b32_e32 v36, v38, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0xfc2757d1, v43, v[34:35]
	v_cndmask_b32_e64 v33, v36, v33, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v34, v40
	v_mad_u64_u32 v[40:41], null, 0x4e441529, v43, v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v34, v41
	v_mad_u64_u32 v[41:42], null, 0xa2f9836e, v43, v[34:35]
	v_cndmask_b32_e64 v34, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v35, v40, v38 :: v_dual_add_nc_u32 v34, v34, v44
	v_dual_cndmask_b32 v41, v41, v39 :: v_dual_cndmask_b32 v40, v42, v40
	v_cndmask_b32_e32 v39, v39, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v38, v41, v35, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v40, v40, v41, s2
	v_cndmask_b32_e64 v35, v35, v39, s2
	v_sub_nc_u32_e32 v41, 32, v34
	v_cndmask_b32_e64 v39, v39, v36, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v40, v40, v38, s3
	v_cndmask_b32_e64 v38, v38, v35, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, v35, v39, s3
	v_cndmask_b32_e64 v33, v39, v33, s3
	v_alignbit_b32 v42, v40, v38, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v37, v38, v35, v41
	v_cndmask_b32_e32 v34, v42, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v35, v33, v41
	v_cndmask_b32_e32 v36, v37, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v37, v34, 29, 1
	v_cndmask_b32_e32 v35, v40, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v34, v36, 30
	v_sub_nc_u32_e32 v39, 0, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v36, v35, 30
	v_alignbit_b32 v33, v35, v33, 30
	v_xor_b32_e32 v38, v38, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v35, v36, v39
	v_xor_b32_e32 v33, v33, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v40, v38
	v_min_u32_e32 v40, 32, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v36, 31, v40
	v_lshlrev_b32_e32 v42, 23, v40
	v_alignbit_b32 v38, v38, v35, v36
	v_alignbit_b32 v33, v35, v33, v36
	v_lshrrev_b32_e32 v36, 29, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v35, v38, v33, 9
	v_lshlrev_b32_e32 v36, 31, v36
	v_lshrrev_b32_e32 v38, 9, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v39, v35
	v_or_b32_e32 v41, 0.5, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v39, 32, v39
	v_sub_nc_u32_e32 v41, v41, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v43, 31, v39
	v_alignbit_b32 v33, v35, v33, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v35, v38, v41
	v_add_lshl_u32 v38, v39, v40, 23
	v_lshrrev_b32_e32 v33, 9, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v39, 0x3fc90fda, v35
	v_sub_nc_u32_e32 v33, v33, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, 0x3fc90fda, v35, -v39
	v_add_nc_u32_e32 v33, 0x33000000, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v35, v35, 0x33a22168, v38
	v_or_b32_e32 v33, v33, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, 0x3fc90fda, v33
	v_lshrrev_b32_e32 v34, 30, v34
	v_dual_add_f32 v33, v39, v35 :: v_dual_add_nc_u32 v34, v37, v34
.LBB0_39:                               ; %Flow237
	s_and_not1_saveexec_b32 s2, s10
; %bb.40:
	v_rndne_f32_e32 v34, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v33, 0xbfc90fda, v34, |v8|
	v_fmamk_f32 v33, v34, 0xb3a22168, v33
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v33, v34, 0xa7c234c4, v33
	v_cvt_i32_f32_e32 v34, v34
; %bb.41:                               ; %_ZL3cosf.exit157
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr35
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB0_43
; %bb.42:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v37, 0
	v_and_or_b32 v45, v9, s2, 0x800000
	v_add_nc_u32_e32 v43, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0xfe5163ab, v45, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v43
	v_cndmask_b32_e64 v44, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, 0x3c439041, v45, v[36:37]
	v_add_nc_u32_e32 v44, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v36, v39
	v_cmp_lt_u32_e64 s2, 31, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0xdb629599, v45, v[36:37]
	v_cndmask_b32_e64 v46, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v35, v39, v35 :: v_dual_add_nc_u32 v46, v46, v44
	v_mov_b32_e32 v36, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v46
	v_mad_u64_u32 v[40:41], null, 0xf534ddc0, v45, v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v36, v41
	v_cndmask_b32_e32 v38, v40, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[41:42], null, 0xfc2757d1, v45, v[36:37]
	v_cndmask_b32_e64 v35, v38, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v36, v42
	v_mad_u64_u32 v[42:43], null, 0x4e441529, v45, v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v36, v43
	v_mad_u64_u32 v[43:44], null, 0xa2f9836e, v45, v[36:37]
	v_cndmask_b32_e64 v36, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v37, v42, v40 :: v_dual_add_nc_u32 v36, v36, v46
	v_dual_cndmask_b32 v43, v43, v41 :: v_dual_cndmask_b32 v42, v44, v42
	v_cndmask_b32_e32 v41, v41, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e64 v40, v43, v37, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v42, v42, v43, s2
	v_cndmask_b32_e64 v37, v37, v41, s2
	v_sub_nc_u32_e32 v43, 32, v36
	v_cndmask_b32_e64 v41, v41, v38, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v42, v42, v40, s3
	v_cndmask_b32_e64 v40, v40, v37, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, v37, v41, s3
	v_cndmask_b32_e64 v35, v41, v35, s3
	v_alignbit_b32 v44, v42, v40, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v39, v40, v37, v43
	v_cndmask_b32_e32 v36, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v37, v35, v43
	v_cndmask_b32_e32 v38, v39, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v39, v36, 29, 1
	v_cndmask_b32_e32 v37, v42, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v36, v38, 30
	v_sub_nc_u32_e32 v41, 0, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v38, v37, 30
	v_alignbit_b32 v35, v37, v35, 30
	v_xor_b32_e32 v40, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v37, v38, v41
	v_xor_b32_e32 v35, v35, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v42, v40
	v_min_u32_e32 v42, 32, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v38, 31, v42
	v_lshlrev_b32_e32 v44, 23, v42
	v_alignbit_b32 v40, v40, v37, v38
	v_alignbit_b32 v35, v37, v35, v38
	v_lshrrev_b32_e32 v38, 29, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v37, v40, v35, 9
	v_lshlrev_b32_e32 v38, 31, v38
	v_lshrrev_b32_e32 v40, 9, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v41, v37
	v_or_b32_e32 v43, 0.5, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v41, 32, v41
	v_sub_nc_u32_e32 v43, v43, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v45, 31, v41
	v_alignbit_b32 v35, v37, v35, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v37, v40, v43
	v_add_lshl_u32 v40, v41, v42, 23
	v_lshrrev_b32_e32 v35, 9, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v41, 0x3fc90fda, v37
	v_sub_nc_u32_e32 v35, v35, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v40, 0x3fc90fda, v37, -v41
	v_add_nc_u32_e32 v35, 0x33000000, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v37, v37, 0x33a22168, v40
	v_or_b32_e32 v35, v35, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, 0x3fc90fda, v35
	v_lshrrev_b32_e32 v36, 30, v36
	v_dual_add_f32 v35, v41, v37 :: v_dual_add_nc_u32 v36, v39, v36
.LBB0_43:                               ; %Flow236
	s_and_not1_saveexec_b32 s2, s10
; %bb.44:
	v_rndne_f32_e32 v36, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, 0xbfc90fda, v36, |v8|
	v_fmamk_f32 v35, v36, 0xb3a22168, v35
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v35, v36, 0xa7c234c4, v35
	v_cvt_i32_f32_e32 v36, v36
; %bb.45:                               ; %_ZL3sinf.exit165
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr38
                                        ; implicit-def: $vgpr37
	s_and_saveexec_b32 s2, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s2
	s_cbranch_execz .LBB0_47
; %bb.46:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v39, 0
	v_and_or_b32 v20, v9, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[37:38], null, 0xfe5163ab, v20, 0
	v_mad_u64_u32 v[40:41], null, 0x3c439041, v20, v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v38, v41
	v_mad_u64_u32 v[41:42], null, 0xdb629599, v20, v[38:39]
	v_add_nc_u32_e32 v16, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v16
	v_mov_b32_e32 v38, v42
	v_cndmask_b32_e64 v45, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[42:43], null, 0xf534ddc0, v20, v[38:39]
	v_cndmask_b32_e32 v37, v41, v37, vcc_lo
	v_add_nc_u32_e32 v16, v45, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v38, v43
	v_cmp_lt_u32_e64 s2, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[43:44], null, 0xfc2757d1, v20, v[38:39]
	v_cndmask_b32_e64 v46, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v16, v46, v16
	v_mov_b32_e32 v38, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v16
	v_mad_u64_u32 v[44:45], null, 0x4e441529, v20, v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v38, v45
	v_mad_u64_u32 v[45:46], null, 0xa2f9836e, v20, v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s3
	v_cndmask_b32_e32 v38, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v39, v45, v43 :: v_dual_add_nc_u32 v16, v20, v16
	v_dual_cndmask_b32 v44, v46, v44 :: v_dual_cndmask_b32 v43, v43, v41
	v_cndmask_b32_e32 v20, v42, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v42, 32, v16
	v_cndmask_b32_e64 v40, v39, v38, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v39, v44, v39, s2
	v_cndmask_b32_e64 v38, v38, v43, s2
	v_cndmask_b32_e64 v43, v43, v20, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e64 v20, v20, v37, s2
	v_cndmask_b32_e64 v39, v39, v40, s3
	v_cndmask_b32_e64 v40, v40, v38, s3
	v_cndmask_b32_e64 v38, v38, v43, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v43, v20, s3
	v_alignbit_b32 v44, v39, v40, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v41, v40, v38, v42
	v_alignbit_b32 v42, v38, v20, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v44, v39 :: v_dual_cndmask_b32 v37, v41, v40
	v_cndmask_b32_e32 v38, v42, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v39, v16, 29, 1
	v_alignbit_b32 v40, v16, v37, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v37, v37, v38, 30
	v_alignbit_b32 v20, v38, v20, 30
	v_sub_nc_u32_e32 v41, 0, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v40, v40, v41
	v_xor_b32_e32 v37, v37, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v20, v20, v41
	v_clz_i32_u32_e32 v42, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v42, 32, v42
	v_sub_nc_u32_e32 v38, 31, v42
	v_lshlrev_b32_e32 v44, 23, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v40, v37, v38
	v_alignbit_b32 v20, v37, v20, v38
	v_lshrrev_b32_e32 v38, 29, v16
	v_lshrrev_b32_e32 v16, 30, v16
	v_alignbit_b32 v37, v40, v20, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v38, 31, v38
	v_lshrrev_b32_e32 v40, 9, v40
	v_clz_i32_u32_e32 v41, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v43, 0.5, v38
	v_min_u32_e32 v41, 32, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v43, v43, v44
	v_sub_nc_u32_e32 v45, 31, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v37, v20, v45
	v_or_b32_e32 v37, v40, v43
	v_add_lshl_u32 v40, v41, v42, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v20, 9, v20
	v_mul_f32_e32 v41, 0x3fc90fda, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v20, v20, v40
	v_fma_f32 v40, 0x3fc90fda, v37, -v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, 0x33000000, v20
	v_fmamk_f32 v37, v37, 0x33a22168, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v20, v38
	v_add_nc_u32_e32 v38, v39, v16
	v_fmac_f32_e32 v37, 0x3fc90fda, v20
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v37, v41, v37
.LBB0_47:                               ; %Flow235
	s_and_not1_saveexec_b32 s2, s7
; %bb.48:
	v_rndne_f32_e32 v16, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0xbfc90fda, v16, |v8|
	v_cvt_i32_f32_e32 v38, v16
	v_fmamk_f32 v20, v16, 0xb3a22168, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v37, v16, 0xa7c234c4, v20
; %bb.49:                               ; %_ZL3cosf.exit171
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v16, v5, s9
	v_mul_lo_u32 v20, v0, s8
	v_cvt_f32_i32_e32 v43, s9
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s7, 0x37d75334
	s_mov_b32 s10, 0
	v_mul_f32_e32 v52, v4, v4
	v_mul_f32_e32 v50, v22, v22
	v_sub_nc_u32_e32 v0, v0, v16
	v_sub_nc_u32_e32 v20, v1, v20
	v_cvt_f32_i32_e32 v16, s8
	v_fmaak_f32 v67, s7, v52, 0xbab64f3b
	v_fmaak_f32 v64, s3, v50, 0x3c0881c4
	v_cvt_f32_i32_e32 v0, v0
	v_cvt_f32_i32_e32 v20, v20
	v_fmaak_f32 v66, s3, v52, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v39, null, v43, v43, v0
	v_div_scale_f32 v40, null, v16, v16, v20
	v_div_scale_f32 v46, vcc_lo, v0, v43, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v41, v39
	v_rcp_f32_e32 v42, v40
	s_waitcnt_depctr 0xfff
	v_fma_f32 v44, -v39, v41, 1.0
	v_fma_f32 v45, -v40, v42, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v41, v44, v41 :: v_dual_fmac_f32 v42, v45, v42
	v_div_scale_f32 v44, s2, v20, v16, v20
	v_mul_f32_e32 v45, v46, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v47, v44, v42
	v_fma_f32 v48, -v39, v45, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v49, -v40, v47, v44
	v_dual_fmac_f32 v45, v48, v41 :: v_dual_mul_f32 v48, v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v47, v49, v42
	v_and_b32_e32 v49, 1, v17
	v_lshlrev_b32_e32 v17, 30, v17
	v_fma_f32 v39, -v39, v45, v46
	v_mul_f32_e32 v46, v12, v12
	v_fma_f32 v40, -v40, v47, v44
	v_and_b32_e32 v44, 1, v25
	v_fmaak_f32 v62, s3, v48, 0x3c0881c4
	v_div_fmas_f32 v39, v39, v41, v45
	s_mov_b32 vcc_lo, s2
	v_and_b32_e32 v45, 1, v21
	v_div_fmas_f32 v40, v40, v42, v47
	v_lshlrev_b32_e32 v21, 30, v21
	v_div_fixup_f32 v0, v39, v43, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v44
	v_fmaak_f32 v60, s3, v46, 0x3c0881c4
	v_div_fixup_f32 v20, v40, v16, v20
	v_and_b32_e32 v59, 0x80000000, v21
	v_cvt_f64_f32_e32 v[41:42], v0
	v_dual_mul_f32 v0, v24, v24 :: v_dual_and_b32 v47, 1, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[39:40], v20
	v_dual_mul_f32 v25, v19, v19 :: v_dual_lshlrev_b32 v20, 30, v25
	v_fmaak_f32 v54, s3, v0, 0x3c0881c4
	v_and_b32_e32 v53, 1, v28
	v_lshlrev_b32_e32 v28, 30, v28
	v_lshlrev_b32_e32 v13, 30, v13
	v_fmaak_f32 v57, s3, v25, 0x3c0881c4
	v_fmaak_f32 v54, v0, v54, 0xbe2aaa9d
	v_fmaak_f32 v55, s7, v0, 0xbab64f3b
	v_dual_fmaak_f32 v58, s7, v25, 0xbab64f3b :: v_dual_and_b32 v51, 1, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fmaak_f32 v57, v25, v57, 0xbe2aaa9d
	v_and_b32_e32 v56, 0x80000000, v20
	v_dual_mul_f32 v54, v0, v54 :: v_dual_lshlrev_b32 v23, 30, v23
	v_fmaak_f32 v63, s7, v48, 0xbab64f3b
	v_cmp_eq_u32_e64 s2, 0, v53
	v_fmac_f32_e32 v24, v24, v54
	v_add_f64 v[41:42], v[41:42], -0.5
	v_add_f64 v[39:40], v[39:40], -0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[39:40], v[39:40]
	v_add_f64 v[39:40], v[41:42], v[41:42]
	v_fmaak_f32 v42, v46, v60, 0xbe2aaa9d
	v_fmaak_f32 v60, v48, v62, 0xbe2aaa9d
	v_fmaak_f32 v41, v25, v58, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v57, v25, v57 :: v_dual_mul_f32 v42, v46, v42
	v_and_b32_e32 v17, 0x80000000, v17
	v_fmaak_f32 v41, v25, v41, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v19, v19, v57 :: v_dual_fmac_f32 v12, v12, v42
	v_xor_b32_e32 v62, v9, v17
	v_fmaak_f32 v17, v50, v64, 0xbe2aaa9d
	v_dual_fmaak_f32 v61, s7, v46, 0xbab64f3b :: v_dual_mul_f32 v60, v48, v60
	v_fmaak_f32 v55, v0, v55, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v17, v50, v17 :: v_dual_and_b32 v28, 0x80000000, v28
	v_fmaak_f32 v58, v46, v61, 0x3d2aabf7
	v_fmaak_f32 v65, s7, v50, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v55, v0, v55, 0xbf000004
	v_fmaak_f32 v61, v48, v63, 0x3d2aabf7
	v_fmaak_f32 v64, v52, v66, 0xbe2aaa9d
	v_fmaak_f32 v58, v46, v58, 0xbf000004
	v_fma_f32 v25, v25, v41, 1.0
	v_fma_f32 v0, v0, v55, 1.0
	v_fmac_f32_e32 v22, v22, v17
	v_fmaak_f32 v63, v50, v65, 0x3d2aabf7
	v_fma_f32 v41, v46, v58, 1.0
	v_dual_mul_f32 v64, v52, v64 :: v_dual_and_b32 v13, 0x80000000, v13
	v_cndmask_b32_e64 v0, -v24, v0, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v45
	v_fmaak_f32 v63, v50, v63, 0xbf000004
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_fmac_f32 v4, v4, v64 :: v_dual_and_b32 v23, 0x80000000, v23
	v_cvt_f32_f64_e32 v17, v[20:21]
	v_cndmask_b32_e64 v19, -v19, v25, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v47
	v_cvt_f32_f64_e32 v20, v[39:40]
	v_fmaak_f32 v65, v52, v67, 0x3d2aabf7
	v_fmaak_f32 v61, v48, v61, 0xbf000004
	v_fma_f32 v21, v50, v63, 1.0
	v_cndmask_b32_e64 v12, -v12, v41, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v51
	v_xor_b32_e32 v23, v9, v23
	v_fmaak_f32 v65, v52, v65, 0xbf000004
	v_fmac_f32_e32 v15, v15, v60
	v_fma_f32 v42, v48, v61, 1.0
	v_cndmask_b32_e32 v21, v21, v22, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v49
	v_fma_f32 v46, v52, v65, 1.0
	v_xor_b32_e32 v28, v9, v28
	v_xor_b32_e32 v0, v56, v0
	v_xor3_b32 v21, v23, v21, v8
	v_cndmask_b32_e32 v15, v42, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
	v_cndmask_b32_e64 v4, v46, v4, s2
	v_xor_b32_e32 v19, v59, v19
	v_xor_b32_e32 v12, v13, v12
	v_xor3_b32 v15, v62, v15, v8
	v_cndmask_b32_e32 v21, 0x7fc00000, v21, vcc_lo
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_xor3_b32 v4, v28, v4, v8
	v_cndmask_b32_e32 v13, 0x7fc00000, v19, vcc_lo
	v_cndmask_b32_e32 v15, 0x7fc00000, v15, vcc_lo
	s_waitcnt vmcnt(2)
	v_dual_mul_f32 v19, v14, v21 :: v_dual_cndmask_b32 v12, 0x7fc00000, v12
	v_cvt_f64_f32_e32 v[21:22], v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v10, v15
	v_fma_f32 v13, v11, v13, -v19
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v7, v12, -v15
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v13, v13, v17 :: v_dual_mul_f32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v12, v20
	v_fma_f32 v0, v18, v0, -v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v13, v0
	v_cvt_f64_f32_e32 v[12:13], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], 0.5, 0.5
	v_mul_f64 v[12:13], v[12:13], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[12:13]
	v_floor_f32_e32 v0, v4
	v_ceil_f32_e32 v12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v0, v0
	v_cvt_f32_i32_e32 v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, v12, v13
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_59
; %bb.50:                               ; %.lr.ph201
	v_dual_mul_f32 v15, v35, v35 :: v_dual_mul_f32 v28, v26, v26
	v_dual_mul_f32 v22, v31, v31 :: v_dual_and_b32 v19, 1, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v24, s7, v15, 0xbab64f3b :: v_dual_lshlrev_b32 v21, 30, v36
	v_fmaak_f32 v23, s3, v15, 0x3c0881c4
	v_cmp_eq_u32_e64 s2, 0, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v36, s3, v22, 0x3c0881c4
	v_fmaak_f32 v39, s7, v22, 0xbab64f3b
	v_fmaak_f32 v24, v15, v24, 0x3d2aabf7
	v_fmaak_f32 v23, v15, v23, 0xbe2aaa9d
	v_and_b32_e32 v19, 1, v32
	v_fmaak_f32 v36, v22, v36, 0xbe2aaa9d
	v_fmaak_f32 v39, v22, v39, 0x3d2aabf7
	v_lshlrev_b32_e32 v25, 30, v32
	v_dual_mul_f32 v23, v15, v23 :: v_dual_fmaak_f32 v40, s3, v28, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v36, v22, v36 :: v_dual_and_b32 v21, 0x80000000, v21
	s_load_b64 s[0:1], s[0:1], 0x20
	v_fmac_f32_e32 v35, v35, v23
	v_fmaak_f32 v23, s7, v28, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v21, v9, v21
	v_dual_fmac_f32 v31, v31, v36 :: v_dual_lshlrev_b32 v32, 30, v34
	v_fmaak_f32 v23, v28, v23, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v24, v15, v24, 0xbf000004 :: v_dual_fmaak_f32 v23, v28, v23, 0xbf000004
	v_fma_f32 v15, v15, v24, 1.0
	v_fmaak_f32 v24, v22, v39, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v22, v22, v24, 1.0
	v_and_b32_e32 v24, 0x80000000, v25
	v_cndmask_b32_e64 v15, v15, v35, s2
	v_cmp_eq_u32_e64 s2, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v22, v31, s2
	v_mul_f32_e32 v31, v33, v33
	v_fmaak_f32 v25, v28, v40, 0xbe2aaa9d
	v_xor_b32_e32 v22, v9, v24
	v_mul_f32_e32 v24, v28, v25
	v_mul_f32_e32 v25, v29, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor3_b32 v19, v22, v19, v8
	v_fma_f32 v22, v28, v23, 1.0
	v_fmac_f32_e32 v26, v26, v24
	v_and_b32_e32 v24, 1, v27
	v_dual_fmaak_f32 v28, s7, v25, 0xbab64f3b :: v_dual_lshlrev_b32 v27, 30, v27
	v_cndmask_b32_e32 v19, 0x7fc00000, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s2, 0, v24
	v_fmaak_f32 v24, v25, v28, 0x3d2aabf7
	v_fmaak_f32 v28, s7, v31, 0xbab64f3b
	v_fmaak_f32 v23, s3, v25, 0x3c0881c4
	v_and_b32_e32 v27, 0x80000000, v27
	v_cndmask_b32_e64 v22, v22, v26, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v25, v23, 0xbe2aaa9d
	v_xor_b32_e32 v9, v9, v27
	v_and_b32_e32 v27, 1, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v23, v25, v23
	v_xor3_b32 v9, v9, v22, v8
	v_xor3_b32 v8, v21, v15, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v29, v23
	v_dual_fmaak_f32 v23, v31, v28, 0x3d2aabf7 :: v_dual_lshlrev_b32 v28, 30, v30
	v_and_b32_e32 v30, 1, v34
	v_fmaak_f32 v26, s3, v31, 0x3c0881c4
	v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
	v_fmaak_f32 v23, v31, v23, 0xbf000004
	v_and_b32_e32 v28, 0x80000000, v28
	v_cmp_eq_u32_e64 s2, 0, v30
	v_fmaak_f32 v26, v31, v26, 0xbe2aaa9d
	v_fmaak_f32 v24, v25, v24, 0xbf000004
	v_fma_f32 v23, v31, v23, 1.0
	v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v25, v24, 1.0
	v_dual_mul_f32 v25, v31, v26 :: v_dual_mul_f32 v26, v37, v37
	v_fmac_f32_e32 v33, v33, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v31, s7, v26, 0xbab64f3b
	v_cndmask_b32_e64 v23, -v33, v23, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v30, v26, v31, 0x3d2aabf7
	v_and_b32_e32 v31, 0x80000000, v32
	v_xor_b32_e32 v23, v31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v23, 0x7fc00000, v23, vcc_lo
	v_dual_mul_f32 v14, v14, v23 :: v_dual_fmaak_f32 v25, s3, v26, 0x3c0881c4
	v_cmp_eq_u32_e64 s2, 0, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v27, v26, v30, 0xbf000004 :: v_dual_fmac_f32 v14, v11, v19
	v_fmaak_f32 v25, v26, v25, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v24, -v29, v24, s2
	v_mul_f32_e32 v25, v26, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v26, v26, v27, 1.0
	v_lshlrev_b32_e32 v27, 30, v38
	v_xor_b32_e32 v24, v28, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v37, v37, v25
	v_dual_cndmask_b32 v22, 0x7fc00000, v24 :: v_dual_and_b32 v25, 1, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v25
	v_mul_f32_e32 v10, v10, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, -v37, v26, s2
	v_and_b32_e32 v26, 0x80000000, v27
	v_fmac_f32_e32 v10, v7, v9
	v_mul_f32_e32 v7, v14, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v23, v26, v25
	v_fmac_f32_e32 v7, v10, v20
	v_cvt_f64_f32_e32 v[9:10], v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, 0x7fc00000, v23, vcc_lo
	v_mul_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v18, v8
	v_add_f32_e32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[7:8], v3
	v_fma_f64 v[7:8], v[7:8], 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[7:8], v[9:10]
	v_cvt_f32_f64_e32 v3, v[7:8]
	v_mul_lo_u32 v7, v6, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v7
	v_mad_u64_u32 v[7:8], null, v6, s6, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, v7, s9, v[0:1]
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_mul_lo_u32 v8, s8, v8
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, s0, v1
	v_add_co_ci_u32_e64 v2, s0, s1, v2, s0
	v_floor_f32_e32 v5, v3
	v_ceil_f32_e32 v6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v5, v5
	v_cvt_f32_i32_e32 v7, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, v6, v7
.LBB0_51:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_53 Depth 2
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB0_58
; %bb.52:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_51 Depth=1
	global_load_b32 v9, v[1:2], off
	v_dual_sub_f32 v10, v4, v13 :: v_dual_mov_b32 v11, v7
	v_cmp_lt_i32_e64 s0, -1, v0
	v_cmp_gt_i32_e64 s1, s9, v0
	v_mov_b32_e32 v13, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e64 v10, 1.0, |v10|
	s_mov_b32 s7, 0
.LBB0_53:                               ;   Parent Loop BB0_51 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v14, 0
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_57
; %bb.54:                               ;   in Loop: Header=BB0_53 Depth=2
	v_cmp_lt_i32_e64 s2, -1, v13
	v_cmp_gt_i32_e64 s3, s8, v13
	v_mov_b32_e32 v14, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s2, s1, s2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_56
; %bb.55:                               ;   in Loop: Header=BB0_53 Depth=2
	v_add_nc_u32_e32 v14, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s2, s4, v14
	v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
	global_load_b32 v14, v[14:15], off
.LBB0_56:                               ; %Flow
                                        ;   in Loop: Header=BB0_53 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_57:                               ;   in Loop: Header=BB0_53 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v14, v10, v14 :: v_dual_add_nc_u32 v13, 1, v13
	v_sub_f32_e32 v15, v3, v11
	v_cvt_f32_i32_e32 v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e64 v15, 1.0, |v15|
	v_cmp_nge_f32_e64 s2, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v15, v14
	s_or_b32 s7, s2, s7
	global_store_b32 v[1:2], v9, off
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_53
.LBB0_58:                               ; %Flow232
                                        ;   in Loop: Header=BB0_51 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	v_add_nc_u32_e32 v0, 1, v0
	v_add_nc_u32_e32 v8, s8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v13, v0
	v_cmp_nge_f32_e64 s0, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s10, s0, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_51
.LBB0_59:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13AffineForwardPKfPKiS0_iPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 68
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13AffineForwardPKfPKiS0_iPf, .Lfunc_end0-_Z13AffineForwardPKfPKiS0_iPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 12112
; NumSgprs: 18
; NumVgprs: 68
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 68
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_ ; -- Begin function _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.globl	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
	.p2align	8
	.type	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_,@function
_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_: ; @_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v2
	s_cbranch_execz .LBB1_171
; %bb.1:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr12
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b64 s[6:7], s[10:11], 0x0
	s_load_b32 s4, s[10:11], 0x8
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s6, s5
	s_xor_b32 s10, s10, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s11, 0, s10
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s11, v0
	s_ashr_i32 s11, s7, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s7, s11
	s_xor_b32 s12, s12, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, s12
	v_mul_hi_u32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v5, v5
	v_add_nc_u32_e32 v4, v2, v3
	v_add_nc_u32_e32 v0, v0, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v1, v0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v4, v1
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v6, s10, v1
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v6 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v6, s5, v3
	s_sub_i32 s5, 0, s12
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	v_cvt_u32_f32_e32 v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v5, s5, v1
	s_ashr_i32 s5, s4, 31
	s_add_i32 s10, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s10, s10, s5
	v_cvt_f32_u32_e32 v7, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v1, v5
	v_rcp_iflag_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v5
	v_add_nc_u32_e32 v4, 1, v0
	s_waitcnt_depctr 0xfff
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_mul_f32 v7, 0x4f7ffffe, v7
	v_xor_b32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v6
	v_ashrrev_i32_e32 v0, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v4, v0
	v_xor_b32_e32 v5, v6, v0
	v_xor_b32_e32 v0, s11, v0
	s_sub_i32 s11, 0, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v5, v1
	v_mul_lo_u32 v6, v1, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v6
	v_subrev_nc_u32_e32 v8, s12, v5
	v_cmp_le_u32_e32 vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v5, v8 :: v_dual_add_nc_u32 v6, 1, v1
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s12, v5
	v_add_nc_u32_e32 v6, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_cvt_u32_f32_e32 v6, v7
	v_xor_b32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, s11, v6
	v_sub_nc_u32_e32 v5, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v6, v7
	v_ashrrev_i32_e32 v0, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v5, v0
	v_add_nc_u32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v7, v0
	v_xor_b32_e32 v0, s5, v0
	v_mul_hi_u32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v1, s10
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v8, s10, v6
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	v_dual_cndmask_b32 v6, v6, v8 :: v_dual_add_nc_u32 v7, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 1, v1
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v0
	v_sub_nc_u32_e32 v8, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v8, 7
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[0:1], off offset:24
	global_load_b32 v9, v[0:1], off
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v15, 0x7fffffff, v14
	v_cmp_ngt_f32_e64 s5, 0x48000000, |v14|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v11, 23, v15
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v10, v15, s2, 0x800000
	v_mad_u64_u32 v[12:13], null, 0xfe5163ab, v10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, v13
	v_add_nc_u32_e32 v13, 0xffffff88, v11
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v10, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v16, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, v23, v13
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v10, v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v13
	v_mov_b32_e32 v16, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v19, v12, vcc_lo
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v10, v[16:17]
	v_add_nc_u32_e32 v13, v24, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v13
	v_mov_b32_e32 v16, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v10, v[16:17]
	v_mov_b32_e32 v16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v10, v[16:17]
	v_mov_b32_e32 v16, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v10, v[16:17]
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s3
	v_cndmask_b32_e32 v16, v22, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v10, v10, v13
	v_dual_cndmask_b32 v17, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_cndmask_b32_e32 v21, v21, v19, vcc_lo
	v_cndmask_b32_e32 v13, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v20, 32, v10
	v_cndmask_b32_e64 v18, v17, v16, s2
	v_cndmask_b32_e64 v17, v22, v17, s2
	v_cndmask_b32_e64 v16, v16, v21, s2
	v_cndmask_b32_e64 v21, v21, v13, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v12, v13, v12, s2
	v_cndmask_b32_e64 v17, v17, v18, s3
	v_cndmask_b32_e64 v18, v18, v16, s3
	v_cndmask_b32_e64 v16, v16, v21, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v21, v12, s3
	v_alignbit_b32 v22, v17, v18, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v18, v16, v20
	v_alignbit_b32 v20, v16, v12, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v22, v17 :: v_dual_cndmask_b32 v13, v19, v18
	v_cndmask_b32_e32 v16, v20, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v17, v10, 29, 1
	v_alignbit_b32 v18, v10, v13, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v13, v13, v16, 30
	v_alignbit_b32 v12, v16, v12, 30
	v_sub_nc_u32_e32 v19, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v13, v16
	v_alignbit_b32 v12, v13, v12, v16
	v_lshrrev_b32_e32 v16, 29, v10
	v_alignbit_b32 v13, v18, v12, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v13, v12, v23
	v_or_b32_e32 v13, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v12, 9, v12
	v_mul_f32_e32 v19, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v18
	v_fma_f32 v18, 0x3fc90fda, v13, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0x33000000, v12
	v_fmamk_f32 v13, v13, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, v12, v16
	v_fmac_f32_e32 v13, 0x3fc90fda, v12
	v_lshrrev_b32_e32 v10, 30, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v12, v19, v13
	v_add_nc_u32_e32 v10, v17, v10
.LBB1_3:                                ; %Flow702
	s_or_saveexec_b32 s2, s10
	v_mul_f32_e64 v22, 0x3f22f983, |v14|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v10, v22
	v_fma_f32 v12, 0xbfc90fda, v10, |v14|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v12, v10, 0xb3a22168, v12
	v_fmamk_f32 v12, v10, 0xa7c234c4, v12
	v_cvt_i32_f32_e32 v10, v10
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v16, v[0:1], off offset:4
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr13
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v19, 0
	v_and_or_b32 v13, v15, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xfe5163ab, v13, 0
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v13, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v18, v21 :: v_dual_add_nc_u32 v21, 0xffffff88, v11
	v_mad_u64_u32 v[23:24], null, 0xdb629599, v13, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v27, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v24 :: v_dual_cndmask_b32 v17, v23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v21, v27, v21
	v_mad_u64_u32 v[24:25], null, 0xf534ddc0, v13, v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v21
	v_mov_b32_e32 v18, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v24, v20, vcc_lo
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[25:26], null, 0xfc2757d1, v13, v[18:19]
	v_cndmask_b32_e64 v17, v20, v17, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v18, v26 :: v_dual_add_nc_u32 v21, v28, v21
	v_cmp_lt_u32_e64 s3, 31, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, 0x4e441529, v13, v[18:19]
	v_mov_b32_e32 v18, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[27:28], null, 0xa2f9836e, v13, v[18:19]
	v_cndmask_b32_e64 v13, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v26, v24 :: v_dual_add_nc_u32 v13, v13, v21
	v_dual_cndmask_b32 v19, v27, v25 :: v_dual_cndmask_b32 v26, v28, v26
	v_cndmask_b32_e32 v25, v25, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v24, 32, v13
	v_cndmask_b32_e64 v21, v19, v18, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v26, v19, s2
	v_cndmask_b32_e64 v18, v18, v25, s2
	v_cndmask_b32_e64 v25, v25, v20, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v19, v21, s3
	v_cndmask_b32_e64 v21, v21, v18, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v25, s3
	v_cndmask_b32_e64 v17, v25, v17, s3
	v_alignbit_b32 v26, v19, v21, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v21, v18, v24
	v_alignbit_b32 v24, v18, v17, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, v26, v19, vcc_lo
	v_dual_cndmask_b32 v19, v23, v21 :: v_dual_cndmask_b32 v18, v24, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v20, v13, 29, 1
	v_alignbit_b32 v21, v13, v19, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v18, v17, 30
	v_sub_nc_u32_e32 v23, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v21, v21, v23
	v_xor_b32_e32 v17, v17, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v24, v21
	v_min_u32_e32 v24, 32, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v26, 23, v24
	v_alignbit_b32 v19, v19, v18, 30
	v_xor_b32_e32 v18, v19, v23
	v_sub_nc_u32_e32 v19, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v21, v18, v19
	v_alignbit_b32 v17, v18, v17, v19
	v_lshrrev_b32_e32 v19, 29, v13
	v_alignbit_b32 v18, v21, v17, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v19, 31, v19
	v_lshrrev_b32_e32 v21, 9, v21
	v_clz_i32_u32_e32 v23, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v25, 0.5, v19
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v25, v25, v26
	v_sub_nc_u32_e32 v27, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v18, v17, v27
	v_or_b32_e32 v18, v21, v25
	v_add_lshl_u32 v21, v23, v24, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v17, 9, v17
	v_mul_f32_e32 v23, 0x3fc90fda, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v21
	v_fma_f32 v21, 0x3fc90fda, v18, -v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v17, 0x33000000, v17
	v_fmamk_f32 v18, v18, 0x33a22168, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v17, v17, v19
	v_fmac_f32_e32 v18, 0x3fc90fda, v17
	v_lshrrev_b32_e32 v17, 30, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v23, v18
	v_add_nc_u32_e32 v19, v20, v17
.LBB1_7:                                ; %Flow701
	s_and_not1_saveexec_b32 s2, s10
; %bb.8:
	v_rndne_f32_e32 v17, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0xbfc90fda, v17, |v14|
	v_cvt_i32_f32_e32 v19, v17
	v_fmamk_f32 v13, v17, 0xb3a22168, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v13, v17, 0xa7c234c4, v13
; %bb.9:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v17, v[0:1], off offset:8
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr21
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_11
; %bb.10:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v18, v15, s2, 0x800000
	v_mad_u64_u32 v[20:21], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v23, v21
	v_add_nc_u32_e32 v21, 0xffffff88, v11
	v_mad_u64_u32 v[25:26], null, 0x3c439041, v18, v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v30, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v23, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, 0xdb629599, v18, v[23:24]
	v_cndmask_b32_e32 v20, v26, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v21, v30, v21
	v_mov_b32_e32 v23, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v21
	v_mad_u64_u32 v[27:28], null, 0xf534ddc0, v18, v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v31, 0, 0xffffffe0, s2
	v_add_nc_u32_e32 v21, v31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v23, v28
	v_cmp_lt_u32_e64 s3, 31, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, 0xfc2757d1, v18, v[23:24]
	v_mov_b32_e32 v23, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, 0x4e441529, v18, v[23:24]
	v_mov_b32_e32 v23, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[30:31], null, 0xa2f9836e, v18, v[23:24]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v23, v29, v27 :: v_dual_add_nc_u32 v18, v18, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v24, v30, v28 :: v_dual_cndmask_b32 v29, v31, v29
	v_dual_cndmask_b32 v28, v28, v26 :: v_dual_cndmask_b32 v21, v27, v25
	v_sub_nc_u32_e32 v27, 32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v24, v23, s2
	v_cndmask_b32_e64 v24, v29, v24, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v28, s2
	v_cndmask_b32_e64 v28, v28, v21, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v20, v21, v20, s2
	v_cndmask_b32_e64 v24, v24, v25, s3
	v_cndmask_b32_e64 v25, v25, v23, s3
	v_cndmask_b32_e64 v23, v23, v28, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v28, v20, s3
	v_alignbit_b32 v29, v24, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v26, v25, v23, v27
	v_alignbit_b32 v27, v23, v20, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v18, v29, v24 :: v_dual_cndmask_b32 v21, v26, v25
	v_cndmask_b32_e32 v23, v27, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v24, v18, 29, 1
	v_alignbit_b32 v25, v18, v21, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v21, v21, v23, 30
	v_alignbit_b32 v20, v23, v20, 30
	v_sub_nc_u32_e32 v26, 0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v25, v25, v26
	v_xor_b32_e32 v21, v21, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v20, v20, v26
	v_clz_i32_u32_e32 v27, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v27, 32, v27
	v_sub_nc_u32_e32 v23, 31, v27
	v_lshlrev_b32_e32 v29, 23, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v25, v25, v21, v23
	v_alignbit_b32 v20, v21, v20, v23
	v_lshrrev_b32_e32 v23, 29, v18
	v_lshrrev_b32_e32 v18, 30, v18
	v_alignbit_b32 v21, v25, v20, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v23, 31, v23
	v_add_nc_u32_e32 v24, v24, v18
	v_lshrrev_b32_e32 v25, 9, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_clz_i32_u32_e32 v26, v21
	v_or_b32_e32 v28, 0.5, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v26, 32, v26
	v_sub_nc_u32_e32 v28, v28, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v30, 31, v26
	v_alignbit_b32 v20, v21, v20, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v21, v25, v28
	v_add_lshl_u32 v25, v26, v27, 23
	v_lshrrev_b32_e32 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, 0x3fc90fda, v21
	v_sub_nc_u32_e32 v20, v20, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, 0x3fc90fda, v21, -v26
	v_add_nc_u32_e32 v20, 0x33000000, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v21, v21, 0x33a22168, v25
	v_or_b32_e32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, 0x3fc90fda, v20
	v_add_f32_e32 v21, v26, v21
.LBB1_11:                               ; %Flow700
	s_and_not1_saveexec_b32 s2, s10
; %bb.12:
	v_rndne_f32_e32 v18, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0xbfc90fda, v18, |v14|
	v_cvt_i32_f32_e32 v24, v18
	v_fmamk_f32 v20, v18, 0xb3a22168, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v21, v18, 0xa7c234c4, v20
; %bb.13:                               ; %_ZL3cosf.exit219
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v18, v[0:1], off offset:12
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr25
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_15
; %bb.14:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v27, 0
	v_and_or_b32 v20, v15, s2, 0x800000
	v_add_nc_u32_e32 v23, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[25:26], null, 0xfe5163ab, v20, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_cndmask_b32_e64 v33, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[28:29], null, 0x3c439041, v20, v[26:27]
	v_add_nc_u32_e32 v23, v33, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v26, v29
	v_cmp_lt_u32_e64 s2, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0xdb629599, v20, v[26:27]
	v_cndmask_b32_e64 v34, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v23, v34, v23
	v_dual_mov_b32 v26, v30 :: v_dual_cndmask_b32 v25, v29, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v23
	v_mad_u64_u32 v[30:31], null, 0xf534ddc0, v20, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v26, v31
	v_mad_u64_u32 v[31:32], null, 0xfc2757d1, v20, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v26, v32
	v_mad_u64_u32 v[32:33], null, 0x4e441529, v20, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v26, v33
	v_mad_u64_u32 v[33:34], null, 0xa2f9836e, v20, v[26:27]
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v32, v30, vcc_lo
	v_dual_cndmask_b32 v23, v30, v28 :: v_dual_add_nc_u32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v27, v33, v31 :: v_dual_cndmask_b32 v32, v34, v32
	v_cndmask_b32_e32 v31, v31, v29, vcc_lo
	v_sub_nc_u32_e32 v30, 32, v20
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v28, v27, v26, s2
	v_cndmask_b32_e64 v27, v32, v27, s2
	v_cndmask_b32_e64 v26, v26, v31, s2
	v_cndmask_b32_e64 v31, v31, v23, s2
	v_cndmask_b32_e64 v23, v23, v25, s2
	v_cndmask_b32_e64 v27, v27, v28, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v28, v28, v26, s3
	v_cndmask_b32_e64 v26, v26, v31, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, v31, v23, s3
	v_alignbit_b32 v32, v27, v28, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v28, v26, v30
	v_alignbit_b32 v30, v26, v23, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v20, v32, v27 :: v_dual_cndmask_b32 v25, v29, v28
	v_cndmask_b32_e32 v26, v30, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v27, v20, 29, 1
	v_alignbit_b32 v28, v20, v25, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v25, v25, v26, 30
	v_alignbit_b32 v23, v26, v23, 30
	v_sub_nc_u32_e32 v29, 0, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v28, v28, v29
	v_xor_b32_e32 v25, v25, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v23, v23, v29
	v_clz_i32_u32_e32 v30, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v30, 32, v30
	v_sub_nc_u32_e32 v26, 31, v30
	v_lshlrev_b32_e32 v32, 23, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v28, v28, v25, v26
	v_alignbit_b32 v23, v25, v23, v26
	v_lshrrev_b32_e32 v26, 29, v20
	v_lshrrev_b32_e32 v20, 30, v20
	v_alignbit_b32 v25, v28, v23, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v26, 31, v26
	v_lshrrev_b32_e32 v28, 9, v28
	v_clz_i32_u32_e32 v29, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v31, 0.5, v26
	v_min_u32_e32 v29, 32, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v31, v31, v32
	v_sub_nc_u32_e32 v33, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v25, v23, v33
	v_or_b32_e32 v25, v28, v31
	v_add_lshl_u32 v28, v29, v30, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v23, 9, v23
	v_mul_f32_e32 v29, 0x3fc90fda, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v23, v23, v28
	v_fma_f32 v28, 0x3fc90fda, v25, -v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v23, 0x33000000, v23
	v_fmamk_f32 v25, v25, 0x33a22168, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v23, v23, v26
	v_dual_fmac_f32 v25, 0x3fc90fda, v23 :: v_dual_add_nc_u32 v26, v27, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v25, v29, v25
.LBB1_15:                               ; %Flow699
	s_and_not1_saveexec_b32 s2, s10
; %bb.16:
	v_rndne_f32_e32 v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v23, 0xbfc90fda, v20, |v14|
	v_cvt_i32_f32_e32 v26, v20
	v_fmamk_f32 v23, v20, 0xb3a22168, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v25, v20, 0xa7c234c4, v23
; %bb.17:                               ; %_ZL3sinf.exit227
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v20, v[0:1], off offset:16
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr27
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_19
; %bb.18:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v29, 0
	v_and_or_b32 v23, v15, s2, 0x800000
	v_add_nc_u32_e32 v35, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, 0xfe5163ab, v23, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v35
	v_cndmask_b32_e64 v36, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0x3c439041, v23, v[28:29]
	v_add_nc_u32_e32 v36, v36, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v28, v31
	v_cmp_lt_u32_e64 s2, 31, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0xdb629599, v23, v[28:29]
	v_cndmask_b32_e64 v37, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v28, v32 :: v_dual_add_nc_u32 v37, v37, v36
	v_cndmask_b32_e32 v27, v31, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v37
	v_mad_u64_u32 v[32:33], null, 0xf534ddc0, v23, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v28, v33
	v_cndmask_b32_e32 v30, v32, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[33:34], null, 0xfc2757d1, v23, v[28:29]
	v_mov_b32_e32 v28, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[34:35], null, 0x4e441529, v23, v[28:29]
	v_mov_b32_e32 v28, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[35:36], null, 0xa2f9836e, v23, v[28:29]
	v_cndmask_b32_e64 v23, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v28, v34, v32 :: v_dual_add_nc_u32 v23, v23, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v29, v35, v33 :: v_dual_cndmask_b32 v34, v36, v34
	v_cndmask_b32_e32 v33, v33, v31, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v29, v28, s2
	v_cndmask_b32_e64 v29, v34, v29, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v28, v28, v33, s2
	v_sub_nc_u32_e32 v34, 32, v23
	v_cndmask_b32_e64 v33, v33, v30, s2
	v_cndmask_b32_e64 v29, v29, v32, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v32, v28, s3
	v_cndmask_b32_e64 v28, v28, v33, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v35, v29, v32, v34
	v_alignbit_b32 v31, v32, v28, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v35, v29, vcc_lo
	v_cndmask_b32_e32 v29, v31, v32, vcc_lo
	v_cndmask_b32_e64 v27, v30, v27, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v30, v23, 29, 1
	v_alignbit_b32 v31, v23, v29, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, v33, v27, s3
	v_sub_nc_u32_e32 v32, 0, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v33, v28, v27, v34
	v_xor_b32_e32 v31, v31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v28, v33, v28, vcc_lo
	v_clz_i32_u32_e32 v33, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v29, v28, 30
	v_alignbit_b32 v27, v28, v27, 30
	v_min_u32_e32 v33, 32, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v28, v29, v32
	v_xor_b32_e32 v27, v27, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v29, 31, v33
	v_lshlrev_b32_e32 v35, 23, v33
	v_alignbit_b32 v31, v31, v28, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v28, v27, v29
	v_lshrrev_b32_e32 v29, 29, v23
	v_lshrrev_b32_e32 v23, 30, v23
	v_alignbit_b32 v28, v31, v27, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v29, 31, v29
	v_lshrrev_b32_e32 v31, 9, v31
	v_clz_i32_u32_e32 v32, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v34, 0.5, v29
	v_min_u32_e32 v32, 32, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, v34, v35
	v_sub_nc_u32_e32 v36, 31, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v28, v27, v36
	v_or_b32_e32 v28, v31, v34
	v_add_lshl_u32 v31, v32, v33, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v27, 9, v27
	v_mul_f32_e32 v32, 0x3fc90fda, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v27, v27, v31
	v_fma_f32 v31, 0x3fc90fda, v28, -v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v27, 0x33000000, v27
	v_fmamk_f32 v28, v28, 0x33a22168, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v27, v27, v29
	v_add_nc_u32_e32 v29, v30, v23
	v_fmac_f32_e32 v28, 0x3fc90fda, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v27, v32, v28
.LBB1_19:                               ; %Flow698
	s_and_not1_saveexec_b32 s2, s10
; %bb.20:
	v_rndne_f32_e32 v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v27, 0xbfc90fda, v23, |v14|
	v_cvt_i32_f32_e32 v29, v23
	v_fmamk_f32 v27, v23, 0xb3a22168, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v27, v23, 0xa7c234c4, v27
; %bb.21:                               ; %_ZL3cosf.exit233
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v23, v[0:1], off offset:20
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr28
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_23
; %bb.22:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v32, 0
	v_and_or_b32 v28, v15, s2, 0x800000
	v_add_nc_u32_e32 v38, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xfe5163ab, v28, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v38
	v_cndmask_b32_e64 v39, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0x3c439041, v28, v[31:32]
	v_add_nc_u32_e32 v39, v39, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v31, v34
	v_cmp_lt_u32_e64 s2, 31, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0xdb629599, v28, v[31:32]
	v_cndmask_b32_e64 v40, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v31, v35 :: v_dual_add_nc_u32 v40, v40, v39
	v_cndmask_b32_e32 v30, v34, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v40
	v_mad_u64_u32 v[35:36], null, 0xf534ddc0, v28, v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v31, v36
	v_cndmask_b32_e32 v33, v35, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[36:37], null, 0xfc2757d1, v28, v[31:32]
	v_mov_b32_e32 v31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[37:38], null, 0x4e441529, v28, v[31:32]
	v_mov_b32_e32 v31, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[38:39], null, 0xa2f9836e, v28, v[31:32]
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v31, v37, v35 :: v_dual_add_nc_u32 v28, v28, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v32, v38, v36 :: v_dual_cndmask_b32 v37, v39, v37
	v_cndmask_b32_e32 v36, v36, v34, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v32, v31, s2
	v_cndmask_b32_e64 v32, v37, v32, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v36, s2
	v_sub_nc_u32_e32 v37, 32, v28
	v_cndmask_b32_e64 v36, v36, v33, s2
	v_cndmask_b32_e64 v32, v32, v35, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, v35, v31, s3
	v_cndmask_b32_e64 v31, v31, v36, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v38, v32, v35, v37
	v_alignbit_b32 v34, v35, v31, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v28, v38, v32, vcc_lo
	v_cndmask_b32_e32 v32, v34, v35, vcc_lo
	v_cndmask_b32_e64 v30, v33, v30, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v33, v28, 29, 1
	v_alignbit_b32 v34, v28, v32, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v36, v30, s3
	v_sub_nc_u32_e32 v35, 0, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v36, v31, v30, v37
	v_xor_b32_e32 v34, v34, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v31, v36, v31, vcc_lo
	v_clz_i32_u32_e32 v36, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v32, v31, 30
	v_alignbit_b32 v30, v31, v30, 30
	v_min_u32_e32 v36, 32, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v31, v32, v35
	v_xor_b32_e32 v30, v30, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, 31, v36
	v_lshlrev_b32_e32 v38, 23, v36
	v_alignbit_b32 v34, v34, v31, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v30, v31, v30, v32
	v_lshrrev_b32_e32 v32, 29, v28
	v_alignbit_b32 v31, v34, v30, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v32, 31, v32
	v_lshrrev_b32_e32 v34, 9, v34
	v_clz_i32_u32_e32 v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v37, 0.5, v32
	v_min_u32_e32 v35, 32, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v37, v37, v38
	v_sub_nc_u32_e32 v39, 31, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v31, v30, v39
	v_or_b32_e32 v31, v34, v37
	v_add_lshl_u32 v34, v35, v36, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v30, 9, v30
	v_mul_f32_e32 v35, 0x3fc90fda, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v30, v30, v34
	v_fma_f32 v34, 0x3fc90fda, v31, -v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v30, 0x33000000, v30
	v_fmamk_f32 v31, v31, 0x33a22168, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v30, v30, v32
	v_fmac_f32_e32 v31, 0x3fc90fda, v30
	v_lshrrev_b32_e32 v30, 30, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v28, v35, v31
	v_add_nc_u32_e32 v32, v33, v30
.LBB1_23:                               ; %Flow697
	s_and_not1_saveexec_b32 s2, s10
; %bb.24:
	v_rndne_f32_e32 v30, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v28, 0xbfc90fda, v30, |v14|
	v_cvt_i32_f32_e32 v32, v30
	v_fmamk_f32 v28, v30, 0xb3a22168, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v28, v30, 0xa7c234c4, v28
; %bb.25:                               ; %_ZL3sinf.exit241
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr30
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_27
; %bb.26:
	s_mov_b32 s2, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v42, v15, s2, 0x800000
	v_mad_u64_u32 v[30:31], null, 0xfe5163ab, v42, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v33, v31
	v_add_nc_u32_e32 v31, 0xffffff88, v11
	v_mad_u64_u32 v[35:36], null, 0x3c439041, v42, v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v31
	v_cndmask_b32_e64 v40, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v33, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v31, v40, v31
	v_mad_u64_u32 v[36:37], null, 0xdb629599, v42, v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s2, 31, v31
	v_mov_b32_e32 v33, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v41, 0, 0xffffffe0, s2
	v_cndmask_b32_e32 v30, v36, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[37:38], null, 0xf534ddc0, v42, v[33:34]
	v_add_nc_u32_e32 v31, v41, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v31
	v_mov_b32_e32 v33, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[38:39], null, 0xfc2757d1, v42, v[33:34]
	v_mov_b32_e32 v33, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[39:40], null, 0x4e441529, v42, v[33:34]
	v_mov_b32_e32 v33, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[40:41], null, 0xa2f9836e, v42, v[33:34]
	v_cndmask_b32_e64 v33, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v34, v39, v37 :: v_dual_add_nc_u32 v31, v33, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v40, v40, v38 :: v_dual_cndmask_b32 v39, v41, v39
	v_dual_cndmask_b32 v38, v38, v36 :: v_dual_cndmask_b32 v33, v37, v35
	v_cmp_eq_u32_e32 vcc_lo, 0, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v40, v34, s2
	v_cndmask_b32_e64 v37, v39, v40, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v38, s2
	v_sub_nc_u32_e32 v39, 32, v31
	v_cndmask_b32_e64 v38, v38, v33, s2
	v_cndmask_b32_e64 v30, v33, v30, s2
	v_cndmask_b32_e64 v37, v37, v35, s3
	v_cndmask_b32_e64 v35, v35, v34, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v38, s3
	v_cndmask_b32_e64 v30, v38, v30, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v37, v35, v39
	v_alignbit_b32 v36, v35, v34, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v34, v30, v39
	v_cndmask_b32_e32 v31, v40, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v33, v36, v35 :: v_dual_cndmask_b32 v34, v38, v34
	v_bfe_u32 v35, v31, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v31, v33, 30
	v_alignbit_b32 v33, v33, v34, 30
	v_alignbit_b32 v30, v34, v30, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v37, 0, v35
	v_xor_b32_e32 v36, v36, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v33, v33, v37
	v_xor_b32_e32 v30, v30, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v38, v36
	v_min_u32_e32 v38, 32, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, 31, v38
	v_lshlrev_b32_e32 v40, 23, v38
	v_alignbit_b32 v36, v36, v33, v34
	v_alignbit_b32 v30, v33, v30, v34
	v_lshrrev_b32_e32 v34, 29, v31
	v_lshrrev_b32_e32 v31, 30, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v36, v30, 9
	v_lshlrev_b32_e32 v34, 31, v34
	v_lshrrev_b32_e32 v36, 9, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v31, v35, v31
	v_clz_i32_u32_e32 v37, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v39, 0.5, v34
	v_min_u32_e32 v37, 32, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v39, v39, v40
	v_sub_nc_u32_e32 v41, 31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v33, v30, v41
	v_or_b32_e32 v33, v36, v39
	v_add_lshl_u32 v36, v37, v38, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v30, 9, v30
	v_mul_f32_e32 v37, 0x3fc90fda, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v30, v30, v36
	v_fma_f32 v36, 0x3fc90fda, v33, -v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v30, 0x33000000, v30
	v_fmamk_f32 v33, v33, 0x33a22168, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v30, v30, v34
	v_fmac_f32_e32 v33, 0x3fc90fda, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v30, v37, v33
.LBB1_27:                               ; %Flow696
	s_and_not1_saveexec_b32 s2, s10
; %bb.28:
	v_rndne_f32_e32 v31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, 0xbfc90fda, v31, |v14|
	v_fmamk_f32 v30, v31, 0xb3a22168, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v30, v31, 0xa7c234c4, v30
	v_cvt_i32_f32_e32 v31, v31
; %bb.29:                               ; %_ZL3sinf.exit249
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr33
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_31
; %bb.30:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v35, 0
	v_and_or_b32 v43, v15, s2, 0x800000
	v_add_nc_u32_e32 v41, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0xfe5163ab, v43, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v41
	v_cndmask_b32_e64 v42, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, 0x3c439041, v43, v[34:35]
	v_add_nc_u32_e32 v42, v42, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v34, v37
	v_cmp_lt_u32_e64 s2, 31, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, 0xdb629599, v43, v[34:35]
	v_cndmask_b32_e64 v44, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v33, v37, v33 :: v_dual_add_nc_u32 v44, v44, v42
	v_mov_b32_e32 v34, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v44
	v_mad_u64_u32 v[38:39], null, 0xf534ddc0, v43, v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v34, v39
	v_cndmask_b32_e32 v36, v38, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0xfc2757d1, v43, v[34:35]
	v_cndmask_b32_e64 v33, v36, v33, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v34, v40
	v_mad_u64_u32 v[40:41], null, 0x4e441529, v43, v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v34, v41
	v_mad_u64_u32 v[41:42], null, 0xa2f9836e, v43, v[34:35]
	v_cndmask_b32_e64 v34, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v35, v40, v38 :: v_dual_add_nc_u32 v34, v34, v44
	v_dual_cndmask_b32 v41, v41, v39 :: v_dual_cndmask_b32 v40, v42, v40
	v_cndmask_b32_e32 v39, v39, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v38, v41, v35, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v40, v40, v41, s2
	v_cndmask_b32_e64 v35, v35, v39, s2
	v_sub_nc_u32_e32 v41, 32, v34
	v_cndmask_b32_e64 v39, v39, v36, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v40, v40, v38, s3
	v_cndmask_b32_e64 v38, v38, v35, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, v35, v39, s3
	v_cndmask_b32_e64 v33, v39, v33, s3
	v_alignbit_b32 v42, v40, v38, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v37, v38, v35, v41
	v_cndmask_b32_e32 v34, v42, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v35, v33, v41
	v_cndmask_b32_e32 v36, v37, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v37, v34, 29, 1
	v_cndmask_b32_e32 v35, v40, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v34, v36, 30
	v_sub_nc_u32_e32 v39, 0, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v36, v35, 30
	v_alignbit_b32 v33, v35, v33, 30
	v_xor_b32_e32 v38, v38, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v35, v36, v39
	v_xor_b32_e32 v33, v33, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v40, v38
	v_min_u32_e32 v40, 32, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v36, 31, v40
	v_lshlrev_b32_e32 v42, 23, v40
	v_alignbit_b32 v38, v38, v35, v36
	v_alignbit_b32 v33, v35, v33, v36
	v_lshrrev_b32_e32 v36, 29, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v35, v38, v33, 9
	v_lshlrev_b32_e32 v36, 31, v36
	v_lshrrev_b32_e32 v38, 9, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v39, v35
	v_or_b32_e32 v41, 0.5, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v39, 32, v39
	v_sub_nc_u32_e32 v41, v41, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v43, 31, v39
	v_alignbit_b32 v33, v35, v33, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v35, v38, v41
	v_add_lshl_u32 v38, v39, v40, 23
	v_lshrrev_b32_e32 v33, 9, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v39, 0x3fc90fda, v35
	v_sub_nc_u32_e32 v33, v33, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, 0x3fc90fda, v35, -v39
	v_add_nc_u32_e32 v33, 0x33000000, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v35, v35, 0x33a22168, v38
	v_or_b32_e32 v33, v33, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, 0x3fc90fda, v33
	v_lshrrev_b32_e32 v34, 30, v34
	v_dual_add_f32 v33, v39, v35 :: v_dual_add_nc_u32 v34, v37, v34
.LBB1_31:                               ; %Flow695
	s_and_not1_saveexec_b32 s2, s10
; %bb.32:
	v_rndne_f32_e32 v34, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v33, 0xbfc90fda, v34, |v14|
	v_fmamk_f32 v33, v34, 0xb3a22168, v33
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v33, v34, 0xa7c234c4, v33
	v_cvt_i32_f32_e32 v34, v34
; %bb.33:                               ; %_ZL3cosf.exit255
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr35
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_35
; %bb.34:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v37, 0
	v_and_or_b32 v45, v15, s2, 0x800000
	v_add_nc_u32_e32 v43, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0xfe5163ab, v45, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v43
	v_cndmask_b32_e64 v44, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, 0x3c439041, v45, v[36:37]
	v_add_nc_u32_e32 v44, v44, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v36, v39
	v_cmp_lt_u32_e64 s2, 31, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0xdb629599, v45, v[36:37]
	v_cndmask_b32_e64 v46, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v35, v39, v35 :: v_dual_add_nc_u32 v46, v46, v44
	v_mov_b32_e32 v36, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v46
	v_mad_u64_u32 v[40:41], null, 0xf534ddc0, v45, v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v36, v41
	v_cndmask_b32_e32 v38, v40, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[41:42], null, 0xfc2757d1, v45, v[36:37]
	v_cndmask_b32_e64 v35, v38, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v36, v42
	v_mad_u64_u32 v[42:43], null, 0x4e441529, v45, v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v36, v43
	v_mad_u64_u32 v[43:44], null, 0xa2f9836e, v45, v[36:37]
	v_cndmask_b32_e64 v36, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v37, v42, v40 :: v_dual_add_nc_u32 v36, v36, v46
	v_dual_cndmask_b32 v43, v43, v41 :: v_dual_cndmask_b32 v42, v44, v42
	v_cndmask_b32_e32 v41, v41, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e64 v40, v43, v37, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v42, v42, v43, s2
	v_cndmask_b32_e64 v37, v37, v41, s2
	v_sub_nc_u32_e32 v43, 32, v36
	v_cndmask_b32_e64 v41, v41, v38, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v42, v42, v40, s3
	v_cndmask_b32_e64 v40, v40, v37, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, v37, v41, s3
	v_cndmask_b32_e64 v35, v41, v35, s3
	v_alignbit_b32 v44, v42, v40, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v39, v40, v37, v43
	v_cndmask_b32_e32 v36, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v37, v35, v43
	v_cndmask_b32_e32 v38, v39, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v39, v36, 29, 1
	v_cndmask_b32_e32 v37, v42, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v36, v38, 30
	v_sub_nc_u32_e32 v41, 0, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v38, v37, 30
	v_alignbit_b32 v35, v37, v35, 30
	v_xor_b32_e32 v40, v40, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v37, v38, v41
	v_xor_b32_e32 v35, v35, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v42, v40
	v_min_u32_e32 v42, 32, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v38, 31, v42
	v_lshlrev_b32_e32 v44, 23, v42
	v_alignbit_b32 v40, v40, v37, v38
	v_alignbit_b32 v35, v37, v35, v38
	v_lshrrev_b32_e32 v38, 29, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v37, v40, v35, 9
	v_lshlrev_b32_e32 v38, 31, v38
	v_lshrrev_b32_e32 v40, 9, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v41, v37
	v_or_b32_e32 v43, 0.5, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v41, 32, v41
	v_sub_nc_u32_e32 v43, v43, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v45, 31, v41
	v_alignbit_b32 v35, v37, v35, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v37, v40, v43
	v_add_lshl_u32 v40, v41, v42, 23
	v_lshrrev_b32_e32 v35, 9, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v41, 0x3fc90fda, v37
	v_sub_nc_u32_e32 v35, v35, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v40, 0x3fc90fda, v37, -v41
	v_add_nc_u32_e32 v35, 0x33000000, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v37, v37, 0x33a22168, v40
	v_or_b32_e32 v35, v35, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, 0x3fc90fda, v35
	v_lshrrev_b32_e32 v36, 30, v36
	v_dual_add_f32 v35, v41, v37 :: v_dual_add_nc_u32 v36, v39, v36
.LBB1_35:                               ; %Flow694
	s_and_not1_saveexec_b32 s2, s10
; %bb.36:
	v_rndne_f32_e32 v36, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, 0xbfc90fda, v36, |v14|
	v_fmamk_f32 v35, v36, 0xb3a22168, v35
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v35, v36, 0xa7c234c4, v35
	v_cvt_i32_f32_e32 v36, v36
; %bb.37:                               ; %_ZL3sinf.exit263
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr38
                                        ; implicit-def: $vgpr37
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_39
; %bb.38:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v39, 0
	v_and_or_b32 v47, v15, s2, 0x800000
	v_add_nc_u32_e32 v45, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, 0xfe5163ab, v47, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v45
	v_cndmask_b32_e64 v46, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[40:41], null, 0x3c439041, v47, v[38:39]
	v_add_nc_u32_e32 v46, v46, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v38, v41
	v_cmp_lt_u32_e64 s2, 31, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[41:42], null, 0xdb629599, v47, v[38:39]
	v_cndmask_b32_e64 v48, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v37, v41, v37 :: v_dual_add_nc_u32 v48, v48, v46
	v_mov_b32_e32 v38, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v48
	v_mad_u64_u32 v[42:43], null, 0xf534ddc0, v47, v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v38, v43
	v_cndmask_b32_e32 v40, v42, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[43:44], null, 0xfc2757d1, v47, v[38:39]
	v_cndmask_b32_e64 v37, v40, v37, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v38, v44
	v_mad_u64_u32 v[44:45], null, 0x4e441529, v47, v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v38, v45
	v_mad_u64_u32 v[45:46], null, 0xa2f9836e, v47, v[38:39]
	v_cndmask_b32_e64 v38, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v39, v44, v42 :: v_dual_add_nc_u32 v38, v38, v48
	v_dual_cndmask_b32 v45, v45, v43 :: v_dual_cndmask_b32 v44, v46, v44
	v_cndmask_b32_e32 v43, v43, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v38
	v_cndmask_b32_e64 v42, v45, v39, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v44, v44, v45, s2
	v_cndmask_b32_e64 v39, v39, v43, s2
	v_sub_nc_u32_e32 v45, 32, v38
	v_cndmask_b32_e64 v43, v43, v40, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v44, v44, v42, s3
	v_cndmask_b32_e64 v42, v42, v39, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v39, v39, v43, s3
	v_cndmask_b32_e64 v37, v43, v37, s3
	v_alignbit_b32 v46, v44, v42, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v41, v42, v39, v45
	v_cndmask_b32_e32 v38, v46, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v39, v37, v45
	v_cndmask_b32_e32 v40, v41, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v41, v38, 29, 1
	v_cndmask_b32_e32 v39, v44, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v38, v40, 30
	v_sub_nc_u32_e32 v43, 0, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v40, v39, 30
	v_alignbit_b32 v37, v39, v37, 30
	v_xor_b32_e32 v42, v42, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v39, v40, v43
	v_xor_b32_e32 v37, v37, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v44, v42
	v_min_u32_e32 v44, 32, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v40, 31, v44
	v_lshlrev_b32_e32 v46, 23, v44
	v_alignbit_b32 v42, v42, v39, v40
	v_alignbit_b32 v37, v39, v37, v40
	v_lshrrev_b32_e32 v40, 29, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v39, v42, v37, 9
	v_lshlrev_b32_e32 v40, 31, v40
	v_lshrrev_b32_e32 v42, 9, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v43, v39
	v_or_b32_e32 v45, 0.5, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v43, 32, v43
	v_sub_nc_u32_e32 v45, v45, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v47, 31, v43
	v_alignbit_b32 v37, v39, v37, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v39, v42, v45
	v_add_lshl_u32 v42, v43, v44, 23
	v_lshrrev_b32_e32 v37, 9, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v43, 0x3fc90fda, v39
	v_sub_nc_u32_e32 v37, v37, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v42, 0x3fc90fda, v39, -v43
	v_add_nc_u32_e32 v37, 0x33000000, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v39, v39, 0x33a22168, v42
	v_or_b32_e32 v37, v37, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, 0x3fc90fda, v37
	v_lshrrev_b32_e32 v38, 30, v38
	v_dual_add_f32 v37, v43, v39 :: v_dual_add_nc_u32 v38, v41, v38
.LBB1_39:                               ; %Flow693
	s_and_not1_saveexec_b32 s2, s10
; %bb.40:
	v_rndne_f32_e32 v38, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, 0xbfc90fda, v38, |v14|
	v_fmamk_f32 v37, v38, 0xb3a22168, v37
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v37, v38, 0xa7c234c4, v37
	v_cvt_i32_f32_e32 v38, v38
; %bb.41:                               ; %_ZL3cosf.exit269
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr40
                                        ; implicit-def: $vgpr39
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s10, exec_lo, s2
	s_cbranch_execz .LBB1_43
; %bb.42:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v41, 0
	v_and_or_b32 v49, v15, s2, 0x800000
	v_add_nc_u32_e32 v47, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0xfe5163ab, v49, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v47
	v_cndmask_b32_e64 v48, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[42:43], null, 0x3c439041, v49, v[40:41]
	v_add_nc_u32_e32 v48, v48, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v40, v43
	v_cmp_lt_u32_e64 s2, 31, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[43:44], null, 0xdb629599, v49, v[40:41]
	v_cndmask_b32_e64 v50, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v39, v43, v39 :: v_dual_add_nc_u32 v50, v50, v48
	v_mov_b32_e32 v40, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v50
	v_mad_u64_u32 v[44:45], null, 0xf534ddc0, v49, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v40, v45
	v_cndmask_b32_e32 v42, v44, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[45:46], null, 0xfc2757d1, v49, v[40:41]
	v_cndmask_b32_e64 v39, v42, v39, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v46
	v_mad_u64_u32 v[46:47], null, 0x4e441529, v49, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v40, v47
	v_mad_u64_u32 v[47:48], null, 0xa2f9836e, v49, v[40:41]
	v_cndmask_b32_e64 v40, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v41, v46, v44 :: v_dual_add_nc_u32 v40, v40, v50
	v_dual_cndmask_b32 v47, v47, v45 :: v_dual_cndmask_b32 v46, v48, v46
	v_cndmask_b32_e32 v45, v45, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v40
	v_cndmask_b32_e64 v44, v47, v41, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v46, v46, v47, s2
	v_cndmask_b32_e64 v41, v41, v45, s2
	v_sub_nc_u32_e32 v47, 32, v40
	v_cndmask_b32_e64 v45, v45, v42, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v46, v46, v44, s3
	v_cndmask_b32_e64 v44, v44, v41, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v41, v41, v45, s3
	v_cndmask_b32_e64 v39, v45, v39, s3
	v_alignbit_b32 v48, v46, v44, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v43, v44, v41, v47
	v_cndmask_b32_e32 v40, v48, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v46, v41, v39, v47
	v_cndmask_b32_e32 v42, v43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v43, v40, 29, 1
	v_cndmask_b32_e32 v41, v46, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v40, v42, 30
	v_sub_nc_u32_e32 v45, 0, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v42, v41, 30
	v_alignbit_b32 v39, v41, v39, 30
	v_xor_b32_e32 v44, v44, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v41, v42, v45
	v_xor_b32_e32 v39, v39, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v46, v44
	v_min_u32_e32 v46, 32, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v42, 31, v46
	v_lshlrev_b32_e32 v48, 23, v46
	v_alignbit_b32 v44, v44, v41, v42
	v_alignbit_b32 v39, v41, v39, v42
	v_lshrrev_b32_e32 v42, 29, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v41, v44, v39, 9
	v_lshlrev_b32_e32 v42, 31, v42
	v_lshrrev_b32_e32 v44, 9, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v45, v41
	v_or_b32_e32 v47, 0.5, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v45, 32, v45
	v_sub_nc_u32_e32 v47, v47, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v49, 31, v45
	v_alignbit_b32 v39, v41, v39, v49
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v41, v44, v47
	v_add_lshl_u32 v44, v45, v46, 23
	v_lshrrev_b32_e32 v39, 9, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v45, 0x3fc90fda, v41
	v_sub_nc_u32_e32 v39, v39, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, 0x3fc90fda, v41, -v45
	v_add_nc_u32_e32 v39, 0x33000000, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v41, v41, 0x33a22168, v44
	v_or_b32_e32 v39, v39, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v41, 0x3fc90fda, v39
	v_lshrrev_b32_e32 v40, 30, v40
	v_dual_add_f32 v39, v45, v41 :: v_dual_add_nc_u32 v40, v43, v40
.LBB1_43:                               ; %Flow692
	s_and_not1_saveexec_b32 s2, s10
; %bb.44:
	v_rndne_f32_e32 v40, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v39, 0xbfc90fda, v40, |v14|
	v_fmamk_f32 v39, v40, 0xb3a22168, v39
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v39, v40, 0xa7c234c4, v39
	v_cvt_i32_f32_e32 v40, v40
; %bb.45:                               ; %_ZL3sinf.exit277
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr42
                                        ; implicit-def: $vgpr41
	s_and_saveexec_b32 s2, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB1_47
; %bb.46:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v43, 0
	v_and_or_b32 v22, v15, s2, 0x800000
	v_add_nc_u32_e32 v11, 0xffffff88, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[41:42], null, 0xfe5163ab, v22, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_cndmask_b32_e64 v49, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[44:45], null, 0x3c439041, v22, v[42:43]
	v_add_nc_u32_e32 v11, v49, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v42, v45
	v_cmp_lt_u32_e64 s2, 31, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[45:46], null, 0xdb629599, v22, v[42:43]
	v_cndmask_b32_e64 v50, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v50, v11
	v_dual_mov_b32 v42, v46 :: v_dual_cndmask_b32 v41, v45, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v11
	v_mad_u64_u32 v[46:47], null, 0xf534ddc0, v22, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v42, v47
	v_mad_u64_u32 v[47:48], null, 0xfc2757d1, v22, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v42, v48
	v_mad_u64_u32 v[48:49], null, 0x4e441529, v22, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v42, v49
	v_mad_u64_u32 v[49:50], null, 0xa2f9836e, v22, v[42:43]
	v_cndmask_b32_e64 v22, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v42, v48, v46 :: v_dual_add_nc_u32 v11, v22, v11
	v_dual_cndmask_b32 v43, v49, v47 :: v_dual_cndmask_b32 v48, v50, v48
	v_dual_cndmask_b32 v47, v47, v45 :: v_dual_cndmask_b32 v22, v46, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v46, 32, v11
	v_cndmask_b32_e64 v44, v43, v42, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v43, v48, v43, s2
	v_cndmask_b32_e64 v42, v42, v47, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v43, v43, v44, s3
	v_cndmask_b32_e64 v44, v44, v42, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v48, v43, v44, v46
	v_cndmask_b32_e32 v11, v48, v43, vcc_lo
	v_cndmask_b32_e64 v47, v47, v22, s2
	v_cndmask_b32_e64 v22, v22, v41, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v43, v11, 29, 1
	v_cndmask_b32_e64 v42, v42, v47, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v22, v47, v22, s3
	v_alignbit_b32 v45, v44, v42, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v46, v42, v22, v46
	v_dual_cndmask_b32 v41, v45, v44 :: v_dual_cndmask_b32 v42, v46, v42
	v_sub_nc_u32_e32 v45, 0, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v11, v41, 30
	v_alignbit_b32 v41, v41, v42, 30
	v_alignbit_b32 v22, v42, v22, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v44, v44, v45
	v_xor_b32_e32 v41, v41, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v22, v22, v45
	v_clz_i32_u32_e32 v46, v44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v46, 32, v46
	v_sub_nc_u32_e32 v42, 31, v46
	v_lshlrev_b32_e32 v48, 23, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v44, v41, v42
	v_alignbit_b32 v22, v41, v22, v42
	v_lshrrev_b32_e32 v42, 29, v11
	v_lshrrev_b32_e32 v11, 30, v11
	v_alignbit_b32 v41, v44, v22, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v42, 31, v42
	v_lshrrev_b32_e32 v44, 9, v44
	v_clz_i32_u32_e32 v45, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v47, 0.5, v42
	v_min_u32_e32 v45, 32, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v47, v47, v48
	v_sub_nc_u32_e32 v49, 31, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v41, v22, v49
	v_or_b32_e32 v41, v44, v47
	v_add_lshl_u32 v44, v45, v46, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v22, 9, v22
	v_mul_f32_e32 v45, 0x3fc90fda, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v44
	v_fma_f32 v44, 0x3fc90fda, v41, -v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v22, 0x33000000, v22
	v_fmamk_f32 v41, v41, 0x33a22168, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v22, v22, v42
	v_dual_fmac_f32 v41, 0x3fc90fda, v22 :: v_dual_add_nc_u32 v42, v43, v11
                                        ; implicit-def: $vgpr22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v41, v45, v41
.LBB1_47:                               ; %Flow691
	s_and_not1_saveexec_b32 s2, s5
; %bb.48:
	v_rndne_f32_e32 v11, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0xbfc90fda, v11, |v14|
	v_cvt_i32_f32_e32 v42, v11
	v_fmamk_f32 v22, v11, 0xb3a22168, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v41, v11, 0xa7c234c4, v22
; %bb.49:                               ; %_ZL3cosf.exit283
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_lo_u32 v11, v5, s7
	v_mul_lo_u32 v22, v4, s6
	v_cvt_f32_i32_e32 v47, s7
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s17, 0x37d75334
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x28
	s_load_b64 s[10:11], s[0:1], 0x38
	s_mov_b32 s16, 0
	s_mov_b32 s5, exec_lo
	v_sub_nc_u32_e32 v4, v4, v11
	v_sub_nc_u32_e32 v11, v2, v22
	v_cvt_f32_i32_e32 v22, s6
	v_mul_f32_e32 v54, v25, v25
	v_mul_f32_e32 v56, v28, v28
	v_cvt_f32_i32_e32 v4, v4
	v_cvt_f32_i32_e32 v11, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v70, s3, v56, 0x3c0881c4
	v_div_scale_f32 v43, null, v47, v47, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v44, null, v22, v22, v11
	v_div_scale_f32 v50, vcc_lo, v4, v47, v4
	v_rcp_f32_e32 v45, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v46, v44
	s_waitcnt_depctr 0xfff
	v_fma_f32 v48, -v43, v45, 1.0
	v_fma_f32 v49, -v44, v46, 1.0
	v_dual_fmac_f32 v45, v48, v45 :: v_dual_fmac_f32 v46, v49, v46
	v_div_scale_f32 v48, s2, v11, v22, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v49, v50, v45
	v_mul_f32_e32 v51, v48, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v52, -v43, v49, v50
	v_fma_f32 v53, -v44, v51, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v49, v52, v45
	v_mul_f32_e32 v52, v13, v13
	v_fmac_f32_e32 v51, v53, v46
	v_and_b32_e32 v55, 1, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v43, -v43, v49, v50
	v_fmaak_f32 v66, s3, v52, 0x3c0881c4
	v_mul_f32_e32 v50, v12, v12
	v_fma_f32 v44, -v44, v51, v48
	v_and_b32_e32 v48, 1, v29
	v_div_fmas_f32 v43, v43, v45, v49
	s_mov_b32 vcc_lo, s2
	v_dual_fmaak_f32 v64, s17, v50, 0xbab64f3b :: v_dual_and_b32 v57, 1, v32
	v_div_fmas_f32 v44, v44, v46, v51
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v4, v43, v47, v4
	v_and_b32_e32 v51, 1, v10
	v_lshlrev_b32_e32 v10, 30, v10
	v_and_b32_e32 v49, 1, v24
	v_div_fixup_f32 v11, v44, v22, v11
	v_cvt_f64_f32_e32 v[45:46], v4
	v_mul_f32_e32 v4, v27, v27
	v_and_b32_e32 v53, 1, v19
	v_and_b32_e32 v65, 0x80000000, v10
	v_cvt_f64_f32_e32 v[43:44], v11
	v_lshlrev_b32_e32 v11, 30, v29
	v_dual_mul_f32 v29, v21, v21 :: v_dual_lshlrev_b32 v32, 30, v32
	v_fmaak_f32 v58, s3, v4, 0x3c0881c4
	v_dual_fmaak_f32 v59, s17, v4, 0xbab64f3b :: v_dual_lshlrev_b32 v26, 30, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v61, s3, v29, 0x3c0881c4
	v_dual_fmaak_f32 v62, s17, v29, 0xbab64f3b :: v_dual_lshlrev_b32 v19, 30, v19
	v_fmaak_f32 v58, v4, v58, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v59, v4, v59, 0x3d2aabf7
	v_fmaak_f32 v61, v29, v61, 0xbe2aaa9d
	v_and_b32_e32 v60, 0x80000000, v11
	v_fmaak_f32 v63, s3, v50, 0x3c0881c4
	v_dual_fmaak_f32 v67, s17, v52, 0xbab64f3b :: v_dual_mul_f32 v58, v4, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v61, v29, v61 :: v_dual_fmaak_f32 v68, s3, v54, 0x3c0881c4
	v_and_b32_e32 v32, 0x80000000, v32
	v_cmp_eq_u32_e32 vcc_lo, 0, v48
	v_fmac_f32_e32 v27, v27, v58
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v21, v21, v61 :: v_dual_lshlrev_b32 v24, 30, v24
	v_cmp_eq_u32_e64 s2, 0, v57
	v_xor_b32_e32 v32, v15, v32
	v_add_f64 v[45:46], v[45:46], -0.5
	v_add_f64 v[43:44], v[43:44], -0.5
	v_add_f64 v[10:11], v[43:44], v[43:44]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[43:44], v[45:46], v[45:46]
	v_dual_fmaak_f32 v45, v29, v62, 0x3d2aabf7 :: v_dual_fmaak_f32 v62, v50, v64, 0x3d2aabf7
	v_fmaak_f32 v64, v52, v67, 0x3d2aabf7
	v_fmaak_f32 v59, v4, v59, 0xbf000004
	v_dual_fmaak_f32 v46, v50, v63, 0xbe2aaa9d :: v_dual_fmaak_f32 v63, v52, v66, 0xbe2aaa9d
	v_fmaak_f32 v66, v54, v68, 0xbe2aaa9d
	v_fmaak_f32 v62, v50, v62, 0xbf000004
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v4, v4, v59, 1.0
	v_fmaak_f32 v71, s17, v56, 0xbab64f3b
	v_dual_fmaak_f32 v45, v29, v45, 0xbf000004 :: v_dual_fmaak_f32 v64, v52, v64, 0xbf000004
	v_mul_f32_e32 v66, v54, v66
	v_cndmask_b32_e64 v4, -v27, v4, vcc_lo
	v_dual_mul_f32 v46, v50, v46 :: v_dual_and_b32 v19, 0x80000000, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v29, v29, v45, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v49
	v_xor_b32_e32 v4, v60, v4
	v_fmac_f32_e32 v25, v25, v66
	v_fmaak_f32 v68, v56, v70, 0xbe2aaa9d
	v_fmac_f32_e32 v12, v12, v46
	v_fma_f32 v45, v50, v62, 1.0
	v_cndmask_b32_e64 v21, -v21, v29, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v51
	v_dual_mul_f32 v68, v56, v68 :: v_dual_fmaak_f32 v69, s17, v54, 0xbab64f3b
	v_dual_mul_f32 v63, v52, v63 :: v_dual_and_b32 v24, 0x80000000, v24
	v_and_b32_e32 v26, 0x80000000, v26
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_fmac_f32 v28, v28, v68 :: v_dual_fmaak_f32 v67, v54, v69, 0x3d2aabf7
	v_cndmask_b32_e64 v12, -v12, v45, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v55
	v_fmac_f32_e32 v13, v13, v63
	v_xor_b32_e32 v26, v15, v26
	v_cvt_f32_f64_e32 v10, v[10:11]
	v_fmaak_f32 v67, v54, v67, 0xbf000004
	v_cvt_f32_f64_e32 v11, v[43:44]
	v_fma_f32 v46, v52, v64, 1.0
	v_xor_b32_e32 v19, v15, v19
	v_xor_b32_e32 v21, v24, v21
	v_fma_f32 v50, v54, v67, 1.0
	v_xor_b32_e32 v12, v65, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, v50, v25, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v53
	v_xor3_b32 v25, v26, v25, v14
	v_cndmask_b32_e32 v13, v46, v13, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v13, v19, v13, v14
	v_cndmask_b32_e32 v19, 0x7fc00000, v25, vcc_lo
	v_cndmask_b32_e32 v21, 0x7fc00000, v21, vcc_lo
	v_cndmask_b32_e32 v12, 0x7fc00000, v12, vcc_lo
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	v_cndmask_b32_e32 v13, 0x7fc00000, v13, vcc_lo
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v19, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v16, v13
	v_fma_f32 v19, v17, v21, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, v9, v12, -v13
	v_mul_f32_e32 v13, v19, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v12, v11
	v_fmaak_f32 v69, v56, v71, 0x3d2aabf7
	v_fmaak_f32 v69, v56, v69, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v52, v56, v69, 1.0
	v_cndmask_b32_e64 v26, v52, v28, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v24, v32, v26, v14
	v_cndmask_b32_e32 v24, 0x7fc00000, v24, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v23, v24
	v_cvt_f64_f32_e32 v[24:25], v47
	v_fma_f32 v4, v20, v4, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v13, v4
	v_cvt_f64_f32_e32 v[12:13], v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], 0.5, 0.5
	v_mul_f64 v[12:13], v[12:13], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v19, v[12:13]
	v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
	v_floor_f32_e32 v4, v19
	v_ceil_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v4, v4
	v_cvt_f32_i32_e32 v24, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 v21, v24
	s_cbranch_execz .LBB1_61
; %bb.50:                               ; %.lr.ph534
	v_dual_mul_f32 v12, v39, v39 :: v_dual_and_b32 v13, 1, v40
	v_dual_mul_f32 v26, v35, v35 :: v_dual_lshlrev_b32 v25, 30, v40
	v_lshlrev_b32_e32 v29, 30, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v27, s3, v12, 0x3c0881c4 :: v_dual_mul_f32 v32, v30, v30
	v_dual_fmaak_f32 v28, s17, v12, 0xbab64f3b :: v_dual_fmaak_f32 v43, s17, v26, 0xbab64f3b
	v_fmaak_f32 v40, s3, v26, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v27, v12, v27, 0xbe2aaa9d
	v_cmp_eq_u32_e64 s0, 0, v13
	v_dual_fmaak_f32 v28, v12, v28, 0x3d2aabf7 :: v_dual_fmaak_f32 v43, v26, v43, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v40, v26, v40, 0xbe2aaa9d :: v_dual_mul_f32 v27, v12, v27
	v_fmaak_f32 v44, s3, v32, 0x3c0881c4
	v_fmaak_f32 v28, v12, v28, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v40, v26, v40 :: v_dual_and_b32 v25, 0x80000000, v25
	v_fmac_f32_e32 v39, v39, v27
	v_and_b32_e32 v13, 1, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v12, v12, v28, 1.0
	v_dual_fmaak_f32 v28, v26, v43, 0xbf000004 :: v_dual_fmac_f32 v35, v35, v40
	v_xor_b32_e32 v25, v15, v25
	v_lshlrev_b32_e32 v36, 30, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v39, s0
	v_fma_f32 v26, v26, v28, 1.0
	v_and_b32_e32 v28, 0x80000000, v29
	v_fmaak_f32 v29, v32, v44, 0xbe2aaa9d
	v_fmaak_f32 v27, s17, v32, 0xbab64f3b
	v_cmp_eq_u32_e64 s0, 0, v13
	v_xor3_b32 v12, v25, v12, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v26, v35, s0
	v_xor_b32_e32 v26, v15, v28
	v_mul_f32_e32 v28, v32, v29
	v_fmaak_f32 v27, v32, v27, 0x3d2aabf7
	v_mul_f32_e32 v35, v37, v37
	v_mul_f32_e32 v29, v33, v33
	v_xor3_b32 v13, v26, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v30, v30, v28 :: v_dual_fmaak_f32 v27, v32, v27, 0xbf000004
	v_and_b32_e32 v28, 1, v31
	v_cndmask_b32_e32 v12, 0x7fc00000, v12, vcc_lo
	v_cndmask_b32_e32 v13, 0x7fc00000, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v26, v32, v27, 1.0
	v_cmp_eq_u32_e64 s0, 0, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v30, s0
	v_dual_fmaak_f32 v30, s3, v35, 0x3c0881c4 :: v_dual_fmaak_f32 v27, s3, v29, 0x3c0881c4
	v_dual_fmaak_f32 v32, s17, v29, 0xbab64f3b :: v_dual_lshlrev_b32 v31, 30, v31
	v_fmaak_f32 v27, v29, v27, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v28, v29, v32, 0x3d2aabf7
	v_and_b32_e32 v31, 0x80000000, v31
	v_fmaak_f32 v32, s17, v35, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v27, v29, v27
	v_fmaak_f32 v28, v29, v28, 0xbf000004
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v15, v31
	v_and_b32_e32 v31, 1, v34
	v_fmac_f32_e32 v33, v33, v27
	v_dual_fmaak_f32 v27, v35, v32, 0x3d2aabf7 :: v_dual_lshlrev_b32 v32, 30, v34
	v_and_b32_e32 v34, 1, v38
	v_fmaak_f32 v30, v35, v30, 0xbe2aaa9d
	v_fma_f32 v28, v29, v28, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmaak_f32 v27, v35, v27, 0xbf000004
	v_and_b32_e32 v32, 0x80000000, v32
	v_cmp_eq_u32_e64 s0, 0, v34
	v_dual_mul_f32 v29, v35, v30 :: v_dual_mul_f32 v30, v41, v41
	v_fma_f32 v27, v35, v27, 1.0
	v_xor3_b32 v15, v15, v26, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v37, v37, v29
	v_fmaak_f32 v35, s17, v30, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, 0x7fc00000, v15, vcc_lo
	v_cndmask_b32_e64 v27, -v37, v27, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v34, v30, v35, 0x3d2aabf7
	v_and_b32_e32 v35, 0x80000000, v36
	v_cmp_eq_u32_e64 s0, 0, v31
	v_fmaak_f32 v31, v30, v34, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v27, v35, v27
	v_cndmask_b32_e64 v28, -v33, v28, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v27, 0x7fc00000, v27, vcc_lo
	v_fmaak_f32 v29, s3, v30, 0x3c0881c4
	v_xor_b32_e32 v28, v32, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, v18, v27
	v_fmaak_f32 v29, v30, v29, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v26, 0x7fc00000, v28, vcc_lo
	v_fmac_f32_e32 v18, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v29, v30, v29
	v_fma_f32 v30, v30, v31, 1.0
	v_lshlrev_b32_e32 v31, 30, v42
	v_mul_f32_e32 v15, v16, v26
	v_fmac_f32_e32 v41, v41, v29
	v_and_b32_e32 v29, 1, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, v9, v14
	v_mul_f32_e32 v9, v18, v10
	v_cmp_eq_u32_e64 s0, 0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, v15, v11
	v_cvt_f64_f32_e32 v[14:15], v22
	v_cndmask_b32_e64 v29, -v41, v30, s0
	v_and_b32_e32 v30, 0x80000000, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v27, v30, v29
	v_cndmask_b32_e32 v13, 0x7fc00000, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v23, v13
	v_lshlrev_b64 v[22:23], 2, v[2:3]
	v_fmac_f32_e32 v13, v20, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v9, v13
	v_cvt_f64_f32_e32 v[12:13], v9
	v_mul_lo_u32 v9, v8, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v5, v9
	v_fma_f64 v[12:13], v[12:13], 0.5, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[12:13], v[14:15]
	v_cvt_f32_f64_e32 v14, v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[12:13], null, v8, s4, v[5:6]
	v_mov_b32_e32 v13, 0
	v_floor_f32_e32 v5, v14
	v_ceil_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, v12, s7, v[4:5]
	v_cvt_i32_f32_e32 v5, v5
	v_mov_b32_e32 v12, 0
	v_cvt_f32_i32_e32 v17, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v15, s6, v8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v23, vcc_lo
	v_cmp_ge_f32_e32 vcc_lo, v16, v17
.LBB1_51:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_53 Depth 2
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB1_59
; %bb.52:                               ; %.lr.ph
                                        ;   in Loop: Header=BB1_51 Depth=1
	v_sub_f32_e32 v18, v19, v24
	v_cmp_lt_i32_e64 s0, -1, v4
	v_cmp_gt_i32_e64 s1, s7, v4
	v_cmp_gt_f32_e64 s2, v24, v19
	v_mov_b32_e32 v22, v17
	v_sub_f32_e64 v18, 1.0, |v18|
	v_mov_b32_e32 v20, v5
	s_mov_b32 s18, 0
.LBB1_53:                               ;   Parent Loop BB1_51 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v23, 0
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB1_57
; %bb.54:                               ;   in Loop: Header=BB1_53 Depth=2
	v_cmp_lt_i32_e64 s3, -1, v20
	v_cmp_gt_i32_e64 s4, s6, v20
	v_mov_b32_e32 v23, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s3, s1, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB1_56
; %bb.55:                               ;   in Loop: Header=BB1_53 Depth=2
	v_add_nc_u32_e32 v23, v15, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v23, s3, s8, v23
	v_add_co_ci_u32_e64 v24, s3, s9, v24, s3
	global_load_b32 v23, v[23:24], off
.LBB1_56:                               ; %Flow686
                                        ;   in Loop: Header=BB1_53 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
.LBB1_57:                               ;   in Loop: Header=BB1_53 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s19
	v_sub_f32_e32 v26, v14, v22
	v_add_nc_u32_e32 v24, v15, v20
	global_load_b32 v32, v[8:9], off
	v_cvt_f64_f32_e32 v[30:31], v13
	v_cvt_f64_f32_e32 v[12:13], v12
	v_sub_f32_e64 v34, 1.0, |v26|
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, v34, v23
	v_mul_f32_e32 v23, v18, v23
	v_ashrrev_i32_e32 v25, 31, v24
	v_cvt_f64_f32_e32 v[26:27], v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_f32_e32 v[28:29], v23
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v24, s3, s14, v24
	v_add_co_ci_u32_e64 v25, s3, s15, v25, s3
	v_cmp_gt_f32_e64 s3, v22, v14
	global_load_b32 v33, v[24:25], off
	v_xor_b32_e32 v23, 0x80000000, v27
	v_xor_b32_e32 v35, 0x80000000, v29
	v_cndmask_b32_e64 v22, v26, v26, s2
	v_cndmask_b32_e64 v26, v28, v28, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v27, s2
	v_cndmask_b32_e64 v27, v35, v29, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], v[30:31]
	v_add_f64 v[26:27], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v13, v[22:23]
	v_cvt_f32_f64_e32 v12, v[26:27]
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v23, v18, v32
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v33, v34, v23 :: v_dual_add_nc_u32 v20, 1, v20
	v_cvt_f32_i32_e32 v22, v20
	global_store_b32 v[24:25], v33, off
	v_cmp_nge_f32_e64 s3, v16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s18, s3, s18
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_53
; %bb.58:                               ; %Flow687
                                        ;   in Loop: Header=BB1_51 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB1_59:                               ; %Flow688
                                        ;   in Loop: Header=BB1_51 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v4, 1, v4
	v_add_nc_u32_e32 v15, s6, v15
	v_cvt_f32_i32_e32 v24, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nge_f32_e64 s0, v21, v24
	s_or_b32 s16, s0, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_51
; %bb.60:                               ; %Flow689
	s_or_b32 exec_lo, exec_lo, s16
.LBB1_61:                               ; %Flow690
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s5
	global_load_b32 v8, v[0:1], off offset:24
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v9, 0x7fffffff, v8
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v8|
	v_lshrrev_b32_e32 v4, 23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s2
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_63
; %bb.62:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v5, v9, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v5, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v5, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v5, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v5, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v5, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v5, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v5, v[15:16]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v5, v5, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v5
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v5, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v17, v5, 29, 1
	v_alignbit_b32 v18, v5, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	v_sub_nc_u32_e32 v19, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v5
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	v_lshrrev_b32_e32 v5, 30, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v14, v19, v15 :: v_dual_add_nc_u32 v15, v17, v5
.LBB1_63:                               ; %Flow685
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v5, 0x3f22f983, |v8|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.64:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v15, v5
	v_fma_f32 v14, 0xbfc90fda, v15, |v8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v14, v15, 0xb3a22168, v14
	v_fmamk_f32 v14, v15, 0xa7c234c4, v14
	v_cvt_i32_f32_e32 v15, v15
; %bb.65:                               ; %_ZL3cosf.exit289
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr16
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_67
; %bb.66:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v18, 0
	v_and_or_b32 v25, v9, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfe5163ab, v25, 0
	v_mad_u64_u32 v[19:20], null, 0x3c439041, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v20
	v_mad_u64_u32 v[20:21], null, 0xdb629599, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v21
	v_mad_u64_u32 v[21:22], null, 0xf534ddc0, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v17, v22 :: v_dual_add_nc_u32 v22, 0xffffff88, v4
	v_mad_u64_u32 v[4:5], null, 0xfc2757d1, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v17, v5 :: v_dual_cndmask_b32 v16, v20, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v23, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v5
	v_mov_b32_e32 v17, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v5, v24, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[17:18]
	v_cndmask_b32_e32 v18, v22, v21, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v23, v4, vcc_lo
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v22, v24, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v4, v4, v20 :: v_dual_add_nc_u32 v5, v17, v5
	v_cndmask_b32_e32 v17, v21, v19, vcc_lo
	v_cndmask_b32_e64 v19, v23, v18, s0
	v_cndmask_b32_e64 v21, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v4, s0
	v_sub_nc_u32_e32 v22, 32, v5
	v_cndmask_b32_e64 v4, v4, v17, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v21, v21, v19, s1
	v_cndmask_b32_e64 v19, v19, v18, s1
	v_cndmask_b32_e64 v16, v17, v16, s0
	v_cndmask_b32_e64 v18, v18, v4, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v21, v19, v22
	v_cndmask_b32_e64 v4, v4, v16, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v19, v18, v22
	v_cndmask_b32_e32 v5, v23, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v18, v4, v22
	v_cndmask_b32_e32 v17, v20, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v19, v5, 29, 1
	v_cndmask_b32_e32 v18, v21, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v5, v17, 30
	v_sub_nc_u32_e32 v20, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v17, v18, 30
	v_alignbit_b32 v4, v18, v4, 30
	v_xor_b32_e32 v16, v16, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v17, v17, v20
	v_xor_b32_e32 v4, v4, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v16
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v16, v16, v17, v18
	v_alignbit_b32 v4, v17, v4, v18
	v_lshrrev_b32_e32 v18, 29, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v16, v4, 9
	v_lshlrev_b32_e32 v18, 31, v18
	v_lshrrev_b32_e32 v16, 9, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v17
	v_or_b32_e32 v22, 0.5, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v24, 31, v20
	v_or_b32_e32 v16, v16, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v4, v17, v4, v24
	v_add_lshl_u32 v17, v20, v21, 23
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v4, 9, v4
	v_sub_nc_u32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v4, 0x33000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v16, v16, 0x33a22168, v17
	v_or_b32_e32 v4, v4, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, 0x3fc90fda, v4
	v_lshrrev_b32_e32 v4, 30, v5
                                        ; implicit-def: $vgpr5
	v_add_f32_e32 v16, v20, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v17, v19, v4
.LBB1_67:                               ; %Flow684
	s_and_not1_saveexec_b32 s0, s2
; %bb.68:
	v_rndne_f32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0xbfc90fda, v4, |v8|
	v_cvt_i32_f32_e32 v17, v4
	v_fmamk_f32 v5, v4, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v16, v4, 0xa7c234c4, v5
; %bb.69:                               ; %_ZL3sinf.exit297
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_mov_b32 s1, 0x37d75334
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v20, v16, v16
	v_mul_f32_e32 v18, v14, v14
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v9, v9, v8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v2
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
	global_load_b32 v6, v[4:5], off
	global_load_b32 v7, v[2:3], off
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_mul_f32_e32 v19, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v14, v14, v19 :: v_dual_mul_f32 v19, v20, v22
	v_dual_fmaak_f32 v21, v18, v21, 0x3d2aabf7 :: v_dual_fmac_f32 v16, v16, v19
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v21, v18, v21, 0xbf000004 :: v_dual_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v15
	v_lshlrev_b32_e32 v15, 30, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v17
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v17, 30, v17
	v_and_b32_e32 v15, 0x80000000, v15
	v_cndmask_b32_e64 v14, -v14, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v17, 0x80000000, v17
	v_xor_b32_e32 v14, v15, v14
	v_cndmask_b32_e32 v16, v19, v16, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v9, v9, v17, v16
	v_add_f32_e32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, 0x7fc00000, v9, vcc_lo
	v_mul_f32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v13, v8
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v8, v6, v8
.LBB1_70:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_70
; %bb.71:                               ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v6, v[0:1], off offset:24
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_73
; %bb.72:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v9, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_alignbit_b32 v18, v9, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v9, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB1_73:                               ; %Flow683
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v17, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.74:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v17
	v_fma_f32 v9, 0xbfc90fda, v14, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v14, 0xb3a22168, v9
	v_fmamk_f32 v9, v14, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v14, v14
; %bb.75:                               ; %_ZL3cosf.exit303
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_77
; %bb.76:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v17, 0
	v_and_or_b32 v25, v8, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[16:17]
	v_add_nc_u32_e32 v7, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v19
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[16:17]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_dual_mov_b32 v16, v20 :: v_dual_cndmask_b32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v21
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v16, v20, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v23, v17, s0
	v_cndmask_b32_e64 v20, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s0
	v_sub_nc_u32_e32 v22, 32, v7
	v_cndmask_b32_e64 v21, v21, v16, s0
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v15, v22
	v_cndmask_b32_e32 v7, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v18 :: v_dual_cndmask_b32 v17, v21, v17
	v_bfe_u32 v18, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v7, v16, 30
	v_alignbit_b32 v16, v16, v17, 30
	v_alignbit_b32 v15, v17, v15, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v20
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v15, v16, v15, v17
	v_lshrrev_b32_e32 v17, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v19, v15, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v16
	v_or_b32_e32 v22, 0.5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v15, v16, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmamk_f32 v16, v16, 0x33a22168, v19
	v_lshrrev_b32_e32 v7, 30, v7
	v_or_b32_e32 v15, v15, v17
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	v_dual_add_f32 v15, v20, v16 :: v_dual_add_nc_u32 v16, v18, v7
.LBB1_77:                               ; %Flow682
	s_and_not1_saveexec_b32 s0, s2
; %bb.78:
	v_rndne_f32_e32 v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0xbfc90fda, v7, |v6|
	v_cvt_i32_f32_e32 v16, v7
	v_fmamk_f32 v15, v7, 0xb3a22168, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v7, 0xa7c234c4, v15
; %bb.79:                               ; %_ZL3sinf.exit311
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v17, v[4:5], off
	global_load_b32 v7, v[2:3], off offset:8
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v20, v15, v15
	v_mul_f32_e32 v18, v9, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v21, v18, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v19
	v_fmac_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, v20, v22
	v_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v14
	v_dual_fmac_f32 v15, v15, v19 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v16, 30, v16
	v_and_b32_e32 v14, 0x80000000, v14
	v_cndmask_b32_e64 v9, -v9, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v9, v14, v9
	v_cndmask_b32_e32 v15, v19, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v8, v8, v16, v15
	v_add_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo
	v_mul_f32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v13, v6
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v8, v17, v6
.LBB1_80:                               ; %atomicrmw.start585
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_80
; %bb.81:                               ; %atomicrmw.end584
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v6, v[0:1], off offset:24
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_83
; %bb.82:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v9, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_alignbit_b32 v18, v9, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v9, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB1_83:                               ; %Flow681
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v17, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.84:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v17
	v_fma_f32 v9, 0xbfc90fda, v14, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v14, 0xb3a22168, v9
	v_fmamk_f32 v9, v14, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v14, v14
; %bb.85:                               ; %_ZL3cosf.exit317
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_87
; %bb.86:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v17, 0
	v_and_or_b32 v25, v8, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[16:17]
	v_add_nc_u32_e32 v7, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v19
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[16:17]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_dual_mov_b32 v16, v20 :: v_dual_cndmask_b32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v21
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v16, v20, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v23, v17, s0
	v_cndmask_b32_e64 v20, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s0
	v_sub_nc_u32_e32 v22, 32, v7
	v_cndmask_b32_e64 v21, v21, v16, s0
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v15, v22
	v_cndmask_b32_e32 v7, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v18 :: v_dual_cndmask_b32 v17, v21, v17
	v_bfe_u32 v18, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v7, v16, 30
	v_alignbit_b32 v16, v16, v17, 30
	v_alignbit_b32 v15, v17, v15, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v20
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v15, v16, v15, v17
	v_lshrrev_b32_e32 v17, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v19, v15, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v16
	v_or_b32_e32 v22, 0.5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v15, v16, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmamk_f32 v16, v16, 0x33a22168, v19
	v_lshrrev_b32_e32 v7, 30, v7
	v_or_b32_e32 v15, v15, v17
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	v_dual_add_f32 v15, v20, v16 :: v_dual_add_nc_u32 v16, v18, v7
.LBB1_87:                               ; %Flow680
	s_and_not1_saveexec_b32 s0, s2
; %bb.88:
	v_rndne_f32_e32 v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0xbfc90fda, v7, |v6|
	v_cvt_i32_f32_e32 v16, v7
	v_fmamk_f32 v15, v7, 0xb3a22168, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v7, 0xa7c234c4, v15
; %bb.89:                               ; %_ZL3sinf.exit325
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v17, v[4:5], off
	global_load_b32 v7, v[2:3], off offset:16
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v20, v15, v15
	v_mul_f32_e32 v18, v9, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v21, v18, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v19
	v_fmac_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, v20, v22
	v_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v14
	v_dual_fmac_f32 v15, v15, v19 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v16, 30, v16
	v_and_b32_e32 v14, 0x80000000, v14
	v_cndmask_b32_e64 v9, -v9, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v9, v14, v9
	v_cndmask_b32_e32 v15, v19, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v8, v8, v16, v15
	v_cvt_f64_f32_e32 v[14:15], v13
	v_add_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo
	v_cvt_f64_f32_e32 v[8:9], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[14:15], v[8:9]
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[14:15], v17
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v8, v[8:9]
.LBB1_90:                               ; %atomicrmw.start591
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_90
; %bb.91:                               ; %atomicrmw.end590
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v6, v[0:1], off offset:24
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_93
; %bb.92:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v9, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_alignbit_b32 v18, v9, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v9, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB1_93:                               ; %Flow679
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v17, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.94:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v17
	v_fma_f32 v9, 0xbfc90fda, v14, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v14, 0xb3a22168, v9
	v_fmamk_f32 v9, v14, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v14, v14
; %bb.95:                               ; %_ZL3cosf.exit331
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_97
; %bb.96:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v17, 0
	v_and_or_b32 v25, v8, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[16:17]
	v_add_nc_u32_e32 v7, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v19
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[16:17]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_dual_mov_b32 v16, v20 :: v_dual_cndmask_b32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v21
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v16, v20, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v23, v17, s0
	v_cndmask_b32_e64 v20, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s0
	v_sub_nc_u32_e32 v22, 32, v7
	v_cndmask_b32_e64 v21, v21, v16, s0
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v15, v22
	v_cndmask_b32_e32 v7, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v18 :: v_dual_cndmask_b32 v17, v21, v17
	v_bfe_u32 v18, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v7, v16, 30
	v_alignbit_b32 v16, v16, v17, 30
	v_alignbit_b32 v15, v17, v15, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v20
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v15, v16, v15, v17
	v_lshrrev_b32_e32 v17, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v19, v15, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v16
	v_or_b32_e32 v22, 0.5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v15, v16, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmamk_f32 v16, v16, 0x33a22168, v19
	v_lshrrev_b32_e32 v7, 30, v7
	v_or_b32_e32 v15, v15, v17
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	v_dual_add_f32 v15, v20, v16 :: v_dual_add_nc_u32 v16, v18, v7
.LBB1_97:                               ; %Flow678
	s_and_not1_saveexec_b32 s0, s2
; %bb.98:
	v_rndne_f32_e32 v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0xbfc90fda, v7, |v6|
	v_cvt_i32_f32_e32 v16, v7
	v_fmamk_f32 v15, v7, 0xb3a22168, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v7, 0xa7c234c4, v15
; %bb.99:                               ; %_ZL3sinf.exit339
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v17, v[4:5], off
	global_load_b32 v7, v[2:3], off offset:4
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v20, v15, v15
	v_mul_f32_e32 v18, v9, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v21, v18, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v19
	v_fmac_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, v20, v22
	v_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v14
	v_dual_fmac_f32 v15, v15, v19 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v16, 30, v16
	v_and_b32_e32 v14, 0x80000000, v14
	v_cndmask_b32_e64 v9, -v9, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v9, v14, v9
	v_cndmask_b32_e32 v15, v19, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v8, v8, v16, v15
	v_sub_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo
	v_mul_f32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v12, v6
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v8, v17, v6
.LBB1_100:                              ; %atomicrmw.start597
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off offset:4 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_100
; %bb.101:                              ; %atomicrmw.end596
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v6, v[0:1], off offset:24
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_103
; %bb.102:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v9, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_alignbit_b32 v18, v9, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v9, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB1_103:                              ; %Flow677
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v17, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.104:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v17
	v_fma_f32 v9, 0xbfc90fda, v14, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v14, 0xb3a22168, v9
	v_fmamk_f32 v9, v14, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v14, v14
; %bb.105:                              ; %_ZL3cosf.exit345
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_107
; %bb.106:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v17, 0
	v_and_or_b32 v25, v8, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[16:17]
	v_add_nc_u32_e32 v7, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v19
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[16:17]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_dual_mov_b32 v16, v20 :: v_dual_cndmask_b32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v21
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v16, v20, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v23, v17, s0
	v_cndmask_b32_e64 v20, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s0
	v_sub_nc_u32_e32 v22, 32, v7
	v_cndmask_b32_e64 v21, v21, v16, s0
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v15, v22
	v_cndmask_b32_e32 v7, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v18 :: v_dual_cndmask_b32 v17, v21, v17
	v_bfe_u32 v18, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v7, v16, 30
	v_alignbit_b32 v16, v16, v17, 30
	v_alignbit_b32 v15, v17, v15, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v20
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v15, v16, v15, v17
	v_lshrrev_b32_e32 v17, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v19, v15, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v16
	v_or_b32_e32 v22, 0.5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v15, v16, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmamk_f32 v16, v16, 0x33a22168, v19
	v_lshrrev_b32_e32 v7, 30, v7
	v_or_b32_e32 v15, v15, v17
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	v_dual_add_f32 v15, v20, v16 :: v_dual_add_nc_u32 v16, v18, v7
.LBB1_107:                              ; %Flow676
	s_and_not1_saveexec_b32 s0, s2
; %bb.108:
	v_rndne_f32_e32 v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0xbfc90fda, v7, |v6|
	v_cvt_i32_f32_e32 v16, v7
	v_fmamk_f32 v15, v7, 0xb3a22168, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v7, 0xa7c234c4, v15
; %bb.109:                              ; %_ZL3sinf.exit353
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v17, v[4:5], off
	global_load_b32 v7, v[2:3], off offset:12
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v20, v15, v15
	v_mul_f32_e32 v18, v9, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v21, v18, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v19
	v_fmac_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, v20, v22
	v_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v14
	v_dual_fmac_f32 v15, v15, v19 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v16, 30, v16
	v_and_b32_e32 v14, 0x80000000, v14
	v_cndmask_b32_e64 v9, -v9, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v9, v14, v9
	v_cndmask_b32_e32 v15, v19, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v8, v8, v16, v15
	v_sub_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo
	v_mul_f32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v12, v6
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v8, v17, v6
.LBB1_110:                              ; %atomicrmw.start603
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off offset:12 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_110
; %bb.111:                              ; %atomicrmw.end602
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v6, v[0:1], off offset:24
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v8, 0x7fffffff, v6
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_113
; %bb.112:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_add_nc_u32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v18
	v_cmp_lt_u32_e64 s0, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v15, v19 :: v_dual_add_nc_u32 v24, v24, v23
	v_cndmask_b32_e32 v14, v18, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v24
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v20
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	v_cndmask_b32_e64 v14, v17, v14, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v21
	v_mad_u64_u32 v[21:22], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v15, v22
	v_mad_u64_u32 v[22:23], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v21, v19, vcc_lo
	v_add_nc_u32_e32 v9, v9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v22, v20 :: v_dual_cndmask_b32 v21, v23, v21
	v_cndmask_b32_e32 v20, v20, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_cndmask_b32_e64 v16, v21, v16, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v20, v20, v17, s0
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v15, v14, v21
	v_cndmask_b32_e32 v9, v22, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_alignbit_b32 v18, v9, v16, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v15, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v19
	v_clz_i32_u32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_alignbit_b32 v15, v18, v14, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v21, 0.5, v16
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_sub_nc_u32_e32 v23, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v18
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v9, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB1_113:                              ; %Flow675
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v17, 0x3f22f983, |v6|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.114:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v17
	v_fma_f32 v9, 0xbfc90fda, v14, |v6|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v14, 0xb3a22168, v9
	v_fmamk_f32 v9, v14, 0xa7c234c4, v9
	v_cvt_i32_f32_e32 v14, v14
; %bb.115:                              ; %_ZL3cosf.exit359
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_117
; %bb.116:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v17, 0
	v_and_or_b32 v25, v8, s0, 0x800000
	v_add_nc_u32_e32 v7, 0xffffff88, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v25, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v23, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0x3c439041, v25, v[16:17]
	v_add_nc_u32_e32 v7, v23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v16, v19
	v_cmp_lt_u32_e64 s0, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xdb629599, v25, v[16:17]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v24, v7
	v_dual_mov_b32 v16, v20 :: v_dual_cndmask_b32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mad_u64_u32 v[20:21], null, 0xf534ddc0, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v21
	v_mad_u64_u32 v[21:22], null, 0xfc2757d1, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v22
	v_mad_u64_u32 v[22:23], null, 0x4e441529, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v16, v23
	v_mad_u64_u32 v[23:24], null, 0xa2f9836e, v25, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v22, v20, vcc_lo
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s1
	v_add_nc_u32_e32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v23, v23, v21 :: v_dual_cndmask_b32 v22, v24, v22
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v16, v20, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v23, v17, s0
	v_cndmask_b32_e64 v20, v22, v23, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s0
	v_sub_nc_u32_e32 v22, 32, v7
	v_cndmask_b32_e64 v21, v21, v16, s0
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v21, s1
	v_cndmask_b32_e64 v15, v21, v15, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v23, v20, v18, v22
	v_alignbit_b32 v19, v18, v17, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v15, v22
	v_cndmask_b32_e32 v7, v23, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v18 :: v_dual_cndmask_b32 v17, v21, v17
	v_bfe_u32 v18, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v7, v16, 30
	v_alignbit_b32 v16, v16, v17, 30
	v_alignbit_b32 v15, v17, v15, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 0, v18
	v_xor_b32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v20
	v_xor_b32_e32 v15, v15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v19, v19, v16, v17
	v_alignbit_b32 v15, v16, v15, v17
	v_lshrrev_b32_e32 v17, 29, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v19, v15, 9
	v_lshlrev_b32_e32 v17, 31, v17
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v20, v16
	v_or_b32_e32 v22, 0.5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v20
	v_alignbit_b32 v15, v16, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v16, v19, v22
	v_add_lshl_u32 v19, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmamk_f32 v16, v16, 0x33a22168, v19
	v_lshrrev_b32_e32 v7, 30, v7
	v_or_b32_e32 v15, v15, v17
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v15
	v_dual_add_f32 v15, v20, v16 :: v_dual_add_nc_u32 v16, v18, v7
.LBB1_117:                              ; %Flow674
	s_and_not1_saveexec_b32 s0, s2
; %bb.118:
	v_rndne_f32_e32 v7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0xbfc90fda, v7, |v6|
	v_cvt_i32_f32_e32 v16, v7
	v_fmamk_f32 v15, v7, 0xb3a22168, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v15, v7, 0xa7c234c4, v15
; %bb.119:                              ; %_ZL3sinf.exit367
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v17, v[4:5], off
	global_load_b32 v7, v[2:3], off offset:20
	s_mov_b32 s1, 0x37d75334
	v_mul_f32_e32 v20, v15, v15
	v_mul_f32_e32 v18, v9, v9
	s_mov_b32 s0, 0xb94c1982
	v_xor_b32_e32 v8, v8, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, s1, v20, 0xbab64f3b
	v_fmaak_f32 v21, s1, v18, 0xbab64f3b
	v_dual_fmaak_f32 v19, s0, v18, 0x3c0881c4 :: v_dual_fmaak_f32 v22, s0, v20, 0x3c0881c4
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v23, v20, v23, 0x3d2aabf7
	v_fmaak_f32 v21, v18, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v19, v18, v19, 0xbe2aaa9d :: v_dual_fmaak_f32 v22, v20, v22, 0xbe2aaa9d
	v_fmaak_f32 v21, v18, v21, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v19, v18, v19
	v_fmac_f32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, v20, v22
	v_fmaak_f32 v22, v20, v23, 0xbf000004
	v_fma_f32 v18, v18, v21, 1.0
	v_and_b32_e32 v21, 1, v14
	v_dual_fmac_f32 v15, v15, v19 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v20, v22, 1.0
	v_and_b32_e32 v20, 1, v16
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_lshlrev_b32_e32 v16, 30, v16
	v_and_b32_e32 v14, 0x80000000, v14
	v_cndmask_b32_e64 v9, -v9, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v16, 0x80000000, v16
	v_xor_b32_e32 v9, v14, v9
	v_cndmask_b32_e32 v15, v19, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v8, v8, v16, v15
	v_cvt_f64_f32_e32 v[14:15], v12
	v_sub_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, 0x7fc00000, v8, vcc_lo
	v_cvt_f64_f32_e32 v[8:9], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[14:15], v[8:9]
	s_waitcnt vmcnt(1)
	v_cvt_f64_f32_e32 v[14:15], v17
	v_mul_f64 v[8:9], v[8:9], v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v8, v[8:9]
.LBB1_120:                              ; %atomicrmw.start609
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v7, v8
	global_atomic_cmpswap_b32 v6, v[2:3], v[6:7], off offset:20 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v6, v7
	v_mov_b32_e32 v7, v6
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_120
; %bb.121:                              ; %atomicrmw.end608
	s_or_b32 exec_lo, exec_lo, s0
	s_clause 0x1
	global_load_b32 v7, v[0:1], off offset:24
	global_load_b32 v6, v[0:1], off
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr14
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, 0x7fffffff, v7
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v7|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v22, 23, v8
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_123
; %bb.122:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v16, 0
	v_and_or_b32 v9, v8, s0, 0x800000
	v_add_nc_u32_e32 v23, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v9, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v23
	v_cndmask_b32_e64 v24, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x3c439041, v9, v[15:16]
	v_mov_b32_e32 v15, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0xdb629599, v9, v[15:16]
	v_dual_mov_b32 v15, v19 :: v_dual_cndmask_b32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, 0xf534ddc0, v9, v[15:16]
	v_mov_b32_e32 v15, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v19, v17, vcc_lo
	v_mad_u64_u32 v[20:21], null, 0xfc2757d1, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v15, v21
	v_add_nc_u32_e32 v21, v24, v23
	v_mad_u64_u32 v[23:24], null, 0x4e441529, v9, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v21
	v_cndmask_b32_e64 v25, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v15, v24
	v_cndmask_b32_e64 v14, v17, v14, s0
	v_add_nc_u32_e32 v21, v25, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[24:25], null, 0xa2f9836e, v9, v[15:16]
	v_cndmask_b32_e32 v15, v23, v19, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v24, v20, vcc_lo
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v23, v25, v23 :: v_dual_cndmask_b32 v20, v20, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v19, v16, v15, s0
	v_add_nc_u32_e32 v9, v9, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v23, v16, s0
	v_cndmask_b32_e64 v15, v15, v20, s0
	v_cndmask_b32_e64 v20, v20, v17, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v21, 32, v9
	v_cndmask_b32_e64 v16, v16, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, v19, v15, s1
	v_cndmask_b32_e64 v15, v15, v20, s1
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v14, v20, v14, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v23, v16, v19, v21
	v_alignbit_b32 v18, v19, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v15, v14, v21
	v_dual_cndmask_b32 v9, v23, v16 :: v_dual_cndmask_b32 v16, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v20, v15, vcc_lo
	v_bfe_u32 v17, v9, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v9, v16, 30
	v_alignbit_b32 v16, v16, v15, 30
	v_alignbit_b32 v14, v15, v14, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, 0, v17
	v_xor_b32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v16, v19
	v_xor_b32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v20, v18
	v_min_u32_e32 v20, 32, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v20
	v_lshlrev_b32_e32 v23, 23, v20
	v_alignbit_b32 v18, v18, v15, v16
	v_alignbit_b32 v14, v15, v14, v16
	v_lshrrev_b32_e32 v16, 29, v9
	v_lshrrev_b32_e32 v9, 30, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v18, v14, 9
	v_lshlrev_b32_e32 v16, 31, v16
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v19, v15
	v_or_b32_e32 v21, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v19, 32, v19
	v_sub_nc_u32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v24, 31, v19
	v_alignbit_b32 v14, v15, v14, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v15, v18, v21
	v_add_lshl_u32 v18, v19, v20, 23
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	v_sub_nc_u32_e32 v14, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v15, -v19
	v_add_nc_u32_e32 v14, 0x33000000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v15, v15, 0x33a22168, v18
	v_or_b32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0x3fc90fda, v14
	v_dual_add_f32 v14, v19, v15 :: v_dual_add_nc_u32 v15, v17, v9
.LBB1_123:                              ; %Flow673
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v26, 0x3f22f983, |v7|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.124:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v9, v26
	v_fma_f32 v14, 0xbfc90fda, v9, |v7|
	v_cvt_i32_f32_e32 v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v14, v9, 0xb3a22168, v14
	v_fmamk_f32 v14, v9, 0xa7c234c4, v14
; %bb.125:                              ; %_ZL3sinf.exit375
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v9, v[0:1], off offset:4
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr17
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_127
; %bb.126:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v18, 0
	v_and_or_b32 v30, v8, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xfe5163ab, v30, 0
	v_mad_u64_u32 v[19:20], null, 0x3c439041, v30, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v20
	v_mad_u64_u32 v[20:21], null, 0xdb629599, v30, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v21
	v_mad_u64_u32 v[23:24], null, 0xf534ddc0, v30, v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v17, v24
	v_mad_u64_u32 v[24:25], null, 0xfc2757d1, v30, v[17:18]
	v_add_nc_u32_e32 v21, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_dual_mov_b32 v17, v25 :: v_dual_cndmask_b32 v16, v20, v16
	v_cndmask_b32_e64 v27, 0, 0xffffffc0, vcc_lo
	v_cndmask_b32_e32 v19, v23, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v21, v27, v21
	v_mad_u64_u32 v[27:28], null, 0x4e441529, v30, v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v21
	v_mov_b32_e32 v17, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, 0, 0xffffffe0, s0
	v_cndmask_b32_e64 v16, v19, v16, s0
	v_mad_u64_u32 v[28:29], null, 0xa2f9836e, v30, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v18, v27, v23 :: v_dual_add_nc_u32 v21, v25, v21
	v_cmp_lt_u32_e64 s1, 31, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v25, v28, v24, vcc_lo
	v_dual_cndmask_b32 v27, v29, v27 :: v_dual_cndmask_b32 v24, v24, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s1
	v_cndmask_b32_e64 v23, v27, v25, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v17, v17, v21
	v_cndmask_b32_e64 v21, v25, v18, s0
	v_cndmask_b32_e64 v18, v18, v24, s0
	v_cndmask_b32_e64 v24, v24, v19, s0
	v_sub_nc_u32_e32 v25, 32, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v21, s1
	v_cndmask_b32_e64 v21, v21, v18, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v24, s1
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_cndmask_b32_e64 v16, v24, v16, s1
	v_alignbit_b32 v27, v23, v21, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v21, v18, v25
	v_alignbit_b32 v24, v18, v16, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v17, v27, v23, vcc_lo
	v_cndmask_b32_e32 v19, v20, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v18, v24, v18, vcc_lo
	v_bfe_u32 v20, v17, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v21, v17, v19, 30
	v_alignbit_b32 v19, v19, v18, 30
	v_alignbit_b32 v16, v18, v16, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 0, v20
	v_xor_b32_e32 v21, v21, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v18, v19, v23
	v_xor_b32_e32 v16, v16, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v24, v21
	v_min_u32_e32 v24, 32, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, 31, v24
	v_lshlrev_b32_e32 v27, 23, v24
	v_alignbit_b32 v21, v21, v18, v19
	v_alignbit_b32 v16, v18, v16, v19
	v_lshrrev_b32_e32 v19, 29, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v18, v21, v16, 9
	v_lshlrev_b32_e32 v19, 31, v19
	v_lshrrev_b32_e32 v21, 9, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v23, v18
	v_or_b32_e32 v25, 0.5, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v23, 32, v23
	v_sub_nc_u32_e32 v25, v25, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v28, 31, v23
	v_alignbit_b32 v16, v18, v16, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v18, v21, v25
	v_add_lshl_u32 v21, v23, v24, 23
	v_lshrrev_b32_e32 v16, 9, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, 0x3fc90fda, v18
	v_sub_nc_u32_e32 v16, v16, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, 0x3fc90fda, v18, -v23
	v_add_nc_u32_e32 v16, 0x33000000, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v18, v18, 0x33a22168, v21
	v_or_b32_e32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, 0x3fc90fda, v16
	v_lshrrev_b32_e32 v16, 30, v17
	v_dual_add_f32 v17, v23, v18 :: v_dual_add_nc_u32 v18, v20, v16
.LBB1_127:                              ; %Flow672
	s_and_not1_saveexec_b32 s0, s3
; %bb.128:
	v_rndne_f32_e32 v16, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v17, 0xbfc90fda, v16, |v7|
	v_cvt_i32_f32_e32 v18, v16
	v_fmamk_f32 v17, v16, 0xb3a22168, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v17, v16, 0xa7c234c4, v17
; %bb.129:                              ; %_ZL3cosf.exit381
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v16, v[0:1], off offset:8
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_131
; %bb.130:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v21, 0
	v_and_or_b32 v32, v8, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v32, 0
	v_mad_u64_u32 v[23:24], null, 0x3c439041, v32, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v20, v24
	v_mad_u64_u32 v[24:25], null, 0xdb629599, v32, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v20, v25 :: v_dual_add_nc_u32 v25, 0xffffff88, v22
	v_mad_u64_u32 v[27:28], null, 0xf534ddc0, v32, v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v25
	v_cndmask_b32_e64 v30, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v20, v28
	v_cndmask_b32_e32 v19, v24, v19, vcc_lo
	v_cndmask_b32_e32 v23, v27, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v25, v30, v25
	v_mad_u64_u32 v[28:29], null, 0xfc2757d1, v32, v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v25
	v_cndmask_b32_e64 v31, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v20, v29
	v_cndmask_b32_e64 v19, v23, v19, s0
	v_add_nc_u32_e32 v25, v31, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0x4e441529, v32, v[20:21]
	v_cmp_lt_u32_e64 s1, 31, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v20, v30
	v_mad_u64_u32 v[30:31], null, 0xa2f9836e, v32, v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v21, v29, v27, vcc_lo
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v30, v30, v28 :: v_dual_cndmask_b32 v29, v31, v29
	v_cndmask_b32_e32 v28, v28, v24, vcc_lo
	v_add_nc_u32_e32 v20, v20, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v30, v21, s0
	v_cndmask_b32_e64 v27, v29, v30, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v28, s0
	v_sub_nc_u32_e32 v29, 32, v20
	v_cndmask_b32_e64 v28, v28, v23, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	v_cndmask_b32_e64 v27, v27, v25, s1
	v_cndmask_b32_e64 v25, v25, v21, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v28, s1
	v_cndmask_b32_e64 v19, v28, v19, s1
	v_alignbit_b32 v30, v27, v25, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v24, v25, v21, v29
	v_alignbit_b32 v28, v21, v19, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v20, v30, v27 :: v_dual_cndmask_b32 v23, v24, v25
	v_cndmask_b32_e32 v21, v28, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v24, v20, 29, 1
	v_alignbit_b32 v25, v20, v23, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v23, v23, v21, 30
	v_alignbit_b32 v19, v21, v19, 30
	v_sub_nc_u32_e32 v27, 0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v25, v25, v27
	v_xor_b32_e32 v21, v23, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v19, v19, v27
	v_clz_i32_u32_e32 v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v28, 32, v28
	v_sub_nc_u32_e32 v23, 31, v28
	v_lshlrev_b32_e32 v30, 23, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v25, v25, v21, v23
	v_alignbit_b32 v19, v21, v19, v23
	v_lshrrev_b32_e32 v23, 29, v20
	v_alignbit_b32 v21, v25, v19, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v23, 31, v23
	v_lshrrev_b32_e32 v25, 9, v25
	v_clz_i32_u32_e32 v27, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v29, 0.5, v23
	v_min_u32_e32 v27, 32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v29, v29, v30
	v_sub_nc_u32_e32 v31, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v21, v19, v31
	v_or_b32_e32 v21, v25, v29
	v_add_lshl_u32 v25, v27, v28, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v19, 9, v19
	v_mul_f32_e32 v27, 0x3fc90fda, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v25
	v_fma_f32 v25, 0x3fc90fda, v21, -v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 0x33000000, v19
	v_fmamk_f32 v21, v21, 0x33a22168, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v19, v19, v23
	v_fmac_f32_e32 v21, 0x3fc90fda, v19
	v_lshrrev_b32_e32 v19, 30, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v20, v27, v21 :: v_dual_add_nc_u32 v21, v24, v19
.LBB1_131:                              ; %Flow671
	s_and_not1_saveexec_b32 s0, s3
; %bb.132:
	v_rndne_f32_e32 v19, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0xbfc90fda, v19, |v7|
	v_cvt_i32_f32_e32 v21, v19
	v_fmamk_f32 v20, v19, 0xb3a22168, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v20, v19, 0xa7c234c4, v20
; %bb.133:                              ; %_ZL3sinf.exit389
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v19, v[0:1], off offset:12
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_135
; %bb.134:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v25, 0
	v_and_or_b32 v34, v8, s0, 0x800000
	v_add_nc_u32_e32 v32, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[23:24], null, 0xfe5163ab, v34, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v32
	v_cndmask_b32_e64 v33, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[27:28], null, 0x3c439041, v34, v[24:25]
	v_dual_mov_b32 v24, v28 :: v_dual_add_nc_u32 v33, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v33
	v_mad_u64_u32 v[28:29], null, 0xdb629599, v34, v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v35, 0, 0xffffffe0, s0
	v_dual_mov_b32 v24, v29 :: v_dual_add_nc_u32 v35, v35, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v28, v23, vcc_lo
	v_cmp_lt_u32_e64 s1, 31, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, 0xf534ddc0, v34, v[24:25]
	v_dual_mov_b32 v24, v30 :: v_dual_cndmask_b32 v27, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xfc2757d1, v34, v[24:25]
	v_cndmask_b32_e64 v23, v27, v23, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v24, v31
	v_mad_u64_u32 v[31:32], null, 0x4e441529, v34, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v24, v32
	v_mad_u64_u32 v[32:33], null, 0xa2f9836e, v34, v[24:25]
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v25, v31, v29 :: v_dual_add_nc_u32 v24, v24, v35
	v_dual_cndmask_b32 v32, v32, v30 :: v_dual_cndmask_b32 v31, v33, v31
	v_cndmask_b32_e32 v30, v30, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v24
	v_cndmask_b32_e64 v29, v32, v25, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v32, s0
	v_cndmask_b32_e64 v25, v25, v30, s0
	v_sub_nc_u32_e32 v32, 32, v24
	v_cndmask_b32_e64 v30, v30, v27, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v29, s1
	v_cndmask_b32_e64 v29, v29, v25, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, v25, v30, s1
	v_cndmask_b32_e64 v23, v30, v23, s1
	v_alignbit_b32 v33, v31, v29, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v28, v29, v25, v32
	v_cndmask_b32_e32 v24, v33, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v25, v23, v32
	v_cndmask_b32_e32 v27, v28, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v28, v24, 29, 1
	v_cndmask_b32_e32 v25, v31, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v24, v27, 30
	v_sub_nc_u32_e32 v30, 0, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v27, v25, 30
	v_alignbit_b32 v23, v25, v23, 30
	v_xor_b32_e32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v25, v27, v30
	v_xor_b32_e32 v23, v23, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v31, v29
	v_min_u32_e32 v31, 32, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v27, 31, v31
	v_lshlrev_b32_e32 v33, 23, v31
	v_alignbit_b32 v29, v29, v25, v27
	v_alignbit_b32 v23, v25, v23, v27
	v_lshrrev_b32_e32 v27, 29, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v25, v29, v23, 9
	v_lshlrev_b32_e32 v27, 31, v27
	v_lshrrev_b32_e32 v29, 9, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v30, v25
	v_or_b32_e32 v32, 0.5, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v30, 32, v30
	v_sub_nc_u32_e32 v32, v32, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v34, 31, v30
	v_alignbit_b32 v23, v25, v23, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v25, v29, v32
	v_add_lshl_u32 v29, v30, v31, 23
	v_lshrrev_b32_e32 v23, 9, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v30, 0x3fc90fda, v25
	v_sub_nc_u32_e32 v23, v23, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, 0x3fc90fda, v25, -v30
	v_add_nc_u32_e32 v23, 0x33000000, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v25, v25, 0x33a22168, v29
	v_or_b32_e32 v23, v23, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, 0x3fc90fda, v23
	v_lshrrev_b32_e32 v23, 30, v24
	v_dual_add_f32 v24, v30, v25 :: v_dual_add_nc_u32 v25, v28, v23
.LBB1_135:                              ; %Flow670
	s_and_not1_saveexec_b32 s0, s3
; %bb.136:
	v_rndne_f32_e32 v23, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v24, 0xbfc90fda, v23, |v7|
	v_cvt_i32_f32_e32 v25, v23
	v_fmamk_f32 v24, v23, 0xb3a22168, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v24, v23, 0xa7c234c4, v24
; %bb.137:                              ; %_ZL3cosf.exit395
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v23, v[0:1], off offset:16
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr27
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_139
; %bb.138:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v29, 0
	v_and_or_b32 v37, v8, s0, 0x800000
	v_add_nc_u32_e32 v35, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, 0xfe5163ab, v37, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v35
	v_cndmask_b32_e64 v36, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0x3c439041, v37, v[28:29]
	v_add_nc_u32_e32 v36, v36, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v28, v31
	v_cmp_lt_u32_e64 s0, 31, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0xdb629599, v37, v[28:29]
	v_cndmask_b32_e64 v38, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v27, v31, v27 :: v_dual_add_nc_u32 v38, v38, v36
	v_mov_b32_e32 v28, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v38
	v_mad_u64_u32 v[32:33], null, 0xf534ddc0, v37, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v28, v33
	v_cndmask_b32_e32 v30, v32, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0xfc2757d1, v37, v[28:29]
	v_cndmask_b32_e64 v27, v30, v27, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v28, v34
	v_mad_u64_u32 v[34:35], null, 0x4e441529, v37, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v28, v35
	v_mad_u64_u32 v[35:36], null, 0xa2f9836e, v37, v[28:29]
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v29, v34, v32 :: v_dual_add_nc_u32 v28, v28, v38
	v_dual_cndmask_b32 v35, v35, v33 :: v_dual_cndmask_b32 v34, v36, v34
	v_cndmask_b32_e32 v33, v33, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v28
	v_cndmask_b32_e64 v32, v35, v29, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v35, s0
	v_cndmask_b32_e64 v29, v29, v33, s0
	v_sub_nc_u32_e32 v35, 32, v28
	v_cndmask_b32_e64 v33, v33, v30, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v34, v32, s1
	v_cndmask_b32_e64 v32, v32, v29, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v29, v33, s1
	v_cndmask_b32_e64 v27, v33, v27, s1
	v_alignbit_b32 v36, v34, v32, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v31, v32, v29, v35
	v_cndmask_b32_e32 v28, v36, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v29, v27, v35
	v_cndmask_b32_e32 v30, v31, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v31, v28, 29, 1
	v_cndmask_b32_e32 v29, v34, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v28, v30, 30
	v_sub_nc_u32_e32 v33, 0, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v30, v30, v29, 30
	v_alignbit_b32 v27, v29, v27, 30
	v_xor_b32_e32 v32, v32, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v29, v30, v33
	v_xor_b32_e32 v27, v27, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v34, v32
	v_min_u32_e32 v34, 32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v30, 31, v34
	v_lshlrev_b32_e32 v36, 23, v34
	v_alignbit_b32 v32, v32, v29, v30
	v_alignbit_b32 v27, v29, v27, v30
	v_lshrrev_b32_e32 v30, 29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v29, v32, v27, 9
	v_lshlrev_b32_e32 v30, 31, v30
	v_lshrrev_b32_e32 v32, 9, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v33, v29
	v_or_b32_e32 v35, 0.5, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v33, 32, v33
	v_sub_nc_u32_e32 v35, v35, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v37, 31, v33
	v_alignbit_b32 v27, v29, v27, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v29, v32, v35
	v_add_lshl_u32 v32, v33, v34, 23
	v_lshrrev_b32_e32 v27, 9, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v33, 0x3fc90fda, v29
	v_sub_nc_u32_e32 v27, v27, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, 0x3fc90fda, v29, -v33
	v_add_nc_u32_e32 v27, 0x33000000, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v29, v29, 0x33a22168, v32
	v_or_b32_e32 v27, v27, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, 0x3fc90fda, v27
	v_lshrrev_b32_e32 v28, 30, v28
	v_dual_add_f32 v27, v33, v29 :: v_dual_add_nc_u32 v28, v31, v28
.LBB1_139:                              ; %Flow669
	s_and_not1_saveexec_b32 s0, s3
; %bb.140:
	v_rndne_f32_e32 v28, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v27, 0xbfc90fda, v28, |v7|
	v_fmamk_f32 v27, v28, 0xb3a22168, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v27, v28, 0xa7c234c4, v27
	v_cvt_i32_f32_e32 v28, v28
; %bb.141:                              ; %_ZL3sinf.exit403
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v0, v[0:1], off offset:20
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr29
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_143
; %bb.142:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v31, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v37, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v37
	v_cndmask_b32_e64 v38, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0x3c439041, v1, v[30:31]
	v_add_nc_u32_e32 v38, v38, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v30, v33
	v_cmp_lt_u32_e64 s0, 31, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0xdb629599, v1, v[30:31]
	v_cndmask_b32_e64 v39, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v30, v34 :: v_dual_add_nc_u32 v39, v39, v38
	v_cndmask_b32_e32 v29, v33, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v39
	v_mad_u64_u32 v[34:35], null, 0xf534ddc0, v1, v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v30, v35
	v_cndmask_b32_e32 v32, v34, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[35:36], null, 0xfc2757d1, v1, v[30:31]
	v_mov_b32_e32 v30, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[36:37], null, 0x4e441529, v1, v[30:31]
	v_mov_b32_e32 v30, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[37:38], null, 0xa2f9836e, v1, v[30:31]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v30, v36, v34 :: v_dual_add_nc_u32 v1, v1, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v31, v37, v35 :: v_dual_cndmask_b32 v36, v38, v36
	v_cndmask_b32_e32 v35, v35, v33, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v31, v30, s0
	v_cndmask_b32_e64 v31, v36, v31, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v30, v30, v35, s0
	v_sub_nc_u32_e32 v36, 32, v1
	v_cndmask_b32_e64 v35, v35, v32, s0
	v_cndmask_b32_e64 v31, v31, v34, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, v34, v30, s1
	v_cndmask_b32_e64 v30, v30, v35, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v37, v31, v34, v36
	v_alignbit_b32 v33, v34, v30, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v37, v31, vcc_lo
	v_cndmask_b32_e32 v31, v33, v34, vcc_lo
	v_cndmask_b32_e64 v29, v32, v29, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v32, v1, 29, 1
	v_alignbit_b32 v33, v1, v31, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v35, v29, s1
	v_sub_nc_u32_e32 v34, 0, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v35, v30, v29, v36
	v_xor_b32_e32 v33, v33, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v35, v30, vcc_lo
	v_clz_i32_u32_e32 v35, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v31, v30, 30
	v_alignbit_b32 v29, v30, v29, 30
	v_min_u32_e32 v35, 32, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v30, v31, v34
	v_xor_b32_e32 v29, v29, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v31, 31, v35
	v_lshlrev_b32_e32 v37, 23, v35
	v_alignbit_b32 v33, v33, v30, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v30, v29, v31
	v_lshrrev_b32_e32 v31, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	v_alignbit_b32 v30, v33, v29, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v31, 31, v31
	v_lshrrev_b32_e32 v33, 9, v33
	v_clz_i32_u32_e32 v34, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v36, 0.5, v31
	v_min_u32_e32 v34, 32, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v36, v36, v37
	v_sub_nc_u32_e32 v38, 31, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v30, v29, v38
	v_or_b32_e32 v30, v33, v36
	v_add_lshl_u32 v33, v34, v35, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v29, 9, v29
	v_mul_f32_e32 v34, 0x3fc90fda, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v29, v29, v33
	v_fma_f32 v33, 0x3fc90fda, v30, -v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v29, 0x33000000, v29
	v_fmamk_f32 v30, v30, 0x33a22168, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v29, v29, v31
	v_fmac_f32_e32 v30, 0x3fc90fda, v29
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v29, v34, v30 :: v_dual_add_nc_u32 v30, v32, v1
.LBB1_143:                              ; %Flow668
	s_and_not1_saveexec_b32 s0, s3
; %bb.144:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v29, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v30, v1
	v_fmamk_f32 v29, v1, 0xb3a22168, v29
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v29, v1, 0xa7c234c4, v29
; %bb.145:                              ; %_ZL3cosf.exit409
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b32 v4, v[4:5], off
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr31
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_147
; %bb.146:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v33, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v5, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v5
	v_cndmask_b32_e64 v39, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0x3c439041, v1, v[32:33]
	v_add_nc_u32_e32 v5, v39, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v32, v35
	v_cmp_lt_u32_e64 s0, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0xdb629599, v1, v[32:33]
	v_cndmask_b32_e64 v40, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v40, v5
	v_mov_b32_e32 v32, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v5
	v_mad_u64_u32 v[36:37], null, 0xf534ddc0, v1, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v32, v37
	v_mad_u64_u32 v[37:38], null, 0xfc2757d1, v1, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v32, v38
	v_mad_u64_u32 v[38:39], null, 0x4e441529, v1, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v32, v39
	v_mad_u64_u32 v[39:40], null, 0xa2f9836e, v1, v[32:33]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v32, v38, v36 :: v_dual_add_nc_u32 v1, v1, v5
	v_dual_cndmask_b32 v33, v39, v37 :: v_dual_cndmask_b32 v38, v40, v38
	v_cndmask_b32_e32 v37, v37, v35, vcc_lo
	v_cndmask_b32_e32 v5, v36, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v36, 32, v1
	v_cndmask_b32_e64 v34, v33, v32, s0
	v_cndmask_b32_e64 v33, v38, v33, s0
	v_cndmask_b32_e64 v32, v32, v37, s0
	v_cndmask_b32_e64 v37, v37, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v33, v33, v34, s1
	v_cndmask_b32_e64 v34, v34, v32, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v37, s1
	v_cndmask_b32_e32 v31, v35, v31, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_alignbit_b32 v38, v33, v34, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v35, v34, v32, v36
	v_cndmask_b32_e64 v5, v5, v31, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v38, v33, vcc_lo
	v_cndmask_b32_e32 v31, v35, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v37, v5, s1
	v_bfe_u32 v33, v1, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v1, v31, 30
	v_alignbit_b32 v36, v32, v5, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, 0, v33
	v_cndmask_b32_e32 v32, v36, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v34, v34, v35
	v_alignbit_b32 v31, v31, v32, 30
	v_alignbit_b32 v5, v32, v5, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v36, v34
	v_xor_b32_e32 v31, v31, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v35
	v_min_u32_e32 v36, 32, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v38, 23, v36
	v_sub_nc_u32_e32 v32, 31, v36
	v_alignbit_b32 v34, v34, v31, v32
	v_alignbit_b32 v5, v31, v5, v32
	v_lshrrev_b32_e32 v32, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v34, v5, 9
	v_lshlrev_b32_e32 v32, 31, v32
	v_lshrrev_b32_e32 v34, 9, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v35, v31
	v_or_b32_e32 v37, 0.5, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v35, 32, v35
	v_sub_nc_u32_e32 v37, v37, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v39, 31, v35
	v_alignbit_b32 v5, v31, v5, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v31, v34, v37
	v_add_lshl_u32 v34, v35, v36, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, 0x3fc90fda, v31
	v_sub_nc_u32_e32 v5, v5, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, 0x3fc90fda, v31, -v35
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v31, v31, 0x33a22168, v34
	v_or_b32_e32 v5, v5, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v31, 0x3fc90fda, v5
	v_add_nc_u32_e32 v5, v33, v1
	v_add_f32_e32 v31, v35, v31
.LBB1_147:                              ; %Flow667
	s_and_not1_saveexec_b32 s0, s3
; %bb.148:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0xbfc90fda, v1, |v7|
	v_fmamk_f32 v5, v1, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v31, v1, 0xa7c234c4, v5
	v_cvt_i32_f32_e32 v5, v1
; %bb.149:                              ; %_ZL3cosf.exit415
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr33
                                        ; implicit-def: $vgpr32
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_151
; %bb.150:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v34, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v40, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v40
	v_cndmask_b32_e64 v41, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[35:36], null, 0x3c439041, v1, v[33:34]
	v_add_nc_u32_e32 v41, v41, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v33, v36
	v_cmp_lt_u32_e64 s0, 31, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, 0xdb629599, v1, v[33:34]
	v_cndmask_b32_e64 v42, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v33, v37 :: v_dual_add_nc_u32 v42, v42, v41
	v_cndmask_b32_e32 v32, v36, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v42
	v_mad_u64_u32 v[37:38], null, 0xf534ddc0, v1, v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v33, v38
	v_cndmask_b32_e32 v35, v37, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, 0xfc2757d1, v1, v[33:34]
	v_cndmask_b32_e64 v32, v35, v32, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v33, v39
	v_mad_u64_u32 v[39:40], null, 0x4e441529, v1, v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v33, v40
	v_mad_u64_u32 v[40:41], null, 0xa2f9836e, v1, v[33:34]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v33, v39, v37, vcc_lo
	v_add_nc_u32_e32 v1, v1, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v34, v40, v38 :: v_dual_cndmask_b32 v39, v41, v39
	v_cndmask_b32_e32 v38, v38, v36, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v37, v34, v33, s0
	v_cndmask_b32_e64 v34, v39, v34, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, v33, v38, s0
	v_sub_nc_u32_e32 v39, 32, v1
	v_cndmask_b32_e64 v38, v38, v35, s0
	v_cndmask_b32_e64 v34, v34, v37, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, v37, v33, s1
	v_cndmask_b32_e64 v33, v33, v38, s1
	v_cndmask_b32_e64 v32, v38, v32, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v34, v37, v39
	v_alignbit_b32 v36, v37, v33, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v33, v32, v39
	v_cndmask_b32_e32 v1, v40, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v34, v36, v37, vcc_lo
	v_cndmask_b32_e32 v33, v38, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v35, v1, 29, 1
	v_alignbit_b32 v36, v1, v34, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v34, v34, v33, 30
	v_alignbit_b32 v32, v33, v32, 30
	v_sub_nc_u32_e32 v37, 0, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v36, v36, v37
	v_xor_b32_e32 v33, v34, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v32, v32, v37
	v_clz_i32_u32_e32 v38, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v38, 32, v38
	v_sub_nc_u32_e32 v34, 31, v38
	v_lshlrev_b32_e32 v40, 23, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v36, v36, v33, v34
	v_alignbit_b32 v32, v33, v32, v34
	v_lshrrev_b32_e32 v34, 29, v1
	v_alignbit_b32 v33, v36, v32, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v34, 31, v34
	v_lshrrev_b32_e32 v36, 9, v36
	v_clz_i32_u32_e32 v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v39, 0.5, v34
	v_min_u32_e32 v37, 32, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v39, v39, v40
	v_sub_nc_u32_e32 v41, 31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v33, v32, v41
	v_or_b32_e32 v33, v36, v39
	v_add_lshl_u32 v36, v37, v38, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v32, 9, v32
	v_mul_f32_e32 v37, 0x3fc90fda, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, v32, v36
	v_fma_f32 v36, 0x3fc90fda, v33, -v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v32, 0x33000000, v32
	v_fmamk_f32 v33, v33, 0x33a22168, v36
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v32, v32, v34
	v_fmac_f32_e32 v33, 0x3fc90fda, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v32, v37, v33
	v_add_nc_u32_e32 v33, v35, v1
.LBB1_151:                              ; %Flow666
	s_and_not1_saveexec_b32 s0, s3
; %bb.152:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v32, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v33, v1
	v_fmamk_f32 v32, v1, 0xb3a22168, v32
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v32, v1, 0xa7c234c4, v32
; %bb.153:                              ; %_ZL3sinf.exit423
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr34
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_155
; %bb.154:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v36, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v42, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v42
	v_cndmask_b32_e64 v43, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[37:38], null, 0x3c439041, v1, v[35:36]
	v_add_nc_u32_e32 v43, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v35, v38
	v_cmp_lt_u32_e64 s0, 31, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, 0xdb629599, v1, v[35:36]
	v_cndmask_b32_e64 v44, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v35, v39 :: v_dual_add_nc_u32 v44, v44, v43
	v_cndmask_b32_e32 v34, v38, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v44
	v_mad_u64_u32 v[39:40], null, 0xf534ddc0, v1, v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v35, v40
	v_cndmask_b32_e32 v37, v39, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[40:41], null, 0xfc2757d1, v1, v[35:36]
	v_cndmask_b32_e64 v34, v37, v34, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v35, v41
	v_mad_u64_u32 v[41:42], null, 0x4e441529, v1, v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v35, v42
	v_mad_u64_u32 v[42:43], null, 0xa2f9836e, v1, v[35:36]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v35, v41, v39, vcc_lo
	v_add_nc_u32_e32 v1, v1, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v36, v42, v40 :: v_dual_cndmask_b32 v41, v43, v41
	v_cndmask_b32_e32 v40, v40, v38, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v39, v36, v35, s0
	v_cndmask_b32_e64 v36, v41, v36, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v35, v40, s0
	v_sub_nc_u32_e32 v41, 32, v1
	v_cndmask_b32_e64 v40, v40, v37, s0
	v_cndmask_b32_e64 v36, v36, v39, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v39, v39, v35, s1
	v_cndmask_b32_e64 v35, v35, v40, s1
	v_cndmask_b32_e64 v34, v40, v34, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v36, v39, v41
	v_alignbit_b32 v38, v39, v35, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v35, v34, v41
	v_cndmask_b32_e32 v1, v42, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v36, v38, v39, vcc_lo
	v_cndmask_b32_e32 v35, v40, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v37, v1, 29, 1
	v_alignbit_b32 v38, v1, v36, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v36, v36, v35, 30
	v_alignbit_b32 v34, v35, v34, 30
	v_sub_nc_u32_e32 v39, 0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v38, v38, v39
	v_xor_b32_e32 v35, v36, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v34, v34, v39
	v_clz_i32_u32_e32 v40, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v40, 32, v40
	v_sub_nc_u32_e32 v36, 31, v40
	v_lshlrev_b32_e32 v42, 23, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v38, v38, v35, v36
	v_alignbit_b32 v34, v35, v34, v36
	v_lshrrev_b32_e32 v36, 29, v1
	v_alignbit_b32 v35, v38, v34, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v36, 31, v36
	v_lshrrev_b32_e32 v38, 9, v38
	v_clz_i32_u32_e32 v39, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v41, 0.5, v36
	v_min_u32_e32 v39, 32, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v41, v41, v42
	v_sub_nc_u32_e32 v43, 31, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v35, v34, v43
	v_or_b32_e32 v35, v38, v41
	v_add_lshl_u32 v38, v39, v40, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v34, 9, v34
	v_mul_f32_e32 v39, 0x3fc90fda, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v34, v34, v38
	v_fma_f32 v38, 0x3fc90fda, v35, -v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v34, 0x33000000, v34
	v_fmamk_f32 v35, v35, 0x33a22168, v38
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v34, v34, v36
	v_fmac_f32_e32 v35, 0x3fc90fda, v34
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v34, v39, v35 :: v_dual_add_nc_u32 v35, v37, v1
.LBB1_155:                              ; %Flow665
	s_and_not1_saveexec_b32 s0, s3
; %bb.156:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v34, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v35, v1
	v_fmamk_f32 v34, v1, 0xb3a22168, v34
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v34, v1, 0xa7c234c4, v34
; %bb.157:                              ; %_ZL3cosf.exit429
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr36
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_159
; %bb.158:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v38, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v44, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v44
	v_cndmask_b32_e64 v45, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[39:40], null, 0x3c439041, v1, v[37:38]
	v_add_nc_u32_e32 v45, v45, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v37, v40
	v_cmp_lt_u32_e64 s0, 31, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[40:41], null, 0xdb629599, v1, v[37:38]
	v_cndmask_b32_e64 v46, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v37, v41 :: v_dual_add_nc_u32 v46, v46, v45
	v_cndmask_b32_e32 v36, v40, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v46
	v_mad_u64_u32 v[41:42], null, 0xf534ddc0, v1, v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v37, v42
	v_cndmask_b32_e32 v39, v41, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[42:43], null, 0xfc2757d1, v1, v[37:38]
	v_cndmask_b32_e64 v36, v39, v36, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v37, v43
	v_mad_u64_u32 v[43:44], null, 0x4e441529, v1, v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v37, v44
	v_mad_u64_u32 v[44:45], null, 0xa2f9836e, v1, v[37:38]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v37, v43, v41, vcc_lo
	v_add_nc_u32_e32 v1, v1, v46
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v38, v44, v42 :: v_dual_cndmask_b32 v43, v45, v43
	v_cndmask_b32_e32 v42, v42, v40, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v41, v38, v37, s0
	v_cndmask_b32_e64 v38, v43, v38, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v37, v37, v42, s0
	v_sub_nc_u32_e32 v43, 32, v1
	v_cndmask_b32_e64 v42, v42, v39, s0
	v_cndmask_b32_e64 v38, v38, v41, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v41, v41, v37, s1
	v_cndmask_b32_e64 v37, v37, v42, s1
	v_cndmask_b32_e64 v36, v42, v36, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v38, v41, v43
	v_alignbit_b32 v40, v41, v37, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v42, v37, v36, v43
	v_cndmask_b32_e32 v1, v44, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v38, v40, v41, vcc_lo
	v_cndmask_b32_e32 v37, v42, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v39, v1, 29, 1
	v_alignbit_b32 v40, v1, v38, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v38, v38, v37, 30
	v_alignbit_b32 v36, v37, v36, 30
	v_sub_nc_u32_e32 v41, 0, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v40, v40, v41
	v_xor_b32_e32 v37, v38, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v36, v36, v41
	v_clz_i32_u32_e32 v42, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v42, 32, v42
	v_sub_nc_u32_e32 v38, 31, v42
	v_lshlrev_b32_e32 v44, 23, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v40, v40, v37, v38
	v_alignbit_b32 v36, v37, v36, v38
	v_lshrrev_b32_e32 v38, 29, v1
	v_alignbit_b32 v37, v40, v36, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v38, 31, v38
	v_lshrrev_b32_e32 v40, 9, v40
	v_clz_i32_u32_e32 v41, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v43, 0.5, v38
	v_min_u32_e32 v41, 32, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v43, v43, v44
	v_sub_nc_u32_e32 v45, 31, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v37, v36, v45
	v_or_b32_e32 v37, v40, v43
	v_add_lshl_u32 v40, v41, v42, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v36, 9, v36
	v_mul_f32_e32 v41, 0x3fc90fda, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v36, v36, v40
	v_fma_f32 v40, 0x3fc90fda, v37, -v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v36, 0x33000000, v36
	v_fmamk_f32 v37, v37, 0x33a22168, v40
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v36, v36, v38
	v_fmac_f32_e32 v37, 0x3fc90fda, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v36, v41, v37
	v_add_nc_u32_e32 v37, v39, v1
.LBB1_159:                              ; %Flow664
	s_and_not1_saveexec_b32 s0, s3
; %bb.160:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v36, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v37, v1
	v_fmamk_f32 v36, v1, 0xb3a22168, v36
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v36, v1, 0xa7c234c4, v36
; %bb.161:                              ; %_ZL3sinf.exit437
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr41
                                        ; implicit-def: $vgpr39
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB1_163
; %bb.162:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v40, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v46, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[38:39], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v46
	v_cndmask_b32_e64 v47, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[41:42], null, 0x3c439041, v1, v[39:40]
	v_add_nc_u32_e32 v47, v47, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v39, v42
	v_cmp_lt_u32_e64 s0, 31, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[42:43], null, 0xdb629599, v1, v[39:40]
	v_cndmask_b32_e64 v48, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v39, v43 :: v_dual_add_nc_u32 v48, v48, v47
	v_cndmask_b32_e32 v38, v42, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v48
	v_mad_u64_u32 v[43:44], null, 0xf534ddc0, v1, v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v39, v44
	v_cndmask_b32_e32 v41, v43, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[44:45], null, 0xfc2757d1, v1, v[39:40]
	v_cndmask_b32_e64 v38, v41, v38, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v39, v45
	v_mad_u64_u32 v[45:46], null, 0x4e441529, v1, v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v39, v46
	v_mad_u64_u32 v[46:47], null, 0xa2f9836e, v1, v[39:40]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v39, v45, v43, vcc_lo
	v_add_nc_u32_e32 v1, v1, v48
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v40, v46, v44 :: v_dual_cndmask_b32 v45, v47, v45
	v_cndmask_b32_e32 v44, v44, v42, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v43, v40, v39, s0
	v_cndmask_b32_e64 v40, v45, v40, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v39, v39, v44, s0
	v_sub_nc_u32_e32 v45, 32, v1
	v_cndmask_b32_e64 v44, v44, v41, s0
	v_cndmask_b32_e64 v40, v40, v43, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v43, v43, v39, s1
	v_cndmask_b32_e64 v39, v39, v44, s1
	v_cndmask_b32_e64 v38, v44, v38, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v46, v40, v43, v45
	v_alignbit_b32 v42, v43, v39, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v44, v39, v38, v45
	v_cndmask_b32_e32 v1, v46, v40, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v40, v42, v43, vcc_lo
	v_cndmask_b32_e32 v39, v44, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v41, v1, 29, 1
	v_alignbit_b32 v42, v1, v40, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v40, v40, v39, 30
	v_alignbit_b32 v38, v39, v38, 30
	v_sub_nc_u32_e32 v43, 0, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v42, v42, v43
	v_xor_b32_e32 v39, v40, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v38, v38, v43
	v_clz_i32_u32_e32 v44, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v44, 32, v44
	v_sub_nc_u32_e32 v40, 31, v44
	v_lshlrev_b32_e32 v46, 23, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v42, v42, v39, v40
	v_alignbit_b32 v38, v39, v38, v40
	v_lshrrev_b32_e32 v40, 29, v1
	v_alignbit_b32 v39, v42, v38, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v40, 31, v40
	v_lshrrev_b32_e32 v42, 9, v42
	v_clz_i32_u32_e32 v43, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v45, 0.5, v40
	v_min_u32_e32 v43, 32, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v45, v45, v46
	v_sub_nc_u32_e32 v47, 31, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v39, v38, v47
	v_or_b32_e32 v39, v42, v45
	v_add_lshl_u32 v42, v43, v44, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v38, 9, v38
	v_mul_f32_e32 v43, 0x3fc90fda, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v38, v38, v42
	v_fma_f32 v42, 0x3fc90fda, v39, -v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v38, 0x33000000, v38
	v_fmamk_f32 v39, v39, 0x33a22168, v42
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v38, v38, v40
	v_add_nc_u32_e32 v41, v41, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, 0x3fc90fda, v38
	v_add_f32_e32 v39, v43, v39
.LBB1_163:                              ; %Flow663
	s_and_not1_saveexec_b32 s0, s3
; %bb.164:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v38, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v41, v1
	v_fmamk_f32 v38, v1, 0xb3a22168, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v39, v1, 0xa7c234c4, v38
; %bb.165:                              ; %_ZL3cosf.exit443
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr40
                                        ; implicit-def: $vgpr38
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB1_167
; %bb.166:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v44, 0
	v_and_or_b32 v1, v8, s0, 0x800000
	v_add_nc_u32_e32 v22, 0xffffff88, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[42:43], null, 0xfe5163ab, v1, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v22
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[45:46], null, 0x3c439041, v1, v[43:44]
	v_add_nc_u32_e32 v22, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v43, v46
	v_cmp_lt_u32_e64 s0, 31, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[46:47], null, 0xdb629599, v1, v[43:44]
	v_cndmask_b32_e64 v26, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v43, v47 :: v_dual_add_nc_u32 v22, v26, v22
	v_cndmask_b32_e32 v42, v46, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v22
	v_mad_u64_u32 v[47:48], null, 0xf534ddc0, v1, v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v43, v48
	v_mad_u64_u32 v[48:49], null, 0xfc2757d1, v1, v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v43, v49
	v_mad_u64_u32 v[49:50], null, 0x4e441529, v1, v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v43, v50 :: v_dual_cndmask_b32 v26, v49, v47
	v_mad_u64_u32 v[50:51], null, 0xa2f9836e, v1, v[43:44]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v43, v48, v46, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v38, v50, v48 :: v_dual_add_nc_u32 v1, v1, v22
	v_cndmask_b32_e32 v40, v51, v49, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v44, v38, v26, s0
	v_cndmask_b32_e64 v38, v40, v38, s0
	v_cndmask_b32_e64 v26, v26, v43, s0
	v_sub_nc_u32_e32 v40, 32, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v38, v38, v44, s1
	v_cndmask_b32_e64 v44, v44, v26, s1
	v_cndmask_b32_e32 v22, v47, v45, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v45, v38, v44, v40
	v_cndmask_b32_e32 v1, v45, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v43, v43, v22, s0
	v_cndmask_b32_e64 v22, v22, v42, s0
	v_bfe_u32 v42, v1, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v26, v43, s1
	v_cndmask_b32_e64 v22, v43, v22, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v46, v44, v26, v40
	v_alignbit_b32 v40, v26, v22, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v38, v46, v44, vcc_lo
	v_sub_nc_u32_e32 v44, 0, v42
	v_cndmask_b32_e32 v26, v40, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v43, v1, v38, 30
	v_alignbit_b32 v38, v38, v26, 30
	v_alignbit_b32 v22, v26, v22, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v43, v43, v44
	v_xor_b32_e32 v26, v38, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v22, v22, v44
	v_clz_i32_u32_e32 v40, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v40, 32, v40
	v_sub_nc_u32_e32 v38, 31, v40
	v_lshlrev_b32_e32 v46, 23, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_alignbit_b32 v43, v43, v26, v38
	v_alignbit_b32 v22, v26, v22, v38
	v_lshrrev_b32_e32 v38, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	v_alignbit_b32 v26, v43, v22, 9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v38, 31, v38
	v_lshrrev_b32_e32 v43, 9, v43
	v_clz_i32_u32_e32 v44, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v45, 0.5, v38
	v_min_u32_e32 v44, 32, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v45, v45, v46
	v_sub_nc_u32_e32 v47, 31, v44
	v_add_lshl_u32 v40, v44, v40, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v22, v26, v22, v47
	v_or_b32_e32 v26, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v22, 9, v22
	v_mul_f32_e32 v43, 0x3fc90fda, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v22, v22, v40
	v_fma_f32 v40, 0x3fc90fda, v26, -v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v22, 0x33000000, v22
	v_fmamk_f32 v26, v26, 0x33a22168, v40
	v_add_nc_u32_e32 v40, v42, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v22, v22, v38
	v_fmac_f32_e32 v26, 0x3fc90fda, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v38, v43, v26
                                        ; implicit-def: $vgpr26
.LBB1_167:                              ; %Flow662
	s_and_not1_saveexec_b32 s0, s2
; %bb.168:
	v_rndne_f32_e32 v1, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v40, v1
	v_fmamk_f32 v22, v1, 0xb3a22168, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v38, v1, 0xa7c234c4, v22
; %bb.169:                              ; %_ZL3sinf.exit451
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v22, v39, v39 :: v_dual_and_b32 v43, 1, v41
	s_mov_b32 s1, 0xb94c1982
	s_mov_b32 s2, 0x37d75334
	global_load_b32 v1, v[2:3], off offset:24
	v_dual_fmaak_f32 v26, s1, v22, 0x3c0881c4 :: v_dual_lshlrev_b32 v41, 30, v41
	v_fmaak_f32 v42, s2, v22, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v43, v31, v31 :: v_dual_fmaak_f32 v26, v22, v26, 0xbe2aaa9d
	v_fmaak_f32 v44, s2, v43, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v42, v22, v42, 0x3d2aabf7
	v_mul_f32_e32 v26, v22, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v42, v22, v42, 0xbf000004
	v_fmac_f32_e32 v39, v39, v26
	v_mul_f32_e32 v26, v34, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, v22, v42, 1.0
	v_fmaak_f32 v42, s1, v26, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, -v39, v22, vcc_lo
	v_and_b32_e32 v39, 0x80000000, v41
	v_fmaak_f32 v41, s2, v26, 0xbab64f3b
	v_fmaak_f32 v42, v26, v42, 0xbe2aaa9d
	v_cmp_class_f32_e64 vcc_lo, v7, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v22, v39, v22
	v_fmaak_f32 v39, v26, v41, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v41, v26, v42 :: v_dual_fmaak_f32 v42, s1, v43, 0x3c0881c4
	v_cndmask_b32_e32 v22, 0x7fc00000, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v39, v26, v39, 0xbf000004
	v_dual_fmac_f32 v34, v34, v41 :: v_dual_fmaak_f32 v41, v43, v42, 0xbe2aaa9d
	v_and_b32_e32 v42, 1, v35
	v_lshlrev_b32_e32 v35, 30, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v26, v26, v39, 1.0
	v_fmaak_f32 v39, v43, v44, 0x3d2aabf7
	v_mul_f32_e32 v41, v43, v41
	v_cmp_eq_u32_e64 s0, 0, v42
	v_dual_mul_f32 v44, v36, v36 :: v_dual_fmac_f32 v31, v31, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, -v34, v26, s0
	v_dual_fmaak_f32 v34, v43, v39, 0xbf000004 :: v_dual_mul_f32 v39, v32, v32
	v_and_b32_e32 v41, 1, v5
	v_lshlrev_b32_e32 v5, 30, v5
	v_fma_f32 v34, v43, v34, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v42, s1, v39, 0x3c0881c4
	v_cmp_eq_u32_e64 s0, 0, v41
	v_fmaak_f32 v43, s2, v39, 0xbab64f3b
	v_and_b32_e32 v5, 0x80000000, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v31, -v31, v34, s0
	v_fmaak_f32 v34, v39, v42, 0xbe2aaa9d
	v_and_b32_e32 v35, 0x80000000, v35
	v_fmaak_f32 v42, s1, v44, 0x3c0881c4
	v_fmaak_f32 v41, v39, v43, 0x3d2aabf7
	v_xor_b32_e32 v5, v5, v31
	v_mul_f32_e32 v34, v39, v34
	v_xor_b32_e32 v26, v35, v26
	v_dual_fmaak_f32 v42, v44, v42, 0xbe2aaa9d :: v_dual_mul_f32 v35, v27, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v43, s2, v44, 0xbab64f3b :: v_dual_fmac_f32 v32, v32, v34
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	v_fmaak_f32 v43, v44, v43, 0x3d2aabf7
	v_fmaak_f32 v41, v39, v41, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v34, v39, v41, 1.0
	v_lshlrev_b32_e32 v39, 30, v33
	v_and_b32_e32 v33, 1, v33
	v_mul_f32_e32 v41, v44, v42
	v_dual_fmaak_f32 v42, v44, v43, 0xbf000004 :: v_dual_lshlrev_b32 v43, 30, v37
	v_and_b32_e32 v37, 1, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s0, 0, v33
	v_fmac_f32_e32 v36, v36, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v41, v44, v42, 1.0
	v_and_b32_e32 v42, 0x80000000, v43
	v_cndmask_b32_e64 v32, v34, v32, s0
	v_cmp_eq_u32_e64 s0, 0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v41, v36, s0
	v_xor_b32_e32 v36, v8, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor3_b32 v31, v36, v34, v7
	v_mul_f32_e32 v36, v20, v20
	v_fmaak_f32 v34, s2, v35, 0xbab64f3b
	v_cndmask_b32_e32 v31, 0x7fc00000, v31, vcc_lo
	v_cndmask_b32_e32 v26, 0x7fc00000, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v34, v35, v34, 0x3d2aabf7
	s_waitcnt vmcnt(4)
	v_mul_f32_e32 v31, v19, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v26, v16, v26, -v31
	v_and_b32_e32 v39, 0x80000000, v39
	v_dual_fmaak_f32 v31, v35, v34, 0xbf000004 :: v_dual_and_b32 v34, 1, v28
	v_lshlrev_b32_e32 v28, 30, v28
	v_mul_f32_e32 v26, v26, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v33, v8, v39
	v_fma_f32 v31, v35, v31, 1.0
	v_cmp_eq_u32_e64 s0, 0, v34
	v_and_b32_e32 v28, 0x80000000, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor3_b32 v32, v33, v32, v7
	v_fmaak_f32 v33, s1, v35, 0x3c0881c4
	v_xor_b32_e32 v28, v8, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v32, 0x7fc00000, v32, vcc_lo
	v_mul_f32_e32 v32, v9, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v6, v5, -v32
	v_fmaak_f32 v32, s1, v36, 0x3c0881c4
	v_dual_fmaak_f32 v33, v35, v33, 0xbe2aaa9d :: v_dual_fmac_f32 v26, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v32, v36, v32, 0xbe2aaa9d :: v_dual_mul_f32 v33, v35, v33
	v_dual_mul_f32 v32, v36, v32 :: v_dual_fmac_f32 v27, v27, v33
	v_fmaak_f32 v33, s2, v36, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v20, v32
	v_lshlrev_b32_e32 v32, 30, v21
	v_fmaak_f32 v33, v36, v33, 0x3d2aabf7
	v_cndmask_b32_e64 v27, v31, v27, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v32, 0x80000000, v32
	v_fmaak_f32 v31, v36, v33, 0xbf000004
	v_mul_f32_e32 v33, v14, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor3_b32 v27, v28, v27, v7
	v_mul_f32_e32 v28, v17, v17
	v_fma_f32 v31, v36, v31, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v34, s1, v33, 0x3c0881c4
	v_and_b32_e32 v21, 1, v21
	v_cmp_eq_u32_e64 s0, 0, v21
	v_fmaak_f32 v21, s2, v33, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v31, v20, s0
	v_xor_b32_e32 v31, v8, v32
	v_fmaak_f32 v32, v33, v34, 0xbe2aaa9d
	v_fmaak_f32 v5, v33, v21, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v20, v31, v20, v7
	v_mul_f32_e32 v21, v33, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0x7fc00000, v20, vcc_lo
	v_dual_fmac_f32 v14, v14, v21 :: v_dual_lshlrev_b32 v21, 30, v15
	v_fmaak_f32 v31, s1, v28, 0x3c0881c4
	v_dual_fmaak_f32 v32, s2, v28, 0xbab64f3b :: v_dual_and_b32 v15, 1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v31, v28, v31, 0xbe2aaa9d
	v_fmaak_f32 v32, v28, v32, 0x3d2aabf7
	v_fmaak_f32 v5, v33, v5, 0xbf000004
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 0, v15
	v_fma_f32 v5, v33, v5, 1.0
	v_mul_f32_e32 v33, v24, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v5, v14, s0
	v_dual_mul_f32 v14, v28, v31 :: v_dual_fmaak_f32 v15, s1, v33, 0x3c0881c4
	v_fmaak_f32 v31, v28, v32, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v17, v17, v14
	v_dual_fmaak_f32 v14, v33, v15, 0xbe2aaa9d :: v_dual_and_b32 v15, 1, v18
	v_lshlrev_b32_e32 v18, 30, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s0, 0, v15
	v_and_b32_e32 v18, 0x80000000, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v14, v33, v14 :: v_dual_and_b32 v21, 0x80000000, v21
	v_fmaak_f32 v32, s2, v33, 0xbab64f3b
	v_xor_b32_e32 v21, v8, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v24, v24, v14
	v_and_b32_e32 v14, 1, v25
	v_fma_f32 v28, v28, v31, 1.0
	v_xor3_b32 v5, v21, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, -v17, v28, s0
	v_mul_f32_e32 v28, v29, v29
	v_cmp_eq_u32_e64 s0, 0, v14
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v18, v15
	v_fmaak_f32 v18, s1, v28, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v18, v28, v18, 0xbe2aaa9d
	v_dual_fmaak_f32 v31, v33, v32, 0x3d2aabf7 :: v_dual_mul_f32 v18, v28, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v17, v33, v31, 0xbf000004
	v_mul_f32_e32 v31, v38, v38
	v_fmac_f32_e32 v29, v29, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v33, v17, 1.0
	v_fmaak_f32 v32, s2, v31, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, -v24, v17, s0
	v_dual_fmaak_f32 v24, s2, v28, 0xbab64f3b :: v_dual_lshlrev_b32 v17, 30, v25
	v_fmaak_f32 v25, s1, v31, 0x3c0881c4
	v_and_b32_e32 v17, 0x80000000, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v24, v28, v24, 0x3d2aabf7
	v_fmaak_f32 v25, v31, v25, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v17, v14
	v_dual_fmaak_f32 v17, v28, v24, 0xbf000004 :: v_dual_mul_f32 v24, v31, v25
	v_lshlrev_b32_e32 v25, 30, v40
	v_fmaak_f32 v32, v31, v32, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v14, 0x7fc00000, v14, vcc_lo
	v_fma_f32 v17, v28, v17, 1.0
	v_fmac_f32_e32 v38, v38, v24
	v_and_b32_e32 v24, 1, v40
	v_fmaak_f32 v18, v31, v32, 0xbf000004
	v_dual_mul_f32 v14, v19, v14 :: v_dual_and_b32 v25, 0x80000000, v25
	v_and_b32_e32 v28, 1, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s0, 0, v24
	v_fma_f32 v18, v31, v18, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v25
	v_lshlrev_b32_e32 v30, 30, v30
	v_cndmask_b32_e64 v18, v18, v38, s0
	v_cmp_eq_u32_e64 s0, 0, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor3_b32 v8, v8, v18, v7
	v_cndmask_b32_e32 v7, 0x7fc00000, v15, vcc_lo
	v_cndmask_b32_e64 v17, -v29, v17, s0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, 0x7fc00000, v8 :: v_dual_mul_f32 v7, v9, v7
	v_fma_f32 v9, v20, -v16, -v14
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v8, v0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, v5, -v6, -v7
	v_mul_f32_e32 v6, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v23, v22, -v8
	v_fmac_f32_e32 v6, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v26, v7
	v_mul_f32_e32 v5, v12, v5
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v5, v4, v5 :: v_dual_and_b32 v24, 0x80000000, v30
	v_xor_b32_e32 v15, v24, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0x7fc00000, v15, vcc_lo
	v_dual_cndmask_b32 v15, 0x7fc00000, v27 :: v_dual_mul_f32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, v15, -v23, -v0
	v_add_f32_e32 v0, v6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v13, v0
	v_fmac_f32_e32 v5, v4, v0
.LBB1_170:                              ; %atomicrmw.start615
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v5
	global_atomic_cmpswap_b32 v0, v[2:3], v[0:1], off offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_170
.LBB1_171:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 72
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_, .Lfunc_end1-_Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 34628
; NumSgprs: 22
; NumVgprs: 72
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 72
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13AffineForwardPKfPKiS0_iPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13AffineForwardPKfPKiS0_iPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     68
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z14AffineBackwardPKfPKiS0_iS0_S0_PfS3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     72
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
