#include "includes.h"
__device__ void set_shared(int *buff, int* G,int off1 , int off2,int n)
{
int m = blockIdx.x+off1*gridDim.x;
int l = threadIdx.x+off2*blockDim.x;
int maxx = blockDim.x-1;

if(m<n && l<n)
{
//If we reach the last element check if n is less than the number of threads
//or if it's the last element of the current row/block
if(l==n-1){
if(blockDim.x > n)
maxx = n-1;
else if(n/blockDim.x==off2)
maxx = (n-1)%blockDim.x;
}

//The first element of each block will write the left corner
//and the last element the right one
if((threadIdx.x ==0 || threadIdx.x==maxx) && maxx!=0)
{
int ad;
//Check if it's the first or the last thread of the block
if(threadIdx.x==0)
ad = -2;
else
ad = 0;

for (int i = m-2; i <= m+2 ; i++)
{
for (int j = l+ad; j <= l+ad+2; j++)
{
int h1 = i - m;
int h2 = j - l;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2+h2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+j)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}
}
}
//Special case for maxx==0:it means the first element is the last one too
//it is necessary to write both sides in share memory
else if(threadIdx.x==maxx && maxx==0)
{
for (int i = m-2; i <= m+2 ; i++)
{
for (int j = l-2; j <= l+2; j++)
{
int h1 = i - m;
int h2 = j - l;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2+h2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+j)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}
}
}
//write only the values above and bellow you
else
{
for (int i = m-2; i <= m+2 ; i++)
{
int h1 = i - m;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+l)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}

}
}
}
__global__ void gpu_update_sign(int *G, double *w , int k , int n ,int *temp, int *flag,int it_b ,int it_t)
{

int buf=0;

__shared__ int buff[5140];

for (int off1 = 0; off1 < it_b; off1++)
{
for(int off2 = 0; off2<it_t;off2++){
//set share memory in every iteration
set_shared(buff,  G, off1 ,  off2, n);

int result;
double sum = 0.0;

//Find the indexes
int x = blockIdx.x+off1*gridDim.x;
int y = threadIdx.x+off2*blockDim.x;
//Sync thread to be sure the share memory is ok
__syncthreads();

if(x<n && y<n){
//Calculate the result
for (int i = 0; i < k; i++){
for (int j = 0; j < k; j++){
sum += ((double)buff[i*(blockDim.x+4)+(threadIdx.x+j)])*w[i*k+j];
}
}
//Evaluate it
if ( sum > 1e-6){
result = 1;
if (result != buff[2*(blockDim.x+4)+threadIdx.x+2])
buf++;
}
else if( sum < -(1e-6)){
result = -1;
if (result != buff[2*(blockDim.x+4)+threadIdx.x+2])
buf++;
}
else
result = buff[2*(blockDim.x+4)+threadIdx.x+2];
//write to final array
temp[x*n+y] =result;
}
//For stability of share memory setting
__syncthreads();
}
//For stability of share memory setting
__syncthreads();
}
*flag+=buf;
}
	.file	"tmpxft_002dde28_00000000-6_gpu_update_sign.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10set_sharedPiS_iii
	.type	_Z10set_sharedPiS_iii, @function
_Z10set_sharedPiS_iii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z10set_sharedPiS_iii, .-_Z10set_sharedPiS_iii
	.globl	_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii
	.type	_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii, @function
_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z15gpu_update_signPiPdiiS_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L4:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii, .-_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii
	.globl	_Z15gpu_update_signPiPdiiS_S_ii
	.type	_Z15gpu_update_signPiPdiiS_S_ii, @function
_Z15gpu_update_signPiPdiiS_S_ii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z15gpu_update_signPiPdiiS_S_iiPiPdiiS_S_ii
	.cfi_endproc
.LFE2034:
	.size	_Z15gpu_update_signPiPdiiS_S_ii, .-_Z15gpu_update_signPiPdiiS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15gpu_update_signPiPdiiS_S_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15gpu_update_signPiPdiiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ void set_shared(int *buff, int* G,int off1 , int off2,int n)
{
int m = blockIdx.x+off1*gridDim.x;
int l = threadIdx.x+off2*blockDim.x;
int maxx = blockDim.x-1;

if(m<n && l<n)
{
//If we reach the last element check if n is less than the number of threads
//or if it's the last element of the current row/block
if(l==n-1){
if(blockDim.x > n)
maxx = n-1;
else if(n/blockDim.x==off2)
maxx = (n-1)%blockDim.x;
}

//The first element of each block will write the left corner
//and the last element the right one
if((threadIdx.x ==0 || threadIdx.x==maxx) && maxx!=0)
{
int ad;
//Check if it's the first or the last thread of the block
if(threadIdx.x==0)
ad = -2;
else
ad = 0;

for (int i = m-2; i <= m+2 ; i++)
{
for (int j = l+ad; j <= l+ad+2; j++)
{
int h1 = i - m;
int h2 = j - l;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2+h2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+j)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}
}
}
//Special case for maxx==0:it means the first element is the last one too
//it is necessary to write both sides in share memory
else if(threadIdx.x==maxx && maxx==0)
{
for (int i = m-2; i <= m+2 ; i++)
{
for (int j = l-2; j <= l+2; j++)
{
int h1 = i - m;
int h2 = j - l;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2+h2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+j)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}
}
}
//write only the values above and bellow you
else
{
for (int i = m-2; i <= m+2 ; i++)
{
int h1 = i - m;
int b_ind_x = 2+h1;
int b_ind_y = threadIdx.x+2;
int g_ind_x = (n+i)%n;
int g_ind_y = (n+l)%n;
buff[b_ind_x*(blockDim.x+4)+b_ind_y] = G[g_ind_x*n+g_ind_y];
}

}
}
}
__global__ void gpu_update_sign(int *G, double *w , int k , int n ,int *temp, int *flag,int it_b ,int it_t)
{

int buf=0;

__shared__ int buff[5140];

for (int off1 = 0; off1 < it_b; off1++)
{
for(int off2 = 0; off2<it_t;off2++){
//set share memory in every iteration
set_shared(buff,  G, off1 ,  off2, n);

int result;
double sum = 0.0;

//Find the indexes
int x = blockIdx.x+off1*gridDim.x;
int y = threadIdx.x+off2*blockDim.x;
//Sync thread to be sure the share memory is ok
__syncthreads();

if(x<n && y<n){
//Calculate the result
for (int i = 0; i < k; i++){
for (int j = 0; j < k; j++){
sum += ((double)buff[i*(blockDim.x+4)+(threadIdx.x+j)])*w[i*k+j];
}
}
//Evaluate it
if ( sum > 1e-6){
result = 1;
if (result != buff[2*(blockDim.x+4)+threadIdx.x+2])
buf++;
}
else if( sum < -(1e-6)){
result = -1;
if (result != buff[2*(blockDim.x+4)+threadIdx.x+2])
buf++;
}
else
result = buff[2*(blockDim.x+4)+threadIdx.x+2];
//write to final array
temp[x*n+y] =result;
}
//For stability of share memory setting
__syncthreads();
}
//For stability of share memory setting
__syncthreads();
}
*flag+=buf;
}
	.text
	.file	"gpu_update_sign.hip"
	.globl	_Z30__device_stub__gpu_update_signPiPdiiS_S_ii # -- Begin function _Z30__device_stub__gpu_update_signPiPdiiS_S_ii
	.type	_Z30__device_stub__gpu_update_signPiPdiiS_S_ii,@function
_Z30__device_stub__gpu_update_signPiPdiiS_S_ii: # @_Z30__device_stub__gpu_update_signPiPdiiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15gpu_update_signPiPdiiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__gpu_update_signPiPdiiS_S_ii, .Lfunc_end0-_Z30__device_stub__gpu_update_signPiPdiiS_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15gpu_update_signPiPdiiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15gpu_update_signPiPdiiS_S_ii,@object # @_Z15gpu_update_signPiPdiiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z15gpu_update_signPiPdiiS_S_ii
	.p2align	3, 0x0
_Z15gpu_update_signPiPdiiS_S_ii:
	.quad	_Z30__device_stub__gpu_update_signPiPdiiS_S_ii
	.size	_Z15gpu_update_signPiPdiiS_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15gpu_update_signPiPdiiS_S_ii"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__gpu_update_signPiPdiiS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15gpu_update_signPiPdiiS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15gpu_update_signPiPdiiS_S_ii ; -- Begin function _Z15gpu_update_signPiPdiiS_S_ii
	.globl	_Z15gpu_update_signPiPdiiS_S_ii
	.p2align	8
	.type	_Z15gpu_update_signPiPdiiS_S_ii,@function
_Z15gpu_update_signPiPdiiS_S_ii:        ; @_Z15gpu_update_signPiPdiiS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x28
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_42
; %bb.1:                                ; %.preheader61.lr.ph
	s_load_b64 s[12:13], s[0:1], 0x10
	s_cmp_gt_i32 s3, 0
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v0
	s_cselect_b32 s14, -1, 0
	s_add_u32 s16, s0, 48
	s_addc_u32 s17, s1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 40, v5
	v_add_nc_u32_e32 v8, 8, v5
	s_mov_b32 s20, 0xa0b5ed8d
	s_mov_b32 s19, 0
	s_mov_b32 s21, 0x3eb0c6f7
	s_mov_b32 s23, 0xbeb0c6f7
	s_mov_b32 s33, 0
	v_add_nc_u32_e32 v6, -1, v0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s26, s13, -1
	s_cmp_gt_i32 s12, 0
	v_add_nc_u32_e32 v9, s13, v0
	s_cselect_b32 s27, -1, 0
	s_ashr_i32 s8, s13, 31
	s_mov_b32 s29, s13
	s_add_i32 s9, s13, s8
	s_add_i32 s30, s13, -2
	s_xor_b32 s28, s9, s8
	s_load_b128 s[8:11], s[0:1], 0x0
	v_cvt_f32_u32_e32 v1, s28
	s_sub_i32 s18, 0, s28
	v_cmp_ne_u32_e64 s0, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_mul_i32 s18, s18, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s18, s1, s18
	s_add_i32 s31, s1, s18
.LBB0_2:                                ; %.preheader61
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_15 Depth 4
                                        ;       Child Loop BB0_21 Depth 3
                                        ;       Child Loop BB0_24 Depth 3
                                        ;         Child Loop BB0_25 Depth 4
                                        ;       Child Loop BB0_30 Depth 3
                                        ;         Child Loop BB0_31 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_41
; %bb.3:                                ; %.lr.ph72
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	s_load_b32 s1, s[16:17], 0x0
	s_load_b32 s18, s[16:17], 0xc
	s_mov_b32 s41, 0
	v_mov_b32_e32 v12, v9
	v_mov_b32_e32 v18, v6
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s34, s1, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s34, s34, s15
	s_cmp_lt_u32 s15, s1
	s_mul_i32 s35, s34, s13
	s_cselect_b32 s1, 12, 18
	s_cmp_lt_i32 s34, s13
	v_mov_b32_e32 v1, s1
	s_cselect_b32 s36, -1, 0
	global_load_u16 v10, v1, s[16:17]
	s_waitcnt vmcnt(0)
	v_cvt_f32_u32_e32 v1, v10
	v_sub_nc_u32_e32 v2, 0, v10
	v_lshlrev_b32_e32 v14, 2, v10
	v_readfirstlane_b32 s1, v10
	v_mov_b32_e32 v11, v0
	v_rcp_iflag_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, 16, v14
	s_cmp_gt_u32 s1, s13
	s_cselect_b32 s37, -1, 0
	s_and_b32 s40, s18, 0xffff
	s_add_i32 s38, s34, -2
	s_lshl_b32 s42, s40, 2
	s_add_i32 s39, s34, 2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_add_i32 s42, s42, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v2, s26, v1
	v_mul_hi_u32 v1, s29, v1
	v_mul_lo_u32 v2, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, v1, v10
	v_add_nc_u32_e32 v15, 1, v1
	v_sub_nc_u32_e32 v2, s26, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, s13, v3
	v_sub_nc_u32_e32 v16, v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v17, v3, v10
	v_cmp_ge_u32_e32 vcc_lo, v3, v10
	v_cmp_ge_u32_e64 s1, v2, v10
	v_cndmask_b32_e32 v1, v1, v15, vcc_lo
	v_cndmask_b32_e32 v3, v3, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, v2, v16, s1
	v_lshl_add_u32 v15, s40, 3, v7
	v_add_nc_u32_e32 v16, 1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ge_u32_e32 vcc_lo, v3, v10
	v_add_nc_u32_e32 v13, -1, v10
	v_sub_nc_u32_e32 v17, v2, v10
	v_cndmask_b32_e32 v16, v1, v16, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v2, v10
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v17, v2, v17, vcc_lo
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;         Child Loop BB0_15 Depth 4
                                        ;       Child Loop BB0_21 Depth 3
                                        ;       Child Loop BB0_24 Depth 3
                                        ;         Child Loop BB0_25 Depth 4
                                        ;       Child Loop BB0_30 Depth 3
                                        ;         Child Loop BB0_31 Depth 4
	v_mad_u64_u32 v[1:2], null, s41, v10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s13, v1
	s_and_b32 s1, s36, vcc_lo
	s_and_saveexec_b32 s18, s1
	s_cbranch_execz .LBB0_27
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, s26, v1
	v_cndmask_b32_e32 v2, v1, v13, vcc_lo
	s_or_b32 s1, vcc_lo, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s22, s1, -1
	s_and_saveexec_b32 s1, s22
	s_cbranch_execz .LBB0_8
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, s41, v16
	v_mov_b32_e32 v2, v13
	s_cbranch_vccnz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v2, v17
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s24, 0
	s_mov_b32 s22, 0
                                        ; implicit-def: $sgpr25
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s43, exec_lo, s1
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, v0, v2
	v_cmp_eq_u32_e64 s1, v0, v2
	s_mov_b32 s25, 0
	s_and_b32 s22, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s24, s1, exec_lo
; %bb.10:                               ; %Flow169
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_saveexec_b32 s1, s43
	v_mov_b32_e32 v21, s25
	s_xor_b32 exec_lo, exec_lo, s1
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_mov_b32_e32 v21, -2
	s_and_not1_b32 s24, s24, exec_lo
	s_or_b32 s22, s22, exec_lo
	s_and_b32 s25, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s24, s24, s25
; %bb.12:                               ; %Flow170
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s24
	s_cbranch_execz .LBB0_18
; %bb.13:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add3_u32 v3, v21, v1, 2
	v_add_nc_u32_e32 v19, v21, v18
	v_add_nc_u32_e32 v20, v21, v12
	v_lshl_add_u32 v21, v21, 2, v8
	s_mov_b32 s24, s38
.LBB0_14:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_15 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s25, s24, s13
	v_dual_mov_b32 v22, v21 :: v_dual_mov_b32 v23, v20
	s_ashr_i32 s43, s25, 31
	v_mov_b32_e32 v24, v19
	s_add_i32 s25, s25, s43
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s25, s25, s43
	s_mul_hi_u32 s44, s25, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s44, s44, s28
	s_sub_i32 s25, s25, s44
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s44, s25, s28
	s_cmp_ge_u32 s25, s28
	s_cselect_b32 s25, s44, s25
	s_sub_i32 s44, s25, s28
	s_cmp_ge_u32 s25, s28
	s_cselect_b32 s25, s44, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s25, s25, s43
	s_sub_i32 s43, s25, s43
	s_mov_b32 s25, 0
	s_mul_i32 s43, s43, s13
.LBB0_15:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_14 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_ashrrev_i32_e32 v25, 31, v23
	v_add_nc_u32_e32 v24, 1, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, v23, v25
	v_add_nc_u32_e32 v23, 1, v23
	v_xor_b32_e32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v27, v26, s31
	v_mul_lo_u32 v27, v27, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v26, v26, v27
	v_subrev_nc_u32_e32 v27, s28, v26
	v_cmp_le_u32_e32 vcc_lo, s28, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v26, v27, vcc_lo
	v_subrev_nc_u32_e32 v27, s28, v26
	v_cmp_le_u32_e32 vcc_lo, s28, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v26, v27, vcc_lo
	v_xor_b32_e32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v25, v26, v25
	v_add_nc_u32_e32 v25, s43, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, s8, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v24, v3
	global_load_b32 v25, v[25:26], off
	s_or_b32 s25, vcc_lo, s25
	s_waitcnt vmcnt(0)
	ds_store_b32 v22, v25
	v_add_nc_u32_e32 v22, 4, v22
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_15
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=3
	s_or_b32 exec_lo, exec_lo, s25
	v_add_nc_u32_e32 v21, v21, v14
	s_add_i32 s25, s24, 1
	s_cmp_ge_i32 s24, s39
	s_mov_b32 s24, s25
	s_cbranch_scc0 .LBB0_14
; %bb.17:                               ; %Flow163
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_b32 s22, s22, exec_lo
.LBB0_18:                               ; %Flow171
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s22
	s_cbranch_execz .LBB0_27
; %bb.19:                               ;   in Loop: Header=BB0_4 Depth=2
	v_or_b32_e32 v2, v2, v0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v2
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_22
; %bb.20:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v1, s13, v1
	v_mov_b32_e32 v19, v8
	s_mov_b32 s22, s34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v2
	v_mul_hi_u32 v3, v1, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v3, s28
	v_sub_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s28, v1
	v_cmp_le_u32_e32 vcc_lo, s28, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v3, s28, v1
	v_cmp_le_u32_e32 vcc_lo, s28, v1
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v1, v2
	v_sub_nc_u32_e32 v3, v1, v2
.LBB0_21:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_i32 s24, s30, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s25, s24, 31
	s_add_i32 s24, s24, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s24, s24, s25
	s_mul_hi_u32 s43, s24, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s43, s43, s28
	s_sub_i32 s24, s24, s43
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s43, s24, s28
	s_cmp_ge_u32 s24, s28
	s_cselect_b32 s24, s43, s24
	s_sub_i32 s43, s24, s28
	s_cmp_ge_u32 s24, s28
	s_cselect_b32 s24, s43, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s24, s24, s25
	s_sub_i32 s24, s24, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s24, s13, v[3:4]
	s_add_i32 s24, s22, -2
	s_add_i32 s22, s22, 1
	s_cmp_ge_i32 s24, s39
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s8, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v1
	v_add_nc_u32_e32 v19, v19, v14
                                        ; implicit-def: $vgpr1_vgpr2
	s_cbranch_scc0 .LBB0_21
.LBB0_22:                               ; %Flow166
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_27
; %bb.23:                               ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v2, v5 :: v_dual_add_nc_u32 v1, 2, v1
	s_mov_b32 s1, s38
.LBB0_24:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_25 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s22, s1, s13
	v_mov_b32_e32 v3, v2
	s_ashr_i32 s24, s22, 31
	v_mov_b32_e32 v19, v11
	s_add_i32 s22, s22, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s22, s22, s24
	s_mul_hi_u32 s25, s22, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s25, s25, s28
	s_sub_i32 s22, s22, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s25, s22, s28
	s_cmp_ge_u32 s22, s28
	s_cselect_b32 s22, s25, s22
	s_sub_i32 s25, s22, s28
	s_cmp_ge_u32 s22, s28
	s_cselect_b32 s22, s25, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s22, s22, s24
	s_sub_i32 s24, s22, s24
	s_mov_b32 s22, 0
	s_mul_i32 s24, s24, s13
.LBB0_25:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_24 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_add_nc_u32_e32 v20, s30, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v21, 31, v20
	v_add_nc_u32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v20, v20, v21
	v_mul_hi_u32 v22, v20, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v22, v22, s28
	v_sub_nc_u32_e32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v22, s28, v20
	v_cmp_le_u32_e32 vcc_lo, s28, v20
	v_cndmask_b32_e32 v20, v20, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v22, s28, v20
	v_cmp_le_u32_e32 vcc_lo, s28, v20
	v_cndmask_b32_e32 v20, v20, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v20, v20, v21
	v_sub_nc_u32_e32 v20, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, s24, v20
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v20, vcc_lo, s8, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v21, vcc_lo
	global_load_b32 v20, v[20:21], off
	v_add_nc_u32_e32 v21, -2, v19
	v_add_nc_u32_e32 v19, 1, v19
	v_cmp_ge_i32_e32 vcc_lo, v21, v1
	s_or_b32 s22, vcc_lo, s22
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v20
	v_add_nc_u32_e32 v3, 4, v3
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_25
; %bb.26:                               ;   in Loop: Header=BB0_24 Depth=3
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v2, v2, v14
	s_add_i32 s22, s1, 1
	s_cmp_ge_i32 s1, s39
	s_mov_b32 s1, s22
	s_cbranch_scc0 .LBB0_24
.LBB0_27:                               ; %Flow174
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	v_mad_u64_u32 v[1:2], null, s41, s40, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s13, v1
	s_and_b32 s18, s36, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s18
	s_cbranch_execz .LBB0_40
; %bb.28:                               ; %.preheader58
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_and_not1_b32 vcc_lo, exec_lo, s27
	s_cbranch_vccnz .LBB0_33
; %bb.29:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v19, v5
	s_mov_b32 s18, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s22, s18
.LBB0_30:                               ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_31 Depth 4
	s_lshl_b64 s[24:25], s[18:19], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v20, v19
	s_add_u32 s24, s10, s24
	s_addc_u32 s25, s11, s25
	s_mov_b32 s43, s12
.LBB0_31:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_30 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	ds_load_b32 v21, v20
	s_load_b64 s[44:45], s[24:25], 0x0
	s_add_i32 s43, s43, -1
	v_add_nc_u32_e32 v20, 4, v20
	s_add_u32 s24, s24, 8
	s_addc_u32 s25, s25, 0
	s_cmp_eq_u32 s43, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[21:22], v21
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], s[44:45], v[21:22], v[2:3]
	s_cbranch_scc0 .LBB0_31
; %bb.32:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_30 Depth=3
	v_add_nc_u32_e32 v19, s42, v19
	s_add_i32 s22, s22, 1
	s_add_i32 s18, s18, s12
	s_cmp_eq_u32 s22, s12
	s_cbranch_scc0 .LBB0_30
.LBB0_33:                               ; %._crit_edge66
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s18, exec_lo
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_nlt_f64_e32 s[20:21], v[2:3]
	s_xor_b32 s18, exec_lo, s18
	s_cbranch_execz .LBB0_37
; %bb.34:                               ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s22, s20
	ds_load_b32 v19, v15
	v_cmp_gt_f64_e32 vcc_lo, s[22:23], v[2:3]
	s_and_saveexec_b32 s22, vcc_lo
	s_cbranch_execz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, -1, v19
	v_mov_b32_e32 v19, -1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_36:                               ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_37:                               ; %Flow159
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_and_not1_saveexec_b32 s18, s18
	s_cbranch_execz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_4 Depth=2
	ds_load_b32 v2, v15
	s_waitcnt lgkmcnt(1)
	v_mov_b32_e32 v19, 1
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 1, v2
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_39:                               ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	v_add_nc_u32_e32 v1, s35, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[1:2], v19, off
.LBB0_40:                               ; %Flow162
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v18, v18, v10
	v_add_nc_u32_e32 v12, v12, v10
	v_add_nc_u32_e32 v11, v11, v10
	s_add_i32 s41, s41, 1
	s_waitcnt_vscnt null, 0x0
	s_cmp_eq_u32 s41, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_41:                               ; %._crit_edge73
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s33, s33, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s33, s2
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_43
.LBB0_42:
	v_mov_b32_e32 v4, 0
.LBB0_43:                               ; %._crit_edge77
	v_mov_b32_e32 v0, 0
	global_load_b32 v1, v0, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, v1, v4
	global_store_b32 v0, v1, s[6:7]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15gpu_update_signPiPdiiS_S_ii
		.amdhsa_group_segment_fixed_size 20560
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15gpu_update_signPiPdiiS_S_ii, .Lfunc_end0-_Z15gpu_update_signPiPdiiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2152
; NumSgprs: 48
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20560 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20560
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15gpu_update_signPiPdiiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     48
    .sgpr_spill_count: 0
    .symbol:         _Z15gpu_update_signPiPdiiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
