//2 layered neural network with LIF neurons
//computing Vm in parallel, Computing Isyn 
//all-all connectivity between 2 layers
//starting point of reading mnist set by 'start'
 
#include<stdio.h>
#include<math.h>
#include<time.h>
#include<stdlib.h>
#include "device_launch_parameters.h"
#include "cuda_runtime_api.h"

#define C 300E-12
#define gL 30E-9
#define VT 20E-3
#define EL -70E-3
#define Rp 3E-3
#define dt 1E-4
#define decay 0.9802
#define decays 0.9231
#define decay1 0.9048
#define WT 5E-9

#define w_lat -1.0E-9		//inhibitory lateral strength

//num of neurons in layer 1 and layer 2
#define p 28
#define q 28
#define N_imgs 50000
#define N2 10		    //no. of neurons in 2nd layer

//Convolution parameters
#define Nw 3
#define L (p-Nw+1)	     //square matrix
#define N1 (12*L*L)	     //no. of neurons in 1st layer
#define Nthrds 1024          //use max no. of threads available per SM
#define Nsyns N1*N2	     //no. of connections
#define T 0.1
#define M 1000

//Training parameters:
#define r 20.0E-11	     //Learning Rate for 100ms 
#define max_epochs 20	     //1 complete presentation of all images

//Variables for image reading
unsigned char *pix_spks_d;
int *d_imgs_lin, img_lin[N_imgs*(p*q+1)];
int test_set[N_imgs][p*q+1];
__device__ int d_imgs[N_imgs][p*q+1];
__device__ double img_spks[p*q][M];
__device__ double syn1[256], syn1s[256], syn[256][M];

__device__ unsigned char in_spk[N1];
__device__ double Isyn[N1][N2], weight[N1][N2];
__device__ double Isyn_tot[N2], Isyn_lat[N2];
__device__ double I_lat[N2];

//weight update variables:
__device__ unsigned char D_op[N2][M];
__device__ signed char err[N2];
__device__ unsigned char Y_op[N2];
__device__ double del_w[N1][N2]; 
__device__ double ci[N1], d_hat[N1];
__device__ double cis[N1], norm_dh; 
__device__ double cil[N2], cils[N2];
__device__ double d_hat_sq[N1];

//Neuron variables:
__device__ int ref_time1[N1],ref_time2[N2];
__device__ double Vm1[N1],Vm2[N2];

////////////CUDA Kernels///////////
__global__ void img_readKernel(int *img)
{
    for(int i=0; i<N_imgs; i++){
        for(int j=0; j<(p*q+1); j++){
	    d_imgs[i][j]=img[i*(p*q+1)+j];
	}
    }
}

__device__ unsigned char pix_spks[256][M];
unsigned char pix_spks_h[256*M];

//uniformly spaced spikes
__global__ void convert2Spks(unsigned char *pix_spks_d)
{

    for(int i=0; i<256; i++) {
	syn1[i]=0.0; syn1s[i]=0.0;
        for(int l=0; l<M; l++) {
	    pix_spks[i][l]=pix_spks_d[i*M+l];
	}
    }

    //Compute the synaptic kernels:
    for(int i=0; i<256; i++) {
        for(int l=0; l<M; l++) {
            syn1[i]*=decay; syn1s[i]*=decays;
            if(pix_spks[i][l]==1) {
                syn1[i]+=1.0;
                syn1s[i]+=1.0;
            }
            syn[i][l]=syn1[i]-syn1s[i];
	}
    }
}

unsigned char pixspks[256*M];

__global__ void pix2spks(int k, int i) 
{
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<(p*q)) {
	img_spks[tx][i]=syn[d_imgs[k][tx+1]][i];
        __syncthreads();
    }
}


__global__ void createDes(int k) {
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<N2) {
	for(int i=0; i<M;i++) {
	    D_op[tx][i]=0;
	}
	if(tx==d_imgs[k][0]) {
	    for(int i=100; i<M; i+=35) 
		D_op[tx][i]=1;
	}
    }
}

/*__global__ void pix2spks(int k)
{
    //Load the spikes trains for the corresponding pixels:
    for(int i=1; i<(p*q+1); i++) {
         for(int l=0; l<M; l++) {
             img_spks[i-1][l]=syn[d_imgs[k][i]][l];
         }
    }

    //Create the desired spike trains:
    for(int j=0; j<N2; j++) {
        for(int i=0; i<M; i++) {
            D_op[j][i]=0;
        }
        if(j==d_imgs[k][0]) {
            //for(int i=100; i<M; i+=50)
            for(int i=100; i<M; i+=35)
                D_op[j][i]=1;
        }
    }
}*/

__device__ double I_in[N1];

__global__ void clear_vars()
{
    int tx=threadIdx.x+blockIdx.x*blockDim.x;
    int ty=threadIdx.y+blockIdx.y*blockDim.y;

    if(tx<N1 && ty<N2) {
    	Vm2[ty]=EL; Isyn_tot[ty]=0.0; 
	ref_time2[ty]=0.0;
	Vm1[tx]=EL; ref_time1[tx]=0.0;
	I_in[tx]=0.0;

	del_w[tx][ty]=0.0; 
	Isyn[tx][ty]=0.0; 
	ci[tx]=0.0; cis[tx]=0.0; d_hat[tx]=0.0;

	cil[ty]=0.0; cils[ty]=0.0;
	Isyn_lat[ty]=0.0;
    }
}

__global__ void LifKernel1(int i)
{
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    double k1, k2;

    if(j<N1) {
	
	if(ref_time1[j]<i) ref_time1[j]=0;

        k1=(-gL*(Vm1[j]-EL)+I_in[j])/C;
	k2=(-gL*((Vm1[j]+dt*k1)-EL)+I_in[j])/C;

	Vm1[j]+=(dt*(k1+k2)/2)*(ref_time1[j]==0);

	if(Vm1[j]<EL) Vm1[j]=EL;

        if(Vm1[j]>=VT) {
	    Vm1[j]=EL;
	    ref_time1[j]=i+round(Rp/dt);
	    in_spk[j]=1;
	} else {
	    in_spk[j]=0;
	}
        __syncthreads();
    }
}

__global__ void LifKernel2(int i)
{
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    double k1, k2;

    if(j<N2) {
	if(ref_time2[j]<i) ref_time2[j]=0;

        k1=(-gL*(Vm2[j]-EL)+Isyn_tot[j]+Isyn_lat[j])/C;
	k2=(-gL*((Vm2[j]+dt*k1)-EL)+Isyn_tot[j]+Isyn_lat[j])/C;

	Vm2[j]+=(dt*(k1+k2)/2)*(ref_time2[j]==0);
	if(Vm2[j]<EL) Vm2[j]=EL;

        if(Vm2[j]>=VT) {
	    Vm2[j]=EL;
	    ref_time2[j]=i+round(Rp/dt);
	    Y_op[j]=1;
	} else {
	    Y_op[j]=0;
	}

	//compute the error:
	err[j]=D_op[j][i]-Y_op[j];

        __syncthreads();
    }
}

//kernels for the total synapses in the network
__global__ void SynKernel(int i)
{
    int ix=blockIdx.x*blockDim.x + threadIdx.x;
    int iy=blockIdx.y*blockDim.y + threadIdx.y;

    if(ix<N1 && iy<N2) {
        if(iy==0) {
   	    ci[ix]=ci[ix]*decay;
	    cis[ix]=cis[ix]*decays;
            if(in_spk[ix]==1) {
	        ci[ix]+=1.0;
	        cis[ix]+=1.0;
	    }
	    d_hat[ix]=d_hat[ix]*decay1 + ((ci[ix]-cis[ix])*dt)/C;
	    d_hat_sq[ix]=d_hat[ix]*d_hat[ix];

	}
	__syncthreads();
        Isyn[ix][iy]=(ci[ix]-cis[ix])*weight[ix][iy];
    }
}

__global__ void Lat_curr(int i)
{
    int ix=blockIdx.x*blockDim.x+threadIdx.x;

    if(ix<N2) {
   	cil[ix]=cil[ix]*decay;
	cils[ix]=cils[ix]*decays;
        if(Y_op[ix]==1) {
	    cil[ix]+=1.0;
	    cils[ix]+=1.0;
	}

	I_lat[ix]=w_lat*(cil[ix]-cils[ix]);

	Isyn_lat[ix]=0;
	for(int k=0; k<N2; k++) {
	    if(k!=ix) {
		Isyn_lat[ix]+=I_lat[k];
	    }
	}
    }
}

__device__ double total_curr[8][N2];
__device__ double total_dhatsq[8];

//optimized version
__global__ void IsynRedKernel(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int tid=threadIdx.x;

    for(unsigned int s=blockDim.x/2;s>0;s>>=1) {
        if(iy<N2 && tid<s && (ix+s)<N1) {
	    Isyn[ix][iy]+=Isyn[ix+s][iy];
	}
	if(iy==0 && tid<s && (ix+s)<N1) {
	    d_hat_sq[ix]+=d_hat_sq[ix+s];
        }
	__syncthreads();
    }

    if(tid==0 && iy<N2) {
	total_curr[blockIdx.x][iy]=Isyn[ix][iy];
	if(iy==0) {
	    total_dhatsq[blockIdx.x]=d_hat_sq[ix];
	}
    }
}

__global__ void reduce1(int i) {
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<N2) {
	double total1=0.0;
	for(int k=0; k<8; k++) {
	    total1+=total_curr[k][tx];
	}
	Isyn_tot[tx]=total1;

        if(tx==0) {
	    double total2=0.0;
	    for(int j=0; j<8; j++) 
		total2+=total_dhatsq[j];

	    norm_dh=sqrt(total2);
	}
    }
}

__global__ void CalcUpdate(int i, double l_rate)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
        if(norm_dh!=0 && err[iy]!=0) {
	    del_w[ix][iy]+=(err[iy]*l_rate*d_hat[ix]/norm_dh);
	}
	__syncthreads();
    }
}

__global__ void WtUpdt()
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
        weight[ix][iy]+=del_w[ix][iy];
    }
}

__global__ void cpyWts(double *wts)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
	wts[ix*N2+iy]=weight[ix][iy];
    }
}

__device__ double w_conv1[Nw][Nw], w_conv2[Nw][Nw];
__device__ double w_conv3[Nw][Nw], w_conv4[Nw][Nw];
__device__ double w_conv5[Nw][Nw], w_conv6[Nw][Nw];
__device__ double w_conv7[Nw][Nw], w_conv8[Nw][Nw];
__device__ double w_conv9[Nw][Nw], w_conv10[Nw][Nw];
__device__ double w_conv11[Nw][Nw], w_conv12[Nw][Nw];

__global__ void initialize2D(double *d_wts, double *c_wts)
{
   for(int i=0; i<N1; i++) {
       for(int j=0; j<N2; j++) {
           weight[i][j]=d_wts[i*N2+j];
	}
    }

    for(int i=0; i<(12*Nw); i++) {
        for(int j=0; j<Nw; j++) {
	    if(i<Nw) {
	    	w_conv1[i][j]=c_wts[i*Nw+j];
	    } else if(i>=Nw && i<(2*Nw)) {
	        w_conv2[i-Nw][j]=c_wts[i*Nw+j];
	    } else if(i>=(2*Nw) && i<(3*Nw)) {
	        w_conv3[i-(2*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(3*Nw) && i<(4*Nw)){
	        w_conv4[i-(3*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(4*Nw) && i<(5*Nw)){
	        w_conv5[i-(4*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(5*Nw) && i<(6*Nw)){
	        w_conv6[i-(5*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(6*Nw) && i<(7*Nw)){
	        w_conv7[i-(6*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(7*Nw) && i<(8*Nw)){
	        w_conv8[i-(7*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(8*Nw) && i<(9*Nw)){
	        w_conv9[i-(8*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(9*Nw) && i<(10*Nw)){
	        w_conv10[i-(9*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(10*Nw) && i<(11*Nw)){
	        w_conv11[i-(10*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(11*Nw) && i<(12*Nw)){
	        w_conv12[i-(11*Nw)][j]=c_wts[i*Nw+j];
	    }
	}
    }
}

__global__ void convKernel1(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv1[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[ix*L+iy]=temp;
    }
}

__global__ void convKernel2(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv2[x][y]*img_spks[(ix+x)*q+iy+y][i]; 
	    }
        }

	I_in[L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel3(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv3[x][y]*img_spks[(ix+x)*q+iy+y][i];
	    }
        }
    
        I_in[2*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel4(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv4[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[3*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel5(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv5[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }
        
	I_in[4*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel6(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv6[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[5*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel7(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv7[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[6*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel8(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv8[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[7*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel9(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv9[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[8*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel10(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv10[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[9*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel11(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv11[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[10*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel12(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv12[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[11*L*L+ix*L+iy]=temp;
    }
}

long timediff(clock_t t1, clock_t t2) {
    long elapsed;
    elapsed = ((double)t2 - t1) / CLOCKS_PER_SEC * 1000;
    return elapsed;
}
 
double h_wts[N1*N2], *d_wts;
double *dcwts;
double h_wts_saved[N1*N2], *d_wts_saved;
double c_wts[12*Nw*Nw];

int main(int argc, char *argv[])
{
    int start=atoi(argv[1]);
    FILE *FW, *FWI;	//to load initial wts and store final wts
    FILE *conv_wt;
 
    clock_t t1, t2;
    long elapsed=0;

    FILE *F_train, *F_lif_spks;

    //for concurrent execution of different kernels:
    cudaStream_t stream2, stream3, stream4, stream5, stream6;
    cudaStream_t stream7, stream8, stream9, stream10, stream11, stream12;
    cudaStream_t stream13, stream14,stream15;

    //set the gpu device:
    cudaSetDevice(4);

    cudaStreamCreate(&stream2);
    cudaStreamCreate(&stream3);
    cudaStreamCreate(&stream4);
    cudaStreamCreate(&stream5);
    cudaStreamCreate(&stream6);
    cudaStreamCreate(&stream7);
    cudaStreamCreate(&stream8);
    cudaStreamCreate(&stream9);
    cudaStreamCreate(&stream10);
    cudaStreamCreate(&stream11);
    cudaStreamCreate(&stream12);
    cudaStreamCreate(&stream13);
    cudaStreamCreate(&stream14);
    cudaStreamCreate(&stream15);

    F_lif_spks = fopen("pixels_spks.csv","r");
    if(F_lif_spks == NULL)
    {
	perror("Error while opening file pixels_spks.csv\n");
	exit(EXIT_FAILURE);
    }

    F_train = fopen("mnist_train.csv","r");
    //F_test = fopen("mnist_test.csv","r");
    if(F_train == NULL)
    {
	perror("Error while opening file mnist_train.csv\n");
	exit(EXIT_FAILURE);
    }

    FWI = fopen("wts_initial.csv","r");
    if(FWI == NULL)
    {
	perror("Error while opening file wts_trained.csv\n");
	exit(EXIT_FAILURE);
    }

    conv_wt=fopen("kernels_3x3.csv","r");
    if(conv_wt==NULL) {
	perror("Error while opening file kernel.csv\n");
    	exit(EXIT_FAILURE);
    }

    printf("Total no. of neurons=%d, no. of synapses to be trained=%d\n",(N1+N2), N1*N2);
    cudaMalloc((void**)&d_imgs_lin,sizeof(int)*(N_imgs*(p*q+1)));
    cudaMalloc((void**)&d_wts,N1*N2*sizeof(double));
    cudaMalloc((void**)&dcwts,12*Nw*Nw*sizeof(double));
    cudaMalloc((void**)&d_wts_saved,N1*N2*sizeof(double));
    cudaMalloc((void**)&pix_spks_d,256*M*sizeof(unsigned char));

    //Read the initial weights: 
    //printf("Reading final trained weights from file\n");
    for(int i=0; i<N1; i++) {
        for(int j=0; j<N2; j++) {
	    fscanf(FWI,"%lf,",&h_wts[i*N2+j]);
	}
    }
    fclose(FWI);

    for(int i=0; i<(12*Nw); i++) {
        for(int j=0; j<Nw; j++) {
	    fscanf(conv_wt,"%lf,",&c_wts[i*Nw+j]);
	}
    }
    fclose(conv_wt);

    for(int i=0; i<(256); i++) {
    	for(int j=0; j<M; j++) {
	    fscanf(F_lif_spks,"%d,",&pix_spks_h[i*M+j]);
	}
    }
    fclose(F_lif_spks);

    cudaMemcpy(pix_spks_d,pix_spks_h,256*M*sizeof(unsigned char),cudaMemcpyHostToDevice);
    cudaMemcpy(d_wts,h_wts,N1*N2*sizeof(double),cudaMemcpyHostToDevice);
    cudaMemcpy(dcwts,c_wts,12*Nw*Nw*sizeof(double),cudaMemcpyHostToDevice);

    initialize2D<<<1,1>>>(d_wts,dcwts);
    cudaDeviceSynchronize();
    cudaFree(d_wts);
    cudaFree(dcwts);

    //Read the images from file:
    for(int n=0;n<N_imgs;n++) {
        for(int j=0;j<(p*q+1);j++) {
            fscanf(F_train,"%d,",&test_set[n][j]);
        }
    }
    fclose(F_train);

    //convert 2D matrix to 1D for transfer to device:
    for(int n=0; n<(N_imgs);n++) {
        for(int j=0;j<(p*q+1);j++) {
            img_lin[n*(p*q+1)+j]=test_set[n][j];
        }
    }

    cudaMemcpy(d_imgs_lin,img_lin,sizeof(int)*(N_imgs*(p*q+1)),cudaMemcpyHostToDevice);

    //call cuda kernel to read in the images:
    img_readKernel<<<1,1>>>(d_imgs_lin);
    cudaThreadSynchronize();
    cudaFree(d_imgs_lin);

    int NBlks=(N1/Nthrds)+1;
    //printf("blocks=%d, threads=%d\n",NBlks,Nthrds);

    dim3 dimGrid(82,1,1);
    dim3 dimBlock(100,10,1);

    dim3 grid_syn(NBlks,10,1);
    dim3 block_syn(Nthrds,1,1);

    //convert pixel values 0 to 255 into spike trains
    convert2Spks<<<1,1>>>(pix_spks_d);
    cudaDeviceSynchronize();
    cudaFree(pix_spks_d);
    
    dim3 convGrid(1,1,1);
    dim3 convBlks(26,26,1);

    double learn=r;
    //CPU time required for computation
    t1 = clock();
           
    int l=0;				//image index
    for(int n=0; n<max_epochs; n++) {
        printf("Epoch=%d\n",n);

	if(n<3) learn=r;
	else if(n>=3 && n<6) learn=r/2;
	else if(n>=6 && n<9) learn=r/4;
	else if(n>=9 && n<12) learn=r/8;
	else if(n>=12 && n<15) learn=r/16;
	else if(n>=15 && n<18) learn=r/32;
	else learn=r/64;

        for(l=0; l<N_imgs; l++) {
            printf("l=%d image %d\n",l,test_set[l][0]);

	    createDes<<<1,10>>>(l);

	    clear_vars<<<dimGrid,dimBlock>>>();
            cudaDeviceSynchronize();

            //simulate for all time steps
            for(int i=0; i<M; i++) {
                pix2spks<<<1,784>>>(l,i);
		///////////////////////////////////////////////////
		cudaDeviceSynchronize();
                convKernel1<<<convGrid,convBlks,0,stream2>>>(i);
                convKernel2<<<convGrid,convBlks,0,stream3>>>(i);
                convKernel3<<<convGrid,convBlks,0,stream4>>>(i);
                convKernel4<<<convGrid,convBlks,0,stream5>>>(i);
                convKernel5<<<convGrid,convBlks,0,stream6>>>(i);
                convKernel6<<<convGrid,convBlks,0,stream7>>>(i);
                convKernel7<<<convGrid,convBlks,0,stream8>>>(i);
                convKernel8<<<convGrid,convBlks,0,stream9>>>(i);
                convKernel9<<<convGrid,convBlks,0,stream10>>>(i);
                convKernel10<<<convGrid,convBlks,0,stream11>>>(i);
                convKernel11<<<convGrid,convBlks,0,stream12>>>(i);
                convKernel12<<<convGrid,convBlks,0,stream13>>>(i);
		/////////////////////////////////////////////////////
		cudaDeviceSynchronize();

                LifKernel1<<<NBlks,Nthrds>>>(i);
		////////////////////////////////////////////////
		cudaDeviceSynchronize();
                SynKernel<<<dimGrid,dimBlock,0,stream14>>>(i);
		Lat_curr<<<1,10,0,stream15>>>(i);
		////////////////////////////////////////////////

                cudaDeviceSynchronize();
                IsynRedKernel<<<grid_syn,block_syn>>>(i);
	        reduce1<<<10,1>>>(i);

		///////////////////////////////////////////////
                cudaDeviceSynchronize();
                LifKernel2<<<1,10>>>(i);
		////////////////////////////////////////////////////
                cudaDeviceSynchronize();
		CalcUpdate<<<dimGrid,dimBlock>>>(i,learn);
	    }

//////////////////////////////////////////////////////////////////////////////
	    WtUpdt<<<dimGrid,dimBlock>>>();
            //cudaDeviceSynchronize();
        }		//end of loops over N_imgs

        t2 = clock();
        elapsed += timediff(t1,t2);
        printf("Elapsed time: %ld ms\n", elapsed);

	char wts_file[25];
	sprintf(wts_file,"wts_gpu%d.txt",n);

	if((FW=fopen(wts_file,"w"))==NULL) {
	    printf("Failed to open file wts_gpu_sample%d.txt\n",n);
        }

	printf("Copying the trained weights to the host for analysis\n");
    	cpyWts<<<dimGrid,dimBlock>>>(d_wts_saved);
	cudaMemcpy(h_wts_saved,d_wts_saved,N1*N2*sizeof(double), cudaMemcpyDeviceToHost);

	//save the weights in a file:
    	for(int i=0; i<N1; i++) {
    	    for(int j=0; j<N2; j++) {
        	fprintf(FW,"%0.14f,",h_wts_saved[i*N2+j]);
            }
            fprintf(FW,"\n");
    	}
	fclose(FW);
    }				//end of n epochs loops

    cudaFree(d_wts_saved);
 
    cudaDeviceReset();
    return(0);
}

	.file	"tmpxft_002799a7_00000000-6_snn_train.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2224:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2224:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z8timediffll
	.type	_Z8timediffll, @function
_Z8timediffll:
.LFB2027:
	.cfi_startproc
	endbr64
	cvtsi2sdq	%rsi, %xmm0
	cvtsi2sdq	%rdi, %xmm1
	subsd	%xmm1, %xmm0
	divsd	.LC0(%rip), %xmm0
	mulsd	.LC1(%rip), %xmm0
	cvttsd2siq	%xmm0, %rax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8timediffll, .-_Z8timediffll
	.globl	_Z34__device_stub__Z14img_readKernelPiPi
	.type	_Z34__device_stub__Z14img_readKernelPiPi, @function
_Z34__device_stub__Z14img_readKernelPiPi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z14img_readKernelPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L4:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z34__device_stub__Z14img_readKernelPiPi, .-_Z34__device_stub__Z14img_readKernelPiPi
	.globl	_Z14img_readKernelPi
	.type	_Z14img_readKernelPi, @function
_Z14img_readKernelPi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z14img_readKernelPiPi
	.cfi_endproc
.LFE2054:
	.size	_Z14img_readKernelPi, .-_Z14img_readKernelPi
	.globl	_Z32__device_stub__Z12convert2SpksPhPh
	.type	_Z32__device_stub__Z12convert2SpksPhPh, @function
_Z32__device_stub__Z12convert2SpksPhPh:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12convert2SpksPh(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L10:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z32__device_stub__Z12convert2SpksPhPh, .-_Z32__device_stub__Z12convert2SpksPhPh
	.globl	_Z12convert2SpksPh
	.type	_Z12convert2SpksPh, @function
_Z12convert2SpksPh:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z12convert2SpksPhPh
	.cfi_endproc
.LFE2056:
	.size	_Z12convert2SpksPh, .-_Z12convert2SpksPh
	.globl	_Z27__device_stub__Z8pix2spksiiii
	.type	_Z27__device_stub__Z8pix2spksiiii, @function
_Z27__device_stub__Z8pix2spksiiii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movl	%esi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8pix2spksii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L15:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z27__device_stub__Z8pix2spksiiii, .-_Z27__device_stub__Z8pix2spksiiii
	.globl	_Z8pix2spksii
	.type	_Z8pix2spksii, @function
_Z8pix2spksii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z8pix2spksiiii
	.cfi_endproc
.LFE2058:
	.size	_Z8pix2spksii, .-_Z8pix2spksii
	.globl	_Z27__device_stub__Z9createDesii
	.type	_Z27__device_stub__Z9createDesii, @function
_Z27__device_stub__Z9createDesii:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z9createDesi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L20:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z27__device_stub__Z9createDesii, .-_Z27__device_stub__Z9createDesii
	.globl	_Z9createDesi
	.type	_Z9createDesi, @function
_Z9createDesi:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z9createDesii
	.cfi_endproc
.LFE2060:
	.size	_Z9createDesi, .-_Z9createDesi
	.globl	_Z29__device_stub__Z10clear_varsvv
	.type	_Z29__device_stub__Z10clear_varsvv, @function
_Z29__device_stub__Z10clear_varsvv:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$72, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movabsq	$4294967297, %rax
	leaq	16(%rsp), %rcx
	leaq	8(%rsp), %rdx
	movl	$1, 32(%rsp)
	leaq	36(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movl	$1, 44(%rsp)
	movq	%rax, 24(%rsp)
	movq	%rax, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	pushq	16(%rsp)
	.cfi_def_cfa_offset 88
	leaq	_Z10clear_varsv(%rip), %rdi
	pushq	16(%rsp)
	.cfi_def_cfa_offset 96
	movq	52(%rsp), %rcx
	movl	60(%rsp), %r8d
	movq	40(%rsp), %rsi
	movl	48(%rsp), %edx
	leaq	64(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
.L25:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$72, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z29__device_stub__Z10clear_varsvv, .-_Z29__device_stub__Z10clear_varsvv
	.globl	_Z10clear_varsv
	.type	_Z10clear_varsv, @function
_Z10clear_varsv:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z10clear_varsvv
	.cfi_endproc
.LFE2062:
	.size	_Z10clear_varsv, .-_Z10clear_varsv
	.globl	_Z29__device_stub__Z10LifKernel1ii
	.type	_Z29__device_stub__Z10LifKernel1ii, @function
_Z29__device_stub__Z10LifKernel1ii:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z10LifKernel1i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L30:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z29__device_stub__Z10LifKernel1ii, .-_Z29__device_stub__Z10LifKernel1ii
	.globl	_Z10LifKernel1i
	.type	_Z10LifKernel1i, @function
_Z10LifKernel1i:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z10LifKernel1ii
	.cfi_endproc
.LFE2064:
	.size	_Z10LifKernel1i, .-_Z10LifKernel1i
	.globl	_Z29__device_stub__Z10LifKernel2ii
	.type	_Z29__device_stub__Z10LifKernel2ii, @function
_Z29__device_stub__Z10LifKernel2ii:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z10LifKernel2i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L35:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z29__device_stub__Z10LifKernel2ii, .-_Z29__device_stub__Z10LifKernel2ii
	.globl	_Z10LifKernel2i
	.type	_Z10LifKernel2i, @function
_Z10LifKernel2i:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z10LifKernel2ii
	.cfi_endproc
.LFE2066:
	.size	_Z10LifKernel2i, .-_Z10LifKernel2i
	.globl	_Z27__device_stub__Z9SynKernelii
	.type	_Z27__device_stub__Z9SynKernelii, @function
_Z27__device_stub__Z9SynKernelii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z9SynKerneli(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L40:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L42
	call	__stack_chk_fail@PLT
.L42:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z27__device_stub__Z9SynKernelii, .-_Z27__device_stub__Z9SynKernelii
	.globl	_Z9SynKerneli
	.type	_Z9SynKerneli, @function
_Z9SynKerneli:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z9SynKernelii
	.cfi_endproc
.LFE2068:
	.size	_Z9SynKerneli, .-_Z9SynKerneli
	.globl	_Z26__device_stub__Z8Lat_currii
	.type	_Z26__device_stub__Z8Lat_currii, @function
_Z26__device_stub__Z8Lat_currii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8Lat_curri(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L45:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z26__device_stub__Z8Lat_currii, .-_Z26__device_stub__Z8Lat_currii
	.globl	_Z8Lat_curri
	.type	_Z8Lat_curri, @function
_Z8Lat_curri:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8Lat_currii
	.cfi_endproc
.LFE2070:
	.size	_Z8Lat_curri, .-_Z8Lat_curri
	.globl	_Z32__device_stub__Z13IsynRedKernelii
	.type	_Z32__device_stub__Z13IsynRedKernelii, @function
_Z32__device_stub__Z13IsynRedKernelii:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z13IsynRedKerneli(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L50:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z32__device_stub__Z13IsynRedKernelii, .-_Z32__device_stub__Z13IsynRedKernelii
	.globl	_Z13IsynRedKerneli
	.type	_Z13IsynRedKerneli, @function
_Z13IsynRedKerneli:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z13IsynRedKernelii
	.cfi_endproc
.LFE2072:
	.size	_Z13IsynRedKerneli, .-_Z13IsynRedKerneli
	.globl	_Z25__device_stub__Z7reduce1ii
	.type	_Z25__device_stub__Z7reduce1ii, @function
_Z25__device_stub__Z7reduce1ii:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z7reduce1i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L55:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z25__device_stub__Z7reduce1ii, .-_Z25__device_stub__Z7reduce1ii
	.globl	_Z7reduce1i
	.type	_Z7reduce1i, @function
_Z7reduce1i:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z7reduce1ii
	.cfi_endproc
.LFE2074:
	.size	_Z7reduce1i, .-_Z7reduce1i
	.globl	_Z30__device_stub__Z10CalcUpdateidid
	.type	_Z30__device_stub__Z10CalcUpdateidid, @function
_Z30__device_stub__Z10CalcUpdateidid:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movsd	%xmm0, (%rsp)
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z10CalcUpdateid(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L60:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L62
	call	__stack_chk_fail@PLT
.L62:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z30__device_stub__Z10CalcUpdateidid, .-_Z30__device_stub__Z10CalcUpdateidid
	.globl	_Z10CalcUpdateid
	.type	_Z10CalcUpdateid, @function
_Z10CalcUpdateid:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10CalcUpdateidid
	.cfi_endproc
.LFE2076:
	.size	_Z10CalcUpdateid, .-_Z10CalcUpdateid
	.globl	_Z24__device_stub__Z6WtUpdtvv
	.type	_Z24__device_stub__Z6WtUpdtvv, @function
_Z24__device_stub__Z6WtUpdtvv:
.LFB2077:
	.cfi_startproc
	endbr64
	subq	$72, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movabsq	$4294967297, %rax
	leaq	16(%rsp), %rcx
	leaq	8(%rsp), %rdx
	movl	$1, 32(%rsp)
	leaq	36(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movl	$1, 44(%rsp)
	movq	%rax, 24(%rsp)
	movq	%rax, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L65
	pushq	16(%rsp)
	.cfi_def_cfa_offset 88
	leaq	_Z6WtUpdtv(%rip), %rdi
	pushq	16(%rsp)
	.cfi_def_cfa_offset 96
	movq	52(%rsp), %rcx
	movl	60(%rsp), %r8d
	movq	40(%rsp), %rsi
	movl	48(%rsp), %edx
	leaq	64(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
.L65:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L67
	call	__stack_chk_fail@PLT
.L67:
	addq	$72, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_Z24__device_stub__Z6WtUpdtvv, .-_Z24__device_stub__Z6WtUpdtvv
	.globl	_Z6WtUpdtv
	.type	_Z6WtUpdtv, @function
_Z6WtUpdtv:
.LFB2078:
	.cfi_startproc
	endbr64
	jmp	_Z24__device_stub__Z6WtUpdtvv
	.cfi_endproc
.LFE2078:
	.size	_Z6WtUpdtv, .-_Z6WtUpdtv
	.globl	_Z25__device_stub__Z6cpyWtsPdPd
	.type	_Z25__device_stub__Z6cpyWtsPdPd, @function
_Z25__device_stub__Z6cpyWtsPdPd:
.LFB2079:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z6cpyWtsPd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L70:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L72
	call	__stack_chk_fail@PLT
.L72:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2079:
	.size	_Z25__device_stub__Z6cpyWtsPdPd, .-_Z25__device_stub__Z6cpyWtsPdPd
	.globl	_Z6cpyWtsPd
	.type	_Z6cpyWtsPd, @function
_Z6cpyWtsPd:
.LFB2080:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z6cpyWtsPdPd
	.cfi_endproc
.LFE2080:
	.size	_Z6cpyWtsPd, .-_Z6cpyWtsPd
	.globl	_Z34__device_stub__Z12initialize2DPdS_PdS_
	.type	_Z34__device_stub__Z12initialize2DPdS_PdS_, @function
_Z34__device_stub__Z12initialize2DPdS_PdS_:
.LFB2081:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L75
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12initialize2DPdS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L75:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L77
	call	__stack_chk_fail@PLT
.L77:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2081:
	.size	_Z34__device_stub__Z12initialize2DPdS_PdS_, .-_Z34__device_stub__Z12initialize2DPdS_PdS_
	.globl	_Z12initialize2DPdS_
	.type	_Z12initialize2DPdS_, @function
_Z12initialize2DPdS_:
.LFB2082:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z12initialize2DPdS_PdS_
	.cfi_endproc
.LFE2082:
	.size	_Z12initialize2DPdS_, .-_Z12initialize2DPdS_
	.globl	_Z30__device_stub__Z11convKernel1ii
	.type	_Z30__device_stub__Z11convKernel1ii, @function
_Z30__device_stub__Z11convKernel1ii:
.LFB2083:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel1i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L80:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L82
	call	__stack_chk_fail@PLT
.L82:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2083:
	.size	_Z30__device_stub__Z11convKernel1ii, .-_Z30__device_stub__Z11convKernel1ii
	.globl	_Z11convKernel1i
	.type	_Z11convKernel1i, @function
_Z11convKernel1i:
.LFB2084:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel1ii
	.cfi_endproc
.LFE2084:
	.size	_Z11convKernel1i, .-_Z11convKernel1i
	.globl	_Z30__device_stub__Z11convKernel2ii
	.type	_Z30__device_stub__Z11convKernel2ii, @function
_Z30__device_stub__Z11convKernel2ii:
.LFB2085:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel2i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L85:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L87
	call	__stack_chk_fail@PLT
.L87:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2085:
	.size	_Z30__device_stub__Z11convKernel2ii, .-_Z30__device_stub__Z11convKernel2ii
	.globl	_Z11convKernel2i
	.type	_Z11convKernel2i, @function
_Z11convKernel2i:
.LFB2086:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel2ii
	.cfi_endproc
.LFE2086:
	.size	_Z11convKernel2i, .-_Z11convKernel2i
	.globl	_Z30__device_stub__Z11convKernel3ii
	.type	_Z30__device_stub__Z11convKernel3ii, @function
_Z30__device_stub__Z11convKernel3ii:
.LFB2087:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel3i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L90:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2087:
	.size	_Z30__device_stub__Z11convKernel3ii, .-_Z30__device_stub__Z11convKernel3ii
	.globl	_Z11convKernel3i
	.type	_Z11convKernel3i, @function
_Z11convKernel3i:
.LFB2088:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel3ii
	.cfi_endproc
.LFE2088:
	.size	_Z11convKernel3i, .-_Z11convKernel3i
	.globl	_Z30__device_stub__Z11convKernel4ii
	.type	_Z30__device_stub__Z11convKernel4ii, @function
_Z30__device_stub__Z11convKernel4ii:
.LFB2089:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L95
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel4i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L95:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L97
	call	__stack_chk_fail@PLT
.L97:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2089:
	.size	_Z30__device_stub__Z11convKernel4ii, .-_Z30__device_stub__Z11convKernel4ii
	.globl	_Z11convKernel4i
	.type	_Z11convKernel4i, @function
_Z11convKernel4i:
.LFB2090:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel4ii
	.cfi_endproc
.LFE2090:
	.size	_Z11convKernel4i, .-_Z11convKernel4i
	.globl	_Z30__device_stub__Z11convKernel5ii
	.type	_Z30__device_stub__Z11convKernel5ii, @function
_Z30__device_stub__Z11convKernel5ii:
.LFB2091:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L100
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel5i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L100:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L102
	call	__stack_chk_fail@PLT
.L102:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2091:
	.size	_Z30__device_stub__Z11convKernel5ii, .-_Z30__device_stub__Z11convKernel5ii
	.globl	_Z11convKernel5i
	.type	_Z11convKernel5i, @function
_Z11convKernel5i:
.LFB2092:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel5ii
	.cfi_endproc
.LFE2092:
	.size	_Z11convKernel5i, .-_Z11convKernel5i
	.globl	_Z30__device_stub__Z11convKernel6ii
	.type	_Z30__device_stub__Z11convKernel6ii, @function
_Z30__device_stub__Z11convKernel6ii:
.LFB2093:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L105
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel6i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L105:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L107
	call	__stack_chk_fail@PLT
.L107:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2093:
	.size	_Z30__device_stub__Z11convKernel6ii, .-_Z30__device_stub__Z11convKernel6ii
	.globl	_Z11convKernel6i
	.type	_Z11convKernel6i, @function
_Z11convKernel6i:
.LFB2094:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel6ii
	.cfi_endproc
.LFE2094:
	.size	_Z11convKernel6i, .-_Z11convKernel6i
	.globl	_Z30__device_stub__Z11convKernel7ii
	.type	_Z30__device_stub__Z11convKernel7ii, @function
_Z30__device_stub__Z11convKernel7ii:
.LFB2095:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L110
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel7i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L110:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L112
	call	__stack_chk_fail@PLT
.L112:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2095:
	.size	_Z30__device_stub__Z11convKernel7ii, .-_Z30__device_stub__Z11convKernel7ii
	.globl	_Z11convKernel7i
	.type	_Z11convKernel7i, @function
_Z11convKernel7i:
.LFB2096:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel7ii
	.cfi_endproc
.LFE2096:
	.size	_Z11convKernel7i, .-_Z11convKernel7i
	.globl	_Z30__device_stub__Z11convKernel8ii
	.type	_Z30__device_stub__Z11convKernel8ii, @function
_Z30__device_stub__Z11convKernel8ii:
.LFB2097:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L115
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel8i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L115:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L117
	call	__stack_chk_fail@PLT
.L117:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2097:
	.size	_Z30__device_stub__Z11convKernel8ii, .-_Z30__device_stub__Z11convKernel8ii
	.globl	_Z11convKernel8i
	.type	_Z11convKernel8i, @function
_Z11convKernel8i:
.LFB2098:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel8ii
	.cfi_endproc
.LFE2098:
	.size	_Z11convKernel8i, .-_Z11convKernel8i
	.globl	_Z30__device_stub__Z11convKernel9ii
	.type	_Z30__device_stub__Z11convKernel9ii, @function
_Z30__device_stub__Z11convKernel9ii:
.LFB2099:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L120
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z11convKernel9i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L120:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L122
	call	__stack_chk_fail@PLT
.L122:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2099:
	.size	_Z30__device_stub__Z11convKernel9ii, .-_Z30__device_stub__Z11convKernel9ii
	.globl	_Z11convKernel9i
	.type	_Z11convKernel9i, @function
_Z11convKernel9i:
.LFB2100:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z11convKernel9ii
	.cfi_endproc
.LFE2100:
	.size	_Z11convKernel9i, .-_Z11convKernel9i
	.globl	_Z31__device_stub__Z12convKernel10ii
	.type	_Z31__device_stub__Z12convKernel10ii, @function
_Z31__device_stub__Z12convKernel10ii:
.LFB2101:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L125
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12convKernel10i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L125:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L127
	call	__stack_chk_fail@PLT
.L127:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2101:
	.size	_Z31__device_stub__Z12convKernel10ii, .-_Z31__device_stub__Z12convKernel10ii
	.globl	_Z12convKernel10i
	.type	_Z12convKernel10i, @function
_Z12convKernel10i:
.LFB2102:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z12convKernel10ii
	.cfi_endproc
.LFE2102:
	.size	_Z12convKernel10i, .-_Z12convKernel10i
	.globl	_Z31__device_stub__Z12convKernel11ii
	.type	_Z31__device_stub__Z12convKernel11ii, @function
_Z31__device_stub__Z12convKernel11ii:
.LFB2103:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L130
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12convKernel11i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L130:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L132
	call	__stack_chk_fail@PLT
.L132:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2103:
	.size	_Z31__device_stub__Z12convKernel11ii, .-_Z31__device_stub__Z12convKernel11ii
	.globl	_Z12convKernel11i
	.type	_Z12convKernel11i, @function
_Z12convKernel11i:
.LFB2104:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z12convKernel11ii
	.cfi_endproc
.LFE2104:
	.size	_Z12convKernel11i, .-_Z12convKernel11i
	.globl	_Z31__device_stub__Z12convKernel12ii
	.type	_Z31__device_stub__Z12convKernel12ii, @function
_Z31__device_stub__Z12convKernel12ii:
.LFB2105:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	52(%rsp), %rsi
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L135
	pushq	32(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z12convKernel12i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 112
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L135:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L137
	call	__stack_chk_fail@PLT
.L137:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2105:
	.size	_Z31__device_stub__Z12convKernel12ii, .-_Z31__device_stub__Z12convKernel12ii
	.globl	_Z12convKernel12i
	.type	_Z12convKernel12i, @function
_Z12convKernel12i:
.LFB2106:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z12convKernel12ii
	.cfi_endproc
.LFE2106:
	.size	_Z12convKernel12i, .-_Z12convKernel12i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"r"
.LC5:
	.string	"pixels_spks.csv"
.LC6:
	.string	"Error while opening file pixels_spks.csv\n"
.LC7:
	.string	"mnist_train.csv"
.LC8:
	.string	"Error while opening file mnist_train.csv\n"
.LC9:
	.string	"wts_initial.csv"
.LC10:
	.string	"Error while opening file wts_trained.csv\n"
.LC11:
	.string	"kernels_3x3.csv"
.LC12:
	.string	"Error while opening file kernel.csv\n"
.LC13:
	.string	"Total no. of neurons=%d, no. of synapses to be trained=%d\n"
.LC14:
	.string	"%lf,"
.LC15:
	.string	"%d,"
.LC16:
	.string	"Epoch=%d\n"
.LC17:
	.string	"l=%d image %d\n"
.LC18:
	.string	"Elapsed time: %ld ms\n"
.LC19:
	.string	"wts_gpu%d.txt"
.LC20:
	.string	"w"
.LC21:
	.string	"Failed to open file wts_gpu_sample%d.txt\n"
.LC22:
	.string	"Copying the trained weights to the host for analysis\n"
.LC23:
	.string	"%0.14f,"
.LC24:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC4(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$296, %rsp
	.cfi_def_cfa_offset 352
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	leaq	40(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	80(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	104(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	112(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	120(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	128(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	136(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	144(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	.LC5(%rip), %rdi
	movq	%r12, %rsi
	call	fopen@PLT
	leaq	.LC6(%rip), %rdi
	testq	%rax, %rax
	je	.L204
	movq	%r12, %rsi
	leaq	.LC7(%rip), %rdi
	movq	%rax, %rbp
	call	fopen@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L142
	leaq	.LC8(%rip), %rdi
.L204:
	call	perror@PLT
	movl	$1, %edi
	call	exit@PLT
.L142:
	leaq	.LC9(%rip), %rdi
	movq	%r12, %rsi
	call	fopen@PLT
	leaq	.LC10(%rip), %rdi
	movq	%rax, %r13
	testq	%rax, %rax
	je	.L204
	movq	%r12, %rsi
	leaq	.LC11(%rip), %rdi
	call	fopen@PLT
	leaq	.LC12(%rip), %rdi
	movq	%rax, %r12
	testq	%rax, %rax
	je	.L204
	movl	$81120, %ecx
	movl	$8122, %edx
	leaq	.LC13(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	h_wts(%rip), %r14
	call	__printf_chk@PLT
	movl	$157000000, %esi
	leaq	d_imgs_lin(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$648960, %esi
	leaq	d_wts(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$864, %esi
	leaq	dcwts(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$648960, %esi
	leaq	d_wts_saved(%rip), %rdi
	call	cudaMalloc@PLT
	movl	$256000, %esi
	leaq	pix_spks_d(%rip), %rdi
	call	cudaMalloc@PLT
	xorl	%ecx, %ecx
.L145:
	imulq	$80, %rcx, %r15
	leaq	(%r15,%r14), %rax
	movl	$10, %r15d
	movq	%rax, 8(%rsp)
.L146:
	movq	8(%rsp), %rdx
	xorl	%eax, %eax
	movq	%r13, %rdi
	movq	%rcx, 16(%rsp)
	leaq	.LC14(%rip), %rsi
	call	__isoc23_fscanf@PLT
	addq	$8, 8(%rsp)
	decl	%r15d
	movq	16(%rsp), %rcx
	jne	.L146
	incq	%rcx
	cmpq	$8112, %rcx
	jne	.L145
	movq	%r13, %rdi
	leaq	c_wts(%rip), %r15
	call	fclose@PLT
	xorl	%ecx, %ecx
.L148:
	imulq	$24, %rcx, %r13
	leaq	0(%r13,%r15), %rax
	movl	$3, %r13d
	movq	%rax, 8(%rsp)
.L149:
	movq	8(%rsp), %rdx
	xorl	%eax, %eax
	movq	%r12, %rdi
	movq	%rcx, 16(%rsp)
	leaq	.LC14(%rip), %rsi
	call	__isoc23_fscanf@PLT
	addq	$8, 8(%rsp)
	decl	%r13d
	movq	16(%rsp), %rcx
	jne	.L149
	incq	%rcx
	cmpq	$36, %rcx
	jne	.L148
	movq	%r12, %rdi
	leaq	pix_spks_h(%rip), %r13
	call	fclose@PLT
.L151:
	xorl	%r12d, %r12d
.L152:
	leaq	(%r12,%r13), %rdx
	xorl	%eax, %eax
	leaq	.LC15(%rip), %rsi
	movq	%rbp, %rdi
	call	__isoc23_fscanf@PLT
	incq	%r12
	leaq	256000+pix_spks_h(%rip), %r9
	cmpq	$1000, %r12
	jne	.L152
	addq	$1000, %r13
	cmpq	%r9, %r13
	jne	.L151
	movq	%rbp, %rdi
	call	fclose@PLT
	movl	$1, %ecx
	movq	pix_spks_d(%rip), %rdi
	movl	$256000, %edx
	leaq	pix_spks_h(%rip), %rsi
	call	cudaMemcpy@PLT
	movq	d_wts(%rip), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$648960, %edx
	call	cudaMemcpy@PLT
	movq	dcwts(%rip), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$864, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 248(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 240(%rsp)
	movq	%rdi, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L154
	movq	dcwts(%rip), %rsi
	movq	d_wts(%rip), %rdi
	call	_Z34__device_stub__Z12initialize2DPdS_PdS_
.L154:
	call	cudaDeviceSynchronize@PLT
	movq	d_wts(%rip), %rdi
	xorl	%ebp, %ebp
	call	cudaFree@PLT
	movq	dcwts(%rip), %rdi
	call	cudaFree@PLT
.L155:
	leaq	test_set(%rip), %rax
	movl	$785, %r13d
	leaq	(%rax,%rbp,4), %r14
.L156:
	movq	%r14, %rdx
	leaq	.LC15(%rip), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	addq	$4, %r14
	decl	%r13d
	jne	.L156
	addq	$785, %rbp
	cmpq	$39250000, %rbp
	jne	.L155
	movq	%rbx, %rdi
	call	fclose@PLT
	leaq	img_lin(%rip), %rdi
	movq	%rbp, %rcx
	leaq	test_set(%rip), %rsi
	rep movsl
	movq	d_imgs_lin(%rip), %rdi
	movl	$1, %ecx
	movl	$157000000, %edx
	leaq	img_lin(%rip), %rsi
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 248(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 240(%rsp)
	movq	%rdi, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L158
	movq	d_imgs_lin(%rip), %rdi
	call	_Z34__device_stub__Z14img_readKernelPiPi
.L158:
	call	cudaThreadSynchronize@PLT
	movq	d_imgs_lin(%rip), %rdi
	call	cudaFree@PLT
	movl	$2147483689, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rax, %rax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rax, 156(%rsp)
	movq	%rdi, %rdx
	movabsq	$42949673060, %rax
	movq	%rax, 168(%rsp)
	subq	$92, %rax
	movq	%rax, 180(%rsp)
	movl	$4194305, %eax
	salq	$10, %rax
	movl	$1, 164(%rsp)
	movl	$1, 176(%rsp)
	movl	$1, 188(%rsp)
	movq	%rax, 192(%rsp)
	movl	$1, 200(%rsp)
	movq	%rdi, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%rdi, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	movq	pix_spks_d(%rip), %rdi
	call	_Z32__device_stub__Z12convert2SpksPhPh
.L159:
	call	cudaDeviceSynchronize@PLT
	movq	pix_spks_d(%rip), %rdi
	xorl	%r12d, %r12d
	call	cudaFree@PLT
	movabsq	$4294967297, %rax
	movl	$1, 212(%rsp)
	movq	%rax, 204(%rsp)
	movabsq	$111669149722, %rax
	movq	%rax, 216(%rsp)
	movl	$1, 224(%rsp)
	call	clock@PLT
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)
.L191:
	movl	%r12d, %edx
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movsd	.LC2(%rip), %xmm1
	movsd	%xmm1, 8(%rsp)
	cmpl	$2, %r12d
	jle	.L160
	movsd	.LC3(%rip), %xmm2
	leal	-3(%r12), %eax
	movsd	%xmm2, 8(%rsp)
	cmpl	$14, %eax
	ja	.L160
	leaq	CSWTCH.241(%rip), %rdx
	movsd	(%rdx,%rax,8), %xmm3
	movsd	%xmm3, 8(%rsp)
.L160:
	leaq	test_set(%rip), %r15
	xorl	%r14d, %r14d
	movabsq	$4294967306, %r13
	movabsq	$4294967297, %rbp
.L185:
	movl	(%r15), %ecx
	movl	%r14d, %edx
	leaq	.LC17(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%rbp, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L161
	movl	%r14d, %edi
	call	_Z27__device_stub__Z9createDesii
.L161:
	movl	176(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	168(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L162
	call	_Z29__device_stub__Z10clear_varsvv
.L162:
	call	cudaDeviceSynchronize@PLT
	xorl	%ebx, %ebx
.L183:
	movl	$268435505, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$4, %rax
	movq	%rbp, %rdi
	movl	$1, %esi
	movl	$1, 248(%rsp)
	movq	%rax, %rdx
	movq	%rax, 240(%rsp)
	movq	%rbp, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L163
	movl	%ebx, %esi
	movl	%r14d, %edi
	call	_Z27__device_stub__Z8pix2spksiiii
.L163:
	call	cudaDeviceSynchronize@PLT
	movl	224(%rsp), %ecx
	xorl	%r8d, %r8d
	movq	40(%rsp), %r9
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L164
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel1ii
.L164:
	movl	224(%rsp), %ecx
	movq	48(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L165
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel2ii
.L165:
	movl	224(%rsp), %ecx
	movq	56(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L166
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel3ii
.L166:
	movl	224(%rsp), %ecx
	movq	64(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L167
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel4ii
.L167:
	movl	224(%rsp), %ecx
	movq	72(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L168
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel5ii
.L168:
	movl	224(%rsp), %ecx
	movq	80(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L169
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel6ii
.L169:
	movl	224(%rsp), %ecx
	movq	88(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L170
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel7ii
.L170:
	movl	224(%rsp), %ecx
	movq	96(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L171
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel8ii
.L171:
	movl	224(%rsp), %ecx
	movq	104(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L172
	movl	%ebx, %edi
	call	_Z30__device_stub__Z11convKernel9ii
.L172:
	movl	224(%rsp), %ecx
	movq	112(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L173
	movl	%ebx, %edi
	call	_Z31__device_stub__Z12convKernel10ii
.L173:
	movl	224(%rsp), %ecx
	movq	120(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L174
	movl	%ebx, %edi
	call	_Z31__device_stub__Z12convKernel11ii
.L174:
	movl	224(%rsp), %ecx
	movq	128(%rsp), %r9
	xorl	%r8d, %r8d
	movq	216(%rsp), %rdx
	movq	204(%rsp), %rdi
	movl	212(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L175
	movl	%ebx, %edi
	call	_Z31__device_stub__Z12convKernel12ii
.L175:
	call	cudaDeviceSynchronize@PLT
	movl	$4194305, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rax
	movl	$536870913, %edi
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	movq	%rax, %rdx
	movq	%rax, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%rdi, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L176
	movl	%ebx, %edi
	call	_Z29__device_stub__Z10LifKernel1ii
.L176:
	call	cudaDeviceSynchronize@PLT
	movl	176(%rsp), %ecx
	xorl	%r8d, %r8d
	movq	136(%rsp), %r9
	movq	168(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L177
	movl	%ebx, %edi
	call	_Z27__device_stub__Z9SynKernelii
.L177:
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movq	144(%rsp), %r9
	movl	$1, %esi
	movq	%r13, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%rbp, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L178
	movl	%ebx, %edi
	call	_Z26__device_stub__Z8Lat_currii
.L178:
	call	cudaDeviceSynchronize@PLT
	movl	200(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	192(%rsp), %rdx
	movq	180(%rsp), %rdi
	movl	188(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L179
	movl	%ebx, %edi
	call	_Z32__device_stub__Z13IsynRedKernelii
.L179:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%r13, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L180
	movl	%ebx, %edi
	call	_Z25__device_stub__Z7reduce1ii
.L180:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, 240(%rsp)
	movl	$1, 248(%rsp)
	movq	%rbp, 228(%rsp)
	movl	$1, 236(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L181
	movl	%ebx, %edi
	call	_Z29__device_stub__Z10LifKernel2ii
.L181:
	call	cudaDeviceSynchronize@PLT
	movl	176(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	168(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L182
	movsd	8(%rsp), %xmm0
	movl	%ebx, %edi
	call	_Z30__device_stub__Z10CalcUpdateidid
.L182:
	incl	%ebx
	cmpl	$1000, %ebx
	jne	.L183
	movl	176(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	168(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L184
	call	_Z24__device_stub__Z6WtUpdtvv
.L184:
	incl	%r14d
	addq	$3140, %r15
	cmpl	$50000, %r14d
	jne	.L185
	call	clock@PLT
	movq	24(%rsp), %rdi
	leaq	255(%rsp), %rbx
	movq	%rax, %rsi
	call	_Z8timediffll
	addq	%rax, 16(%rsp)
	movq	16(%rsp), %rdx
	xorl	%eax, %eax
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	movl	%r12d, %r8d
	movl	$25, %edx
	leaq	.LC19(%rip), %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__sprintf_chk@PLT
	movq	%rbx, %rdi
	leaq	.LC20(%rip), %rsi
	call	fopen@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	.L186
	movl	%r12d, %edx
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L186:
	leaq	.LC22(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	176(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	168(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L187
	movq	d_wts_saved(%rip), %rdi
	call	_Z25__device_stub__Z6cpyWtsPdPd
.L187:
	movq	d_wts_saved(%rip), %rsi
	leaq	h_wts_saved(%rip), %r13
	movl	$2, %ecx
	xorl	%ebp, %ebp
	movl	$648960, %edx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
.L188:
	imulq	$80, %rbp, %rcx
	xorl	%r15d, %r15d
	leaq	0(%r13,%rcx), %r14
.L189:
	movsd	(%r14,%r15,8), %xmm0
	movl	$2, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	leaq	.LC23(%rip), %rdx
	incq	%r15
	call	__fprintf_chk@PLT
	cmpq	$10, %r15
	jne	.L189
	leaq	.LC24(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%eax, %eax
	incq	%rbp
	movl	$2, %esi
	call	__fprintf_chk@PLT
	cmpq	$8112, %rbp
	jne	.L188
	movq	%rbx, %rdi
	incl	%r12d
	call	fclose@PLT
	cmpl	$20, %r12d
	jne	.L191
	movq	d_wts_saved(%rip), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L192
	call	__stack_chk_fail@PLT
.L192:
	addq	$296, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC27:
	.string	"_Z12convKernel12i"
.LC28:
	.string	"_Z12convKernel11i"
.LC29:
	.string	"_Z12convKernel10i"
.LC30:
	.string	"_Z11convKernel9i"
.LC31:
	.string	"_Z11convKernel8i"
.LC32:
	.string	"_Z11convKernel7i"
.LC33:
	.string	"_Z11convKernel6i"
.LC34:
	.string	"_Z11convKernel5i"
.LC35:
	.string	"_Z11convKernel4i"
.LC36:
	.string	"_Z11convKernel3i"
.LC37:
	.string	"_Z11convKernel2i"
.LC38:
	.string	"_Z11convKernel1i"
.LC39:
	.string	"_Z12initialize2DPdS_"
.LC40:
	.string	"_Z6cpyWtsPd"
.LC41:
	.string	"_Z6WtUpdtv"
.LC42:
	.string	"_Z10CalcUpdateid"
.LC43:
	.string	"_Z7reduce1i"
.LC44:
	.string	"_Z13IsynRedKerneli"
.LC45:
	.string	"_Z8Lat_curri"
.LC46:
	.string	"_Z9SynKerneli"
.LC47:
	.string	"_Z10LifKernel2i"
.LC48:
	.string	"_Z10LifKernel1i"
.LC49:
	.string	"_Z10clear_varsv"
.LC50:
	.string	"_Z9createDesi"
.LC51:
	.string	"_Z8pix2spksii"
.LC52:
	.string	"_Z12convert2SpksPh"
.LC53:
	.string	"_Z14img_readKernelPi"
.LC54:
	.string	"d_imgs"
.LC55:
	.string	"img_spks"
.LC56:
	.string	"syn1"
.LC57:
	.string	"syn1s"
.LC58:
	.string	"syn"
.LC59:
	.string	"in_spk"
.LC60:
	.string	"Isyn"
.LC61:
	.string	"weight"
.LC62:
	.string	"Isyn_tot"
.LC63:
	.string	"Isyn_lat"
.LC64:
	.string	"I_lat"
.LC65:
	.string	"D_op"
.LC66:
	.string	"err"
.LC67:
	.string	"Y_op"
.LC68:
	.string	"del_w"
.LC69:
	.string	"ci"
.LC70:
	.string	"d_hat"
.LC71:
	.string	"cis"
.LC72:
	.string	"norm_dh"
.LC73:
	.string	"cil"
.LC74:
	.string	"cils"
.LC75:
	.string	"d_hat_sq"
.LC76:
	.string	"ref_time1"
.LC77:
	.string	"ref_time2"
.LC78:
	.string	"Vm1"
.LC79:
	.string	"Vm2"
.LC80:
	.string	"pix_spks"
.LC81:
	.string	"I_in"
.LC82:
	.string	"total_curr"
.LC83:
	.string	"total_dhatsq"
.LC84:
	.string	"w_conv1"
.LC85:
	.string	"w_conv2"
.LC86:
	.string	"w_conv3"
.LC87:
	.string	"w_conv4"
.LC88:
	.string	"w_conv5"
.LC89:
	.string	"w_conv6"
.LC90:
	.string	"w_conv7"
.LC91:
	.string	"w_conv8"
.LC92:
	.string	"w_conv9"
.LC93:
	.string	"w_conv10"
.LC94:
	.string	"w_conv11"
.LC95:
	.string	"w_conv12"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2108:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12convKernel12i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12convKernel11i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12convKernel10i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel9i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel8i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC32(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel7i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel6i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel5i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC35(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z11convKernel4i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel3i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11convKernel1i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12initialize2DPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC40(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6cpyWtsPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6WtUpdtv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10CalcUpdateid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC43(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z7reduce1i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13IsynRedKerneli(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8Lat_curri(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9SynKerneli(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10LifKernel2i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC48(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10LifKernel1i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10clear_varsv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9createDesi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC51(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z8pix2spksii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12convert2SpksPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14img_readKernelPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC54(%rip), %rdx
	movl	$157000000, %r9d
	leaq	_ZL6d_imgs(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$6272000, %r9d
	leaq	_ZL8img_spks(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2048, %r9d
	leaq	_ZL4syn1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2048, %r9d
	leaq	_ZL5syn1s(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2048000, %r9d
	leaq	_ZL3syn(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8112, %r9d
	leaq	_ZL6in_spk(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$648960, %r9d
	leaq	_ZL4Isyn(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$648960, %r9d
	leaq	_ZL6weight(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL8Isyn_tot(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL8Isyn_lat(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC64(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL5I_lat(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC65(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$10000, %r9d
	leaq	_ZL4D_op(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC66(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$10, %r9d
	leaq	_ZL3err(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC67(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$10, %r9d
	leaq	_ZL4Y_op(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC68(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$648960, %r9d
	leaq	_ZL5del_w(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC69(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL2ci(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC70(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL5d_hat(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC71(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL3cis(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC72(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7norm_dh(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC73(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL3cil(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC74(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL4cils(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC75(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL8d_hat_sq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC76(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$32448, %r9d
	leaq	_ZL9ref_time1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC77(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$40, %r9d
	leaq	_ZL9ref_time2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC78(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL3Vm1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC79(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$80, %r9d
	leaq	_ZL3Vm2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC80(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$256000, %r9d
	leaq	_ZL8pix_spks(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC81(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64896, %r9d
	leaq	_ZL4I_in(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC82(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$640, %r9d
	leaq	_ZL10total_curr(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC83(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$64, %r9d
	leaq	_ZL12total_dhatsq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC84(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC85(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC86(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC87(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC88(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv5(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC89(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv6(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC90(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv7(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC91(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv8(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC92(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL7w_conv9(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC93(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL8w_conv10(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC94(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL8w_conv11(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC95(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL8w_conv12(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2108:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata
	.align 32
	.type	CSWTCH.241, @object
	.size	CSWTCH.241, 120
CSWTCH.241:
	.long	-640172613
	.long	1037794527
	.long	-640172613
	.long	1037794527
	.long	-640172613
	.long	1037794527
	.long	-640172613
	.long	1036745951
	.long	-640172613
	.long	1036745951
	.long	-640172613
	.long	1036745951
	.long	-640172613
	.long	1035697375
	.long	-640172613
	.long	1035697375
	.long	-640172613
	.long	1035697375
	.long	-640172613
	.long	1034648799
	.long	-640172613
	.long	1034648799
	.long	-640172613
	.long	1034648799
	.long	-640172613
	.long	1033600223
	.long	-640172613
	.long	1033600223
	.long	-640172613
	.long	1033600223
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	c_wts
	.bss
	.align 32
	.type	c_wts, @object
	.size	c_wts, 864
c_wts:
	.zero	864
	.globl	d_wts_saved
	.align 8
	.type	d_wts_saved, @object
	.size	d_wts_saved, 8
d_wts_saved:
	.zero	8
	.globl	h_wts_saved
	.align 32
	.type	h_wts_saved, @object
	.size	h_wts_saved, 648960
h_wts_saved:
	.zero	648960
	.globl	dcwts
	.align 8
	.type	dcwts, @object
	.size	dcwts, 8
dcwts:
	.zero	8
	.globl	d_wts
	.align 8
	.type	d_wts, @object
	.size	d_wts, 8
d_wts:
	.zero	8
	.globl	h_wts
	.align 32
	.type	h_wts, @object
	.size	h_wts, 648960
h_wts:
	.zero	648960
	.local	_ZL8w_conv12
	.comm	_ZL8w_conv12,72,32
	.local	_ZL8w_conv11
	.comm	_ZL8w_conv11,72,32
	.local	_ZL8w_conv10
	.comm	_ZL8w_conv10,72,32
	.local	_ZL7w_conv9
	.comm	_ZL7w_conv9,72,32
	.local	_ZL7w_conv8
	.comm	_ZL7w_conv8,72,32
	.local	_ZL7w_conv7
	.comm	_ZL7w_conv7,72,32
	.local	_ZL7w_conv6
	.comm	_ZL7w_conv6,72,32
	.local	_ZL7w_conv5
	.comm	_ZL7w_conv5,72,32
	.local	_ZL7w_conv4
	.comm	_ZL7w_conv4,72,32
	.local	_ZL7w_conv3
	.comm	_ZL7w_conv3,72,32
	.local	_ZL7w_conv2
	.comm	_ZL7w_conv2,72,32
	.local	_ZL7w_conv1
	.comm	_ZL7w_conv1,72,32
	.local	_ZL12total_dhatsq
	.comm	_ZL12total_dhatsq,64,32
	.local	_ZL10total_curr
	.comm	_ZL10total_curr,640,32
	.local	_ZL4I_in
	.comm	_ZL4I_in,64896,32
	.globl	pixspks
	.align 32
	.type	pixspks, @object
	.size	pixspks, 256000
pixspks:
	.zero	256000
	.globl	pix_spks_h
	.align 32
	.type	pix_spks_h, @object
	.size	pix_spks_h, 256000
pix_spks_h:
	.zero	256000
	.local	_ZL8pix_spks
	.comm	_ZL8pix_spks,256000,32
	.local	_ZL3Vm2
	.comm	_ZL3Vm2,80,32
	.local	_ZL3Vm1
	.comm	_ZL3Vm1,64896,32
	.local	_ZL9ref_time2
	.comm	_ZL9ref_time2,40,32
	.local	_ZL9ref_time1
	.comm	_ZL9ref_time1,32448,32
	.local	_ZL8d_hat_sq
	.comm	_ZL8d_hat_sq,64896,32
	.local	_ZL4cils
	.comm	_ZL4cils,80,32
	.local	_ZL3cil
	.comm	_ZL3cil,80,32
	.local	_ZL7norm_dh
	.comm	_ZL7norm_dh,8,8
	.local	_ZL3cis
	.comm	_ZL3cis,64896,32
	.local	_ZL5d_hat
	.comm	_ZL5d_hat,64896,32
	.local	_ZL2ci
	.comm	_ZL2ci,64896,32
	.local	_ZL5del_w
	.comm	_ZL5del_w,648960,32
	.local	_ZL4Y_op
	.comm	_ZL4Y_op,10,8
	.local	_ZL3err
	.comm	_ZL3err,10,8
	.local	_ZL4D_op
	.comm	_ZL4D_op,10000,32
	.local	_ZL5I_lat
	.comm	_ZL5I_lat,80,32
	.local	_ZL8Isyn_lat
	.comm	_ZL8Isyn_lat,80,32
	.local	_ZL8Isyn_tot
	.comm	_ZL8Isyn_tot,80,32
	.local	_ZL6weight
	.comm	_ZL6weight,648960,32
	.local	_ZL4Isyn
	.comm	_ZL4Isyn,648960,32
	.local	_ZL6in_spk
	.comm	_ZL6in_spk,8112,32
	.local	_ZL3syn
	.comm	_ZL3syn,2048000,32
	.local	_ZL5syn1s
	.comm	_ZL5syn1s,2048,32
	.local	_ZL4syn1
	.comm	_ZL4syn1,2048,32
	.local	_ZL8img_spks
	.comm	_ZL8img_spks,6272000,32
	.local	_ZL6d_imgs
	.comm	_ZL6d_imgs,157000000,32
	.globl	test_set
	.align 32
	.type	test_set, @object
	.size	test_set, 157000000
test_set:
	.zero	157000000
	.globl	img_lin
	.align 32
	.type	img_lin, @object
	.size	img_lin, 157000000
img_lin:
	.zero	157000000
	.globl	d_imgs_lin
	.align 8
	.type	d_imgs_lin, @object
	.size	d_imgs_lin, 8
d_imgs_lin:
	.zero	8
	.globl	pix_spks_d
	.align 8
	.type	pix_spks_d, @object
	.size	pix_spks_d, 8
pix_spks_d:
	.zero	8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1093567616
	.align 8
.LC1:
	.long	0
	.long	1083129856
	.align 8
.LC2:
	.long	-640172613
	.long	1038843103
	.align 8
.LC3:
	.long	-640172613
	.long	1032551647
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//2 layered neural network with LIF neurons
//computing Vm in parallel, Computing Isyn 
//all-all connectivity between 2 layers
//starting point of reading mnist set by 'start'
 

#include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include<stdlib.h>

#include "hip/hip_runtime_api.h"

#define C 300E-12
#define gL 30E-9
#define VT 20E-3
#define EL -70E-3
#define Rp 3E-3
#define dt 1E-4
#define decay 0.9802
#define decays 0.9231
#define decay1 0.9048
#define WT 5E-9

#define w_lat -1.0E-9		//inhibitory lateral strength

//num of neurons in layer 1 and layer 2
#define p 28
#define q 28
#define N_imgs 50000
#define N2 10		    //no. of neurons in 2nd layer

//Convolution parameters
#define Nw 3
#define L (p-Nw+1)	     //square matrix
#define N1 (12*L*L)	     //no. of neurons in 1st layer
#define Nthrds 1024          //use max no. of threads available per SM
#define Nsyns N1*N2	     //no. of connections
#define T 0.1
#define M 1000

//Training parameters:
#define r 20.0E-11	     //Learning Rate for 100ms 
#define max_epochs 20	     //1 complete presentation of all images

//Variables for image reading
unsigned char *pix_spks_d;
int *d_imgs_lin, img_lin[N_imgs*(p*q+1)];
int test_set[N_imgs][p*q+1];
__device__ int d_imgs[N_imgs][p*q+1];
__device__ double img_spks[p*q][M];
__device__ double syn1[256], syn1s[256], syn[256][M];

__device__ unsigned char in_spk[N1];
__device__ double Isyn[N1][N2], weight[N1][N2];
__device__ double Isyn_tot[N2], Isyn_lat[N2];
__device__ double I_lat[N2];

//weight update variables:
__device__ unsigned char D_op[N2][M];
__device__ signed char err[N2];
__device__ unsigned char Y_op[N2];
__device__ double del_w[N1][N2]; 
__device__ double ci[N1], d_hat[N1];
__device__ double cis[N1], norm_dh; 
__device__ double cil[N2], cils[N2];
__device__ double d_hat_sq[N1];

//Neuron variables:
__device__ int ref_time1[N1],ref_time2[N2];
__device__ double Vm1[N1],Vm2[N2];

////////////CUDA Kernels///////////
__global__ void img_readKernel(int *img)
{
    for(int i=0; i<N_imgs; i++){
        for(int j=0; j<(p*q+1); j++){
	    d_imgs[i][j]=img[i*(p*q+1)+j];
	}
    }
}

__device__ unsigned char pix_spks[256][M];
unsigned char pix_spks_h[256*M];

//uniformly spaced spikes
__global__ void convert2Spks(unsigned char *pix_spks_d)
{

    for(int i=0; i<256; i++) {
	syn1[i]=0.0; syn1s[i]=0.0;
        for(int l=0; l<M; l++) {
	    pix_spks[i][l]=pix_spks_d[i*M+l];
	}
    }

    //Compute the synaptic kernels:
    for(int i=0; i<256; i++) {
        for(int l=0; l<M; l++) {
            syn1[i]*=decay; syn1s[i]*=decays;
            if(pix_spks[i][l]==1) {
                syn1[i]+=1.0;
                syn1s[i]+=1.0;
            }
            syn[i][l]=syn1[i]-syn1s[i];
	}
    }
}

unsigned char pixspks[256*M];

__global__ void pix2spks(int k, int i) 
{
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<(p*q)) {
	img_spks[tx][i]=syn[d_imgs[k][tx+1]][i];
        __syncthreads();
    }
}


__global__ void createDes(int k) {
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<N2) {
	for(int i=0; i<M;i++) {
	    D_op[tx][i]=0;
	}
	if(tx==d_imgs[k][0]) {
	    for(int i=100; i<M; i+=35) 
		D_op[tx][i]=1;
	}
    }
}

/*__global__ void pix2spks(int k)
{
    //Load the spikes trains for the corresponding pixels:
    for(int i=1; i<(p*q+1); i++) {
         for(int l=0; l<M; l++) {
             img_spks[i-1][l]=syn[d_imgs[k][i]][l];
         }
    }

    //Create the desired spike trains:
    for(int j=0; j<N2; j++) {
        for(int i=0; i<M; i++) {
            D_op[j][i]=0;
        }
        if(j==d_imgs[k][0]) {
            //for(int i=100; i<M; i+=50)
            for(int i=100; i<M; i+=35)
                D_op[j][i]=1;
        }
    }
}*/

__device__ double I_in[N1];

__global__ void clear_vars()
{
    int tx=threadIdx.x+blockIdx.x*blockDim.x;
    int ty=threadIdx.y+blockIdx.y*blockDim.y;

    if(tx<N1 && ty<N2) {
    	Vm2[ty]=EL; Isyn_tot[ty]=0.0; 
	ref_time2[ty]=0.0;
	Vm1[tx]=EL; ref_time1[tx]=0.0;
	I_in[tx]=0.0;

	del_w[tx][ty]=0.0; 
	Isyn[tx][ty]=0.0; 
	ci[tx]=0.0; cis[tx]=0.0; d_hat[tx]=0.0;

	cil[ty]=0.0; cils[ty]=0.0;
	Isyn_lat[ty]=0.0;
    }
}

__global__ void LifKernel1(int i)
{
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    double k1, k2;

    if(j<N1) {
	
	if(ref_time1[j]<i) ref_time1[j]=0;

        k1=(-gL*(Vm1[j]-EL)+I_in[j])/C;
	k2=(-gL*((Vm1[j]+dt*k1)-EL)+I_in[j])/C;

	Vm1[j]+=(dt*(k1+k2)/2)*(ref_time1[j]==0);

	if(Vm1[j]<EL) Vm1[j]=EL;

        if(Vm1[j]>=VT) {
	    Vm1[j]=EL;
	    ref_time1[j]=i+round(Rp/dt);
	    in_spk[j]=1;
	} else {
	    in_spk[j]=0;
	}
        __syncthreads();
    }
}

__global__ void LifKernel2(int i)
{
    int j = blockIdx.x * blockDim.x + threadIdx.x;
    double k1, k2;

    if(j<N2) {
	if(ref_time2[j]<i) ref_time2[j]=0;

        k1=(-gL*(Vm2[j]-EL)+Isyn_tot[j]+Isyn_lat[j])/C;
	k2=(-gL*((Vm2[j]+dt*k1)-EL)+Isyn_tot[j]+Isyn_lat[j])/C;

	Vm2[j]+=(dt*(k1+k2)/2)*(ref_time2[j]==0);
	if(Vm2[j]<EL) Vm2[j]=EL;

        if(Vm2[j]>=VT) {
	    Vm2[j]=EL;
	    ref_time2[j]=i+round(Rp/dt);
	    Y_op[j]=1;
	} else {
	    Y_op[j]=0;
	}

	//compute the error:
	err[j]=D_op[j][i]-Y_op[j];

        __syncthreads();
    }
}

//kernels for the total synapses in the network
__global__ void SynKernel(int i)
{
    int ix=blockIdx.x*blockDim.x + threadIdx.x;
    int iy=blockIdx.y*blockDim.y + threadIdx.y;

    if(ix<N1 && iy<N2) {
        if(iy==0) {
   	    ci[ix]=ci[ix]*decay;
	    cis[ix]=cis[ix]*decays;
            if(in_spk[ix]==1) {
	        ci[ix]+=1.0;
	        cis[ix]+=1.0;
	    }
	    d_hat[ix]=d_hat[ix]*decay1 + ((ci[ix]-cis[ix])*dt)/C;
	    d_hat_sq[ix]=d_hat[ix]*d_hat[ix];

	}
	__syncthreads();
        Isyn[ix][iy]=(ci[ix]-cis[ix])*weight[ix][iy];
    }
}

__global__ void Lat_curr(int i)
{
    int ix=blockIdx.x*blockDim.x+threadIdx.x;

    if(ix<N2) {
   	cil[ix]=cil[ix]*decay;
	cils[ix]=cils[ix]*decays;
        if(Y_op[ix]==1) {
	    cil[ix]+=1.0;
	    cils[ix]+=1.0;
	}

	I_lat[ix]=w_lat*(cil[ix]-cils[ix]);

	Isyn_lat[ix]=0;
	for(int k=0; k<N2; k++) {
	    if(k!=ix) {
		Isyn_lat[ix]+=I_lat[k];
	    }
	}
    }
}

__device__ double total_curr[8][N2];
__device__ double total_dhatsq[8];

//optimized version
__global__ void IsynRedKernel(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int tid=threadIdx.x;

    for(unsigned int s=blockDim.x/2;s>0;s>>=1) {
        if(iy<N2 && tid<s && (ix+s)<N1) {
	    Isyn[ix][iy]+=Isyn[ix+s][iy];
	}
	if(iy==0 && tid<s && (ix+s)<N1) {
	    d_hat_sq[ix]+=d_hat_sq[ix+s];
        }
	__syncthreads();
    }

    if(tid==0 && iy<N2) {
	total_curr[blockIdx.x][iy]=Isyn[ix][iy];
	if(iy==0) {
	    total_dhatsq[blockIdx.x]=d_hat_sq[ix];
	}
    }
}

__global__ void reduce1(int i) {
    int tx=threadIdx.x+blockIdx.x*blockDim.x;

    if(tx<N2) {
	double total1=0.0;
	for(int k=0; k<8; k++) {
	    total1+=total_curr[k][tx];
	}
	Isyn_tot[tx]=total1;

        if(tx==0) {
	    double total2=0.0;
	    for(int j=0; j<8; j++) 
		total2+=total_dhatsq[j];

	    norm_dh=sqrt(total2);
	}
    }
}

__global__ void CalcUpdate(int i, double l_rate)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
        if(norm_dh!=0 && err[iy]!=0) {
	    del_w[ix][iy]+=(err[iy]*l_rate*d_hat[ix]/norm_dh);
	}
	__syncthreads();
    }
}

__global__ void WtUpdt()
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
        weight[ix][iy]+=del_w[ix][iy];
    }
}

__global__ void cpyWts(double *wts)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;

    if(ix<N1 && iy<N2) {
	wts[ix*N2+iy]=weight[ix][iy];
    }
}

__device__ double w_conv1[Nw][Nw], w_conv2[Nw][Nw];
__device__ double w_conv3[Nw][Nw], w_conv4[Nw][Nw];
__device__ double w_conv5[Nw][Nw], w_conv6[Nw][Nw];
__device__ double w_conv7[Nw][Nw], w_conv8[Nw][Nw];
__device__ double w_conv9[Nw][Nw], w_conv10[Nw][Nw];
__device__ double w_conv11[Nw][Nw], w_conv12[Nw][Nw];

__global__ void initialize2D(double *d_wts, double *c_wts)
{
   for(int i=0; i<N1; i++) {
       for(int j=0; j<N2; j++) {
           weight[i][j]=d_wts[i*N2+j];
	}
    }

    for(int i=0; i<(12*Nw); i++) {
        for(int j=0; j<Nw; j++) {
	    if(i<Nw) {
	    	w_conv1[i][j]=c_wts[i*Nw+j];
	    } else if(i>=Nw && i<(2*Nw)) {
	        w_conv2[i-Nw][j]=c_wts[i*Nw+j];
	    } else if(i>=(2*Nw) && i<(3*Nw)) {
	        w_conv3[i-(2*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(3*Nw) && i<(4*Nw)){
	        w_conv4[i-(3*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(4*Nw) && i<(5*Nw)){
	        w_conv5[i-(4*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(5*Nw) && i<(6*Nw)){
	        w_conv6[i-(5*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(6*Nw) && i<(7*Nw)){
	        w_conv7[i-(6*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(7*Nw) && i<(8*Nw)){
	        w_conv8[i-(7*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(8*Nw) && i<(9*Nw)){
	        w_conv9[i-(8*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(9*Nw) && i<(10*Nw)){
	        w_conv10[i-(9*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(10*Nw) && i<(11*Nw)){
	        w_conv11[i-(10*Nw)][j]=c_wts[i*Nw+j];
	    } else if(i>=(11*Nw) && i<(12*Nw)){
	        w_conv12[i-(11*Nw)][j]=c_wts[i*Nw+j];
	    }
	}
    }
}

__global__ void convKernel1(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv1[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[ix*L+iy]=temp;
    }
}

__global__ void convKernel2(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv2[x][y]*img_spks[(ix+x)*q+iy+y][i]; 
	    }
        }

	I_in[L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel3(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv3[x][y]*img_spks[(ix+x)*q+iy+y][i];
	    }
        }
    
        I_in[2*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel4(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv4[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[3*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel5(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv5[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }
        
	I_in[4*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel6(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv6[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[5*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel7(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv7[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[6*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel8(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv8[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[7*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel9(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv9[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[8*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel10(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv10[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[9*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel11(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv11[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[10*L*L+ix*L+iy]=temp;
    }
}

__global__ void convKernel12(int i)
{
    int ix=threadIdx.x+blockIdx.x*blockDim.x;
    int iy=threadIdx.y+blockIdx.y*blockDim.y;
    int x, y;

    if(ix<L && iy<L) {
        double temp=0.0;
	for(x=0; x<Nw; x++) {
	    for(y=0; y<Nw; y++) {
	        temp+=WT*w_conv12[x][y]*img_spks[(ix+x)*q+iy+y][i];
            }
        }

	I_in[11*L*L+ix*L+iy]=temp;
    }
}

long timediff(clock_t t1, clock_t t2) {
    long elapsed;
    elapsed = ((double)t2 - t1) / CLOCKS_PER_SEC * 1000;
    return elapsed;
}
 
double h_wts[N1*N2], *d_wts;
double *dcwts;
double h_wts_saved[N1*N2], *d_wts_saved;
double c_wts[12*Nw*Nw];

int main(int argc, char *argv[])
{
    int start=atoi(argv[1]);
    FILE *FW, *FWI;	//to load initial wts and store final wts
    FILE *conv_wt;
 
    clock_t t1, t2;
    long elapsed=0;

    FILE *F_train, *F_lif_spks;

    //for concurrent execution of different kernels:
    hipStream_t stream2, stream3, stream4, stream5, stream6;
    hipStream_t stream7, stream8, stream9, stream10, stream11, stream12;
    hipStream_t stream13, stream14,stream15;

    //set the gpu device:
    hipSetDevice(4);

    hipStreamCreate(&stream2);
    hipStreamCreate(&stream3);
    hipStreamCreate(&stream4);
    hipStreamCreate(&stream5);
    hipStreamCreate(&stream6);
    hipStreamCreate(&stream7);
    hipStreamCreate(&stream8);
    hipStreamCreate(&stream9);
    hipStreamCreate(&stream10);
    hipStreamCreate(&stream11);
    hipStreamCreate(&stream12);
    hipStreamCreate(&stream13);
    hipStreamCreate(&stream14);
    hipStreamCreate(&stream15);

    F_lif_spks = fopen("pixels_spks.csv","r");
    if(F_lif_spks == NULL)
    {
	perror("Error while opening file pixels_spks.csv\n");
	exit(EXIT_FAILURE);
    }

    F_train = fopen("mnist_train.csv","r");
    //F_test = fopen("mnist_test.csv","r");
    if(F_train == NULL)
    {
	perror("Error while opening file mnist_train.csv\n");
	exit(EXIT_FAILURE);
    }

    FWI = fopen("wts_initial.csv","r");
    if(FWI == NULL)
    {
	perror("Error while opening file wts_trained.csv\n");
	exit(EXIT_FAILURE);
    }

    conv_wt=fopen("kernels_3x3.csv","r");
    if(conv_wt==NULL) {
	perror("Error while opening file kernel.csv\n");
    	exit(EXIT_FAILURE);
    }

    printf("Total no. of neurons=%d, no. of synapses to be trained=%d\n",(N1+N2), N1*N2);
    hipMalloc((void**)&d_imgs_lin,sizeof(int)*(N_imgs*(p*q+1)));
    hipMalloc((void**)&d_wts,N1*N2*sizeof(double));
    hipMalloc((void**)&dcwts,12*Nw*Nw*sizeof(double));
    hipMalloc((void**)&d_wts_saved,N1*N2*sizeof(double));
    hipMalloc((void**)&pix_spks_d,256*M*sizeof(unsigned char));

    //Read the initial weights: 
    //printf("Reading final trained weights from file\n");
    for(int i=0; i<N1; i++) {
        for(int j=0; j<N2; j++) {
	    fscanf(FWI,"%lf,",&h_wts[i*N2+j]);
	}
    }
    fclose(FWI);

    for(int i=0; i<(12*Nw); i++) {
        for(int j=0; j<Nw; j++) {
	    fscanf(conv_wt,"%lf,",&c_wts[i*Nw+j]);
	}
    }
    fclose(conv_wt);

    for(int i=0; i<(256); i++) {
    	for(int j=0; j<M; j++) {
	    fscanf(F_lif_spks,"%d,",&pix_spks_h[i*M+j]);
	}
    }
    fclose(F_lif_spks);

    hipMemcpy(pix_spks_d,pix_spks_h,256*M*sizeof(unsigned char),hipMemcpyHostToDevice);
    hipMemcpy(d_wts,h_wts,N1*N2*sizeof(double),hipMemcpyHostToDevice);
    hipMemcpy(dcwts,c_wts,12*Nw*Nw*sizeof(double),hipMemcpyHostToDevice);

    initialize2D<<<1,1>>>(d_wts,dcwts);
    hipDeviceSynchronize();
    hipFree(d_wts);
    hipFree(dcwts);

    //Read the images from file:
    for(int n=0;n<N_imgs;n++) {
        for(int j=0;j<(p*q+1);j++) {
            fscanf(F_train,"%d,",&test_set[n][j]);
        }
    }
    fclose(F_train);

    //convert 2D matrix to 1D for transfer to device:
    for(int n=0; n<(N_imgs);n++) {
        for(int j=0;j<(p*q+1);j++) {
            img_lin[n*(p*q+1)+j]=test_set[n][j];
        }
    }

    hipMemcpy(d_imgs_lin,img_lin,sizeof(int)*(N_imgs*(p*q+1)),hipMemcpyHostToDevice);

    //call cuda kernel to read in the images:
    img_readKernel<<<1,1>>>(d_imgs_lin);
    hipDeviceSynchronize();
    hipFree(d_imgs_lin);

    int NBlks=(N1/Nthrds)+1;
    //printf("blocks=%d, threads=%d\n",NBlks,Nthrds);

    dim3 dimGrid(82,1,1);
    dim3 dimBlock(100,10,1);

    dim3 grid_syn(NBlks,10,1);
    dim3 block_syn(Nthrds,1,1);

    //convert pixel values 0 to 255 into spike trains
    convert2Spks<<<1,1>>>(pix_spks_d);
    hipDeviceSynchronize();
    hipFree(pix_spks_d);
    
    dim3 convGrid(1,1,1);
    dim3 convBlks(26,26,1);

    double learn=r;
    //CPU time required for computation
    t1 = clock();
           
    int l=0;				//image index
    for(int n=0; n<max_epochs; n++) {
        printf("Epoch=%d\n",n);

	if(n<3) learn=r;
	else if(n>=3 && n<6) learn=r/2;
	else if(n>=6 && n<9) learn=r/4;
	else if(n>=9 && n<12) learn=r/8;
	else if(n>=12 && n<15) learn=r/16;
	else if(n>=15 && n<18) learn=r/32;
	else learn=r/64;

        for(l=0; l<N_imgs; l++) {
            printf("l=%d image %d\n",l,test_set[l][0]);

	    createDes<<<1,10>>>(l);

	    clear_vars<<<dimGrid,dimBlock>>>();
            hipDeviceSynchronize();

            //simulate for all time steps
            for(int i=0; i<M; i++) {
                pix2spks<<<1,784>>>(l,i);
		///////////////////////////////////////////////////
		hipDeviceSynchronize();
                convKernel1<<<convGrid,convBlks,0,stream2>>>(i);
                convKernel2<<<convGrid,convBlks,0,stream3>>>(i);
                convKernel3<<<convGrid,convBlks,0,stream4>>>(i);
                convKernel4<<<convGrid,convBlks,0,stream5>>>(i);
                convKernel5<<<convGrid,convBlks,0,stream6>>>(i);
                convKernel6<<<convGrid,convBlks,0,stream7>>>(i);
                convKernel7<<<convGrid,convBlks,0,stream8>>>(i);
                convKernel8<<<convGrid,convBlks,0,stream9>>>(i);
                convKernel9<<<convGrid,convBlks,0,stream10>>>(i);
                convKernel10<<<convGrid,convBlks,0,stream11>>>(i);
                convKernel11<<<convGrid,convBlks,0,stream12>>>(i);
                convKernel12<<<convGrid,convBlks,0,stream13>>>(i);
		/////////////////////////////////////////////////////
		hipDeviceSynchronize();

                LifKernel1<<<NBlks,Nthrds>>>(i);
		////////////////////////////////////////////////
		hipDeviceSynchronize();
                SynKernel<<<dimGrid,dimBlock,0,stream14>>>(i);
		Lat_curr<<<1,10,0,stream15>>>(i);
		////////////////////////////////////////////////

                hipDeviceSynchronize();
                IsynRedKernel<<<grid_syn,block_syn>>>(i);
	        reduce1<<<10,1>>>(i);

		///////////////////////////////////////////////
                hipDeviceSynchronize();
                LifKernel2<<<1,10>>>(i);
		////////////////////////////////////////////////////
                hipDeviceSynchronize();
		CalcUpdate<<<dimGrid,dimBlock>>>(i,learn);
	    }

//////////////////////////////////////////////////////////////////////////////
	    WtUpdt<<<dimGrid,dimBlock>>>();
            //cudaDeviceSynchronize();
        }		//end of loops over N_imgs

        t2 = clock();
        elapsed += timediff(t1,t2);
        printf("Elapsed time: %ld ms\n", elapsed);

	char wts_file[25];
	sprintf(wts_file,"wts_gpu%d.txt",n);

	if((FW=fopen(wts_file,"w"))==NULL) {
	    printf("Failed to open file wts_gpu_sample%d.txt\n",n);
        }

	printf("Copying the trained weights to the host for analysis\n");
    	cpyWts<<<dimGrid,dimBlock>>>(d_wts_saved);
	hipMemcpy(h_wts_saved,d_wts_saved,N1*N2*sizeof(double), hipMemcpyDeviceToHost);

	//save the weights in a file:
    	for(int i=0; i<N1; i++) {
    	    for(int j=0; j<N2; j++) {
        	fprintf(FW,"%0.14f,",h_wts_saved[i*N2+j]);
            }
            fprintf(FW,"\n");
    	}
	fclose(FW);
    }				//end of n epochs loops

    hipFree(d_wts_saved);
 
    hipDeviceReset();
    return(0);
}

	.text
	.file	"snn_train.hip"
	.globl	_Z29__device_stub__img_readKernelPi # -- Begin function _Z29__device_stub__img_readKernelPi
	.type	_Z29__device_stub__img_readKernelPi,@function
_Z29__device_stub__img_readKernelPi:    # @_Z29__device_stub__img_readKernelPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14img_readKernelPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__img_readKernelPi, .Lfunc_end0-_Z29__device_stub__img_readKernelPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__convert2SpksPh # -- Begin function _Z27__device_stub__convert2SpksPh
	.type	_Z27__device_stub__convert2SpksPh,@function
_Z27__device_stub__convert2SpksPh:      # @_Z27__device_stub__convert2SpksPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12convert2SpksPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__convert2SpksPh, .Lfunc_end1-_Z27__device_stub__convert2SpksPh
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__pix2spksii   # -- Begin function _Z23__device_stub__pix2spksii
	.type	_Z23__device_stub__pix2spksii,@function
_Z23__device_stub__pix2spksii:          # @_Z23__device_stub__pix2spksii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8pix2spksii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__pix2spksii, .Lfunc_end2-_Z23__device_stub__pix2spksii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__createDesi   # -- Begin function _Z24__device_stub__createDesi
	.type	_Z24__device_stub__createDesi,@function
_Z24__device_stub__createDesi:          # @_Z24__device_stub__createDesi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9createDesi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z24__device_stub__createDesi, .Lfunc_end3-_Z24__device_stub__createDesi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__clear_varsv  # -- Begin function _Z25__device_stub__clear_varsv
	.type	_Z25__device_stub__clear_varsv,@function
_Z25__device_stub__clear_varsv:         # @_Z25__device_stub__clear_varsv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z10clear_varsv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__clear_varsv, .Lfunc_end4-_Z25__device_stub__clear_varsv
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__LifKernel1i  # -- Begin function _Z25__device_stub__LifKernel1i
	.type	_Z25__device_stub__LifKernel1i,@function
_Z25__device_stub__LifKernel1i:         # @_Z25__device_stub__LifKernel1i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10LifKernel1i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__LifKernel1i, .Lfunc_end5-_Z25__device_stub__LifKernel1i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__LifKernel2i  # -- Begin function _Z25__device_stub__LifKernel2i
	.type	_Z25__device_stub__LifKernel2i,@function
_Z25__device_stub__LifKernel2i:         # @_Z25__device_stub__LifKernel2i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10LifKernel2i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z25__device_stub__LifKernel2i, .Lfunc_end6-_Z25__device_stub__LifKernel2i
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__SynKerneli   # -- Begin function _Z24__device_stub__SynKerneli
	.type	_Z24__device_stub__SynKerneli,@function
_Z24__device_stub__SynKerneli:          # @_Z24__device_stub__SynKerneli
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9SynKerneli, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z24__device_stub__SynKerneli, .Lfunc_end7-_Z24__device_stub__SynKerneli
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__Lat_curri    # -- Begin function _Z23__device_stub__Lat_curri
	.type	_Z23__device_stub__Lat_curri,@function
_Z23__device_stub__Lat_curri:           # @_Z23__device_stub__Lat_curri
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Lat_curri, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z23__device_stub__Lat_curri, .Lfunc_end8-_Z23__device_stub__Lat_curri
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__IsynRedKerneli # -- Begin function _Z28__device_stub__IsynRedKerneli
	.type	_Z28__device_stub__IsynRedKerneli,@function
_Z28__device_stub__IsynRedKerneli:      # @_Z28__device_stub__IsynRedKerneli
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13IsynRedKerneli, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z28__device_stub__IsynRedKerneli, .Lfunc_end9-_Z28__device_stub__IsynRedKerneli
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__reduce1i     # -- Begin function _Z22__device_stub__reduce1i
	.type	_Z22__device_stub__reduce1i,@function
_Z22__device_stub__reduce1i:            # @_Z22__device_stub__reduce1i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7reduce1i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z22__device_stub__reduce1i, .Lfunc_end10-_Z22__device_stub__reduce1i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__CalcUpdateid # -- Begin function _Z25__device_stub__CalcUpdateid
	.type	_Z25__device_stub__CalcUpdateid,@function
_Z25__device_stub__CalcUpdateid:        # @_Z25__device_stub__CalcUpdateid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10CalcUpdateid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z25__device_stub__CalcUpdateid, .Lfunc_end11-_Z25__device_stub__CalcUpdateid
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__WtUpdtv      # -- Begin function _Z21__device_stub__WtUpdtv
	.type	_Z21__device_stub__WtUpdtv,@function
_Z21__device_stub__WtUpdtv:             # @_Z21__device_stub__WtUpdtv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z6WtUpdtv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z21__device_stub__WtUpdtv, .Lfunc_end12-_Z21__device_stub__WtUpdtv
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__cpyWtsPd     # -- Begin function _Z21__device_stub__cpyWtsPd
	.type	_Z21__device_stub__cpyWtsPd,@function
_Z21__device_stub__cpyWtsPd:            # @_Z21__device_stub__cpyWtsPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6cpyWtsPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z21__device_stub__cpyWtsPd, .Lfunc_end13-_Z21__device_stub__cpyWtsPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__initialize2DPdS_ # -- Begin function _Z27__device_stub__initialize2DPdS_
	.type	_Z27__device_stub__initialize2DPdS_,@function
_Z27__device_stub__initialize2DPdS_:    # @_Z27__device_stub__initialize2DPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12initialize2DPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z27__device_stub__initialize2DPdS_, .Lfunc_end14-_Z27__device_stub__initialize2DPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel1i # -- Begin function _Z26__device_stub__convKernel1i
	.type	_Z26__device_stub__convKernel1i,@function
_Z26__device_stub__convKernel1i:        # @_Z26__device_stub__convKernel1i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel1i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z26__device_stub__convKernel1i, .Lfunc_end15-_Z26__device_stub__convKernel1i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel2i # -- Begin function _Z26__device_stub__convKernel2i
	.type	_Z26__device_stub__convKernel2i,@function
_Z26__device_stub__convKernel2i:        # @_Z26__device_stub__convKernel2i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel2i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z26__device_stub__convKernel2i, .Lfunc_end16-_Z26__device_stub__convKernel2i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel3i # -- Begin function _Z26__device_stub__convKernel3i
	.type	_Z26__device_stub__convKernel3i,@function
_Z26__device_stub__convKernel3i:        # @_Z26__device_stub__convKernel3i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel3i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z26__device_stub__convKernel3i, .Lfunc_end17-_Z26__device_stub__convKernel3i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel4i # -- Begin function _Z26__device_stub__convKernel4i
	.type	_Z26__device_stub__convKernel4i,@function
_Z26__device_stub__convKernel4i:        # @_Z26__device_stub__convKernel4i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel4i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z26__device_stub__convKernel4i, .Lfunc_end18-_Z26__device_stub__convKernel4i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel5i # -- Begin function _Z26__device_stub__convKernel5i
	.type	_Z26__device_stub__convKernel5i,@function
_Z26__device_stub__convKernel5i:        # @_Z26__device_stub__convKernel5i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel5i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z26__device_stub__convKernel5i, .Lfunc_end19-_Z26__device_stub__convKernel5i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel6i # -- Begin function _Z26__device_stub__convKernel6i
	.type	_Z26__device_stub__convKernel6i,@function
_Z26__device_stub__convKernel6i:        # @_Z26__device_stub__convKernel6i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel6i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z26__device_stub__convKernel6i, .Lfunc_end20-_Z26__device_stub__convKernel6i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel7i # -- Begin function _Z26__device_stub__convKernel7i
	.type	_Z26__device_stub__convKernel7i,@function
_Z26__device_stub__convKernel7i:        # @_Z26__device_stub__convKernel7i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel7i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z26__device_stub__convKernel7i, .Lfunc_end21-_Z26__device_stub__convKernel7i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel8i # -- Begin function _Z26__device_stub__convKernel8i
	.type	_Z26__device_stub__convKernel8i,@function
_Z26__device_stub__convKernel8i:        # @_Z26__device_stub__convKernel8i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel8i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z26__device_stub__convKernel8i, .Lfunc_end22-_Z26__device_stub__convKernel8i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convKernel9i # -- Begin function _Z26__device_stub__convKernel9i
	.type	_Z26__device_stub__convKernel9i,@function
_Z26__device_stub__convKernel9i:        # @_Z26__device_stub__convKernel9i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convKernel9i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z26__device_stub__convKernel9i, .Lfunc_end23-_Z26__device_stub__convKernel9i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__convKernel10i # -- Begin function _Z27__device_stub__convKernel10i
	.type	_Z27__device_stub__convKernel10i,@function
_Z27__device_stub__convKernel10i:       # @_Z27__device_stub__convKernel10i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12convKernel10i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z27__device_stub__convKernel10i, .Lfunc_end24-_Z27__device_stub__convKernel10i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__convKernel11i # -- Begin function _Z27__device_stub__convKernel11i
	.type	_Z27__device_stub__convKernel11i,@function
_Z27__device_stub__convKernel11i:       # @_Z27__device_stub__convKernel11i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12convKernel11i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	_Z27__device_stub__convKernel11i, .Lfunc_end25-_Z27__device_stub__convKernel11i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__convKernel12i # -- Begin function _Z27__device_stub__convKernel12i
	.type	_Z27__device_stub__convKernel12i,@function
_Z27__device_stub__convKernel12i:       # @_Z27__device_stub__convKernel12i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12convKernel12i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	_Z27__device_stub__convKernel12i, .Lfunc_end26-_Z27__device_stub__convKernel12i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z8timediffll
.LCPI27_0:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI27_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	_Z8timediffll
	.type	_Z8timediffll,@function
_Z8timediffll:                          # @_Z8timediffll
	.cfi_startproc
# %bb.0:
	cvtsi2sd	%rsi, %xmm0
	cvtsi2sd	%rdi, %xmm1
	subsd	%xmm1, %xmm0
	divsd	.LCPI27_0(%rip), %xmm0
	mulsd	.LCPI27_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	retq
.Lfunc_end27:
	.size	_Z8timediffll, .Lfunc_end27-_Z8timediffll
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI28_0:
	.quad	0x3deb7cdfd9d7bdbb              # double 2.0000000000000001E-10
.LCPI28_1:
	.quad	0x3ddb7cdfd9d7bdbb              # double 1.0E-10
.LCPI28_2:
	.quad	0x3dcb7cdfd9d7bdbb              # double 5.0000000000000002E-11
.LCPI28_3:
	.quad	0x3dbb7cdfd9d7bdbb              # double 2.5000000000000001E-11
.LCPI28_4:
	.quad	0x3dab7cdfd9d7bdbb              # double 1.25E-11
.LCPI28_6:
	.quad	0x412e848000000000              # double 1.0E+6
.LCPI28_7:
	.quad	0x408f400000000000              # double 1000
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	3, 0x0
.LCPI28_5:
	.quad	0x3d8b7cdfd9d7bdbb              # double 3.1250000000000001E-12
	.quad	0x3d9b7cdfd9d7bdbb              # double 6.2500000000000002E-12
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4, %edi
	callq	hipSetDevice
	leaq	168(%rsp), %rdi
	callq	hipStreamCreate
	leaq	160(%rsp), %rdi
	callq	hipStreamCreate
	leaq	152(%rsp), %rdi
	callq	hipStreamCreate
	leaq	144(%rsp), %rdi
	callq	hipStreamCreate
	leaq	136(%rsp), %rdi
	callq	hipStreamCreate
	leaq	128(%rsp), %rdi
	callq	hipStreamCreate
	leaq	120(%rsp), %rdi
	callq	hipStreamCreate
	leaq	112(%rsp), %rdi
	callq	hipStreamCreate
	leaq	104(%rsp), %rdi
	callq	hipStreamCreate
	leaq	96(%rsp), %rdi
	callq	hipStreamCreate
	leaq	88(%rsp), %rdi
	callq	hipStreamCreate
	leaq	80(%rsp), %rdi
	callq	hipStreamCreate
	leaq	72(%rsp), %rdi
	callq	hipStreamCreate
	leaq	64(%rsp), %rdi
	callq	hipStreamCreate
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB28_1
# %bb.3:
	movq	%rax, %r15
	movl	$.L.str.3, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB28_4
# %bb.5:
	movq	%rax, %rbx
	movl	$.L.str.5, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB28_6
# %bb.7:
	movq	%rax, %r12
	movq	%rbx, (%rsp)                    # 8-byte Spill
	movl	$.L.str.7, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB28_8
# %bb.9:
	movq	%rax, %rbx
	movl	$.L.str.9, %edi
	movl	$8122, %esi                     # imm = 0x1FBA
	movl	$81120, %edx                    # imm = 0x13CE0
	xorl	%eax, %eax
	callq	printf
	movl	$d_imgs_lin, %edi
	movl	$157000000, %esi                # imm = 0x95BA140
	callq	hipMalloc
	movl	$d_wts, %edi
	movl	$648960, %esi                   # imm = 0x9E700
	callq	hipMalloc
	movl	$dcwts, %edi
	movl	$864, %esi                      # imm = 0x360
	callq	hipMalloc
	movl	$d_wts_saved, %edi
	movl	$648960, %esi                   # imm = 0x9E700
	callq	hipMalloc
	movl	$pix_spks_d, %edi
	movl	$256000, %esi                   # imm = 0x3E800
	callq	hipMalloc
	movl	$h_wts, %r13d
	xorl	%ebp, %ebp
.LBB28_10:                              # %.preheader462
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB28_11 Depth 2
	xorl	%r14d, %r14d
.LBB28_11:                              #   Parent Loop BB28_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r14,%r13), %rdx
	movl	$.L.str.10, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$8, %r14
	cmpq	$80, %r14
	jne	.LBB28_11
# %bb.12:                               #   in Loop: Header=BB28_10 Depth=1
	incq	%rbp
	addq	$80, %r13
	cmpq	$8112, %rbp                     # imm = 0x1FB0
	jne	.LBB28_10
# %bb.13:
	movq	%r12, %rdi
	callq	fclose
	movl	$c_wts, %r12d
	xorl	%r13d, %r13d
.LBB28_14:                              # %.preheader461
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB28_15 Depth 2
	xorl	%r14d, %r14d
.LBB28_15:                              #   Parent Loop BB28_14 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r12,%r14), %rdx
	movl	$.L.str.10, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$8, %r14
	cmpq	$24, %r14
	jne	.LBB28_15
# %bb.16:                               #   in Loop: Header=BB28_14 Depth=1
	incq	%r13
	addq	$24, %r12
	cmpq	$36, %r13
	jne	.LBB28_14
# %bb.17:
	movq	%rbx, %rdi
	callq	fclose
	movl	$pix_spks_h, %ebx
	xorl	%r12d, %r12d
	movq	(%rsp), %r13                    # 8-byte Reload
.LBB28_18:                              # %.preheader460
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB28_19 Depth 2
	xorl	%r14d, %r14d
.LBB28_19:                              #   Parent Loop BB28_18 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%rbx,%r14), %rdx
	movl	$.L.str.11, %esi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	incq	%r14
	cmpq	$1000, %r14                     # imm = 0x3E8
	jne	.LBB28_19
# %bb.20:                               #   in Loop: Header=BB28_18 Depth=1
	incq	%r12
	addq	$1000, %rbx                     # imm = 0x3E8
	cmpq	$256, %r12                      # imm = 0x100
	jne	.LBB28_18
# %bb.21:
	movabsq	$4294967297, %rbx               # imm = 0x100000001
	movq	%r15, %rdi
	callq	fclose
	movq	pix_spks_d(%rip), %rdi
	movl	$pix_spks_h, %esi
	movl	$256000, %edx                   # imm = 0x3E800
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_wts(%rip), %rdi
	movl	$h_wts, %esi
	movl	$648960, %edx                   # imm = 0x9E700
	movl	$1, %ecx
	callq	hipMemcpy
	movq	dcwts(%rip), %rdi
	movl	$c_wts, %esi
	movl	$864, %edx                      # imm = 0x360
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_23
# %bb.22:
	movq	d_wts(%rip), %rdi
	movq	dcwts(%rip), %rsi
	callq	_Z27__device_stub__initialize2DPdS_
.LBB28_23:
	callq	hipDeviceSynchronize
	movq	d_wts(%rip), %rdi
	callq	hipFree
	movq	dcwts(%rip), %rdi
	callq	hipFree
	movl	$test_set, %r15d
	xorl	%r12d, %r12d
.LBB28_24:                              # %.preheader459
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB28_25 Depth 2
	xorl	%r14d, %r14d
.LBB28_25:                              #   Parent Loop BB28_24 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r15,%r14), %rdx
	movl	$.L.str.11, %esi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r14
	cmpq	$3140, %r14                     # imm = 0xC44
	jne	.LBB28_25
# %bb.26:                               #   in Loop: Header=BB28_24 Depth=1
	incq	%r12
	addq	$3140, %r15                     # imm = 0xC44
	cmpq	$50000, %r12                    # imm = 0xC350
	jne	.LBB28_24
# %bb.27:
	movq	%r13, %rdi
	callq	fclose
	xorl	%r14d, %r14d
.LBB28_28:                              # %.preheader458
                                        # =>This Inner Loop Header: Depth=1
	leaq	img_lin(%r14), %rdi
	leaq	test_set(%r14), %rsi
	movl	$3140, %edx                     # imm = 0xC44
	callq	memcpy@PLT
	addq	$3140, %r14                     # imm = 0xC44
	cmpq	$157000000, %r14                # imm = 0x95BA140
	jne	.LBB28_28
# %bb.29:
	movq	d_imgs_lin(%rip), %rdi
	movl	$img_lin, %esi
	movl	$157000000, %edx                # imm = 0x95BA140
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_31
# %bb.30:
	movq	d_imgs_lin(%rip), %rdi
	callq	_Z29__device_stub__img_readKernelPi
.LBB28_31:
	callq	hipDeviceSynchronize
	movq	d_imgs_lin(%rip), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_33
# %bb.32:
	movq	pix_spks_d(%rip), %rdi
	callq	_Z27__device_stub__convert2SpksPh
.LBB28_33:
	movabsq	$111669149722, %r14             # imm = 0x1A0000001A
	movabsq	$42949673060, %r13              # imm = 0xA00000064
	callq	hipDeviceSynchronize
	movq	pix_spks_d(%rip), %rdi
	callq	hipFree
	callq	clock
	cvtsi2sd	%rax, %xmm0
	movsd	%xmm0, 40(%rsp)                 # 8-byte Spill
	leaq	9(%rbx), %r12
	leaq	81(%rbx), %rax
	movq	%rax, (%rsp)                    # 8-byte Spill
	leaq	783(%rbx), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	7(%rbx), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
.LBB28_34:                              # =>This Loop Header: Depth=1
                                        #     Child Loop BB28_41 Depth 2
                                        #       Child Loop BB28_46 Depth 3
                                        #     Child Loop BB28_95 Depth 2
                                        #       Child Loop BB28_96 Depth 3
	movl	$.L.str.12, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	movsd	.LCPI28_0(%rip), %xmm0          # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	cmpl	$3, %ebp
	jb	.LBB28_40
# %bb.35:                               #   in Loop: Header=BB28_34 Depth=1
	movsd	.LCPI28_1(%rip), %xmm0          # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	cmpl	$6, %ebp
	jb	.LBB28_40
# %bb.36:                               #   in Loop: Header=BB28_34 Depth=1
	movsd	.LCPI28_2(%rip), %xmm0          # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	cmpl	$9, %ebp
	jb	.LBB28_40
# %bb.37:                               #   in Loop: Header=BB28_34 Depth=1
	movsd	.LCPI28_3(%rip), %xmm0          # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	cmpl	$12, %ebp
	jb	.LBB28_40
# %bb.38:                               #   in Loop: Header=BB28_34 Depth=1
	movsd	.LCPI28_4(%rip), %xmm0          # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	cmpl	$15, %ebp
	jb	.LBB28_40
# %bb.39:                               #   in Loop: Header=BB28_34 Depth=1
	xorl	%eax, %eax
	cmpl	$18, %ebp
	setb	%al
	movsd	.LCPI28_5(,%rax,8), %xmm0       # xmm0 = mem[0],zero
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
.LBB28_40:                              #   in Loop: Header=BB28_34 Depth=1
	movl	%ebp, 12(%rsp)                  # 4-byte Spill
	xorl	%r15d, %r15d
.LBB28_41:                              #   Parent Loop BB28_34 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB28_46 Depth 3
	imulq	$3140, %r15, %rax               # imm = 0xC44
	movl	test_set(%rax), %edx
	movl	$.L.str.13, %edi
	movl	%r15d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_43
# %bb.42:                               #   in Loop: Header=BB28_41 Depth=2
	movl	%r15d, %edi
	callq	_Z24__device_stub__createDesi
.LBB28_43:                              #   in Loop: Header=BB28_41 Depth=2
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_45
# %bb.44:                               #   in Loop: Header=BB28_41 Depth=2
	callq	_Z25__device_stub__clear_varsv
.LBB28_45:                              #   in Loop: Header=BB28_41 Depth=2
	callq	hipDeviceSynchronize
	xorl	%ebp, %ebp
.LBB28_46:                              #   Parent Loop BB28_34 Depth=1
                                        #     Parent Loop BB28_41 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_48
# %bb.47:                               #   in Loop: Header=BB28_46 Depth=3
	movq	24(%rsp), %rdi                  # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi
	movl	%ebp, %esi
	callq	_Z23__device_stub__pix2spksii
.LBB28_48:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	movq	168(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_50
# %bb.49:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel1i
.LBB28_50:                              #   in Loop: Header=BB28_46 Depth=3
	movq	160(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_52
# %bb.51:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel2i
.LBB28_52:                              #   in Loop: Header=BB28_46 Depth=3
	movq	152(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_54
# %bb.53:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel3i
.LBB28_54:                              #   in Loop: Header=BB28_46 Depth=3
	movq	144(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_56
# %bb.55:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel4i
.LBB28_56:                              #   in Loop: Header=BB28_46 Depth=3
	movq	136(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_58
# %bb.57:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel5i
.LBB28_58:                              #   in Loop: Header=BB28_46 Depth=3
	movq	128(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_60
# %bb.59:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel6i
.LBB28_60:                              #   in Loop: Header=BB28_46 Depth=3
	movq	120(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_62
# %bb.61:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel7i
.LBB28_62:                              #   in Loop: Header=BB28_46 Depth=3
	movq	112(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_64
# %bb.63:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel8i
.LBB28_64:                              #   in Loop: Header=BB28_46 Depth=3
	movq	104(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_66
# %bb.65:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z26__device_stub__convKernel9i
.LBB28_66:                              #   in Loop: Header=BB28_46 Depth=3
	movq	96(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_68
# %bb.67:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z27__device_stub__convKernel10i
.LBB28_68:                              #   in Loop: Header=BB28_46 Depth=3
	movq	88(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_70
# %bb.69:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z27__device_stub__convKernel11i
.LBB28_70:                              #   in Loop: Header=BB28_46 Depth=3
	movq	80(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_72
# %bb.71:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z27__device_stub__convKernel12i
.LBB28_72:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	leaq	1023(%rbx), %r15
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_74
# %bb.73:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z25__device_stub__LifKernel1i
.LBB28_74:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	movq	72(%rsp), %r9
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_76
# %bb.75:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z24__device_stub__SynKerneli
.LBB28_76:                              #   in Loop: Header=BB28_46 Depth=3
	movq	64(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_78
# %bb.77:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z23__device_stub__Lat_curri
.LBB28_78:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	leaq	-92(%r13), %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_80
# %bb.79:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z28__device_stub__IsynRedKerneli
.LBB28_80:                              #   in Loop: Header=BB28_46 Depth=3
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_82
# %bb.81:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z22__device_stub__reduce1i
.LBB28_82:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_84
# %bb.83:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	callq	_Z25__device_stub__LifKernel2i
.LBB28_84:                              #   in Loop: Header=BB28_46 Depth=3
	callq	hipDeviceSynchronize
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_86
# %bb.85:                               #   in Loop: Header=BB28_46 Depth=3
	movl	%ebp, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_Z25__device_stub__CalcUpdateid
.LBB28_86:                              #   in Loop: Header=BB28_46 Depth=3
	incl	%ebp
	cmpl	$1000, %ebp                     # imm = 0x3E8
	jne	.LBB28_46
# %bb.87:                               #   in Loop: Header=BB28_41 Depth=2
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_89
# %bb.88:                               #   in Loop: Header=BB28_41 Depth=2
	callq	_Z21__device_stub__WtUpdtv
.LBB28_89:                              #   in Loop: Header=BB28_41 Depth=2
	movq	24(%rsp), %r15                  # 8-byte Reload
	incq	%r15
	cmpq	$50000, %r15                    # imm = 0xC350
	jne	.LBB28_41
# %bb.90:                               #   in Loop: Header=BB28_34 Depth=1
	callq	clock
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	subsd	40(%rsp), %xmm0                 # 8-byte Folded Reload
	divsd	.LCPI28_6(%rip), %xmm0
	mulsd	.LCPI28_7(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	movq	32(%rsp), %rsi                  # 8-byte Reload
	addq	%rax, %rsi
	movl	$.L.str.14, %edi
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.15, %esi
	leaq	176(%rsp), %r15
	movq	%r15, %rdi
	movl	12(%rsp), %edx                  # 4-byte Reload
	xorl	%eax, %eax
	callq	sprintf
	movl	$.L.str.16, %esi
	movq	%r15, %rdi
	callq	fopen
	movq	%rax, %rbp
	testq	%rax, %rax
	jne	.LBB28_92
# %bb.91:                               #   in Loop: Header=BB28_34 Depth=1
	movl	$.L.str.17, %edi
	movl	12(%rsp), %esi                  # 4-byte Reload
	xorl	%eax, %eax
	callq	printf
.LBB28_92:                              #   in Loop: Header=BB28_34 Depth=1
	movl	$.Lstr, %edi
	callq	puts@PLT
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB28_94
# %bb.93:                               #   in Loop: Header=BB28_34 Depth=1
	movq	d_wts_saved(%rip), %rdi
	callq	_Z21__device_stub__cpyWtsPd
.LBB28_94:                              #   in Loop: Header=BB28_34 Depth=1
	movq	d_wts_saved(%rip), %rsi
	movl	$h_wts_saved, %r15d
	movl	$h_wts_saved, %edi
	movl	$648960, %edx                   # imm = 0x9E700
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
.LBB28_95:                              # %.preheader
                                        #   Parent Loop BB28_34 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB28_96 Depth 3
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
.LBB28_96:                              #   Parent Loop BB28_34 Depth=1
                                        #     Parent Loop BB28_95 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movsd	(%r15,%r13,8), %xmm0            # xmm0 = mem[0],zero
	movl	$.L.str.19, %esi
	movq	%rbp, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r13
	cmpq	$10, %r13
	jne	.LBB28_96
# %bb.97:                               #   in Loop: Header=BB28_95 Depth=2
	movl	$10, %edi
	movq	%rbp, %rsi
	callq	fputc@PLT
	movq	24(%rsp), %rax                  # 8-byte Reload
	incq	%rax
	addq	$80, %r15
	cmpq	$8112, %rax                     # imm = 0x1FB0
	jne	.LBB28_95
# %bb.98:                               #   in Loop: Header=BB28_34 Depth=1
	movq	%rbp, %rdi
	callq	fclose
	movl	12(%rsp), %ebp                  # 4-byte Reload
	incl	%ebp
	cmpl	$20, %ebp
	movabsq	$42949673060, %r13              # imm = 0xA00000064
	jne	.LBB28_34
# %bb.99:
	movq	d_wts_saved(%rip), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB28_1:
	.cfi_def_cfa_offset 272
	movl	$.L.str.2, %edi
	jmp	.LBB28_2
.LBB28_4:
	movl	$.L.str.4, %edi
	jmp	.LBB28_2
.LBB28_6:
	movl	$.L.str.6, %edi
	jmp	.LBB28_2
.LBB28_8:
	movl	$.L.str.8, %edi
.LBB28_2:
	callq	perror
	movl	$1, %edi
	callq	exit
.Lfunc_end28:
	.size	main, .Lfunc_end28-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB29_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB29_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14img_readKernelPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12convert2SpksPh, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8pix2spksii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9createDesi, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10clear_varsv, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10LifKernel1i, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10LifKernel2i, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9SynKerneli, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Lat_curri, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13IsynRedKerneli, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7reduce1i, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10CalcUpdateid, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6WtUpdtv, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6cpyWtsPd, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12initialize2DPdS_, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel1i, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel2i, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel3i, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel4i, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel5i, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel6i, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel7i, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel8i, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convKernel9i, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12convKernel10i, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12convKernel11i, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12convKernel12i, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_imgs, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movl	$157000000, %r9d                # imm = 0x95BA140
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$img_spks, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movl	$6272000, %r9d                  # imm = 0x5FB400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$syn1, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movl	$2048, %r9d                     # imm = 0x800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$syn1s, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movl	$2048, %r9d                     # imm = 0x800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$syn, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movl	$2048000, %r9d                  # imm = 0x1F4000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$in_spk, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movl	$8112, %r9d                     # imm = 0x1FB0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Isyn, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movl	$648960, %r9d                   # imm = 0x9E700
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$weight, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movl	$648960, %r9d                   # imm = 0x9E700
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Isyn_tot, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Isyn_lat, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$I_lat, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$D_op, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movl	$10000, %r9d                    # imm = 0x2710
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$err, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movl	$10, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Y_op, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movl	$10, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$del_w, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movl	$648960, %r9d                   # imm = 0x9E700
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$ci, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_hat, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$cis, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$norm_dh, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$cil, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$cils, %esi
	movl	$.L__unnamed_48, %edx
	movl	$.L__unnamed_48, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$d_hat_sq, %esi
	movl	$.L__unnamed_49, %edx
	movl	$.L__unnamed_49, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$ref_time1, %esi
	movl	$.L__unnamed_50, %edx
	movl	$.L__unnamed_50, %ecx
	movl	$32448, %r9d                    # imm = 0x7EC0
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$ref_time2, %esi
	movl	$.L__unnamed_51, %edx
	movl	$.L__unnamed_51, %ecx
	movl	$40, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Vm1, %esi
	movl	$.L__unnamed_52, %edx
	movl	$.L__unnamed_52, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$Vm2, %esi
	movl	$.L__unnamed_53, %edx
	movl	$.L__unnamed_53, %ecx
	movl	$80, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$pix_spks, %esi
	movl	$.L__unnamed_54, %edx
	movl	$.L__unnamed_54, %ecx
	movl	$256000, %r9d                   # imm = 0x3E800
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$I_in, %esi
	movl	$.L__unnamed_55, %edx
	movl	$.L__unnamed_55, %ecx
	movl	$64896, %r9d                    # imm = 0xFD80
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$total_curr, %esi
	movl	$.L__unnamed_56, %edx
	movl	$.L__unnamed_56, %ecx
	movl	$640, %r9d                      # imm = 0x280
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$total_dhatsq, %esi
	movl	$.L__unnamed_57, %edx
	movl	$.L__unnamed_57, %ecx
	movl	$64, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv1, %esi
	movl	$.L__unnamed_58, %edx
	movl	$.L__unnamed_58, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv2, %esi
	movl	$.L__unnamed_59, %edx
	movl	$.L__unnamed_59, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv3, %esi
	movl	$.L__unnamed_60, %edx
	movl	$.L__unnamed_60, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv4, %esi
	movl	$.L__unnamed_61, %edx
	movl	$.L__unnamed_61, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv5, %esi
	movl	$.L__unnamed_62, %edx
	movl	$.L__unnamed_62, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv6, %esi
	movl	$.L__unnamed_63, %edx
	movl	$.L__unnamed_63, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv7, %esi
	movl	$.L__unnamed_64, %edx
	movl	$.L__unnamed_64, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv8, %esi
	movl	$.L__unnamed_65, %edx
	movl	$.L__unnamed_65, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv9, %esi
	movl	$.L__unnamed_66, %edx
	movl	$.L__unnamed_66, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv10, %esi
	movl	$.L__unnamed_67, %edx
	movl	$.L__unnamed_67, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv11, %esi
	movl	$.L__unnamed_68, %edx
	movl	$.L__unnamed_68, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$w_conv12, %esi
	movl	$.L__unnamed_69, %edx
	movl	$.L__unnamed_69, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end29:
	.size	__hip_module_ctor, .Lfunc_end29-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB30_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB30_2:
	retq
.Lfunc_end30:
	.size	__hip_module_dtor, .Lfunc_end30-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	pix_spks_d,@object              # @pix_spks_d
	.bss
	.globl	pix_spks_d
	.p2align	3, 0x0
pix_spks_d:
	.quad	0
	.size	pix_spks_d, 8

	.type	d_imgs_lin,@object              # @d_imgs_lin
	.globl	d_imgs_lin
	.p2align	3, 0x0
d_imgs_lin:
	.quad	0
	.size	d_imgs_lin, 8

	.type	img_lin,@object                 # @img_lin
	.globl	img_lin
	.p2align	4, 0x0
img_lin:
	.zero	157000000
	.size	img_lin, 157000000

	.type	test_set,@object                # @test_set
	.globl	test_set
	.p2align	4, 0x0
test_set:
	.zero	157000000
	.size	test_set, 157000000

	.type	d_imgs,@object                  # @d_imgs
	.local	d_imgs
	.comm	d_imgs,157000000,16
	.type	img_spks,@object                # @img_spks
	.local	img_spks
	.comm	img_spks,6272000,16
	.type	syn1,@object                    # @syn1
	.local	syn1
	.comm	syn1,2048,16
	.type	syn1s,@object                   # @syn1s
	.local	syn1s
	.comm	syn1s,2048,16
	.type	syn,@object                     # @syn
	.local	syn
	.comm	syn,2048000,16
	.type	in_spk,@object                  # @in_spk
	.local	in_spk
	.comm	in_spk,8112,16
	.type	Isyn,@object                    # @Isyn
	.local	Isyn
	.comm	Isyn,648960,16
	.type	weight,@object                  # @weight
	.local	weight
	.comm	weight,648960,16
	.type	Isyn_tot,@object                # @Isyn_tot
	.local	Isyn_tot
	.comm	Isyn_tot,80,16
	.type	Isyn_lat,@object                # @Isyn_lat
	.local	Isyn_lat
	.comm	Isyn_lat,80,16
	.type	I_lat,@object                   # @I_lat
	.local	I_lat
	.comm	I_lat,80,16
	.type	D_op,@object                    # @D_op
	.local	D_op
	.comm	D_op,10000,16
	.type	err,@object                     # @err
	.local	err
	.comm	err,10,1
	.type	Y_op,@object                    # @Y_op
	.local	Y_op
	.comm	Y_op,10,1
	.type	del_w,@object                   # @del_w
	.local	del_w
	.comm	del_w,648960,16
	.type	ci,@object                      # @ci
	.local	ci
	.comm	ci,64896,16
	.type	d_hat,@object                   # @d_hat
	.local	d_hat
	.comm	d_hat,64896,16
	.type	cis,@object                     # @cis
	.local	cis
	.comm	cis,64896,16
	.type	norm_dh,@object                 # @norm_dh
	.local	norm_dh
	.comm	norm_dh,8,8
	.type	cil,@object                     # @cil
	.local	cil
	.comm	cil,80,16
	.type	cils,@object                    # @cils
	.local	cils
	.comm	cils,80,16
	.type	d_hat_sq,@object                # @d_hat_sq
	.local	d_hat_sq
	.comm	d_hat_sq,64896,16
	.type	ref_time1,@object               # @ref_time1
	.local	ref_time1
	.comm	ref_time1,32448,16
	.type	ref_time2,@object               # @ref_time2
	.local	ref_time2
	.comm	ref_time2,40,16
	.type	Vm1,@object                     # @Vm1
	.local	Vm1
	.comm	Vm1,64896,16
	.type	Vm2,@object                     # @Vm2
	.local	Vm2
	.comm	Vm2,80,16
	.type	_Z14img_readKernelPi,@object    # @_Z14img_readKernelPi
	.section	.rodata,"a",@progbits
	.globl	_Z14img_readKernelPi
	.p2align	3, 0x0
_Z14img_readKernelPi:
	.quad	_Z29__device_stub__img_readKernelPi
	.size	_Z14img_readKernelPi, 8

	.type	pix_spks,@object                # @pix_spks
	.local	pix_spks
	.comm	pix_spks,256000,16
	.type	pix_spks_h,@object              # @pix_spks_h
	.bss
	.globl	pix_spks_h
	.p2align	4, 0x0
pix_spks_h:
	.zero	256000
	.size	pix_spks_h, 256000

	.type	_Z12convert2SpksPh,@object      # @_Z12convert2SpksPh
	.section	.rodata,"a",@progbits
	.globl	_Z12convert2SpksPh
	.p2align	3, 0x0
_Z12convert2SpksPh:
	.quad	_Z27__device_stub__convert2SpksPh
	.size	_Z12convert2SpksPh, 8

	.type	pixspks,@object                 # @pixspks
	.bss
	.globl	pixspks
	.p2align	4, 0x0
pixspks:
	.zero	256000
	.size	pixspks, 256000

	.type	_Z8pix2spksii,@object           # @_Z8pix2spksii
	.section	.rodata,"a",@progbits
	.globl	_Z8pix2spksii
	.p2align	3, 0x0
_Z8pix2spksii:
	.quad	_Z23__device_stub__pix2spksii
	.size	_Z8pix2spksii, 8

	.type	_Z9createDesi,@object           # @_Z9createDesi
	.globl	_Z9createDesi
	.p2align	3, 0x0
_Z9createDesi:
	.quad	_Z24__device_stub__createDesi
	.size	_Z9createDesi, 8

	.type	I_in,@object                    # @I_in
	.local	I_in
	.comm	I_in,64896,16
	.type	_Z10clear_varsv,@object         # @_Z10clear_varsv
	.globl	_Z10clear_varsv
	.p2align	3, 0x0
_Z10clear_varsv:
	.quad	_Z25__device_stub__clear_varsv
	.size	_Z10clear_varsv, 8

	.type	_Z10LifKernel1i,@object         # @_Z10LifKernel1i
	.globl	_Z10LifKernel1i
	.p2align	3, 0x0
_Z10LifKernel1i:
	.quad	_Z25__device_stub__LifKernel1i
	.size	_Z10LifKernel1i, 8

	.type	_Z10LifKernel2i,@object         # @_Z10LifKernel2i
	.globl	_Z10LifKernel2i
	.p2align	3, 0x0
_Z10LifKernel2i:
	.quad	_Z25__device_stub__LifKernel2i
	.size	_Z10LifKernel2i, 8

	.type	_Z9SynKerneli,@object           # @_Z9SynKerneli
	.globl	_Z9SynKerneli
	.p2align	3, 0x0
_Z9SynKerneli:
	.quad	_Z24__device_stub__SynKerneli
	.size	_Z9SynKerneli, 8

	.type	_Z8Lat_curri,@object            # @_Z8Lat_curri
	.globl	_Z8Lat_curri
	.p2align	3, 0x0
_Z8Lat_curri:
	.quad	_Z23__device_stub__Lat_curri
	.size	_Z8Lat_curri, 8

	.type	total_curr,@object              # @total_curr
	.local	total_curr
	.comm	total_curr,640,16
	.type	total_dhatsq,@object            # @total_dhatsq
	.local	total_dhatsq
	.comm	total_dhatsq,64,16
	.type	_Z13IsynRedKerneli,@object      # @_Z13IsynRedKerneli
	.globl	_Z13IsynRedKerneli
	.p2align	3, 0x0
_Z13IsynRedKerneli:
	.quad	_Z28__device_stub__IsynRedKerneli
	.size	_Z13IsynRedKerneli, 8

	.type	_Z7reduce1i,@object             # @_Z7reduce1i
	.globl	_Z7reduce1i
	.p2align	3, 0x0
_Z7reduce1i:
	.quad	_Z22__device_stub__reduce1i
	.size	_Z7reduce1i, 8

	.type	_Z10CalcUpdateid,@object        # @_Z10CalcUpdateid
	.globl	_Z10CalcUpdateid
	.p2align	3, 0x0
_Z10CalcUpdateid:
	.quad	_Z25__device_stub__CalcUpdateid
	.size	_Z10CalcUpdateid, 8

	.type	_Z6WtUpdtv,@object              # @_Z6WtUpdtv
	.globl	_Z6WtUpdtv
	.p2align	3, 0x0
_Z6WtUpdtv:
	.quad	_Z21__device_stub__WtUpdtv
	.size	_Z6WtUpdtv, 8

	.type	_Z6cpyWtsPd,@object             # @_Z6cpyWtsPd
	.globl	_Z6cpyWtsPd
	.p2align	3, 0x0
_Z6cpyWtsPd:
	.quad	_Z21__device_stub__cpyWtsPd
	.size	_Z6cpyWtsPd, 8

	.type	w_conv1,@object                 # @w_conv1
	.local	w_conv1
	.comm	w_conv1,72,16
	.type	w_conv2,@object                 # @w_conv2
	.local	w_conv2
	.comm	w_conv2,72,16
	.type	w_conv3,@object                 # @w_conv3
	.local	w_conv3
	.comm	w_conv3,72,16
	.type	w_conv4,@object                 # @w_conv4
	.local	w_conv4
	.comm	w_conv4,72,16
	.type	w_conv5,@object                 # @w_conv5
	.local	w_conv5
	.comm	w_conv5,72,16
	.type	w_conv6,@object                 # @w_conv6
	.local	w_conv6
	.comm	w_conv6,72,16
	.type	w_conv7,@object                 # @w_conv7
	.local	w_conv7
	.comm	w_conv7,72,16
	.type	w_conv8,@object                 # @w_conv8
	.local	w_conv8
	.comm	w_conv8,72,16
	.type	w_conv9,@object                 # @w_conv9
	.local	w_conv9
	.comm	w_conv9,72,16
	.type	w_conv10,@object                # @w_conv10
	.local	w_conv10
	.comm	w_conv10,72,16
	.type	w_conv11,@object                # @w_conv11
	.local	w_conv11
	.comm	w_conv11,72,16
	.type	w_conv12,@object                # @w_conv12
	.local	w_conv12
	.comm	w_conv12,72,16
	.type	_Z12initialize2DPdS_,@object    # @_Z12initialize2DPdS_
	.globl	_Z12initialize2DPdS_
	.p2align	3, 0x0
_Z12initialize2DPdS_:
	.quad	_Z27__device_stub__initialize2DPdS_
	.size	_Z12initialize2DPdS_, 8

	.type	_Z11convKernel1i,@object        # @_Z11convKernel1i
	.globl	_Z11convKernel1i
	.p2align	3, 0x0
_Z11convKernel1i:
	.quad	_Z26__device_stub__convKernel1i
	.size	_Z11convKernel1i, 8

	.type	_Z11convKernel2i,@object        # @_Z11convKernel2i
	.globl	_Z11convKernel2i
	.p2align	3, 0x0
_Z11convKernel2i:
	.quad	_Z26__device_stub__convKernel2i
	.size	_Z11convKernel2i, 8

	.type	_Z11convKernel3i,@object        # @_Z11convKernel3i
	.globl	_Z11convKernel3i
	.p2align	3, 0x0
_Z11convKernel3i:
	.quad	_Z26__device_stub__convKernel3i
	.size	_Z11convKernel3i, 8

	.type	_Z11convKernel4i,@object        # @_Z11convKernel4i
	.globl	_Z11convKernel4i
	.p2align	3, 0x0
_Z11convKernel4i:
	.quad	_Z26__device_stub__convKernel4i
	.size	_Z11convKernel4i, 8

	.type	_Z11convKernel5i,@object        # @_Z11convKernel5i
	.globl	_Z11convKernel5i
	.p2align	3, 0x0
_Z11convKernel5i:
	.quad	_Z26__device_stub__convKernel5i
	.size	_Z11convKernel5i, 8

	.type	_Z11convKernel6i,@object        # @_Z11convKernel6i
	.globl	_Z11convKernel6i
	.p2align	3, 0x0
_Z11convKernel6i:
	.quad	_Z26__device_stub__convKernel6i
	.size	_Z11convKernel6i, 8

	.type	_Z11convKernel7i,@object        # @_Z11convKernel7i
	.globl	_Z11convKernel7i
	.p2align	3, 0x0
_Z11convKernel7i:
	.quad	_Z26__device_stub__convKernel7i
	.size	_Z11convKernel7i, 8

	.type	_Z11convKernel8i,@object        # @_Z11convKernel8i
	.globl	_Z11convKernel8i
	.p2align	3, 0x0
_Z11convKernel8i:
	.quad	_Z26__device_stub__convKernel8i
	.size	_Z11convKernel8i, 8

	.type	_Z11convKernel9i,@object        # @_Z11convKernel9i
	.globl	_Z11convKernel9i
	.p2align	3, 0x0
_Z11convKernel9i:
	.quad	_Z26__device_stub__convKernel9i
	.size	_Z11convKernel9i, 8

	.type	_Z12convKernel10i,@object       # @_Z12convKernel10i
	.globl	_Z12convKernel10i
	.p2align	3, 0x0
_Z12convKernel10i:
	.quad	_Z27__device_stub__convKernel10i
	.size	_Z12convKernel10i, 8

	.type	_Z12convKernel11i,@object       # @_Z12convKernel11i
	.globl	_Z12convKernel11i
	.p2align	3, 0x0
_Z12convKernel11i:
	.quad	_Z27__device_stub__convKernel11i
	.size	_Z12convKernel11i, 8

	.type	_Z12convKernel12i,@object       # @_Z12convKernel12i
	.globl	_Z12convKernel12i
	.p2align	3, 0x0
_Z12convKernel12i:
	.quad	_Z27__device_stub__convKernel12i
	.size	_Z12convKernel12i, 8

	.type	h_wts,@object                   # @h_wts
	.bss
	.globl	h_wts
	.p2align	4, 0x0
h_wts:
	.zero	648960
	.size	h_wts, 648960

	.type	d_wts,@object                   # @d_wts
	.globl	d_wts
	.p2align	3, 0x0
d_wts:
	.quad	0
	.size	d_wts, 8

	.type	dcwts,@object                   # @dcwts
	.globl	dcwts
	.p2align	3, 0x0
dcwts:
	.quad	0
	.size	dcwts, 8

	.type	h_wts_saved,@object             # @h_wts_saved
	.globl	h_wts_saved
	.p2align	4, 0x0
h_wts_saved:
	.zero	648960
	.size	h_wts_saved, 648960

	.type	d_wts_saved,@object             # @d_wts_saved
	.globl	d_wts_saved
	.p2align	3, 0x0
d_wts_saved:
	.quad	0
	.size	d_wts_saved, 8

	.type	c_wts,@object                   # @c_wts
	.globl	c_wts
	.p2align	4, 0x0
c_wts:
	.zero	864
	.size	c_wts, 864

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"pixels_spks.csv"
	.size	.L.str, 16

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Error while opening file pixels_spks.csv\n"
	.size	.L.str.2, 42

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"mnist_train.csv"
	.size	.L.str.3, 16

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Error while opening file mnist_train.csv\n"
	.size	.L.str.4, 42

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"wts_initial.csv"
	.size	.L.str.5, 16

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Error while opening file wts_trained.csv\n"
	.size	.L.str.6, 42

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"kernels_3x3.csv"
	.size	.L.str.7, 16

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Error while opening file kernel.csv\n"
	.size	.L.str.8, 37

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Total no. of neurons=%d, no. of synapses to be trained=%d\n"
	.size	.L.str.9, 59

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"%lf,"
	.size	.L.str.10, 5

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"%d,"
	.size	.L.str.11, 4

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Epoch=%d\n"
	.size	.L.str.12, 10

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"l=%d image %d\n"
	.size	.L.str.13, 15

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"Elapsed time: %ld ms\n"
	.size	.L.str.14, 22

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"wts_gpu%d.txt"
	.size	.L.str.15, 14

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"w"
	.size	.L.str.16, 2

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Failed to open file wts_gpu_sample%d.txt\n"
	.size	.L.str.17, 42

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"%0.14f,"
	.size	.L.str.19, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14img_readKernelPi"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12convert2SpksPh"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8pix2spksii"
	.size	.L__unnamed_3, 14

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z9createDesi"
	.size	.L__unnamed_4, 14

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z10clear_varsv"
	.size	.L__unnamed_5, 16

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z10LifKernel1i"
	.size	.L__unnamed_6, 16

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z10LifKernel2i"
	.size	.L__unnamed_7, 16

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z9SynKerneli"
	.size	.L__unnamed_8, 14

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z8Lat_curri"
	.size	.L__unnamed_9, 13

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z13IsynRedKerneli"
	.size	.L__unnamed_10, 19

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z7reduce1i"
	.size	.L__unnamed_11, 12

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z10CalcUpdateid"
	.size	.L__unnamed_12, 17

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z6WtUpdtv"
	.size	.L__unnamed_13, 11

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z6cpyWtsPd"
	.size	.L__unnamed_14, 12

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z12initialize2DPdS_"
	.size	.L__unnamed_15, 21

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z11convKernel1i"
	.size	.L__unnamed_16, 17

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z11convKernel2i"
	.size	.L__unnamed_17, 17

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"_Z11convKernel3i"
	.size	.L__unnamed_18, 17

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"_Z11convKernel4i"
	.size	.L__unnamed_19, 17

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"_Z11convKernel5i"
	.size	.L__unnamed_20, 17

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"_Z11convKernel6i"
	.size	.L__unnamed_21, 17

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"_Z11convKernel7i"
	.size	.L__unnamed_22, 17

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"_Z11convKernel8i"
	.size	.L__unnamed_23, 17

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"_Z11convKernel9i"
	.size	.L__unnamed_24, 17

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"_Z12convKernel10i"
	.size	.L__unnamed_25, 18

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"_Z12convKernel11i"
	.size	.L__unnamed_26, 18

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"_Z12convKernel12i"
	.size	.L__unnamed_27, 18

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"d_imgs"
	.size	.L__unnamed_28, 7

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"img_spks"
	.size	.L__unnamed_29, 9

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"syn1"
	.size	.L__unnamed_30, 5

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"syn1s"
	.size	.L__unnamed_31, 6

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"syn"
	.size	.L__unnamed_32, 4

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"in_spk"
	.size	.L__unnamed_33, 7

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"Isyn"
	.size	.L__unnamed_34, 5

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"weight"
	.size	.L__unnamed_35, 7

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"Isyn_tot"
	.size	.L__unnamed_36, 9

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"Isyn_lat"
	.size	.L__unnamed_37, 9

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"I_lat"
	.size	.L__unnamed_38, 6

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"D_op"
	.size	.L__unnamed_39, 5

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"err"
	.size	.L__unnamed_40, 4

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"Y_op"
	.size	.L__unnamed_41, 5

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"del_w"
	.size	.L__unnamed_42, 6

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"ci"
	.size	.L__unnamed_43, 3

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"d_hat"
	.size	.L__unnamed_44, 6

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"cis"
	.size	.L__unnamed_45, 4

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"norm_dh"
	.size	.L__unnamed_46, 8

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"cil"
	.size	.L__unnamed_47, 4

	.type	.L__unnamed_48,@object          # @47
.L__unnamed_48:
	.asciz	"cils"
	.size	.L__unnamed_48, 5

	.type	.L__unnamed_49,@object          # @48
.L__unnamed_49:
	.asciz	"d_hat_sq"
	.size	.L__unnamed_49, 9

	.type	.L__unnamed_50,@object          # @49
.L__unnamed_50:
	.asciz	"ref_time1"
	.size	.L__unnamed_50, 10

	.type	.L__unnamed_51,@object          # @50
.L__unnamed_51:
	.asciz	"ref_time2"
	.size	.L__unnamed_51, 10

	.type	.L__unnamed_52,@object          # @51
.L__unnamed_52:
	.asciz	"Vm1"
	.size	.L__unnamed_52, 4

	.type	.L__unnamed_53,@object          # @52
.L__unnamed_53:
	.asciz	"Vm2"
	.size	.L__unnamed_53, 4

	.type	.L__unnamed_54,@object          # @53
.L__unnamed_54:
	.asciz	"pix_spks"
	.size	.L__unnamed_54, 9

	.type	.L__unnamed_55,@object          # @54
.L__unnamed_55:
	.asciz	"I_in"
	.size	.L__unnamed_55, 5

	.type	.L__unnamed_56,@object          # @55
.L__unnamed_56:
	.asciz	"total_curr"
	.size	.L__unnamed_56, 11

	.type	.L__unnamed_57,@object          # @56
.L__unnamed_57:
	.asciz	"total_dhatsq"
	.size	.L__unnamed_57, 13

	.type	.L__unnamed_58,@object          # @57
.L__unnamed_58:
	.asciz	"w_conv1"
	.size	.L__unnamed_58, 8

	.type	.L__unnamed_59,@object          # @58
.L__unnamed_59:
	.asciz	"w_conv2"
	.size	.L__unnamed_59, 8

	.type	.L__unnamed_60,@object          # @59
.L__unnamed_60:
	.asciz	"w_conv3"
	.size	.L__unnamed_60, 8

	.type	.L__unnamed_61,@object          # @60
.L__unnamed_61:
	.asciz	"w_conv4"
	.size	.L__unnamed_61, 8

	.type	.L__unnamed_62,@object          # @61
.L__unnamed_62:
	.asciz	"w_conv5"
	.size	.L__unnamed_62, 8

	.type	.L__unnamed_63,@object          # @62
.L__unnamed_63:
	.asciz	"w_conv6"
	.size	.L__unnamed_63, 8

	.type	.L__unnamed_64,@object          # @63
.L__unnamed_64:
	.asciz	"w_conv7"
	.size	.L__unnamed_64, 8

	.type	.L__unnamed_65,@object          # @64
.L__unnamed_65:
	.asciz	"w_conv8"
	.size	.L__unnamed_65, 8

	.type	.L__unnamed_66,@object          # @65
.L__unnamed_66:
	.asciz	"w_conv9"
	.size	.L__unnamed_66, 8

	.type	.L__unnamed_67,@object          # @66
.L__unnamed_67:
	.asciz	"w_conv10"
	.size	.L__unnamed_67, 9

	.type	.L__unnamed_68,@object          # @67
.L__unnamed_68:
	.asciz	"w_conv11"
	.size	.L__unnamed_68, 9

	.type	.L__unnamed_69,@object          # @68
.L__unnamed_69:
	.asciz	"w_conv12"
	.size	.L__unnamed_69, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Copying the trained weights to the host for analysis"
	.size	.Lstr, 53

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__img_readKernelPi
	.addrsig_sym _Z27__device_stub__convert2SpksPh
	.addrsig_sym _Z23__device_stub__pix2spksii
	.addrsig_sym _Z24__device_stub__createDesi
	.addrsig_sym _Z25__device_stub__clear_varsv
	.addrsig_sym _Z25__device_stub__LifKernel1i
	.addrsig_sym _Z25__device_stub__LifKernel2i
	.addrsig_sym _Z24__device_stub__SynKerneli
	.addrsig_sym _Z23__device_stub__Lat_curri
	.addrsig_sym _Z28__device_stub__IsynRedKerneli
	.addrsig_sym _Z22__device_stub__reduce1i
	.addrsig_sym _Z25__device_stub__CalcUpdateid
	.addrsig_sym _Z21__device_stub__WtUpdtv
	.addrsig_sym _Z21__device_stub__cpyWtsPd
	.addrsig_sym _Z27__device_stub__initialize2DPdS_
	.addrsig_sym _Z26__device_stub__convKernel1i
	.addrsig_sym _Z26__device_stub__convKernel2i
	.addrsig_sym _Z26__device_stub__convKernel3i
	.addrsig_sym _Z26__device_stub__convKernel4i
	.addrsig_sym _Z26__device_stub__convKernel5i
	.addrsig_sym _Z26__device_stub__convKernel6i
	.addrsig_sym _Z26__device_stub__convKernel7i
	.addrsig_sym _Z26__device_stub__convKernel8i
	.addrsig_sym _Z26__device_stub__convKernel9i
	.addrsig_sym _Z27__device_stub__convKernel10i
	.addrsig_sym _Z27__device_stub__convKernel11i
	.addrsig_sym _Z27__device_stub__convKernel12i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym pix_spks_d
	.addrsig_sym d_imgs_lin
	.addrsig_sym img_lin
	.addrsig_sym test_set
	.addrsig_sym d_imgs
	.addrsig_sym img_spks
	.addrsig_sym syn1
	.addrsig_sym syn1s
	.addrsig_sym syn
	.addrsig_sym in_spk
	.addrsig_sym Isyn
	.addrsig_sym weight
	.addrsig_sym Isyn_tot
	.addrsig_sym Isyn_lat
	.addrsig_sym I_lat
	.addrsig_sym D_op
	.addrsig_sym err
	.addrsig_sym Y_op
	.addrsig_sym del_w
	.addrsig_sym ci
	.addrsig_sym d_hat
	.addrsig_sym cis
	.addrsig_sym norm_dh
	.addrsig_sym cil
	.addrsig_sym cils
	.addrsig_sym d_hat_sq
	.addrsig_sym ref_time1
	.addrsig_sym ref_time2
	.addrsig_sym Vm1
	.addrsig_sym Vm2
	.addrsig_sym _Z14img_readKernelPi
	.addrsig_sym pix_spks
	.addrsig_sym pix_spks_h
	.addrsig_sym _Z12convert2SpksPh
	.addrsig_sym _Z8pix2spksii
	.addrsig_sym _Z9createDesi
	.addrsig_sym I_in
	.addrsig_sym _Z10clear_varsv
	.addrsig_sym _Z10LifKernel1i
	.addrsig_sym _Z10LifKernel2i
	.addrsig_sym _Z9SynKerneli
	.addrsig_sym _Z8Lat_curri
	.addrsig_sym total_curr
	.addrsig_sym total_dhatsq
	.addrsig_sym _Z13IsynRedKerneli
	.addrsig_sym _Z7reduce1i
	.addrsig_sym _Z10CalcUpdateid
	.addrsig_sym _Z6WtUpdtv
	.addrsig_sym _Z6cpyWtsPd
	.addrsig_sym w_conv1
	.addrsig_sym w_conv2
	.addrsig_sym w_conv3
	.addrsig_sym w_conv4
	.addrsig_sym w_conv5
	.addrsig_sym w_conv6
	.addrsig_sym w_conv7
	.addrsig_sym w_conv8
	.addrsig_sym w_conv9
	.addrsig_sym w_conv10
	.addrsig_sym w_conv11
	.addrsig_sym w_conv12
	.addrsig_sym _Z12initialize2DPdS_
	.addrsig_sym _Z11convKernel1i
	.addrsig_sym _Z11convKernel2i
	.addrsig_sym _Z11convKernel3i
	.addrsig_sym _Z11convKernel4i
	.addrsig_sym _Z11convKernel5i
	.addrsig_sym _Z11convKernel6i
	.addrsig_sym _Z11convKernel7i
	.addrsig_sym _Z11convKernel8i
	.addrsig_sym _Z11convKernel9i
	.addrsig_sym _Z12convKernel10i
	.addrsig_sym _Z12convKernel11i
	.addrsig_sym _Z12convKernel12i
	.addrsig_sym h_wts
	.addrsig_sym d_wts
	.addrsig_sym dcwts
	.addrsig_sym h_wts_saved
	.addrsig_sym d_wts_saved
	.addrsig_sym c_wts
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14img_readKernelPi    ; -- Begin function _Z14img_readKernelPi
	.globl	_Z14img_readKernelPi
	.p2align	8
	.type	_Z14img_readKernelPi,@function
_Z14img_readKernelPi:                   ; @_Z14img_readKernelPi
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b32 s6, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_imgs@rel32@lo+4
	s_addc_u32 s3, s3, d_imgs@rel32@hi+12
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	s_mov_b64 s[4:5], 0
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s0, s4
	s_addc_u32 s9, s1, s5
	global_load_b32 v1, v0, s[8:9]
	s_add_u32 s8, s2, s4
	s_addc_u32 s9, s3, s5
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s4, 0xc44
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v1, s[8:9]
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s6, s6, 1
	s_add_u32 s0, s0, 0xc44
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 0xc44
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_u32 s6, 0xc350
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14img_readKernelPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 10
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14img_readKernelPi, .Lfunc_end0-_Z14img_readKernelPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 10
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12convert2SpksPh      ; -- Begin function _Z12convert2SpksPh
	.globl	_Z12convert2SpksPh
	.p2align	8
	.type	_Z12convert2SpksPh,@function
_Z12convert2SpksPh:                     ; @_Z12convert2SpksPh
; %bb.0:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, pix_spks@rel32@lo+4
	s_addc_u32 s3, s3, pix_spks@rel32@hi+12
	s_mov_b32 s4, s5
.LBB1_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, syn1@rel32@lo+4
	s_addc_u32 s7, s7, syn1@rel32@hi+12
	s_lshl_b64 s[8:9], s[4:5], 3
	s_mov_b32 s10, s5
	s_mov_b32 s11, s5
	s_add_u32 s12, s8, s6
	s_addc_u32 s13, s9, s7
	v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, syn1s@rel32@lo+4
	s_addc_u32 s7, s7, syn1s@rel32@hi+12
	s_add_u32 s8, s8, s6
	s_addc_u32 s9, s9, s7
	s_mov_b64 s[6:7], 0
	s_clause 0x1
	global_store_b64 v0, v[1:2], s[12:13]
	global_store_b64 v0, v[1:2], s[8:9]
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s8, s0, s6
	s_addc_u32 s9, s1, s7
	global_load_u8 v1, v0, s[8:9]
	s_add_u32 s8, s2, s6
	s_addc_u32 s9, s3, s7
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmpk_eq_i32 s6, 0x3e8
	s_waitcnt vmcnt(0)
	global_store_b8 v0, v1, s[8:9]
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s4, s4, 1
	s_add_u32 s0, s0, 0x3e8
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 0x3e8
	s_addc_u32 s3, s3, 0
	s_cmpk_lg_i32 s4, 0x100
	s_cbranch_scc1 .LBB1_1
; %bb.4:                                ; %.preheader.preheader
	v_mov_b32_e32 v4, 0
	s_mov_b32 s9, 0
	s_mov_b32 s4, 0x63f14120
	s_mov_b32 s6, 0x2de00d2
	s_mov_b32 s5, 0x3fef5dcc
	s_mov_b32 s7, 0x3fed8a09
	s_mov_b32 s8, s9
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, pix_spks@rel32@lo+4
	s_addc_u32 s1, s1, pix_spks@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, syn@rel32@lo+4
	s_addc_u32 s3, s3, syn@rel32@hi+12
.LBB1_5:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_6 Depth 2
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, syn1@rel32@lo+4
	s_addc_u32 s11, s11, syn1@rel32@hi+12
	s_lshl_b64 s[12:13], s[8:9], 3
	s_mov_b64 s[16:17], s[2:3]
	s_add_u32 s10, s12, s10
	s_addc_u32 s11, s13, s11
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, syn1s@rel32@lo+4
	s_addc_u32 s15, s15, syn1s@rel32@hi+12
	s_add_u32 s12, s12, s14
	s_addc_u32 s13, s13, s15
	s_clause 0x1
	global_load_b64 v[2:3], v4, s[10:11]
	global_load_b64 v[0:1], v4, s[12:13]
	s_mov_b64 s[14:15], 0
.LBB1_6:                                ;   Parent Loop BB1_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_waitcnt vmcnt(1)
	v_mul_f64 v[2:3], v[2:3], s[4:5]
	global_load_u8 v5, v4, s[18:19]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[0:1], v[0:1], s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 1, v5
	s_cbranch_vccnz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=2
	v_add_f64 v[2:3], v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], 1.0
.LBB1_8:                                ;   in Loop: Header=BB1_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[2:3], -v[0:1]
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	global_store_b64 v4, v[5:6], s[16:17]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmpk_eq_i32 s14, 0x3e8
	s_cbranch_scc0 .LBB1_6
; %bb.9:                                ;   in Loop: Header=BB1_5 Depth=1
	s_add_i32 s8, s8, 1
	s_add_u32 s0, s0, 0x3e8
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 0x1f40
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s8, 0x100
	s_clause 0x1
	global_store_b64 v4, v[2:3], s[10:11]
	global_store_b64 v4, v[0:1], s[12:13]
	s_cbranch_scc0 .LBB1_5
; %bb.10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12convert2SpksPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12convert2SpksPh, .Lfunc_end1-_Z12convert2SpksPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 592
; NumSgprs: 22
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8pix2spksii           ; -- Begin function _Z8pix2spksii
	.globl	_Z8pix2spksii
	.p2align	8
	.type	_Z8pix2spksii,@function
_Z8pix2spksii:                          ; @_Z8pix2spksii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x310, v1
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_imgs@rel32@lo+4
	s_addc_u32 s3, s3, d_imgs@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s0, 0xc44
	s_mul_hi_i32 s0, s0, 0xc44
	s_add_u32 s2, s4, s2
	s_addc_u32 s0, s0, s3
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s0, v3, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, syn@rel32@lo+4
	s_addc_u32 s3, s3, syn@rel32@hi+12
	s_mov_b32 s0, s1
	s_ashr_i32 s1, s1, 31
	global_load_b32 v0, v[2:3], off offset:4
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s0, s2
	s_addc_u32 s3, s1, s3
	s_waitcnt vmcnt(0)
	v_mad_i64_i32 v[2:3], null, 0x1f40, v0, s[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[4:5], null, 0x1f40, v1, s[0:1]
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB2_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8pix2spksii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8pix2spksii, .Lfunc_end2-_Z8pix2spksii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 284
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9createDesi           ; -- Begin function _Z9createDesi
	.globl	_Z9createDesi
	.p2align	8
	.type	_Z9createDesi,@function
_Z9createDesi:                          ; @_Z9createDesi
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 10, v2
	s_cbranch_execz .LBB3_6
; %bb.1:                                ; %.preheader13
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, D_op@rel32@lo+4
	s_addc_u32 s3, s3, D_op@rel32@hi+12
	v_mov_b32_e32 v3, 0
	v_mad_i64_i32 v[0:1], null, 0x3e8, v2, s[2:3]
	s_mov_b64 s[2:3], 0
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v4, vcc_lo, v0, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x3e8
	global_store_b8 v[4:5], v3, off
	s_cbranch_scc0 .LBB3_2
; %bb.3:
	s_load_b32 s2, s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, d_imgs@rel32@lo+4
	s_addc_u32 s1, s1, d_imgs@rel32@hi+12
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s2, 0xc44
	s_mul_hi_i32 s2, s2, 0xc44
	s_add_u32 s0, s3, s0
	s_addc_u32 s1, s2, s1
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_6
; %bb.4:                                ; %.preheader.preheader
	v_mov_b32_e32 v2, 1
	s_mov_b64 s[0:1], 0x64
.LBB3_5:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v3, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
	s_add_u32 s2, s0, 35
	s_addc_u32 s3, s1, 0
	s_cmpk_lt_u32 s0, 0x3c5
	s_mov_b64 s[0:1], s[2:3]
	global_store_b8 v[3:4], v2, off
	s_cbranch_scc1 .LBB3_5
.LBB3_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9createDesi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z9createDesi, .Lfunc_end3-_Z9createDesi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10clear_varsv         ; -- Begin function _Z10clear_varsv
	.globl	_Z10clear_varsv
	.p2align	8
	.type	_Z10clear_varsv,@function
_Z10clear_varsv:                        ; @_Z10clear_varsv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s0, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s1, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x1fb0, v0
	v_cmp_gt_i32_e64 s0, 10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Vm2@rel32@lo+4
	s_addc_u32 s1, s1, Vm2@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, Isyn_tot@rel32@lo+4
	s_addc_u32 s5, s5, Isyn_tot@rel32@hi+12
	s_mov_b32 s2, 0x1eb851ec
	s_mov_b32 s6, 0
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_lshlrev_b64 v[9:10], 2, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s3, 0xbfb1eb85
	s_mov_b32 s7, s6
	v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
	v_add_co_u32 v7, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v11, vcc_lo, v3, s4
	v_lshlrev_b64 v[15:16], 3, v[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ref_time2@rel32@lo+4
	s_addc_u32 s1, s1, ref_time2@rel32@hi+12
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, s0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Vm1@rel32@lo+4
	s_addc_u32 s1, s1, Vm1@rel32@hi+12
	v_add_co_u32 v17, vcc_lo, v15, s0
	v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ref_time1@rel32@lo+4
	s_addc_u32 s3, s3, ref_time1@rel32@hi+12
	v_add_co_ci_u32_e32 v18, vcc_lo, s1, v16, vcc_lo
	v_mov_b32_e32 v19, 0
	v_add_co_u32 v1, vcc_lo, v1, s2
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_store_b64 v[7:8], v[5:6], off
	global_store_b64 v[11:12], v[13:14], off
	global_store_b32 v[9:10], v19, off
	global_store_b64 v[17:18], v[5:6], off
	global_store_b32 v[1:2], v19, off
	v_mad_i64_i32 v[1:2], null, 0x50, v0, v[3:4]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	v_add_co_u32 v5, vcc_lo, v15, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, del_w@rel32@lo+4
	s_addc_u32 s3, s3, del_w@rel32@hi+12
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v16, vcc_lo
	v_add_co_u32 v7, vcc_lo, v1, s2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Isyn@rel32@lo+4
	s_addc_u32 s1, s1, Isyn@rel32@hi+12
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, v1, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ci@rel32@lo+4
	s_addc_u32 s3, s3, ci@rel32@hi+12
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v9, vcc_lo, v15, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v16, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, cis@rel32@lo+4
	s_addc_u32 s1, s1, cis@rel32@hi+12
	global_store_b64 v[5:6], v[13:14], off
	global_store_b64 v[7:8], v[13:14], off
	global_store_b64 v[0:1], v[13:14], off
	global_store_b64 v[9:10], v[13:14], off
	v_add_co_u32 v0, vcc_lo, v15, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_hat@rel32@lo+4
	s_addc_u32 s3, s3, d_hat@rel32@hi+12
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v16, vcc_lo
	v_add_co_u32 v5, vcc_lo, v15, s2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, cil@rel32@lo+4
	s_addc_u32 s1, s1, cil@rel32@hi+12
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v16, vcc_lo
	v_add_co_u32 v7, vcc_lo, v3, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, cils@rel32@lo+4
	s_addc_u32 s3, s3, cils@rel32@hi+12
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, v3, s2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Isyn_lat@rel32@lo+4
	s_addc_u32 s1, s1, Isyn_lat@rel32@hi+12
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
	global_store_b64 v[0:1], v[13:14], off
	global_store_b64 v[5:6], v[13:14], off
	global_store_b64 v[7:8], v[13:14], off
	global_store_b64 v[9:10], v[13:14], off
	global_store_b64 v[2:3], v[13:14], off
.LBB4_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10clear_varsv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z10clear_varsv, .Lfunc_end4-_Z10clear_varsv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 764
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10LifKernel1i         ; -- Begin function _Z10LifKernel1i
	.globl	_Z10LifKernel1i
	.p2align	8
	.type	_Z10LifKernel1i,@function
_Z10LifKernel1i:                        ; @_Z10LifKernel1i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x1fb0, v1
	s_cbranch_execz .LBB5_6
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ref_time1@rel32@lo+4
	s_addc_u32 s3, s3, ref_time1@rel32@hi+12
	s_load_b32 s0, s[0:1], 0x0
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_i32_e64 s0, v0
	s_cbranch_execz .LBB5_3
; %bb.2:
	v_mov_b32_e32 v0, 0
	global_store_b32 v[3:4], v0, off
.LBB5_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[7:8], 3, v[1:2]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Vm1@rel32@lo+4
	s_addc_u32 s3, s3, Vm1@rel32@hi+12
	s_mov_b32 s4, 0x29a4692b
	s_mov_b32 s5, 0xbe601b2b
	s_mov_b32 s6, 0xe361ce4c
	s_mov_b32 s7, 0x3df49da7
	v_add_co_u32 v5, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, I_in@rel32@lo+4
	s_addc_u32 s3, s3, I_in@rel32@hi+12
	v_add_co_u32 v7, vcc_lo, v7, s2
	global_load_b64 v[9:10], v[5:6], off
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_mov_b32 s3, 0x3fb1eb85
	s_mov_b32 s2, 0x1eb851ec
	s_mov_b32 s8, 0xeb1c432d
	global_load_b64 v[7:8], v[7:8], off
	s_mov_b32 s9, 0x3f1a36e2
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(1)
	v_add_f64 v[11:12], v[9:10], s[2:3]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], s[4:5], v[7:8]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[11:12]
	v_div_scale_f64 v[19:20], vcc_lo, v[11:12], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[19:20], v[15:16]
	v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
	v_div_fixup_f64 v[11:12], v[13:14], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[11:12], s[8:9], v[9:10]
	v_add_f64 v[13:14], v[13:14], s[2:3]
	s_mov_b32 s3, 0xbfb1eb85
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[13:14], s[4:5], v[7:8]
	v_div_scale_f64 v[13:14], null, s[6:7], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[7:8], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_div_fixup_f64 v[7:8], v[13:14], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[11:12], v[7:8]
	v_mul_f64 v[7:8], v[7:8], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[7:8], 0.5
	v_cndmask_b32_e64 v8, 0, 0x3ff00000, vcc_lo
	v_mov_b32_e32 v7, 0
	v_fma_f64 v[8:9], v[11:12], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[8:9]
	s_mov_b32 s2, 0x47ae147b
	s_mov_b32 s3, 0x3f947ae1
	v_cndmask_b32_e32 v8, 0x1eb851ec, v8, vcc_lo
	v_cndmask_b32_e32 v9, 0xbfb1eb85, v9, vcc_lo
	global_store_b64 v[5:6], v[8:9], off
	v_cmpx_le_f64_e32 s[2:3], v[8:9]
	s_cbranch_execz .LBB5_5
; %bb.4:
	s_add_i32 s0, s0, 30
	v_dual_mov_b32 v8, 0x1eb851ec :: v_dual_mov_b32 v7, 1
	v_dual_mov_b32 v9, 0xbfb1eb85 :: v_dual_mov_b32 v0, s0
	global_store_b64 v[5:6], v[8:9], off
	global_store_b32 v[3:4], v0, off
.LBB5_5:
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, in_spk@rel32@lo+4
	s_addc_u32 s1, s1, in_spk@rel32@hi+12
	v_add_co_u32 v0, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_store_b8 v[0:1], v7, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB5_6:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10LifKernel1i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z10LifKernel1i, .Lfunc_end5-_Z10LifKernel1i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 804
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10LifKernel2i         ; -- Begin function _Z10LifKernel2i
	.globl	_Z10LifKernel2i
	.p2align	8
	.type	_Z10LifKernel2i,@function
_Z10LifKernel2i:                        ; @_Z10LifKernel2i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 10, v1
	s_cbranch_execz .LBB6_6
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ref_time2@rel32@lo+4
	s_addc_u32 s3, s3, ref_time2@rel32@hi+12
	s_load_b32 s0, s[0:1], 0x0
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_gt_i32_e64 s0, v0
	s_cbranch_execz .LBB6_3
; %bb.2:
	v_mov_b32_e32 v0, 0
	global_store_b32 v[3:4], v0, off
.LBB6_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[7:8], 3, v[1:2]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Vm2@rel32@lo+4
	s_addc_u32 s3, s3, Vm2@rel32@hi+12
	s_mov_b32 s4, 0x29a4692b
	s_mov_b32 s5, 0xbe601b2b
	s_mov_b32 s6, 0xe361ce4c
	s_mov_b32 s7, 0x3df49da7
	v_add_co_u32 v5, vcc_lo, v7, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Isyn_tot@rel32@lo+4
	s_addc_u32 s3, s3, Isyn_tot@rel32@hi+12
	v_add_co_u32 v11, vcc_lo, v7, s2
	global_load_b64 v[9:10], v[5:6], off
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v8, vcc_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Isyn_lat@rel32@lo+4
	s_addc_u32 s3, s3, Isyn_lat@rel32@hi+12
	v_add_co_u32 v7, vcc_lo, v7, s2
	global_load_b64 v[11:12], v[11:12], off
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	s_mov_b32 s3, 0x3fb1eb85
	s_mov_b32 s2, 0x1eb851ec
	s_mov_b32 s8, 0xeb1c432d
	global_load_b64 v[7:8], v[7:8], off
	s_mov_b32 s9, 0x3f1a36e2
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(2)
	v_add_f64 v[13:14], v[9:10], s[2:3]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], s[4:5], v[11:12]
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[7:8], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], v[13:14]
	v_div_scale_f64 v[21:22], vcc_lo, v[13:14], s[6:7], v[13:14]
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[13:14], v[15:16], s[6:7], v[13:14]
	v_fma_f64 v[15:16], v[13:14], s[8:9], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], s[2:3]
	s_mov_b32 s3, 0xbfb1eb85
	v_fma_f64 v[11:12], v[15:16], s[4:5], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_div_scale_f64 v[11:12], null, s[6:7], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[15:16], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[7:8], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	v_fma_f64 v[11:12], -v[11:12], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[19:20]
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_div_fixup_f64 v[7:8], v[11:12], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[13:14], v[7:8]
	v_mul_f64 v[7:8], v[7:8], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[7:8], 0.5
	v_cndmask_b32_e64 v8, 0, 0x3ff00000, vcc_lo
	v_mov_b32_e32 v7, 0
	v_fma_f64 v[8:9], v[11:12], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[8:9]
	s_mov_b32 s2, 0x47ae147b
	s_mov_b32 s3, 0x3f947ae1
	v_cndmask_b32_e32 v8, 0x1eb851ec, v8, vcc_lo
	v_cndmask_b32_e32 v9, 0xbfb1eb85, v9, vcc_lo
	global_store_b64 v[5:6], v[8:9], off
	v_cmpx_le_f64_e32 s[2:3], v[8:9]
	s_cbranch_execz .LBB6_5
; %bb.4:
	s_add_i32 s2, s0, 30
	v_dual_mov_b32 v8, 0x1eb851ec :: v_dual_mov_b32 v7, 1
	v_dual_mov_b32 v9, 0xbfb1eb85 :: v_dual_mov_b32 v0, s2
	global_store_b64 v[5:6], v[8:9], off
	global_store_b32 v[3:4], v0, off
.LBB6_5:
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, D_op@rel32@lo+4
	s_addc_u32 s3, s3, D_op@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, Y_op@rel32@lo+4
	s_addc_u32 s5, s5, Y_op@rel32@hi+12
	s_ashr_i32 s1, s0, 31
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_i64_i32 v[3:4], null, 0x3e8, v1, s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, err@rel32@lo+4
	s_addc_u32 s1, s1, err@rel32@hi+12
	global_load_u8 v5, v[3:4], off
	v_add_co_u32 v3, vcc_lo, v1, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_nc_u16 v2, v5, v7
	global_store_b8 v[3:4], v7, off
	global_store_b8 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB6_6:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10LifKernel2i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z10LifKernel2i, .Lfunc_end6-_Z10LifKernel2i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 972
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9SynKerneli           ; -- Begin function _Z9SynKerneli
	.globl	_Z9SynKerneli
	.p2align	8
	.type	_Z9SynKerneli,@function
_Z9SynKerneli:                          ; @_Z9SynKerneli
; %bb.0:
	s_load_b32 s0, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s0, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s1, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, 0x1fb0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s0, 10, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB7_6
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[0:1]
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB7_5
; %bb.2:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ci@rel32@lo+4
	s_addc_u32 s3, s3, ci@rel32@hi+12
	v_add_co_u32 v5, vcc_lo, v3, s2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, cis@rel32@lo+4
	s_addc_u32 s5, s5, cis@rel32@hi+12
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
	global_load_b64 v[9:10], v[5:6], off
	global_load_b64 v[11:12], v[7:8], off
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, in_spk@rel32@lo+4
	s_addc_u32 s3, s3, in_spk@rel32@hi+12
	v_add_co_u32 v13, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, 0x63f14120
	s_mov_b32 s4, 0x2de00d2
	s_mov_b32 s3, 0x3fef5dcc
	global_load_u8 v1, v[13:14], off
	s_mov_b32 s5, 0x3fed8a09
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(2)
	v_mul_f64 v[9:10], v[9:10], s[2:3]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[11:12], v[11:12], s[4:5]
	global_store_b64 v[5:6], v[9:10], off
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 1, v1
	s_cbranch_execz .LBB7_4
; %bb.3:
	v_add_f64 v[9:10], v[9:10], 1.0
	v_add_f64 v[11:12], v[11:12], 1.0
	global_store_b64 v[5:6], v[9:10], off
	global_store_b64 v[7:8], v[11:12], off
.LBB7_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_f64 v[5:6], v[9:10], -v[11:12]
	s_mov_b32 s2, 0xeb1c432d
	s_mov_b32 s3, 0x3f1a36e2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_hat@rel32@lo+4
	s_addc_u32 s5, s5, d_hat@rel32@hi+12
	v_add_co_u32 v11, vcc_lo, v3, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
	global_load_b64 v[13:14], v[11:12], off
	v_mul_f64 v[5:6], v[5:6], s[2:3]
	s_mov_b32 s2, 0xe361ce4c
	s_mov_b32 s3, 0x3df49da7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_div_scale_f64 v[7:8], null, s[2:3], s[2:3], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[15:16], v[9:10]
	v_div_scale_f64 v[15:16], vcc_lo, v[5:6], s[2:3], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[15:16], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[17:18]
	v_div_fixup_f64 v[5:6], v[7:8], s[2:3], v[5:6]
	s_mov_b32 s2, 0x212d7732
	s_mov_b32 s3, 0x3fecf41f
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[5:6], v[13:14], s[2:3], v[5:6]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_hat_sq@rel32@lo+4
	s_addc_u32 s3, s3, d_hat_sq@rel32@hi+12
	v_add_co_u32 v9, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[7:8], v[5:6], v[5:6]
	global_store_b64 v[11:12], v[5:6], off
	global_store_b64 v[9:10], v[7:8], off
.LBB7_5:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ci@rel32@lo+4
	s_addc_u32 s1, s1, ci@rel32@hi+12
	v_add_co_u32 v5, vcc_lo, v3, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, cis@rel32@lo+4
	s_addc_u32 s3, s3, cis@rel32@hi+12
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[7:8], v[3:4], off
	v_ashrrev_i32_e32 v3, 31, v2
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, weight@rel32@lo+4
	s_addc_u32 s1, s1, weight@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	v_mad_i64_i32 v[3:4], null, 0x50, v0, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Isyn@rel32@lo+4
	s_addc_u32 s1, s1, Isyn@rel32@hi+12
	v_add_co_u32 v2, vcc_lo, v3, s0
	global_load_b64 v[0:1], v[0:1], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[0:1], v[5:6], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
.LBB7_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9SynKerneli
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z9SynKerneli, .Lfunc_end7-_Z9SynKerneli
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 908
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8Lat_curri            ; -- Begin function _Z8Lat_curri
	.globl	_Z8Lat_curri
	.p2align	8
	.type	_Z8Lat_curri,@function
_Z8Lat_curri:                           ; @_Z8Lat_curri
; %bb.0:
	s_load_b32 s0, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 10, v1
	s_cbranch_execz .LBB8_7
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, cil@rel32@lo+4
	s_addc_u32 s1, s1, cil@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, cils@rel32@lo+4
	s_addc_u32 s3, s3, cils@rel32@hi+12
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Y_op@rel32@lo+4
	s_addc_u32 s1, s1, Y_op@rel32@hi+12
	global_load_b64 v[9:10], v[5:6], off
	global_load_b64 v[11:12], v[7:8], off
	v_add_co_u32 v13, vcc_lo, v1, s0
	v_add_co_ci_u32_e32 v14, vcc_lo, s1, v2, vcc_lo
	s_mov_b32 s0, 0x63f14120
	s_mov_b32 s2, 0x2de00d2
	s_mov_b32 s1, 0x3fef5dcc
	global_load_u8 v0, v[13:14], off
	s_mov_b32 s3, 0x3fed8a09
	s_waitcnt vmcnt(2)
	v_mul_f64 v[9:10], v[9:10], s[0:1]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[11:12], v[11:12], s[2:3]
	s_mov_b32 s0, exec_lo
	global_store_b64 v[5:6], v[9:10], off
	global_store_b64 v[7:8], v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 1, v0
	s_cbranch_execz .LBB8_3
; %bb.2:
	v_add_f64 v[9:10], v[9:10], 1.0
	v_add_f64 v[11:12], v[11:12], 1.0
	global_store_b64 v[5:6], v[9:10], off
	global_store_b64 v[7:8], v[11:12], off
.LBB8_3:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[5:6], v[9:10], -v[11:12]
	s_mov_b32 s0, 0xe826d695
	s_mov_b32 s1, 0xbe112e0b
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[9:10], v[5:6], s[0:1]
	v_mov_b32_e32 v5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_lat@rel32@lo+4
	s_addc_u32 s1, s1, I_lat@rel32@hi+12
	v_add_co_u32 v11, vcc_lo, v3, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, Isyn_lat@rel32@lo+4
	s_addc_u32 s3, s3, Isyn_lat@rel32@hi+12
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v3, s2
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
	s_mov_b32 s2, 0
	global_store_b64 v[11:12], v[9:10], off
	global_store_b64 v[7:8], v[2:3], off
.LBB8_4:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e64 s2, v1
	s_cbranch_execz .LBB8_6
; %bb.5:                                ;   in Loop: Header=BB8_4 Depth=1
	global_load_b64 v[3:4], v2, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[5:6], v[3:4], v[5:6]
	global_store_b64 v[7:8], v[5:6], off
.LBB8_6:                                ;   in Loop: Header=BB8_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s2, s2, 1
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s2, 10
	s_cbranch_scc1 .LBB8_4
.LBB8_7:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Lat_curri
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z8Lat_curri, .Lfunc_end8-_Z8Lat_curri
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 520
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13IsynRedKerneli      ; -- Begin function _Z13IsynRedKerneli
	.globl	_Z13IsynRedKerneli
	.p2align	8
	.type	_Z13IsynRedKerneli,@function
_Z13IsynRedKerneli:                     ; @_Z13IsynRedKerneli
; %bb.0:
	s_load_b32 s0, s[0:1], 0x14
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s3, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, s15, s1, v[5:6]
	v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
	v_cmp_lt_u16_e64 s0, s0, 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, exec_lo, s0
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_gt_i32_e64 s0, 10, v2
	v_cmp_eq_u32_e64 s1, 0, v2
	s_cbranch_vccnz .LBB9_7
; %bb.1:                                ; %.lr.ph
	v_lshlrev_b64 v[5:6], 3, v[2:3]
	v_lshlrev_b64 v[7:8], 3, v[0:1]
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_hat_sq@rel32@lo+4
	s_addc_u32 s5, s5, d_hat_sq@rel32@hi+12
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, Isyn@rel32@lo+4
	s_addc_u32 s7, s7, Isyn@rel32@hi+12
	v_mov_b32_e32 v12, 0
	v_mad_i64_i32 v[9:10], null, 0x50, v0, v[5:6]
	v_add_co_u32 v7, vcc_lo, v7, s4
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
.LBB9_2:                                ; =>This Inner Loop Header: Depth=1
	s_lshr_b32 s4, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, s4, v0
	v_cmp_gt_u32_e32 vcc_lo, s4, v4
	v_cmp_gt_u32_e64 s2, 0x1fb0, v11
	s_and_b32 s5, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB9_4
; %bb.3:                                ;   in Loop: Header=BB9_2 Depth=1
	v_mad_u64_u32 v[13:14], null, 0x50, v11, v[5:6]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, Isyn@rel32@lo+4
	s_addc_u32 s7, s7, Isyn@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s2, v13, s6
	v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
	s_clause 0x1
	global_load_b64 v[13:14], v[13:14], off
	global_load_b64 v[15:16], v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	global_store_b64 v[9:10], v[13:14], off
.LBB9_4:                                ;   in Loop: Header=BB9_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_cmp_gt_u32_e64 s2, 0x1fb0, v11
	s_and_b32 s5, s1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s5
	s_cbranch_execz .LBB9_6
; %bb.5:                                ;   in Loop: Header=BB9_2 Depth=1
	v_lshlrev_b64 v[13:14], 3, v[11:12]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, d_hat_sq@rel32@lo+4
	s_addc_u32 s7, s7, d_hat_sq@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
	s_clause 0x1
	global_load_b64 v[13:14], v[13:14], off
	global_load_b64 v[15:16], v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[13:14], v[15:16]
	global_store_b64 v[7:8], v[13:14], off
.LBB9_6:                                ;   in Loop: Header=BB9_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB9_2
.LBB9_7:                                ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cmp_gt_i32_e64 s0, 10, v2
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB9_10
; %bb.8:
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Isyn@rel32@lo+4
	s_addc_u32 s1, s1, Isyn@rel32@hi+12
	s_mul_i32 s2, s14, 0x50
	s_mul_hi_u32 s3, s14, 0x50
	v_mad_i64_i32 v[5:6], null, 0x50, v0, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v5, s0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, total_curr@rel32@lo+4
	s_addc_u32 s1, s1, total_curr@rel32@hi+12
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_load_b64 v[5:6], v[5:6], off
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[5:6], off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB9_10
; %bb.9:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, total_dhatsq@rel32@lo+4
	s_addc_u32 s1, s1, total_dhatsq@rel32@hi+12
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_lshl_b64 s[2:3], s[14:15], 3
	v_mov_b32_e32 v2, 0
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, d_hat_sq@rel32@lo+4
	s_addc_u32 s3, s3, d_hat_sq@rel32@hi+12
	v_add_co_u32 v0, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB9_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13IsynRedKerneli
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z13IsynRedKerneli, .Lfunc_end9-_Z13IsynRedKerneli
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 788
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7reduce1i             ; -- Begin function _Z7reduce1i
	.globl	_Z7reduce1i
	.p2align	8
	.type	_Z7reduce1i,@function
_Z7reduce1i:                            ; @_Z7reduce1i
; %bb.0:
	s_load_b32 s0, s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e32 10, v1
	s_cbranch_execz .LBB10_7
; %bb.1:                                ; %.preheader17
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, total_curr@rel32@lo+4
	s_addc_u32 s1, s1, total_curr@rel32@hi+12
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
	s_mov_b64 s[0:1], 0
.LBB10_2:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v7, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
	s_add_u32 s0, s0, 0x50
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x280
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[7:8]
	s_cbranch_scc0 .LBB10_2
; %bb.3:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, Isyn_tot@rel32@lo+4
	s_addc_u32 s1, s1, Isyn_tot@rel32@hi+12
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	global_store_b64 v[2:3], v[4:5], off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB10_7
; %bb.4:                                ; %.preheader.preheader
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b64 s[0:1], 0
.LBB10_5:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, total_dhatsq@rel32@lo+4
	s_addc_u32 s3, s3, total_dhatsq@rel32@hi+12
	s_add_u32 s2, s0, s2
	s_addc_u32 s3, s1, s3
	s_add_u32 s0, s0, 8
	s_load_b64 s[2:3], s[2:3], 0x0
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 64
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], s[2:3]
	s_cbranch_scc0 .LBB10_5
; %bb.6:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s0, 0xffffff80, 0
	v_lshlrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_rsq_f64_e32 v[2:3], v[0:1]
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[4:5], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, norm_dh@rel32@lo+4
	s_addc_u32 s1, s1, norm_dh@rel32@hi+12
	v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[0:1], s[0:1]
.LBB10_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7reduce1i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z7reduce1i, .Lfunc_end10-_Z7reduce1i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10CalcUpdateid        ; -- Begin function _Z10CalcUpdateid
	.globl	_Z10CalcUpdateid
	.p2align	8
	.type	_Z10CalcUpdateid,@function
_Z10CalcUpdateid:                       ; @_Z10CalcUpdateid
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
	v_cmp_gt_i32_e32 vcc_lo, 0x1fb0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, 10, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB11_5
; %bb.1:
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, norm_dh@rel32@lo+4
	s_addc_u32 s3, s3, norm_dh@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_f64_e64 s4, s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB11_4
; %bb.2:
	v_ashrrev_i32_e32 v3, 31, v2
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, err@rel32@lo+4
	s_addc_u32 s5, s5, err@rel32@hi+12
	v_add_co_u32 v4, vcc_lo, v2, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	global_load_u8 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB11_4
; %bb.3:
	v_ashrrev_i32_e32 v1, 31, v0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, d_hat@rel32@lo+4
	s_addc_u32 s5, s5, d_hat@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x8
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_bfe_i32 v1, v4, 0, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_i32 v1, v1, 0, 16
	v_add_co_u32 v5, vcc_lo, v5, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_cvt_f64_i32_e32 v[7:8], v1
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	global_load_b64 v[5:6], v[5:6], off
	v_mad_i64_i32 v[10:11], null, 0x50, v0, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, del_w@rel32@lo+4
	s_addc_u32 s1, s1, del_w@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v10, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[4:5], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[6:7], null, s[2:3], s[2:3], v[4:5]
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_div_scale_f64 v[10:11], vcc_lo, v[4:5], s[2:3], v[4:5]
	v_mul_f64 v[12:13], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[6:7], s[2:3], v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	global_store_b64 v[0:1], v[2:3], off
.LBB11_4:
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB11_5:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10CalcUpdateid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z10CalcUpdateid, .Lfunc_end11-_Z10CalcUpdateid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 532
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6WtUpdtv              ; -- Begin function _Z6WtUpdtv
	.globl	_Z6WtUpdtv
	.p2align	8
	.type	_Z6WtUpdtv,@function
_Z6WtUpdtv:                             ; @_Z6WtUpdtv
; %bb.0:
	s_load_b32 s0, s[0:1], 0xc
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s1, s0, 16
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s0, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s1, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x1fb0, v0
	v_cmp_gt_i32_e64 s0, 10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB12_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, del_w@rel32@lo+4
	s_addc_u32 s1, s1, del_w@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, weight@rel32@lo+4
	s_addc_u32 s3, s3, weight@rel32@hi+12
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_i64_i32 v[3:4], null, 0x50, v0, v[1:2]
	v_add_co_u32 v0, vcc_lo, v3, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[4:5], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	global_store_b64 v[2:3], v[0:1], off
.LBB12_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6WtUpdtv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z6WtUpdtv, .Lfunc_end12-_Z6WtUpdtv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6cpyWtsPd             ; -- Begin function _Z6cpyWtsPd
	.globl	_Z6cpyWtsPd
	.p2align	8
	.type	_Z6cpyWtsPd,@function
_Z6cpyWtsPd:                            ; @_Z6cpyWtsPd
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0x1fb0, v0
	v_cmp_gt_i32_e64 s2, 10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB13_2
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, weight@rel32@lo+4
	s_addc_u32 s3, s3, weight@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_i64_i32 v[4:5], null, 0x50, v0, v[2:3]
	v_add_co_u32 v2, vcc_lo, v4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, 10, v[1:2]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB13_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6cpyWtsPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	_Z6cpyWtsPd, .Lfunc_end13-_Z6cpyWtsPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12initialize2DPdS_    ; -- Begin function _Z12initialize2DPdS_
	.globl	_Z12initialize2DPdS_
	.p2align	8
	.type	_Z12initialize2DPdS_,@function
_Z12initialize2DPdS_:                   ; @_Z12initialize2DPdS_
; %bb.0:
	s_load_b128 s[12:15], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, weight@rel32@lo+4
	s_addc_u32 s1, s1, weight@rel32@hi+12
.LBB14_1:                               ; %.preheader122
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB14_2 Depth 2
	s_mov_b64 s[2:3], 0
.LBB14_2:                               ;   Parent Loop BB14_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s12, s2
	s_addc_u32 s7, s13, s3
	global_load_b64 v[1:2], v0, s[6:7]
	s_add_u32 s6, s0, s2
	s_addc_u32 s7, s1, s3
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0x50
	s_waitcnt vmcnt(0)
	global_store_b64 v0, v[1:2], s[6:7]
	s_cbranch_scc0 .LBB14_2
; %bb.3:                                ;   in Loop: Header=BB14_1 Depth=1
	s_add_i32 s4, s4, 1
	s_add_u32 s12, s12, 0x50
	s_addc_u32 s13, s13, 0
	s_add_u32 s0, s0, 0x50
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s4, 0x1fb0
	s_cbranch_scc1 .LBB14_1
; %bb.4:                                ; %.preheader.preheader
	v_mov_b32_e32 v2, 0
	s_mov_b32 s13, 0
	s_mov_b32 s11, -3
	s_mov_b32 s20, s13
.LBB14_5:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB14_6 Depth 2
	s_mul_i32 s2, s11, 24
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, w_conv2@rel32@lo+4
	s_addc_u32 s1, s1, w_conv2@rel32@hi+12
	s_mul_hi_u32 s3, s11, 24
	s_add_u32 s21, s2, s0
	s_addc_u32 s22, s3, s1
	s_cmp_gt_u32 s20, 2
	s_mov_b64 s[16:17], 0
	s_cselect_b32 s0, -1, 0
	s_cmp_gt_u32 s20, 5
	s_cselect_b32 s1, -1, 0
	s_cmp_gt_u32 s20, 8
	s_cselect_b32 s2, -1, 0
	s_cmp_gt_u32 s20, 11
	s_cselect_b32 s3, -1, 0
	s_cmp_gt_u32 s20, 14
	s_cselect_b32 s4, -1, 0
	s_cmp_gt_u32 s20, 17
	s_cselect_b32 s5, -1, 0
	s_cmp_gt_u32 s20, 20
	s_cselect_b32 s6, -1, 0
	s_cmp_gt_u32 s20, 23
	s_cselect_b32 s7, -1, 0
	s_cmp_gt_u32 s20, 26
	s_cselect_b32 s8, -1, 0
	s_cmp_gt_u32 s20, 29
	s_cselect_b32 s9, -1, 0
	s_cmp_gt_u32 s20, 32
	s_cselect_b32 s10, -1, 0
	s_sub_i32 s12, s20, 33
	s_sub_i32 s18, s20, 30
	s_sub_i32 s19, s20, 27
	s_sub_i32 s37, s20, 24
	s_sub_i32 s23, s20, 21
	s_sub_i32 s24, s20, 18
	s_add_i32 s25, s20, -15
	s_add_i32 s26, s20, -12
	s_add_i32 s27, s20, -9
	s_add_i32 s28, s20, -6
	s_and_b32 s0, exec_lo, s0
	s_and_b32 s1, exec_lo, s1
	s_and_b32 s2, exec_lo, s2
	s_and_b32 s3, exec_lo, s3
	s_and_b32 s4, exec_lo, s4
	s_and_b32 s5, exec_lo, s5
	s_and_b32 s6, exec_lo, s6
	s_and_b32 s7, exec_lo, s7
	s_and_b32 s8, exec_lo, s8
	s_and_b32 s9, exec_lo, s9
	s_and_b32 s10, exec_lo, s10
	s_mul_hi_u32 s29, s12, 24
	s_mul_i32 s30, s12, 24
	s_mul_hi_u32 s31, s18, 24
	s_mul_i32 s33, s18, 24
	s_mul_hi_u32 s34, s19, 24
	s_mul_i32 s35, s19, 24
	s_mul_hi_u32 s36, s37, 24
	s_mul_i32 s37, s37, 24
	s_mov_b32 s12, s13
.LBB14_6:                               ;   Parent Loop BB14_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_u32 s18, s14, s16
	s_addc_u32 s19, s15, s17
	s_mov_b32 s38, -1
	global_load_b64 v[0:1], v2, s[18:19]
	s_mov_b32 vcc_lo, s0
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_48
; %bb.7:                                ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s1
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_45
; %bb.8:                                ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s2
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_42
; %bb.9:                                ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s3
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_39
; %bb.10:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s4
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_36
; %bb.11:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s5
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_33
; %bb.12:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s6
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_30
; %bb.13:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s7
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_27
; %bb.14:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s8
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_24
; %bb.15:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s9
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_21
; %bb.16:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 vcc_lo, s10
                                        ; implicit-def: $sgpr18_sgpr19
	s_cbranch_vccz .LBB14_18
; %bb.17:                               ;   in Loop: Header=BB14_6 Depth=2
	s_lshl_b64 s[18:19], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s30, s18
	s_addc_u32 s39, s29, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv12@rel32@lo+4
	s_addc_u32 s19, s19, w_conv12@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
	s_mov_b32 s38, 0
.LBB14_18:                              ; %Flow
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_20
; %bb.19:                               ;   in Loop: Header=BB14_6 Depth=2
	s_lshl_b64 s[18:19], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s33, s18
	s_addc_u32 s39, s31, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv11@rel32@lo+4
	s_addc_u32 s19, s19, w_conv11@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_20:                              ; %Flow150
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_21:                              ; %Flow151
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_23
; %bb.22:                               ;   in Loop: Header=BB14_6 Depth=2
	s_lshl_b64 s[18:19], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s35, s18
	s_addc_u32 s39, s34, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv10@rel32@lo+4
	s_addc_u32 s19, s19, w_conv10@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_23:                              ; %Flow152
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_24:                              ; %Flow153
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_26
; %bb.25:                               ;   in Loop: Header=BB14_6 Depth=2
	s_lshl_b64 s[18:19], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s38, s37, s18
	s_addc_u32 s39, s36, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv9@rel32@lo+4
	s_addc_u32 s19, s19, w_conv9@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_26:                              ; %Flow154
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_27:                              ; %Flow155
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_29
; %bb.28:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s23, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s23, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv8@rel32@lo+4
	s_addc_u32 s19, s19, w_conv8@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_29:                              ; %Flow156
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_30:                              ; %Flow157
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_32
; %bb.31:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s24, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s24, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv7@rel32@lo+4
	s_addc_u32 s19, s19, w_conv7@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_32:                              ; %Flow158
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_33:                              ; %Flow159
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_35
; %bb.34:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s25, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s25, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv6@rel32@lo+4
	s_addc_u32 s19, s19, w_conv6@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_35:                              ; %Flow160
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_36:                              ; %Flow161
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_38
; %bb.37:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s26, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s26, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv5@rel32@lo+4
	s_addc_u32 s19, s19, w_conv5@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_38:                              ; %Flow162
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_39:                              ; %Flow163
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_41
; %bb.40:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s27, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s27, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv4@rel32@lo+4
	s_addc_u32 s19, s19, w_conv4@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_41:                              ; %Flow164
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_42:                              ; %Flow165
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_44
; %bb.43:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s28, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s28, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv3@rel32@lo+4
	s_addc_u32 s19, s19, w_conv3@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_44:                              ; %Flow166
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_45:                              ; %Flow167
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_47
; %bb.46:                               ;   in Loop: Header=BB14_6 Depth=2
	s_add_u32 s18, s21, s16
	s_addc_u32 s19, s22, s17
.LBB14_47:                              ; %Flow168
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_mov_b32 s38, 0
.LBB14_48:                              ; %Flow169
                                        ;   in Loop: Header=BB14_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s38
	s_cbranch_vccnz .LBB14_50
; %bb.49:                               ;   in Loop: Header=BB14_6 Depth=2
	s_mul_i32 s38, s20, 24
	s_lshl_b64 s[18:19], s[12:13], 3
	s_mul_hi_u32 s39, s20, 24
	s_add_u32 s38, s38, s18
	s_addc_u32 s39, s39, s19
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, w_conv1@rel32@lo+4
	s_addc_u32 s19, s19, w_conv1@rel32@hi+12
	s_add_u32 s18, s38, s18
	s_addc_u32 s19, s39, s19
.LBB14_50:                              ;   in Loop: Header=BB14_6 Depth=2
	s_add_i32 s12, s12, 1
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_eq_u32 s16, 24
	s_waitcnt vmcnt(0)
	global_store_b64 v2, v[0:1], s[18:19]
	s_cbranch_scc0 .LBB14_6
; %bb.51:                               ;   in Loop: Header=BB14_5 Depth=1
	s_add_i32 s20, s20, 1
	s_add_u32 s14, s14, 24
	s_addc_u32 s15, s15, 0
	s_add_i32 s11, s11, 1
	s_cmp_eq_u32 s20, 36
	s_cbranch_scc0 .LBB14_5
; %bb.52:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12initialize2DPdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 40
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end14:
	.size	_Z12initialize2DPdS_, .Lfunc_end14-_Z12initialize2DPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1268
; NumSgprs: 42
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11convKernel1i        ; -- Begin function _Z11convKernel1i
	.globl	_Z11convKernel1i
	.p2align	8
	.type	_Z11convKernel1i,@function
_Z11convKernel1i:                       ; @_Z11convKernel1i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB15_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv1@rel32@lo+4
	s_addc_u32 s5, s5, w_conv1@rel32@hi+12
.LBB15_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB15_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB15_3:                               ;   Parent Loop BB15_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB15_3
; %bb.4:                                ;   in Loop: Header=BB15_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB15_2
; %bb.5:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v0, 26, v[1:2]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB15_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel1i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end15:
	.size	_Z11convKernel1i, .Lfunc_end15-_Z11convKernel1i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel2i        ; -- Begin function _Z11convKernel2i
	.globl	_Z11convKernel2i
	.p2align	8
	.type	_Z11convKernel2i,@function
_Z11convKernel2i:                       ; @_Z11convKernel2i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB16_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv2@rel32@lo+4
	s_addc_u32 s5, s5, w_conv2@rel32@hi+12
.LBB16_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB16_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB16_3:                               ;   Parent Loop BB16_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB16_3
; %bb.4:                                ;   in Loop: Header=BB16_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB16_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x2a4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB16_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel2i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end16:
	.size	_Z11convKernel2i, .Lfunc_end16-_Z11convKernel2i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel3i        ; -- Begin function _Z11convKernel3i
	.globl	_Z11convKernel3i
	.p2align	8
	.type	_Z11convKernel3i,@function
_Z11convKernel3i:                       ; @_Z11convKernel3i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB17_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv3@rel32@lo+4
	s_addc_u32 s5, s5, w_conv3@rel32@hi+12
.LBB17_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB17_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB17_3:                               ;   Parent Loop BB17_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB17_3
; %bb.4:                                ;   in Loop: Header=BB17_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB17_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x548
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB17_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel3i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end17:
	.size	_Z11convKernel3i, .Lfunc_end17-_Z11convKernel3i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel4i        ; -- Begin function _Z11convKernel4i
	.globl	_Z11convKernel4i
	.p2align	8
	.type	_Z11convKernel4i,@function
_Z11convKernel4i:                       ; @_Z11convKernel4i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB18_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv4@rel32@lo+4
	s_addc_u32 s5, s5, w_conv4@rel32@hi+12
.LBB18_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB18_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB18_3:                               ;   Parent Loop BB18_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB18_3
; %bb.4:                                ;   in Loop: Header=BB18_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB18_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x7ec
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB18_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel4i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end18:
	.size	_Z11convKernel4i, .Lfunc_end18-_Z11convKernel4i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel5i        ; -- Begin function _Z11convKernel5i
	.globl	_Z11convKernel5i
	.p2align	8
	.type	_Z11convKernel5i,@function
_Z11convKernel5i:                       ; @_Z11convKernel5i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB19_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv5@rel32@lo+4
	s_addc_u32 s5, s5, w_conv5@rel32@hi+12
.LBB19_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB19_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB19_3:                               ;   Parent Loop BB19_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB19_3
; %bb.4:                                ;   in Loop: Header=BB19_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB19_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0xa90
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB19_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel5i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end19:
	.size	_Z11convKernel5i, .Lfunc_end19-_Z11convKernel5i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel6i        ; -- Begin function _Z11convKernel6i
	.globl	_Z11convKernel6i
	.p2align	8
	.type	_Z11convKernel6i,@function
_Z11convKernel6i:                       ; @_Z11convKernel6i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB20_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv6@rel32@lo+4
	s_addc_u32 s5, s5, w_conv6@rel32@hi+12
.LBB20_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB20_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB20_3:                               ;   Parent Loop BB20_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB20_3
; %bb.4:                                ;   in Loop: Header=BB20_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB20_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0xd34
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB20_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel6i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end20:
	.size	_Z11convKernel6i, .Lfunc_end20-_Z11convKernel6i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel7i        ; -- Begin function _Z11convKernel7i
	.globl	_Z11convKernel7i
	.p2align	8
	.type	_Z11convKernel7i,@function
_Z11convKernel7i:                       ; @_Z11convKernel7i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB21_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv7@rel32@lo+4
	s_addc_u32 s5, s5, w_conv7@rel32@hi+12
.LBB21_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB21_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB21_3:                               ;   Parent Loop BB21_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB21_3
; %bb.4:                                ;   in Loop: Header=BB21_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB21_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0xfd8
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB21_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel7i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end21:
	.size	_Z11convKernel7i, .Lfunc_end21-_Z11convKernel7i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel8i        ; -- Begin function _Z11convKernel8i
	.globl	_Z11convKernel8i
	.p2align	8
	.type	_Z11convKernel8i,@function
_Z11convKernel8i:                       ; @_Z11convKernel8i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB22_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv8@rel32@lo+4
	s_addc_u32 s5, s5, w_conv8@rel32@hi+12
.LBB22_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB22_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB22_3:                               ;   Parent Loop BB22_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB22_3
; %bb.4:                                ;   in Loop: Header=BB22_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB22_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x127c
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB22_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel8i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end22:
	.size	_Z11convKernel8i, .Lfunc_end22-_Z11convKernel8i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z11convKernel9i        ; -- Begin function _Z11convKernel9i
	.globl	_Z11convKernel9i
	.p2align	8
	.type	_Z11convKernel9i,@function
_Z11convKernel9i:                       ; @_Z11convKernel9i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB23_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv9@rel32@lo+4
	s_addc_u32 s5, s5, w_conv9@rel32@hi+12
.LBB23_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB23_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB23_3:                               ;   Parent Loop BB23_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB23_3
; %bb.4:                                ;   in Loop: Header=BB23_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB23_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x1520
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB23_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convKernel9i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end23:
	.size	_Z11convKernel9i, .Lfunc_end23-_Z11convKernel9i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12convKernel10i       ; -- Begin function _Z12convKernel10i
	.globl	_Z12convKernel10i
	.p2align	8
	.type	_Z12convKernel10i,@function
_Z12convKernel10i:                      ; @_Z12convKernel10i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB24_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv10@rel32@lo+4
	s_addc_u32 s5, s5, w_conv10@rel32@hi+12
.LBB24_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB24_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB24_3:                               ;   Parent Loop BB24_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB24_3
; %bb.4:                                ;   in Loop: Header=BB24_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB24_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x17c4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB24_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12convKernel10i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end24:
	.size	_Z12convKernel10i, .Lfunc_end24-_Z12convKernel10i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12convKernel11i       ; -- Begin function _Z12convKernel11i
	.globl	_Z12convKernel11i
	.p2align	8
	.type	_Z12convKernel11i,@function
_Z12convKernel11i:                      ; @_Z12convKernel11i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB25_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv11@rel32@lo+4
	s_addc_u32 s5, s5, w_conv11@rel32@hi+12
.LBB25_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB25_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB25_3:                               ;   Parent Loop BB25_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB25_3
; %bb.4:                                ;   in Loop: Header=BB25_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB25_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x1a68
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB25_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12convKernel11i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end25:
	.size	_Z12convKernel11i, .Lfunc_end25-_Z12convKernel11i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12convKernel12i       ; -- Begin function _Z12convKernel12i
	.globl	_Z12convKernel12i
	.p2align	8
	.type	_Z12convKernel12i,@function
_Z12convKernel12i:                      ; @_Z12convKernel12i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x14
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 26, v2
	s_cbranch_execz .LBB26_6
; %bb.1:                                ; %.preheader22
	s_load_b32 s0, s[0:1], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, img_spks@rel32@lo+4
	s_addc_u32 s3, s3, img_spks@rel32@hi+12
	v_mad_u64_u32 v[4:5], null, v0, 28, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[0:1], 3
	s_mov_b32 s0, 0xe2308c3a
	s_add_u32 s2, s4, s2
	s_mov_b32 s1, 0x3e35798e
	s_addc_u32 s3, s5, s3
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, w_conv12@rel32@lo+4
	s_addc_u32 s5, s5, w_conv12@rel32@hi+12
.LBB26_2:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB26_3 Depth 2
	v_mad_i64_i32 v[5:6], null, 0x1f40, v4, s[2:3]
	s_mov_b64 s[6:7], 0
.LBB26_3:                               ;   Parent Loop BB26_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b64 v[7:8], v[5:6], off
	s_add_u32 s10, s4, s6
	s_addc_u32 s11, s5, s7
	v_add_co_u32 v5, vcc_lo, 0x1f40, v5
	s_load_b64 s[10:11], s[10:11], 0x0
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[9:10], s[10:11], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
	s_cbranch_scc1 .LBB26_3
; %bb.4:                                ;   in Loop: Header=BB26_2 Depth=1
	s_add_i32 s8, s8, 1
	v_add_nc_u32_e32 v4, 28, v4
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s8, 3
	s_cbranch_scc1 .LBB26_2
; %bb.5:
	v_mul_lo_u32 v0, v0, 26
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, I_in@rel32@lo+4
	s_addc_u32 s1, s1, I_in@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, v1, 0x1d0c
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB26_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12convKernel12i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end26:
	.size	_Z12convKernel12i, .Lfunc_end26-_Z12convKernel12i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_imgs                  ; @d_imgs
	.type	d_imgs,@object
	.section	.bss,"aw",@nobits
	.globl	d_imgs
	.p2align	4, 0x0
d_imgs:
	.zero	157000000
	.size	d_imgs, 157000000

	.protected	img_spks                ; @img_spks
	.type	img_spks,@object
	.globl	img_spks
	.p2align	4, 0x0
img_spks:
	.zero	6272000
	.size	img_spks, 6272000

	.protected	syn1                    ; @syn1
	.type	syn1,@object
	.globl	syn1
	.p2align	4, 0x0
syn1:
	.zero	2048
	.size	syn1, 2048

	.protected	syn1s                   ; @syn1s
	.type	syn1s,@object
	.globl	syn1s
	.p2align	4, 0x0
syn1s:
	.zero	2048
	.size	syn1s, 2048

	.protected	syn                     ; @syn
	.type	syn,@object
	.globl	syn
	.p2align	4, 0x0
syn:
	.zero	2048000
	.size	syn, 2048000

	.protected	in_spk                  ; @in_spk
	.type	in_spk,@object
	.globl	in_spk
	.p2align	4, 0x0
in_spk:
	.zero	8112
	.size	in_spk, 8112

	.protected	Isyn                    ; @Isyn
	.type	Isyn,@object
	.globl	Isyn
	.p2align	4, 0x0
Isyn:
	.zero	648960
	.size	Isyn, 648960

	.protected	weight                  ; @weight
	.type	weight,@object
	.globl	weight
	.p2align	4, 0x0
weight:
	.zero	648960
	.size	weight, 648960

	.protected	Isyn_tot                ; @Isyn_tot
	.type	Isyn_tot,@object
	.globl	Isyn_tot
	.p2align	4, 0x0
Isyn_tot:
	.zero	80
	.size	Isyn_tot, 80

	.protected	Isyn_lat                ; @Isyn_lat
	.type	Isyn_lat,@object
	.globl	Isyn_lat
	.p2align	4, 0x0
Isyn_lat:
	.zero	80
	.size	Isyn_lat, 80

	.protected	I_lat                   ; @I_lat
	.type	I_lat,@object
	.globl	I_lat
	.p2align	4, 0x0
I_lat:
	.zero	80
	.size	I_lat, 80

	.protected	D_op                    ; @D_op
	.type	D_op,@object
	.globl	D_op
	.p2align	4, 0x0
D_op:
	.zero	10000
	.size	D_op, 10000

	.protected	err                     ; @err
	.type	err,@object
	.globl	err
err:
	.zero	10
	.size	err, 10

	.protected	Y_op                    ; @Y_op
	.type	Y_op,@object
	.globl	Y_op
Y_op:
	.zero	10
	.size	Y_op, 10

	.protected	del_w                   ; @del_w
	.type	del_w,@object
	.globl	del_w
	.p2align	4, 0x0
del_w:
	.zero	648960
	.size	del_w, 648960

	.protected	ci                      ; @ci
	.type	ci,@object
	.globl	ci
	.p2align	4, 0x0
ci:
	.zero	64896
	.size	ci, 64896

	.protected	d_hat                   ; @d_hat
	.type	d_hat,@object
	.globl	d_hat
	.p2align	4, 0x0
d_hat:
	.zero	64896
	.size	d_hat, 64896

	.protected	cis                     ; @cis
	.type	cis,@object
	.globl	cis
	.p2align	4, 0x0
cis:
	.zero	64896
	.size	cis, 64896

	.protected	norm_dh                 ; @norm_dh
	.type	norm_dh,@object
	.globl	norm_dh
	.p2align	3, 0x0
norm_dh:
	.quad	0x0000000000000000              ; double 0
	.size	norm_dh, 8

	.protected	cil                     ; @cil
	.type	cil,@object
	.globl	cil
	.p2align	4, 0x0
cil:
	.zero	80
	.size	cil, 80

	.protected	cils                    ; @cils
	.type	cils,@object
	.globl	cils
	.p2align	4, 0x0
cils:
	.zero	80
	.size	cils, 80

	.protected	d_hat_sq                ; @d_hat_sq
	.type	d_hat_sq,@object
	.globl	d_hat_sq
	.p2align	4, 0x0
d_hat_sq:
	.zero	64896
	.size	d_hat_sq, 64896

	.protected	ref_time1               ; @ref_time1
	.type	ref_time1,@object
	.globl	ref_time1
	.p2align	4, 0x0
ref_time1:
	.zero	32448
	.size	ref_time1, 32448

	.protected	ref_time2               ; @ref_time2
	.type	ref_time2,@object
	.globl	ref_time2
	.p2align	4, 0x0
ref_time2:
	.zero	40
	.size	ref_time2, 40

	.protected	Vm1                     ; @Vm1
	.type	Vm1,@object
	.globl	Vm1
	.p2align	4, 0x0
Vm1:
	.zero	64896
	.size	Vm1, 64896

	.protected	Vm2                     ; @Vm2
	.type	Vm2,@object
	.globl	Vm2
	.p2align	4, 0x0
Vm2:
	.zero	80
	.size	Vm2, 80

	.protected	pix_spks                ; @pix_spks
	.type	pix_spks,@object
	.globl	pix_spks
	.p2align	4, 0x0
pix_spks:
	.zero	256000
	.size	pix_spks, 256000

	.protected	I_in                    ; @I_in
	.type	I_in,@object
	.globl	I_in
	.p2align	4, 0x0
I_in:
	.zero	64896
	.size	I_in, 64896

	.protected	total_curr              ; @total_curr
	.type	total_curr,@object
	.globl	total_curr
	.p2align	4, 0x0
total_curr:
	.zero	640
	.size	total_curr, 640

	.protected	total_dhatsq            ; @total_dhatsq
	.type	total_dhatsq,@object
	.globl	total_dhatsq
	.p2align	4, 0x0
total_dhatsq:
	.zero	64
	.size	total_dhatsq, 64

	.protected	w_conv1                 ; @w_conv1
	.type	w_conv1,@object
	.globl	w_conv1
	.p2align	4, 0x0
w_conv1:
	.zero	72
	.size	w_conv1, 72

	.protected	w_conv2                 ; @w_conv2
	.type	w_conv2,@object
	.globl	w_conv2
	.p2align	4, 0x0
w_conv2:
	.zero	72
	.size	w_conv2, 72

	.protected	w_conv3                 ; @w_conv3
	.type	w_conv3,@object
	.globl	w_conv3
	.p2align	4, 0x0
w_conv3:
	.zero	72
	.size	w_conv3, 72

	.protected	w_conv4                 ; @w_conv4
	.type	w_conv4,@object
	.globl	w_conv4
	.p2align	4, 0x0
w_conv4:
	.zero	72
	.size	w_conv4, 72

	.protected	w_conv5                 ; @w_conv5
	.type	w_conv5,@object
	.globl	w_conv5
	.p2align	4, 0x0
w_conv5:
	.zero	72
	.size	w_conv5, 72

	.protected	w_conv6                 ; @w_conv6
	.type	w_conv6,@object
	.globl	w_conv6
	.p2align	4, 0x0
w_conv6:
	.zero	72
	.size	w_conv6, 72

	.protected	w_conv7                 ; @w_conv7
	.type	w_conv7,@object
	.globl	w_conv7
	.p2align	4, 0x0
w_conv7:
	.zero	72
	.size	w_conv7, 72

	.protected	w_conv8                 ; @w_conv8
	.type	w_conv8,@object
	.globl	w_conv8
	.p2align	4, 0x0
w_conv8:
	.zero	72
	.size	w_conv8, 72

	.protected	w_conv9                 ; @w_conv9
	.type	w_conv9,@object
	.globl	w_conv9
	.p2align	4, 0x0
w_conv9:
	.zero	72
	.size	w_conv9, 72

	.protected	w_conv10                ; @w_conv10
	.type	w_conv10,@object
	.globl	w_conv10
	.p2align	4, 0x0
w_conv10:
	.zero	72
	.size	w_conv10, 72

	.protected	w_conv11                ; @w_conv11
	.type	w_conv11,@object
	.globl	w_conv11
	.p2align	4, 0x0
w_conv11:
	.zero	72
	.size	w_conv11, 72

	.protected	w_conv12                ; @w_conv12
	.type	w_conv12,@object
	.globl	w_conv12
	.p2align	4, 0x0
w_conv12:
	.zero	72
	.size	w_conv12, 72

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_imgs
	.addrsig_sym img_spks
	.addrsig_sym syn1
	.addrsig_sym syn1s
	.addrsig_sym syn
	.addrsig_sym in_spk
	.addrsig_sym Isyn
	.addrsig_sym weight
	.addrsig_sym Isyn_tot
	.addrsig_sym Isyn_lat
	.addrsig_sym I_lat
	.addrsig_sym D_op
	.addrsig_sym err
	.addrsig_sym Y_op
	.addrsig_sym del_w
	.addrsig_sym ci
	.addrsig_sym d_hat
	.addrsig_sym cis
	.addrsig_sym norm_dh
	.addrsig_sym cil
	.addrsig_sym cils
	.addrsig_sym d_hat_sq
	.addrsig_sym ref_time1
	.addrsig_sym ref_time2
	.addrsig_sym Vm1
	.addrsig_sym Vm2
	.addrsig_sym pix_spks
	.addrsig_sym I_in
	.addrsig_sym total_curr
	.addrsig_sym total_dhatsq
	.addrsig_sym w_conv1
	.addrsig_sym w_conv2
	.addrsig_sym w_conv3
	.addrsig_sym w_conv4
	.addrsig_sym w_conv5
	.addrsig_sym w_conv6
	.addrsig_sym w_conv7
	.addrsig_sym w_conv8
	.addrsig_sym w_conv9
	.addrsig_sym w_conv10
	.addrsig_sym w_conv11
	.addrsig_sym w_conv12
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14img_readKernelPi
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z14img_readKernelPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12convert2SpksPh
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    .sgpr_spill_count: 0
    .symbol:         _Z12convert2SpksPh.kd
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    .sgpr_spill_count: 0
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    .language:       OpenCL C
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    .language:       OpenCL C
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    .sgpr_spill_count: 0
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  - .args:
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    .language:       OpenCL C
    .language_version:
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    .name:           _Z10LifKernel2i
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    .sgpr_spill_count: 0
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
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...

	.end_amdgpu_metadata
