/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NOTICE TO USER:
 *
 * This source code is subject to NVIDIA ownership rights under U.S. and
 * international Copyright laws.  Users and possessors of this source code
 * are hereby granted a nonexclusive, royalty-free license to use this code
 * in individual and commercial software.
 *
 * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
 * CODE FOR ANY PURPOSE.  IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
 * IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
 * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 * OF USE, DATA OR PROFITS,  WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
 * OR OTHER TORTIOUS ACTION,  ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OR PERFORMANCE OF THIS SOURCE CODE.
 *
 * U.S. Government End Users.   This source code is a "commercial item" as
 * that term is defined at  48 C.F.R. 2.101 (OCT 1995), consisting  of
 * "commercial computer  software"  and "commercial computer software
 * documentation" as such terms are  used in 48 C.F.R. 12.212 (SEPT 1995)
 * and is provided to the U.S. Government only as a commercial end item.
 * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
 * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
 * source code with only those rights set forth herein.
 *
 * Any use of this source code in individual and commercial software must
 * include, in the user documentation and internal comments to the code,
 * the above Disclaimer and U.S. Government End Users Notice.
 */


// A simple macro to divide and round-up
#define DIVUP(A,B) ( (A)%(B) == 0 ? (A)/(B) : ((A) / (B) + 1) )

// macro to clamp to min & max value:
#define CLAMP(A,B,C) ( (A) < (B) ? (B) : (A) > (C) ? (C) : (A) )

// Declare constant memory for our convolution filter
__constant__ float FilterCoeff[9];

// Here's the CPU data for our filter which we'll copy into the constant memory
float FilterCoeff_CPU[9] = { -1.0f, -2.0f, -1.0f,
               -2.0f, 12.0f, -2.0f,
               -1.0f, -2.0f, -1.0f};



#define BLOCK_W 16
#define BLOCK_H 16
#define TILE_W (BLOCK_W * 4 + 16)  // need 8 pixel aprons because we are doing 64-bit reads)
#define TILE_H (BLOCK_H + 2)


__global__ void Convolution3x3Kernel(uchar4 * in_image, uchar4 * out_image, int width, int height, int pitch32)
{

  // This is a pointer to the shared memory we use for the image tile
  __shared__ unsigned char smem[TILE_W*TILE_H];
  int2 * smem_64bit = (int2*)smem;

  // Compute the thread index overall
  int X = __mul24(blockDim.x,blockIdx.x) + threadIdx.x;  
  int Y = __mul24(blockDim.y,blockIdx.y) + threadIdx.y;
  
  // variables to hold the addresses we are going to write & read in GMEM & SMEM
  int smem_idx;
  int gmem_idx;

  // Perform 64-bit reads, so only some of the threads need to participate.  
  // we'll cast the source image to a 64-bit data type (e.g. int2) and them read into a the smem with the same
  // 64-bit casting
  
  if(threadIdx.x < BLOCK_W / 2 + 2)
  {
    int row = CLAMP(Y-1,0,height-1);
    int col = __mul24(blockDim.x>>1,blockIdx.x) + threadIdx.x - 1;  // reading 8 bytes / thread, but only 1/2 of the block is used so divide blockDim / 2
    col = CLAMP(col,0,width>>3-1);
    gmem_idx = __mul24(row,pitch32>>1) + col;            // must divide the pitch32 & X by 2 since it's a 64-bit address
    smem_idx = __mul24(threadIdx.y,TILE_W/8) + threadIdx.x;        // the index into the 64-bit casted smem
  
    // Perform the read
    smem_64bit[smem_idx] = ((int2*)in_image)[gmem_idx];

    // two rows need to read again for the lower apron rows
    if(threadIdx.y < 2)
    {
      row = CLAMP(Y + BLOCK_H - 1,0,height-1);      
      gmem_idx = __mul24(row,pitch32>>1) + col;  
      smem_idx += TILE_W/8 * BLOCK_H;
      smem_64bit[smem_idx] = ((int2*)in_image)[gmem_idx];
    }
  }
    

  // Now we need to wait until all threads in this block have finished reading
  // their respective pixels into SMEM
  __syncthreads();
  if(X < width && Y < height) 
  {
    // Now for the convolutions.  
    uchar4 out;  // variable to store our output
    unsigned int f_idx = 0;  // index into the filter coefficients
    float sum;  

    // compute the location of the pixel in smem we are going to start to process.  
    // this will be the pixel to the top-left of the active pixel
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +7;

    // now do the math.  We'll use floating point since it's fastest
    // Pixel 1
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.x = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 2
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +8;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.y = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 3
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) + 9;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.z = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 4
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +10;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.w = (unsigned char)CLAMP(sum,0,255.0f);

    // **DEBUG**
    // The following lines of code are useful for debugging 
    // They simply copy the value of the primary pixels back to the output rather
    // than performing the convolution.  Thus, it's easy to tell if the GMEM is loaded
    // into SMEM properly. It's also useful to shift the offsets to insure the aprons are correct
    //out.x = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+7];
    //out.y = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+8];
    //out.z = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+9];
    //out.w = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+10];

    
    // Finally, write out the result!    
    gmem_idx = __mul24(Y,pitch32) + X;
    out_image[gmem_idx] = out;
  }
}



// Function to preform an arbitrary 3x3 convolution on a grayscale 8-bit image
extern "C" cudaError_t Convolution3x3(unsigned char * src, unsigned char * dest, int width, int height, size_t pitch)
{
  cudaError_t cerr;

  // First, copy data for the filter coefficients into constant memory
  cerr = cudaMemcpyToSymbol(FilterCoeff,FilterCoeff_CPU,9*sizeof(float));
  if(cerr != cudaSuccess) return(cerr);

  // Compute our block & grid dimensions
  dim3 BlockSz(BLOCK_W,BLOCK_H,1);
  dim3 GridSz(DIVUP(width,BlockSz.x*4),DIVUP(height,BlockSz.y),1);
  
  
  Convolution3x3Kernel<<<GridSz,BlockSz>>>((uchar4*)src, (uchar4*)dest,
                            width, height, (int)pitch/4);

  // Wait for this function to complete before we return
  cerr = cudaThreadSynchronize();

  return(cerr);  

}

	.file	"tmpxft_002cca38_00000000-6_Convolution3x3.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii
	.type	_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii, @function
_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z20Convolution3x3KernelP6uchar4S0_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii, .-_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii
	.globl	_Z20Convolution3x3KernelP6uchar4S0_iii
	.type	_Z20Convolution3x3KernelP6uchar4S0_iii, @function
_Z20Convolution3x3KernelP6uchar4S0_iii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii
	.cfi_endproc
.LFE2034:
	.size	_Z20Convolution3x3KernelP6uchar4S0_iii, .-_Z20Convolution3x3KernelP6uchar4S0_iii
	.globl	Convolution3x3
	.type	Convolution3x3, @function
Convolution3x3:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	leaq	FilterCoeff_CPU(%rip), %rsi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	leaq	_ZL11FilterCoeff(%rip), %rdi
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%ecx, %r12d
	xorl	%ecx, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	movl	$36, %edx
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movq	%r8, %rbx
	movl	$1, %r8d
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	call	cudaMemcpyToSymbol@PLT
	testl	%eax, %eax
	jne	.L8
	movl	%r12d, %edx
	movl	%r12d, %eax
	movl	%ebp, %ecx
	movl	$1, %esi
	andl	$15, %edx
	shrl	$4, %eax
	cmpl	$1, %edx
	movl	%ebp, %edx
	sbbl	$-1, %eax
	andl	$63, %ecx
	shrl	$6, %edx
	cmpl	$1, %ecx
	movl	%eax, 24(%rsp)
	movl	$1, %ecx
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 20(%rsp)
	movq	20(%rsp), %rdi
	movabsq	$68719476752, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movl	%ebx, %eax
	movl	$4, %ecx
	movq	%r14, %rsi
	movq	%r13, %rdi
	cltd
	idivl	%ecx
	movl	%r12d, %ecx
	movl	%ebp, %edx
	movl	%eax, %r8d
	call	_Z52__device_stub__Z20Convolution3x3KernelP6uchar4S0_iiiP6uchar4S0_iii
.L12:
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	cudaThreadSynchronize@PLT
.L8:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	Convolution3x3, .-Convolution3x3
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20Convolution3x3KernelP6uchar4S0_iii"
.LC1:
	.string	"FilterCoeff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20Convolution3x3KernelP6uchar4S0_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$36, %r9d
	leaq	_ZL11FilterCoeff(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	FilterCoeff_CPU
	.data
	.align 32
	.type	FilterCoeff_CPU, @object
	.size	FilterCoeff_CPU, 36
FilterCoeff_CPU:
	.long	-1082130432
	.long	-1073741824
	.long	-1082130432
	.long	-1073741824
	.long	1094713344
	.long	-1073741824
	.long	-1082130432
	.long	-1073741824
	.long	-1082130432
	.local	_ZL11FilterCoeff
	.comm	_ZL11FilterCoeff,36,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
 * Copyright 1993-2009 NVIDIA Corporation.  All rights reserved.
 *
 * NOTICE TO USER:
 *
 * This source code is subject to NVIDIA ownership rights under U.S. and
 * international Copyright laws.  Users and possessors of this source code
 * are hereby granted a nonexclusive, royalty-free license to use this code
 * in individual and commercial software.
 *
 * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
 * CODE FOR ANY PURPOSE.  IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
 * IMPLIED WARRANTY OF ANY KIND.  NVIDIA DISCLAIMS ALL WARRANTIES WITH
 * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
 * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
 * OF USE, DATA OR PROFITS,  WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
 * OR OTHER TORTIOUS ACTION,  ARISING OUT OF OR IN CONNECTION WITH THE USE
 * OR PERFORMANCE OF THIS SOURCE CODE.
 *
 * U.S. Government End Users.   This source code is a "commercial item" as
 * that term is defined at  48 C.F.R. 2.101 (OCT 1995), consisting  of
 * "commercial computer  software"  and "commercial computer software
 * documentation" as such terms are  used in 48 C.F.R. 12.212 (SEPT 1995)
 * and is provided to the U.S. Government only as a commercial end item.
 * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
 * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
 * source code with only those rights set forth herein.
 *
 * Any use of this source code in individual and commercial software must
 * include, in the user documentation and internal comments to the code,
 * the above Disclaimer and U.S. Government End Users Notice.
 */


// A simple macro to divide and round-up
#define DIVUP(A,B) ( (A)%(B) == 0 ? (A)/(B) : ((A) / (B) + 1) )

// macro to clamp to min & max value:
#define CLAMP(A,B,C) ( (A) < (B) ? (B) : (A) > (C) ? (C) : (A) )

// Declare constant memory for our convolution filter
__constant__ float FilterCoeff[9];

// Here's the CPU data for our filter which we'll copy into the constant memory
float FilterCoeff_CPU[9] = { -1.0f, -2.0f, -1.0f,
               -2.0f, 12.0f, -2.0f,
               -1.0f, -2.0f, -1.0f};



#define BLOCK_W 16
#define BLOCK_H 16
#define TILE_W (BLOCK_W * 4 + 16)  // need 8 pixel aprons because we are doing 64-bit reads)
#define TILE_H (BLOCK_H + 2)


__global__ void Convolution3x3Kernel(uchar4 * in_image, uchar4 * out_image, int width, int height, int pitch32)
{

  // This is a pointer to the shared memory we use for the image tile
  __shared__ unsigned char smem[TILE_W*TILE_H];
  int2 * smem_64bit = (int2*)smem;

  // Compute the thread index overall
  int X = __mul24(blockDim.x,blockIdx.x) + threadIdx.x;  
  int Y = __mul24(blockDim.y,blockIdx.y) + threadIdx.y;
  
  // variables to hold the addresses we are going to write & read in GMEM & SMEM
  int smem_idx;
  int gmem_idx;

  // Perform 64-bit reads, so only some of the threads need to participate.  
  // we'll cast the source image to a 64-bit data type (e.g. int2) and them read into a the smem with the same
  // 64-bit casting
  
  if(threadIdx.x < BLOCK_W / 2 + 2)
  {
    int row = CLAMP(Y-1,0,height-1);
    int col = __mul24(blockDim.x>>1,blockIdx.x) + threadIdx.x - 1;  // reading 8 bytes / thread, but only 1/2 of the block is used so divide blockDim / 2
    col = CLAMP(col,0,width>>3-1);
    gmem_idx = __mul24(row,pitch32>>1) + col;            // must divide the pitch32 & X by 2 since it's a 64-bit address
    smem_idx = __mul24(threadIdx.y,TILE_W/8) + threadIdx.x;        // the index into the 64-bit casted smem
  
    // Perform the read
    smem_64bit[smem_idx] = ((int2*)in_image)[gmem_idx];

    // two rows need to read again for the lower apron rows
    if(threadIdx.y < 2)
    {
      row = CLAMP(Y + BLOCK_H - 1,0,height-1);      
      gmem_idx = __mul24(row,pitch32>>1) + col;  
      smem_idx += TILE_W/8 * BLOCK_H;
      smem_64bit[smem_idx] = ((int2*)in_image)[gmem_idx];
    }
  }
    

  // Now we need to wait until all threads in this block have finished reading
  // their respective pixels into SMEM
  __syncthreads();
  if(X < width && Y < height) 
  {
    // Now for the convolutions.  
    uchar4 out;  // variable to store our output
    unsigned int f_idx = 0;  // index into the filter coefficients
    float sum;  

    // compute the location of the pixel in smem we are going to start to process.  
    // this will be the pixel to the top-left of the active pixel
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +7;

    // now do the math.  We'll use floating point since it's fastest
    // Pixel 1
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.x = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 2
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +8;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.y = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 3
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) + 9;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.z = (unsigned char)CLAMP(sum,0,255.0f);

    // Pixel 4
    f_idx = 0;
    smem_idx = __mul24(threadIdx.y,TILE_W) + (threadIdx.x<<2) +10;
    sum = FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+2];
    smem_idx += TILE_W;
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx];
    sum += FilterCoeff[f_idx++] * (float)smem[smem_idx+1];
    sum += FilterCoeff[f_idx] * (float)smem[smem_idx+2];
    out.w = (unsigned char)CLAMP(sum,0,255.0f);

    // **DEBUG**
    // The following lines of code are useful for debugging 
    // They simply copy the value of the primary pixels back to the output rather
    // than performing the convolution.  Thus, it's easy to tell if the GMEM is loaded
    // into SMEM properly. It's also useful to shift the offsets to insure the aprons are correct
    //out.x = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+7];
    //out.y = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+8];
    //out.z = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+9];
    //out.w = smem[(threadIdx.y+1)*TILE_W + threadIdx.x*4+10];

    
    // Finally, write out the result!    
    gmem_idx = __mul24(Y,pitch32) + X;
    out_image[gmem_idx] = out;
  }
}



// Function to preform an arbitrary 3x3 convolution on a grayscale 8-bit image
extern "C" hipError_t Convolution3x3(unsigned char * src, unsigned char * dest, int width, int height, size_t pitch)
{
  hipError_t cerr;

  // First, copy data for the filter coefficients into constant memory
  cerr = hipMemcpyToSymbol(HIP_SYMBOL(FilterCoeff),FilterCoeff_CPU,9*sizeof(float));
  if(cerr != hipSuccess) return(cerr);

  // Compute our block & grid dimensions
  dim3 BlockSz(BLOCK_W,BLOCK_H,1);
  dim3 GridSz(DIVUP(width,BlockSz.x*4),DIVUP(height,BlockSz.y),1);
  
  
  Convolution3x3Kernel<<<GridSz,BlockSz>>>((uchar4*)src, (uchar4*)dest,
                            width, height, (int)pitch/4);

  // Wait for this function to complete before we return
  cerr = hipDeviceSynchronize();

  return(cerr);  

}

	.text
	.file	"Convolution3x3.hip"
	.globl	_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii # -- Begin function _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.type	_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@function
_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii: # @_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, .Lfunc_end0-_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.cfi_endproc
                                        # -- End function
	.globl	Convolution3x3                  # -- Begin function Convolution3x3
	.type	Convolution3x3,@function
Convolution3x3:                         # @Convolution3x3
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %r12
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movl	$FilterCoeff, %edi
	movl	$FilterCoeff_CPU, %esi
	movl	$36, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	je	.LBB1_1
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 48
	movl	%ebp, %eax
	andl	$63, %eax
	movl	%ebp, %ecx
	shrl	$6, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%ebx, %eax
	andl	$15, %eax
	movl	%ebx, %edi
	shrl	$4, %edi
	cmpl	$1, %eax
	sbbl	$-1, %edi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:
	leal	3(%r12), %r8d
	testl	%r12d, %r12d
	cmovnsl	%r12d, %r8d
	sarl	$2, %r8d
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	callq	_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
.LBB1_3:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipDeviceSynchronize            # TAILCALL
.Lfunc_end1:
	.size	Convolution3x3, .Lfunc_end1-Convolution3x3
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$FilterCoeff, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	FilterCoeff,@object             # @FilterCoeff
	.local	FilterCoeff
	.comm	FilterCoeff,36,16
	.type	FilterCoeff_CPU,@object         # @FilterCoeff_CPU
	.data
	.globl	FilterCoeff_CPU
	.p2align	4, 0x0
FilterCoeff_CPU:
	.long	0xbf800000                      # float -1
	.long	0xc0000000                      # float -2
	.long	0xbf800000                      # float -1
	.long	0xc0000000                      # float -2
	.long	0x41400000                      # float 12
	.long	0xc0000000                      # float -2
	.long	0xbf800000                      # float -1
	.long	0xc0000000                      # float -2
	.long	0xbf800000                      # float -1
	.size	FilterCoeff_CPU, 36

	.type	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@object # @_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.section	.rodata,"a",@progbits
	.globl	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.p2align	3, 0x0
_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii:
	.quad	_Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.size	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii"
	.size	.L__unnamed_1, 56

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"FilterCoeff"
	.size	.L__unnamed_2, 12

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym FilterCoeff
	.addrsig_sym FilterCoeff_CPU
	.addrsig_sym _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii ; -- Begin function _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.globl	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
	.p2align	8
	.type	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii,@function
_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii: ; @_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_bfe_i32 s9, s15, 0x180000
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s8, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s9, s7, v[3:4]
	s_and_b32 s7, s8, 0xffff
	s_bfe_i32 s8, s14, 0x180000
	s_mov_b32 s9, exec_lo
	v_cmpx_gt_u32_e32 10, v4
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_lshr_b32 s10, s7, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v1, -1, v0
	s_mul_i32 s11, s10, s8
	s_add_i32 s10, s5, -1
	v_add3_u32 v2, v4, s11, -1
	s_ashr_i32 s11, s4, 2
	v_min_i32_e32 v1, s10, v1
	v_lshlrev_b32_e32 v7, 3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_min_i32_e32 v5, s11, v2
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_and_b32_e32 v6, 0xffffff, v1
	s_bfe_i32 s11, s6, 0x180001
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v2, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_i32_i24 v5, v2, s11, v1
	v_mul_u32_u24_e32 v2, 10, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, v2, 3, v7
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_cmp_gt_u32_e32 vcc_lo, 2, v3
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_add_nc_u32_e32 v5, 15, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v5
	v_cndmask_b32_e32 v5, s10, v5, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, -16, v0
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_i32_i24 v5, v5, s11, v1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6] offset:1280
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_mad_u64_u32 v[1:2], null, s8, s7, v[4:5]
	v_cmp_gt_i32_e64 s0, s5, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, FilterCoeff@rel32@lo+4
	s_addc_u32 s1, s1, FilterCoeff@rel32@hi+12
	v_mad_i32_i24 v0, v0, s6, v1
	s_load_b256 s[8:15], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 2, v4
	s_load_b32 s0, s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_mad_u32_u24 v4, 0x50, v3, v2
	ds_load_u8 v5, v4 offset:7
	ds_load_2addr_b32 v[2:3], v4 offset0:2 offset1:22
	ds_load_u8 v6, v4 offset:87
	ds_load_u8 v7, v4 offset:167
	ds_load_b32 v8, v4 offset:168
	ds_load_u8 v9, v4 offset:12
	ds_load_u8 v10, v4 offset:172
	ds_load_u8 v4, v4 offset:92
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_ubyte0_e32 v5, v5
	v_cvt_f32_ubyte0_e32 v11, v2
	v_cvt_f32_ubyte2_e32 v16, v2
	v_cvt_f32_ubyte1_e32 v12, v2
	v_cvt_f32_ubyte3_e32 v2, v2
	v_cvt_f32_ubyte1_e32 v14, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v17, s9, v11 :: v_dual_mul_f32 v20, s9, v16
	v_cvt_f32_ubyte1_e32 v18, v8
	v_mul_f32_e32 v21, s9, v2
	v_cvt_f32_ubyte0_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v17, s8, v5 :: v_dual_fmac_f32 v20, s8, v12
	v_mul_f32_e32 v19, s9, v12
	v_cvt_f32_ubyte0_e32 v5, v9
	v_cvt_f32_ubyte2_e32 v9, v3
	v_cvt_f32_ubyte0_e32 v13, v3
	v_dual_fmac_f32 v20, s10, v2 :: v_dual_fmac_f32 v19, s8, v11
	v_cvt_f32_ubyte3_e32 v2, v3
	v_cvt_f32_ubyte0_e32 v3, v4
	v_cvt_f32_ubyte2_e32 v4, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v20, s11, v14 :: v_dual_fmac_f32 v21, s8, v16
	v_cvt_f32_ubyte0_e32 v7, v7
	v_cvt_f32_ubyte0_e32 v15, v8
	v_dual_fmac_f32 v20, s12, v9 :: v_dual_fmac_f32 v17, s10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, s13, v2 :: v_dual_fmac_f32 v19, s10, v16
	v_fmac_f32_e32 v17, s11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, s14, v18 :: v_dual_fmac_f32 v21, s10, v5
	v_dual_fmac_f32 v17, s12, v13 :: v_dual_fmac_f32 v20, s15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, s11, v9
	v_fmac_f32_e32 v17, s13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v21, s12, v2
	v_cvt_f32_ubyte3_e32 v2, v8
	v_fmac_f32_e32 v19, s11, v13
	v_fmac_f32_e32 v17, s14, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, s13, v3 :: v_dual_fmac_f32 v20, s0, v2
	v_fmac_f32_e32 v19, s12, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v17, s15, v15
	v_cvt_f32_ubyte0_e32 v3, v10
	v_fmac_f32_e32 v21, s14, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, s13, v9
	v_fmac_f32_e32 v17, s0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, s15, v2
	v_fmac_f32_e32 v19, s14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v17
	v_fmac_f32_e32 v21, s0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, s15, v18
	v_cndmask_b32_e32 v2, 0x437f0000, v17, vcc_lo
	v_fmac_f32_e32 v19, s0, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v19
	v_cndmask_b32_e32 v3, 0x437f0000, v19, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v21
	v_cndmask_b32_e32 v4, 0x437f0000, v21, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x437f0000, v20
	v_cndmask_b32_e32 v5, 0x437f0000, v20, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v19
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v3, v3
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v17
	v_lshlrev_b16 v3, 8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v4, v4
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v20
	v_lshlrev_b16 v4, 8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v2, v2
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_cvt_i32_f32_e32 v5, v5
	v_or_b32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, v5, v4
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 16, v3
	v_or_b32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
		.amdhsa_group_segment_fixed_size 1440
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii, .Lfunc_end0-_Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1028
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1440 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	FilterCoeff             ; @FilterCoeff
	.type	FilterCoeff,@object
	.section	.bss,"aw",@nobits
	.globl	FilterCoeff
	.p2align	4, 0x0
FilterCoeff:
	.zero	36
	.size	FilterCoeff, 36

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym FilterCoeff
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1440
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20Convolution3x3KernelP15HIP_vector_typeIhLj4EES1_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
