/**
 * Copyright 2019 Matthew Oliver
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#include <cstdint>

__device__ __forceinline__ float clamp(const float f, const float a, const float b)
{
    return fmaxf(a, fminf(f, b));
}

__device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv)
{
    // Get YCbCr values
    const float luma = static_cast<float>(yuv.x);
    const float chromaCb = static_cast<float>(yuv.y) - 128.0f;
    const float chromaCr = static_cast<float>(yuv.z) - 128.0f;

    // Convert to RGB using BT601
    return make_float3(
        luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb);
}

struct Pixel2
{
    float3 m_pixels[2];
};

struct NV12Planes
{
    uint8_t* m_plane1;
    uint8_t* m_plane2;
};

template<typename T>
struct RGBPlanes
{
    T* m_plane1;
    T* m_plane2;
    T* m_plane3;
};

__device__ __forceinline__ Pixel2 getNV12ToRGB(
    const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep)
{
    // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved
    // There are 1 U+V sample for every 2x2 Y block
    //  Y1  Y2  Y3  Y4  Y5  Y5
    //  Y7  Y8  Y9  Y10 Y11 Y12
    //  Y13 Y14 Y15 Y16 Y17 Y18
    //  Y19 Y20 Y21 Y22 Y23 Y24
    //
    //  U1 V1 U2 V2 U2 V3
    //  U4 V4 U5 V5 U6 V6
    //
    //  UV1 is used for Y1 Y2 Y7 Y8
    //  UV2 is used for Y3 Y4 Y9 Y10
    //  UV4 is used for Y13 Y14 Y19 Y20
    // etc.
    // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows
    //  To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4
    //  This replaces 2 Y loads at a time with 2 UV loads for each 2xY row

    uchar3 yuvi[2];
    const uint32_t sourceOffset = y * sourceStep + x;
    yuvi[0].x = source.m_plane1[sourceOffset];
    yuvi[1].x = source.m_plane1[sourceOffset + 1];

    const uint32_t chromaOffset = y >> 1;
    const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x;
    const uint8_t chromaCb = source.m_plane2[chromaSourceOffset];
    const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1];

    // This doesn't perform any chroma interpolation, this feature would need to be added later if needed

    yuvi[0].y = chromaCb;
    yuvi[0].z = chromaCr;
    yuvi[1].y = chromaCb;
    yuvi[1].z = chromaCr;

    Pixel2 rgb;
    rgb.m_pixels[0] = YUVToRGB(yuvi[0]);
    rgb.m_pixels[1] = YUVToRGB(yuvi[1]);

    return rgb;
}

template<typename T>
class UpPack
{
public:
    typedef float3 Type;
};

template<>
class UpPack<uint8_t>
{
public:
    typedef uchar3 Type;
};

template<typename T>
__device__ __forceinline__ T getRGB(const float3 pixel)
{
    // Normalise float values
    return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f));
}

template<>
__device__ __forceinline__ uchar3 getRGB(const float3 pixel)
{
    return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f));
}

template<typename T>
__device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep,
    const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep)
{
    const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1);
    const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y;

    if (x >= width - 1 || y >= height) {
        return;
    }

    Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep);

    const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]);
    const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]);
    const uint32_t destOffset = y * destStep + x;
    dest.m_plane1[destOffset] = pixel1.x;
    dest.m_plane1[destOffset + 1] = pixel2.x;
    dest.m_plane2[destOffset] = pixel1.y;
    dest.m_plane2[destOffset + 1] = pixel2.y;
    dest.m_plane3[destOffset] = pixel1.z;
    dest.m_plane3[destOffset + 1] = pixel2.z;
}

extern "C" {
__global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width,
    const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep)
{
    convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep);
}

__global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width,
    const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep)
{
    convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float));
}
}
	.file	"tmpxft_00208e3d_00000000-6_FFFRFormatConvert.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2016:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2016:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj
	.type	_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, @function
_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 120(%rsp)
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 168
	leaq	convertNV12ToRGB8P(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 176
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj, .-_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj
	.globl	convertNV12ToRGB8P
	.type	convertNV12ToRGB8P, @function
convertNV12ToRGB8P:
.LFB2039:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, (%rsp)
	movq	%rsp, %rdi
	movq	%rsi, 8(%rsp)
	movl	%edx, %esi
	movl	%ecx, %edx
	movl	%r8d, %ecx
	leaq	32(%rsp), %r8
	call	_Z65__device_stub__Z18convertNV12ToRGB8P10NV12Planesjjj9RGBPlanesIhEjRK10NV12PlanesjjjRK9RGBPlanesIhEj
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	convertNV12ToRGB8P, .-convertNV12ToRGB8P
	.globl	_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj
	.type	_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, @function
_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%esi, 12(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, 8(%rsp)
	leaq	24(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	32(%rsp), %rcx
	movl	%r9d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 120(%rsp)
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	32(%rsp)
	.cfi_def_cfa_offset 168
	leaq	convertNV12ToRGB32FP(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 176
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L9:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj, .-_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj
	.globl	convertNV12ToRGB32FP
	.type	convertNV12ToRGB32FP, @function
convertNV12ToRGB32FP:
.LFB2041:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, (%rsp)
	movq	%rsp, %rdi
	movq	%rsi, 8(%rsp)
	movl	%edx, %esi
	movl	%ecx, %edx
	movl	%r8d, %ecx
	leaq	32(%rsp), %r8
	call	_Z67__device_stub__Z20convertNV12ToRGB32FP10NV12Planesjjj9RGBPlanesIfEjRK10NV12PlanesjjjRK9RGBPlanesIfEj
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	convertNV12ToRGB32FP, .-convertNV12ToRGB32FP
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"convertNV12ToRGB32FP"
.LC1:
	.string	"convertNV12ToRGB8P"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	convertNV12ToRGB32FP(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	convertNV12ToRGB8P(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * Copyright 2019 Matthew Oliver
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <hip/hip_runtime.h>
#include <cstdint>

__device__ __forceinline__ float clamp(const float f, const float a, const float b)
{
    return fmaxf(a, fminf(f, b));
}

__device__ __forceinline__ float3 YUVToRGB(const uchar3 yuv)
{
    // Get YCbCr values
    const float luma = static_cast<float>(yuv.x);
    const float chromaCb = static_cast<float>(yuv.y) - 128.0f;
    const float chromaCr = static_cast<float>(yuv.z) - 128.0f;

    // Convert to RGB using BT601
    return make_float3(
        luma + 1.13983 * chromaCr, luma - 0.39465f * chromaCb - 0.58060f * chromaCr, luma + 2.03211f * chromaCb);
}

struct Pixel2
{
    float3 m_pixels[2];
};

struct NV12Planes
{
    uint8_t* m_plane1;
    uint8_t* m_plane2;
};

template<typename T>
struct RGBPlanes
{
    T* m_plane1;
    T* m_plane2;
    T* m_plane3;
};

__device__ __forceinline__ Pixel2 getNV12ToRGB(
    const uint32_t x, const uint32_t y, const NV12Planes source, const uint32_t sourceStep)
{
    // NV12 is stored as 2 planes: the first plane contains Y the second plane contains U+V interleaved
    // There are 1 U+V sample for every 2x2 Y block
    //  Y1  Y2  Y3  Y4  Y5  Y5
    //  Y7  Y8  Y9  Y10 Y11 Y12
    //  Y13 Y14 Y15 Y16 Y17 Y18
    //  Y19 Y20 Y21 Y22 Y23 Y24
    //
    //  U1 V1 U2 V2 U2 V3
    //  U4 V4 U5 V5 U6 V6
    //
    //  UV1 is used for Y1 Y2 Y7 Y8
    //  UV2 is used for Y3 Y4 Y9 Y10
    //  UV4 is used for Y13 Y14 Y19 Y20
    // etc.
    // Reading a 2x2 Y block requires 2 memory reads as it is split over 2 rows
    //  To try and be a bit more cache friendly Y is processed in 2 pixels (row) at a time instead of 4
    //  This replaces 2 Y loads at a time with 2 UV loads for each 2xY row

    uchar3 yuvi[2];
    const uint32_t sourceOffset = y * sourceStep + x;
    yuvi[0].x = source.m_plane1[sourceOffset];
    yuvi[1].x = source.m_plane1[sourceOffset + 1];

    const uint32_t chromaOffset = y >> 1;
    const uint32_t chromaSourceOffset = chromaOffset * sourceStep + x;
    const uint8_t chromaCb = source.m_plane2[chromaSourceOffset];
    const uint8_t chromaCr = source.m_plane2[chromaSourceOffset + 1];

    // This doesn't perform any chroma interpolation, this feature would need to be added later if needed

    yuvi[0].y = chromaCb;
    yuvi[0].z = chromaCr;
    yuvi[1].y = chromaCb;
    yuvi[1].z = chromaCr;

    Pixel2 rgb;
    rgb.m_pixels[0] = YUVToRGB(yuvi[0]);
    rgb.m_pixels[1] = YUVToRGB(yuvi[1]);

    return rgb;
}

template<typename T>
class UpPack
{
public:
    typedef float3 Type;
};

template<>
class UpPack<uint8_t>
{
public:
    typedef uchar3 Type;
};

template<typename T>
__device__ __forceinline__ T getRGB(const float3 pixel)
{
    // Normalise float values
    return make_float3(__saturatef(pixel.x / 255.0f), __saturatef(pixel.y / 255.0f), __saturatef(pixel.z / 255.0f));
}

template<>
__device__ __forceinline__ uchar3 getRGB(const float3 pixel)
{
    return make_uchar3(clamp(pixel.x, 0.0f, 255.0f), clamp(pixel.y, 0.0f, 255.0f), clamp(pixel.z, 0.0f, 255.0f));
}

template<typename T>
__device__ __forceinline__ void convertNV12ToRGBP(const NV12Planes source, const uint32_t sourceStep,
    const uint32_t width, const uint32_t height, RGBPlanes<T> dest, const uint32_t destStep)
{
    const uint32_t x = blockIdx.x * (blockDim.x << 1) + (threadIdx.x << 1);
    const uint32_t y = blockIdx.y * blockDim.y + threadIdx.y;

    if (x >= width - 1 || y >= height) {
        return;
    }

    Pixel2 pixels = getNV12ToRGB(x, y, source, sourceStep);

    const auto pixel1 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[0]);
    const auto pixel2 = getRGB<typename UpPack<T>::Type>(pixels.m_pixels[1]);
    const uint32_t destOffset = y * destStep + x;
    dest.m_plane1[destOffset] = pixel1.x;
    dest.m_plane1[destOffset + 1] = pixel2.x;
    dest.m_plane2[destOffset] = pixel1.y;
    dest.m_plane2[destOffset + 1] = pixel2.y;
    dest.m_plane3[destOffset] = pixel1.z;
    dest.m_plane3[destOffset + 1] = pixel2.z;
}

extern "C" {
__global__ void convertNV12ToRGB8P(const NV12Planes source, const uint32_t sourceStep, const uint32_t width,
    const uint32_t height, const RGBPlanes<uint8_t> dest, const uint32_t destStep)
{
    convertNV12ToRGBP<uint8_t>(source, sourceStep, width, height, dest, destStep);
}

__global__ void convertNV12ToRGB32FP(const NV12Planes source, const uint32_t sourceStep, const uint32_t width,
    const uint32_t height, const RGBPlanes<float> dest, const uint32_t destStep)
{
    convertNV12ToRGBP<float>(source, sourceStep, width, height, dest, destStep / sizeof(float));
}
}
	.text
	.file	"FFFRFormatConvert.hip"
	.globl	__device_stub__convertNV12ToRGB8P # -- Begin function __device_stub__convertNV12ToRGB8P
	.type	__device_stub__convertNV12ToRGB8P,@function
__device_stub__convertNV12ToRGB8P:      # @__device_stub__convertNV12ToRGB8P
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	64(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsi, 8(%rax)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %rdi
	movl	%r9d, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rcx, 24(%rbx)
	leaq	176(%rsp), %rax
	movq	%rax, 32(%rbx)
	movq	%rdi, 40(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$convertNV12ToRGB8P, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__convertNV12ToRGB8P, .Lfunc_end0-__device_stub__convertNV12ToRGB8P
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__convertNV12ToRGB32FP # -- Begin function __device_stub__convertNV12ToRGB32FP
	.type	__device_stub__convertNV12ToRGB32FP,@function
__device_stub__convertNV12ToRGB32FP:    # @__device_stub__convertNV12ToRGB32FP
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	64(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsi, 8(%rax)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %rdi
	movl	%r9d, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rcx, 24(%rbx)
	leaq	176(%rsp), %rax
	movq	%rax, 32(%rbx)
	movq	%rdi, 40(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$convertNV12ToRGB32FP, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__convertNV12ToRGB32FP, .Lfunc_end1-__device_stub__convertNV12ToRGB32FP
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$convertNV12ToRGB8P, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$convertNV12ToRGB32FP, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	convertNV12ToRGB8P,@object      # @convertNV12ToRGB8P
	.section	.rodata,"a",@progbits
	.globl	convertNV12ToRGB8P
	.p2align	3, 0x0
convertNV12ToRGB8P:
	.quad	__device_stub__convertNV12ToRGB8P
	.size	convertNV12ToRGB8P, 8

	.type	convertNV12ToRGB32FP,@object    # @convertNV12ToRGB32FP
	.globl	convertNV12ToRGB32FP
	.p2align	3, 0x0
convertNV12ToRGB32FP:
	.quad	__device_stub__convertNV12ToRGB32FP
	.size	convertNV12ToRGB32FP, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"convertNV12ToRGB8P"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"convertNV12ToRGB32FP"
	.size	.L__unnamed_2, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__convertNV12ToRGB8P
	.addrsig_sym __device_stub__convertNV12ToRGB32FP
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym convertNV12ToRGB8P
	.addrsig_sym convertNV12ToRGB32FP
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	convertNV12ToRGB8P      ; -- Begin function convertNV12ToRGB8P
	.globl	convertNV12ToRGB8P
	.p2align	8
	.type	convertNV12ToRGB8P,@function
convertNV12ToRGB8P:                     ; @convertNV12ToRGB8P
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 1, v1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s3
	v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
	v_lshl_add_u32 v1, s14, 1, v3
	s_add_i32 s2, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s6, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_lshrrev_b32_e32 v4, 1, v0
	s_mov_b32 s2, 0x61cffeb0
	s_mov_b32 s3, 0x3ff23cbe
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
	v_add_nc_u32_e32 v5, 1, v2
	v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	global_load_u8 v4, v5, s[10:11]
	v_add_nc_u32_e32 v5, 1, v3
	s_clause 0x1
	global_load_u8 v8, v3, s[8:9]
	global_load_u8 v9, v5, s[8:9]
	global_load_u8 v10, v2, s[10:11]
	s_waitcnt vmcnt(3)
	v_cvt_f32_ubyte0_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v11, 0xc3000000, v2
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[2:3], v8
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[6:7], v9
	v_cvt_f64_f32_e32 v[4:5], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
	v_fma_f64 v[4:5], v[4:5], s[2:3], v[6:7]
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x38
	s_load_b64 s[0:1], s[0:1], 0x30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v6, v[2:3]
	v_cvt_f32_f64_e32 v4, v[4:5]
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v5, v10
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	v_cvt_f32_ubyte0_e32 v0, v8
	v_cvt_f32_ubyte0_e32 v3, v9
	v_add_f32_e32 v1, 0xc3000000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmamk_f32 v5, v1, 0xbeca0f91, v0
	v_fmac_f32_e32 v0, 0x40020e17, v1
	v_fmamk_f32 v7, v1, 0xbeca0f91, v3
	v_fmac_f32_e32 v3, 0x40020e17, v1
	v_add_nc_u32_e32 v1, 1, v2
	v_fmac_f32_e32 v5, 0xbf14a234, v11
	v_minmax_f32 v0, v0, 0x437f0000, 0
	v_fmac_f32_e32 v7, 0xbf14a234, v11
	v_minmax_f32 v3, v3, 0x437f0000, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_minmax_f32 v5, v5, 0x437f0000, 0
	v_cvt_i32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_minmax_f32 v7, v7, 0x437f0000, 0
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v7, v7
	v_minmax_f32 v6, v6, 0x437f0000, 0
	v_minmax_f32 v4, v4, 0x437f0000, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v6, v6
	v_cvt_i32_f32_e32 v4, v4
	s_clause 0x1
	global_store_b8 v2, v6, s[4:5]
	global_store_b8 v1, v4, s[4:5]
	s_clause 0x1
	global_store_b8 v2, v5, s[6:7]
	global_store_b8 v1, v7, s[6:7]
	s_clause 0x1
	global_store_b8 v2, v0, s[0:1]
	global_store_b8 v1, v3, s[0:1]
.LBB0_2:                                ; %_Z17convertNV12ToRGBPIhEv10NV12Planesjjj9RGBPlanesIT_Ej.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel convertNV12ToRGB8P
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	convertNV12ToRGB8P, .Lfunc_end0-convertNV12ToRGB8P
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 592
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	convertNV12ToRGB32FP    ; -- Begin function convertNV12ToRGB32FP
	.globl	convertNV12ToRGB32FP
	.p2align	8
	.type	convertNV12ToRGB32FP,@function
convertNV12ToRGB32FP:                   ; @convertNV12ToRGB32FP
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 1, v1
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s3
	v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
	v_lshl_add_u32 v1, s14, 1, v3
	s_add_i32 s2, s5, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u32_e64 s2, s6, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_lshrrev_b32_e32 v4, 1, v0
	s_mov_b32 s2, 0x61cffeb0
	s_mov_b32 s3, 0x3ff23cbe
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
	v_add_nc_u32_e32 v5, 1, v2
	v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	global_load_u8 v4, v5, s[10:11]
	v_add_nc_u32_e32 v5, 1, v3
	s_clause 0x1
	global_load_u8 v14, v3, s[8:9]
	global_load_u8 v15, v5, s[8:9]
	global_load_u8 v12, v2, s[10:11]
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x38
	s_load_b64 s[0:1], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s8, s8, 2
	s_waitcnt vmcnt(3)
	v_cvt_f32_ubyte0_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v16, 0xc3000000, v2
	s_waitcnt vmcnt(2)
	v_cvt_f64_u32_e32 v[2:3], v14
	s_waitcnt vmcnt(1)
	v_cvt_f64_u32_e32 v[6:7], v15
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v17, v12
	v_cvt_f32_ubyte0_e32 v14, v14
	v_cvt_f64_f32_e32 v[4:5], v16
	v_cvt_f32_ubyte0_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, 0xc3000000, v17
	v_fmamk_f32 v20, v17, 0xbeca0f91, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, 0xbf14a234, v16
	v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
	v_fma_f64 v[4:5], v[4:5], s[2:3], v[6:7]
	v_div_scale_f32 v28, s2, v20, 0x437f0000, v20
	v_fmamk_f32 v21, v17, 0xbeca0f91, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, 0xbf14a234, v16
	v_div_scale_f32 v16, null, 0x437f0000, 0x437f0000, v20
	v_rcp_f32_e32 v24, v16
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v16, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v31, v24
	v_mul_f32_e32 v36, v28, v24
	v_cvt_f32_f64_e32 v18, v[2:3]
	v_mad_u64_u32 v[6:7], null, v0, s8, v[1:2]
	v_mov_b32_e32 v7, 0
	v_cvt_f32_f64_e32 v19, v[4:5]
	v_fma_f32 v43, -v16, v36, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	v_add_nc_u32_e32 v6, 1, v6
	v_fmac_f32_e32 v36, v43, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v6
	v_div_scale_f32 v32, null, 0x437f0000, 0x437f0000, v18
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
	v_div_scale_f32 v33, null, 0x437f0000, 0x437f0000, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v34, v32
	v_div_scale_f32 v40, vcc_lo, v18, 0x437f0000, v18
	v_fma_f32 v16, -v16, v36, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v32, v34, 1.0
	v_dual_fmac_f32 v15, 0x40020e17, v17 :: v_dual_fmac_f32 v34, v37, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v7, null, 0x437f0000, 0x437f0000, v15
	v_div_scale_f32 v26, s1, v15, 0x437f0000, v15
	v_div_scale_f32 v37, s4, v19, 0x437f0000, v19
	v_rcp_f32_e32 v23, v7
	v_mul_f32_e32 v42, v40, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v45, -v32, v42, v40
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v7, v23, 1.0
	v_fmac_f32_e32 v14, 0x40020e17, v17
	v_dual_fmac_f32 v42, v45, v34 :: v_dual_fmac_f32 v23, v30, v23
	v_rcp_f32_e32 v30, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, 0x437f0000, 0x437f0000, v14
	v_div_scale_f32 v25, s0, v14, 0x437f0000, v14
	v_rcp_f32_e32 v17, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v39, -v33, v30, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v39, v30
	v_div_scale_f32 v22, null, 0x437f0000, 0x437f0000, v21
	v_fma_f32 v29, -v6, v17, 1.0
	v_div_scale_f32 v31, s3, v21, 0x437f0000, v21
	v_rcp_f32_e32 v27, v22
	v_mul_f32_e32 v44, v37, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v29, v17
	v_mul_f32_e32 v35, v25, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v22, v27, 1.0
	v_fma_f32 v38, -v6, v35, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, v29, v27
	v_mul_f32_e32 v29, v26, v23
	v_mul_f32_e32 v39, v31, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v41, -v7, v29, v26
	v_fmac_f32_e32 v29, v41, v23
	v_fma_f32 v41, -v33, v44, v37
	v_fmac_f32_e32 v35, v38, v17
	v_fma_f32 v38, -v22, v39, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v7, -v7, v29, v26
	v_fmac_f32_e32 v44, v41, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v6, -v6, v35, v25
	v_fma_f32 v25, -v32, v42, v40
	v_fmac_f32_e32 v39, v38, v27
	v_fma_f32 v26, -v33, v44, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v25, v34, v42
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v22, -v22, v39, v31
	v_div_fmas_f32 v16, v16, v24, v36
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v6, v6, v17, v35
	v_div_fixup_f32 v17, v25, 0x437f0000, v18
	s_mov_b32 vcc_lo, s4
	v_div_fixup_f32 v16, v16, 0x437f0000, v20
	v_div_fmas_f32 v18, v26, v30, v44
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v6, v6, 0x437f0000, v14
	v_div_fmas_f32 v20, v22, v27, v39
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v17
	v_div_fixup_f32 v18, v18, 0x437f0000, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v20, v20, 0x437f0000, v21
	v_cndmask_b32_e32 v14, 1.0, v17, vcc_lo
	s_mov_b32 vcc_lo, s1
	v_div_fmas_f32 v7, v7, v23, v29
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v16
	v_div_fixup_f32 v7, v7, 0x437f0000, v15
	v_cndmask_b32_e32 v19, 1.0, v16, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v6
	v_cndmask_b32_e32 v21, 1.0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v17
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v18
	v_cndmask_b32_e32 v15, 1.0, v18, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e32 v16, 0, v19, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v20
	v_cndmask_b32_e32 v17, 1.0, v20, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e32 v6, 0, v21, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v7
	v_cndmask_b32_e32 v19, 1.0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v20
	v_cndmask_b32_e32 v17, 0, v17, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e32 v7, 0, v19, vcc_lo
	s_clause 0x1
	global_store_b32 v[8:9], v14, off
	global_store_b32 v[12:13], v15, off
	s_clause 0x1
	global_store_b32 v[10:11], v16, off
	global_store_b32 v[2:3], v17, off
	s_clause 0x1
	global_store_b32 v[0:1], v6, off
	global_store_b32 v[4:5], v7, off
.LBB1_2:                                ; %_Z17convertNV12ToRGBPIfEv10NV12Planesjjj9RGBPlanesIT_Ej.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel convertNV12ToRGB32FP
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	convertNV12ToRGB32FP, .Lfunc_end1-convertNV12ToRGB32FP
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1280
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           16
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           24
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           convertNV12ToRGB8P
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         convertNV12ToRGB8P.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           16
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           24
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           convertNV12ToRGB32FP
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         convertNV12ToRGB32FP.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
