
__global__ void mapping(double *point_cloud, 
const double *img1, const double *img2, 
const double *img3, const double *img4, 
const double *T,
const double *P1, const double *P2, const double *P3, const double *P4, 
const double *ratiox, const double *ratioy, const double *ratioz,
const int *img_width, const int *img_height)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;
    int idy = blockIdx.y*blockDim.y + threadIdx.y;
    int idz = threadIdx.z;
    int width = gridDim.x*blockDim.x;
    int height = gridDim.y*blockDim.y;
    
    int index = idz*width*height + idx*height + idy;
	
	//grid to coordinates
	double mx = idx*ratiox[0];
	double my = idy*ratioy[0];
	double mz = idz*ratioz[0];
	
	
	//world coordinates
	double x = T[0]*mx + T[4]*my + T[8]*mz + T[12];
	double y = T[1]*mx + T[5]*my + T[9]*mz + T[13];
	double z = mz;
	
	
	//image coordinates
	double u1 = P1[0]*x + P1[3]*y + P1[6]*z + P1[9];
	double v1 = P1[1]*x + P1[4]*y + P1[7]*z + P1[10];
	double norm1 = P1[2]*x + P1[5]*y + P1[8]*z + P1[11];
	u1/=norm1;
	v1/=norm1;
	
	double u2 = P2[0]*x + P2[3]*y + P2[6]*z + P2[9];
	double v2 = P2[1]*x + P2[4]*y + P2[7]*z + P2[10];
	double norm2 = P2[2]*x + P2[5]*y + P2[8]*z + P2[11];
	u2/=norm2;
	v2/=norm2;
	
	double u3 = P3[0]*x + P3[3]*y + P3[6]*z + P3[9];
	double v3 = P3[1]*x + P3[4]*y + P3[7]*z + P3[10];
	double norm3 = P3[2]*x + P3[5]*y + P3[8]*z + P3[11];
	u3/=norm3;
	v3/=norm3;
	
	double u4 = P4[0]*x + P4[3]*y + P4[6]*z + P4[9];
	double v4 = P4[1]*x + P4[4]*y + P4[7]*z + P4[10];
	double norm4 = P4[2]*x + P4[5]*y + P4[8]*z + P4[11];
	u4/=norm4;
	v4/=norm4;

	int u11 = (u1);
	int u22 = (u2);
	int u33 = (u3);
	int u44 = (u4);
	
	int v11 = (v1);
	int v22 = (v2);
	int v33 = (v3);
	int v44 = (v4);
	
	int final_width = img_width[0];
	int final_height = img_height[0];
	
	int seen_record[4] = {0};
	
	//decide the point cloud
	if((u11>0)&&(u11<final_width)&&(v11>0)&&(v11<final_height))
		seen_record[0] = 1;
	
	if((u22>0)&&(u22<final_width)&&(v22>0)&&(v22<final_height))
		seen_record[1] = 1;
		
	if((u33>0)&&(u33<final_width)&&(v33>0)&&(v33<final_height))
		seen_record[2] = 1;
	
	if((u44>0)&&(u44<final_width)&&(v44>0)&&(v44<final_height))
		seen_record[3] = 1;	
		
	int sum = 0;
		
	if((seen_record[0]==1)&&(img1[u11*final_height+v11]!=0))
		++sum;
				
	if((seen_record[1]==1)&&(img2[u22*final_height+v22]!=0))
		++sum;
			
	if((seen_record[2]==1)&&(img3[u33*final_height+v33]!=0))
		++sum;
			
	if((seen_record[3]==1)&&(img4[u44*final_height+v44]!=0))
		++sum;	
	
	point_cloud[index] = 0;
	if(sum>=3)
	{
		point_cloud[index] = 1;
	}
}
	.file	"tmpxft_00346ebc_00000000-6_visual_hull_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.type	_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, @function
_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	352(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	360(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	368(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	136(%rsp)
	.cfi_def_cfa_offset 344
	leaq	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 352
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L2:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, .-_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.globl	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.type	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, @function
_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_PdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.cfi_endproc
.LFE2033:
	.size	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, .-_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

__global__ void mapping(double *point_cloud, 
const double *img1, const double *img2, 
const double *img3, const double *img4, 
const double *T,
const double *P1, const double *P2, const double *P3, const double *P4, 
const double *ratiox, const double *ratioy, const double *ratioz,
const int *img_width, const int *img_height)
{
    int idx = blockIdx.x*blockDim.x + threadIdx.x;
    int idy = blockIdx.y*blockDim.y + threadIdx.y;
    int idz = threadIdx.z;
    int width = gridDim.x*blockDim.x;
    int height = gridDim.y*blockDim.y;
    
    int index = idz*width*height + idx*height + idy;
	
	//grid to coordinates
	double mx = idx*ratiox[0];
	double my = idy*ratioy[0];
	double mz = idz*ratioz[0];
	
	
	//world coordinates
	double x = T[0]*mx + T[4]*my + T[8]*mz + T[12];
	double y = T[1]*mx + T[5]*my + T[9]*mz + T[13];
	double z = mz;
	
	
	//image coordinates
	double u1 = P1[0]*x + P1[3]*y + P1[6]*z + P1[9];
	double v1 = P1[1]*x + P1[4]*y + P1[7]*z + P1[10];
	double norm1 = P1[2]*x + P1[5]*y + P1[8]*z + P1[11];
	u1/=norm1;
	v1/=norm1;
	
	double u2 = P2[0]*x + P2[3]*y + P2[6]*z + P2[9];
	double v2 = P2[1]*x + P2[4]*y + P2[7]*z + P2[10];
	double norm2 = P2[2]*x + P2[5]*y + P2[8]*z + P2[11];
	u2/=norm2;
	v2/=norm2;
	
	double u3 = P3[0]*x + P3[3]*y + P3[6]*z + P3[9];
	double v3 = P3[1]*x + P3[4]*y + P3[7]*z + P3[10];
	double norm3 = P3[2]*x + P3[5]*y + P3[8]*z + P3[11];
	u3/=norm3;
	v3/=norm3;
	
	double u4 = P4[0]*x + P4[3]*y + P4[6]*z + P4[9];
	double v4 = P4[1]*x + P4[4]*y + P4[7]*z + P4[10];
	double norm4 = P4[2]*x + P4[5]*y + P4[8]*z + P4[11];
	u4/=norm4;
	v4/=norm4;

	int u11 = (u1);
	int u22 = (u2);
	int u33 = (u3);
	int u44 = (u4);
	
	int v11 = (v1);
	int v22 = (v2);
	int v33 = (v3);
	int v44 = (v4);
	
	int final_width = img_width[0];
	int final_height = img_height[0];
	
	int seen_record[4] = {0};
	
	//decide the point cloud
	if((u11>0)&&(u11<final_width)&&(v11>0)&&(v11<final_height))
		seen_record[0] = 1;
	
	if((u22>0)&&(u22<final_width)&&(v22>0)&&(v22<final_height))
		seen_record[1] = 1;
		
	if((u33>0)&&(u33<final_width)&&(v33>0)&&(v33<final_height))
		seen_record[2] = 1;
	
	if((u44>0)&&(u44<final_width)&&(v44>0)&&(v44<final_height))
		seen_record[3] = 1;	
		
	int sum = 0;
		
	if((seen_record[0]==1)&&(img1[u11*final_height+v11]!=0))
		++sum;
				
	if((seen_record[1]==1)&&(img2[u22*final_height+v22]!=0))
		++sum;
			
	if((seen_record[2]==1)&&(img3[u33*final_height+v33]!=0))
		++sum;
			
	if((seen_record[3]==1)&&(img4[u44*final_height+v44]!=0))
		++sum;	
	
	point_cloud[index] = 0;
	if(sum>=3)
	{
		point_cloud[index] = 1;
	}
}
	.text
	.file	"visual_hull_test.hip"
	.globl	_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_ # -- Begin function _Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.type	_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_,@function
_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_: # @_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, .Lfunc_end0-_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_,@object # @_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.section	.rodata,"a",@progbits
	.globl	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.p2align	3, 0x0
_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_:
	.quad	_Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.size	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_"
	.size	.L__unnamed_1, 55

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_ ; -- Begin function _Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.globl	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
	.p2align	8
	.type	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_,@function
_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_: ; @_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x84
	v_bfe_u32 v3, v0, 10, 10
	s_load_b256 s[68:75], s[0:1], 0x40
	v_and_b32_e32 v6, 0x3ff, v0
	v_bfe_u32 v9, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s33, s2, 0xffff
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_load_b64 s[20:21], s[74:75], 0x0
	v_mad_u64_u32 v[2:3], null, s14, s33, v[6:7]
	s_load_b512 s[4:19], s[0:1], 0x0
	s_load_b64 s[34:35], s[72:73], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b128 s[28:31], s[14:15], 0x20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[4:5], v1
	v_cvt_f64_i32_e32 v[6:7], v2
	s_load_b128 s[36:39], s[14:15], 0x40
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], s[20:21], v[4:5]
	s_load_b256 s[20:27], s[0:1], 0x60
	v_cvt_f64_i32_e32 v[3:4], v9
	v_mul_f64 v[5:6], s[34:35], v[6:7]
	s_waitcnt lgkmcnt(0)
	s_load_b64 s[20:21], s[20:21], 0x0
	s_load_b128 s[40:43], s[14:15], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f64 v[7:8], v[10:11], s[30:31]
	v_mul_f64 v[10:11], s[28:29], v[10:11]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[3:4], s[20:21], v[3:4]
	s_load_b128 s[28:31], s[14:15], 0x60
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[7:8], v[5:6], s[42:43], v[7:8]
	v_fma_f64 v[5:6], v[5:6], s[40:41], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[3:4], s[38:39], v[7:8]
	v_fma_f64 v[5:6], v[3:4], s[36:37], v[5:6]
	s_load_b512 s[36:51], s[16:17], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], s[30:31], v[7:8]
	v_add_f64 v[5:6], s[28:29], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], s[42:43], v[7:8]
	v_mul_f64 v[12:13], v[7:8], s[46:47]
	v_mul_f64 v[14:15], v[7:8], s[44:45]
	v_fma_f64 v[10:11], v[5:6], s[36:37], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[5:6], s[40:41], v[12:13]
	v_fma_f64 v[14:15], v[5:6], s[38:39], v[14:15]
	s_load_b256 s[36:43], s[16:17], 0x40
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[3:4], s[48:49], v[10:11]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[12:13], v[3:4], s[36:37], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[3:4], s[50:51], v[14:15]
	v_add_f64 v[10:11], s[38:39], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], s[42:43], v[12:13]
	v_add_f64 v[14:15], s[40:41], v[14:15]
	s_load_b32 s35, s[22:23], 0x0
	s_load_b32 s34, s[24:25], 0x0
	s_load_b64 s[14:15], s[0:1], 0x78
	s_clause 0x1
	s_load_b512 s[52:67], s[18:19], 0x0
	s_load_b256 s[84:91], s[18:19], 0x40
	s_clause 0x1
	s_load_b512 s[36:51], s[68:69], 0x0
	s_load_b256 s[76:83], s[68:69], 0x40
	s_clause 0x1
	s_load_b512 s[16:31], s[70:71], 0x0
	s_load_b256 s[68:75], s[70:71], 0x40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], v[10:11]
	v_div_scale_f64 v[18:19], null, v[12:13], v[12:13], v[14:15]
	v_div_scale_f64 v[28:29], vcc_lo, v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[20:21], v[16:17]
	v_rcp_f64_e32 v[22:23], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
	v_fma_f64 v[26:27], -v[18:19], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	v_div_scale_f64 v[24:25], s2, v[14:15], v[12:13], v[14:15]
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[28:29], v[20:21]
	v_mul_f64 v[30:31], v[24:25], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[16:17], v[26:27], v[28:29]
	v_fma_f64 v[18:19], -v[18:19], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[26:27]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[18:19], v[18:19], v[22:23], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[10:11], v[16:17], v[12:13], v[10:11]
	v_div_fixup_f64 v[12:13], v[18:19], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v11, v[10:11]
	v_mov_b32_e32 v10, 0
	v_cvt_i32_f64_e32 v0, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0, v11
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s35, v11
	v_cmp_lt_i32_e64 s1, 0, v0
	v_cmp_gt_i32_e64 s2, s34, v0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.1:
	v_mad_u64_u32 v[12:13], null, s34, v11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_neq_f64_e32 vcc_lo, 0, v[10:11]
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s1, vcc_lo
; %bb.2:
	v_mov_b32_e32 v10, 1
; %bb.3:                                ; %Flow280
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[11:12], v[7:8], s[58:59]
	v_mul_f64 v[13:14], v[7:8], s[62:63]
	v_mul_f64 v[15:16], v[7:8], s[60:61]
	v_fma_f64 v[11:12], v[5:6], s[52:53], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[5:6], s[56:57], v[13:14]
	v_fma_f64 v[15:16], v[5:6], s[54:55], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[3:4], s[64:65], v[11:12]
	v_fma_f64 v[13:14], v[3:4], s[84:85], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[3:4], s[66:67], v[15:16]
	v_add_f64 v[11:12], s[86:87], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], s[90:91], v[13:14]
	v_add_f64 v[15:16], s[88:89], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, v[13:14], v[13:14], v[11:12]
	v_div_scale_f64 v[19:20], null, v[13:14], v[13:14], v[15:16]
	v_div_scale_f64 v[29:30], vcc_lo, v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[21:22], v[17:18]
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_div_scale_f64 v[25:26], s0, v[15:16], v[13:14], v[15:16]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], -v[17:18], v[27:28], v[29:30]
	v_fma_f64 v[19:20], -v[19:20], v[31:32], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[17:18], v[17:18], v[21:22], v[27:28]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[11:12], v[17:18], v[13:14], v[11:12]
	v_div_fixup_f64 v[13:14], v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v11, v[11:12]
	v_cvt_i32_f64_e32 v0, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0, v11
	v_cmp_gt_i32_e64 s0, s35, v11
	v_cmp_lt_i32_e64 s1, 0, v0
	v_cmp_gt_i32_e64 s2, s34, v0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_8
; %bb.5:
	v_mad_u64_u32 v[12:13], null, s34, v11, v[0:1]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[11:12], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s8, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[11:12]
; %bb.6:
	v_add_nc_u32_e32 v10, 1, v10
; %bb.7:                                ; %Flow279
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_8:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[11:12], v[7:8], s[42:43]
	v_mul_f64 v[13:14], v[7:8], s[46:47]
	v_mul_f64 v[15:16], v[7:8], s[44:45]
	v_fma_f64 v[11:12], v[5:6], s[36:37], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[5:6], s[40:41], v[13:14]
	v_fma_f64 v[15:16], v[5:6], s[38:39], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[3:4], s[48:49], v[11:12]
	v_fma_f64 v[13:14], v[3:4], s[76:77], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[3:4], s[50:51], v[15:16]
	v_add_f64 v[11:12], s[78:79], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], s[82:83], v[13:14]
	v_add_f64 v[15:16], s[80:81], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[17:18], null, v[13:14], v[13:14], v[11:12]
	v_div_scale_f64 v[19:20], null, v[13:14], v[13:14], v[15:16]
	v_div_scale_f64 v[29:30], vcc_lo, v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[21:22], v[17:18]
	v_rcp_f64_e32 v[23:24], v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[19:20], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_div_scale_f64 v[25:26], s0, v[15:16], v[13:14], v[15:16]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], -v[17:18], v[27:28], v[29:30]
	v_fma_f64 v[19:20], -v[19:20], v[31:32], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[17:18], v[17:18], v[21:22], v[27:28]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[19:20], v[19:20], v[23:24], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[11:12], v[17:18], v[13:14], v[11:12]
	v_div_fixup_f64 v[13:14], v[19:20], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v11, v[11:12]
	v_cvt_i32_f64_e32 v0, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0, v11
	v_cmp_gt_i32_e64 s0, s35, v11
	v_cmp_lt_i32_e64 s1, 0, v0
	v_cmp_gt_i32_e64 s2, s34, v0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_12
; %bb.9:
	v_mad_u64_u32 v[12:13], null, s34, v11, v[0:1]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[11:12], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s10, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[11:12]
; %bb.10:
	v_add_nc_u32_e32 v10, 1, v10
; %bb.11:                               ; %Flow278
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_12:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[11:12], v[7:8], s[22:23]
	v_mul_f64 v[13:14], v[7:8], s[26:27]
	v_mul_f64 v[7:8], v[7:8], s[24:25]
	v_fma_f64 v[11:12], v[5:6], s[16:17], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[5:6], s[20:21], v[13:14]
	v_fma_f64 v[5:6], v[5:6], s[18:19], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[7:8], v[3:4], s[28:29], v[11:12]
	v_fma_f64 v[11:12], v[3:4], s[68:69], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[3:4], s[30:31], v[5:6]
	v_add_f64 v[5:6], s[70:71], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], s[74:75], v[11:12]
	v_add_f64 v[3:4], s[72:73], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[5:6]
	v_div_scale_f64 v[13:14], null, v[7:8], v[7:8], v[3:4]
	v_div_scale_f64 v[23:24], vcc_lo, v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[15:16], v[11:12]
	v_rcp_f64_e32 v[17:18], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	v_div_scale_f64 v[19:20], s0, v[3:4], v[7:8], v[3:4]
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[21:22], v[23:24], v[15:16]
	v_mul_f64 v[25:26], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], -v[11:12], v[21:22], v[23:24]
	v_fma_f64 v[13:14], -v[13:14], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[21:22]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[13:14], v[13:14], v[17:18], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[5:6], v[11:12], v[7:8], v[5:6]
	v_div_fixup_f64 v[7:8], v[13:14], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v3, v[5:6]
	v_cvt_i32_f64_e32 v0, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_i32_e32 vcc_lo, 0, v3
	v_cmp_gt_i32_e64 s0, s35, v3
	v_cmp_lt_i32_e64 s1, 0, v0
	v_cmp_gt_i32_e64 s2, s34, v0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_16
; %bb.13:
	v_mad_u64_u32 v[4:5], null, s34, v3, v[0:1]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[3:4], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s12, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f64_e32 0, v[3:4]
; %bb.14:
	v_add_nc_u32_e32 v10, 1, v10
; %bb.15:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_16:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_lo_u32 v0, s14, v9
	s_mul_i32 s0, s15, s3
	v_cmp_lt_u32_e32 vcc_lo, 2, v10
	v_mad_u64_u32 v[3:4], null, v0, s33, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, s0, v3, v[1:2]
	v_cndmask_b32_e64 v3, 0, 0x3ff00000, vcc_lo
	v_mov_b32_e32 v2, 0
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 92
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_, .Lfunc_end0-_Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2428
; NumSgprs: 94
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 94
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_
    .private_segment_fixed_size: 0
    .sgpr_count:     94
    .sgpr_spill_count: 0
    .symbol:         _Z7mappingPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_PKiS3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
