/*
    Mmult application 
    Written by: Riccardo Fontanini
    Start date: 3 May 2018
    Note:  This program is created to multiply 3 matrix
     R O T A S
     O P E R A
     T E N E T
     A R E P O
     S A T O R

*/
#include <stdio.h>

#ifndef N
  #define N 1024
#endif

#ifndef BLOCKDIM
  #define BLOCKDIM 32
#endif


void __global__ shared_mmult(int *A, int *B, int *C) {
  __shared__ int s_A [BLOCKDIM * BLOCKDIM];
  __shared__ int s_B [BLOCKDIM * BLOCKDIM];
  int value = 0;
  int block_index = threadIdx.y * BLOCKDIM + threadIdx.x;
  int xa, ya, xb, yb = 0;
  ya = blockIdx.y;
  xb = blockIdx.x;
  /*
  se matrice 3*3 e multipla di 32
  (blockIdx.y; blockIdx.c) == (0, 0) -> siamo nel blocco C00 = A00 * B00 + A01 * B10 + A02 * B20
  (blockIdx.y; blockIdx.x) == (0, 1) -> siamo nel blocco C01 = A00 * B01 + A01 * B11 + A02 * B21
  (blockIdx.y; blockIdx.x) == (1, 0) -> siamo nel blocco C10 = A10 * B00 + A11 * B10 + A12 * B20
  (blockIdx.y; blockIdx.x) == (1, 1) -> siamo nel blocco C11 = A10 * B01 + A11 * B11 + A12 * B21
  e così via...

  */

  for(int i = 0; i < N/BLOCKDIM; i++) {
    //copy global memory Axaya and Bxbyb to shared memory
    xa = i;
    yb = i;
    *(s_A + block_index) = *(A + ( (ya * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + xa * BLOCKDIM));
    *(s_B + block_index) = *(B + ( (yb * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + xb * BLOCKDIM));

    if(blockIdx.y * BLOCKDIM + threadIdx.y >= N || blockIdx.x * BLOCKDIM + threadIdx.x >= N)
      return;

    __syncthreads();

    for (int k = 0; k < BLOCKDIM; k++)
      value += *(s_A + threadIdx.y * BLOCKDIM + k) * *(s_B + k * BLOCKDIM + threadIdx.x);

    __syncthreads();
  }

  *(C + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM)) = value;

}

void __global__ simple_mmult(int *A, int *B, int *C) {
  int value = 0;
  for (int k = 0; k < N; k++)
    value += *(A + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (k + blockIdx.x * BLOCKDIM) ) * *(B + ( (blockIdx.y * BLOCKDIM) + k ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM));
  *(C + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM)) =  value;

}


int main () {

  int NN = N * N;
  int *A, *B, *C;
  cudaMallocManaged (&A, NN * sizeof (int));
  cudaMallocManaged (&B, NN * sizeof (int));
  cudaMallocManaged (&C, NN * sizeof (int));
  cudaDeviceSynchronize();
  fprintf(stderr, "PRIma\n");
  int *ptrA = A;
  int *ptrB = B;
  int *ptrC = C;
  for (int i = 0; i < N; i++)
    for (int j = 0; j < N; j++, ptrA++, ptrB++, ptrC++) {
      *ptrA = i * N + j;
      *ptrB = *ptrC = 0;
      if (i == j) *ptrB = 1;
    }
  cudaDeviceSynchronize();
  fprintf(stderr, "seconda\n");

  fprintf (stderr, "La visualizzazione delle matrici è stata limitata a 10x10\n");
  fprintf (stderr, "Matrix A\n");
  ptrA = A;
  for (int i = 0; i < 10; i++) {
    ptrA = A + i * N;
    for (int j = 0; j < 10; j++, ptrA++)
      fprintf (stderr, "%2d ", *ptrA);
    fprintf (stderr, "\n");
  }
  fprintf (stderr, "\n\n\n");

  fprintf (stderr, "Matrix B\n");
  ptrB = B;
  for (int i = 0; i < 10; i++) {
    ptrB = B + i * N;
    for (int j = 0; j < 10; j++, ptrB++)
      fprintf (stderr, "%2d ", *ptrB);
    fprintf (stderr, "\n");
  }
  fprintf (stderr, "\n\n\n");
  cudaDeviceSynchronize ();
  dim3 blocksPerGrid (N/BLOCKDIM, N/BLOCKDIM);
  dim3 threadsPerBlock (BLOCKDIM, BLOCKDIM);
  #ifdef SIMPLE
    simple_mmult <<< blocksPerGrid, threadsPerBlock>>> (A, B, C);
    cudaDeviceSynchronize ();
    ptrC = C;
    fprintf (stderr, "Matrix C SIMPLE (not shared memory)\n");
    for (int i = 0; i < 10; i++) {
      ptrC = C + i * N;
      for (int j = 0; j < 10; j++, ptrC++)
        fprintf (stderr, "%2d ", *ptrC);
      fprintf (stderr, "\n");
    }
    fprintf (stderr, "\n\n\n");
  #endif
  int dimSHARED = 3 * ( BLOCKDIM * BLOCKDIM * sizeof(int));
  shared_mmult <<< blocksPerGrid, threadsPerBlock>>> (A, B, C);
  cudaDeviceSynchronize ();

  fprintf (stderr, "Matrix C Shared memory\n");
  ptrC = C;
  for (int i = 0; i < 10; i++) {
    ptrC = C + i * N;
    for (int j = 0; j < 10; j++, ptrC++)
      fprintf (stderr, "%2d ", *ptrC);
    fprintf (stderr, "\n");
  }

  return 0;

}

	.file	"tmpxft_002c9192_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_
	.type	_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_, @function
_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12shared_mmultPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_, .-_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_
	.globl	_Z12shared_mmultPiS_S_
	.type	_Z12shared_mmultPiS_S_, @function
_Z12shared_mmultPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z12shared_mmultPiS_S_, .-_Z12shared_mmultPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"PRIma\n"
.LC1:
	.string	"seconda\n"
.LC2:
	.string	"La visualizzazione delle matrici \303\250 stata limitata a 10x10\n"
.LC3:
	.string	"Matrix A\n"
.LC4:
	.string	"%2d "
.LC5:
	.string	"\n"
.LC6:
	.string	"\n\n\n"
.LC7:
	.string	"Matrix B\n"
.LC8:
	.string	"Matrix C Shared memory\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1, %edx
	movl	$4194304, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$4194304, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$4194304, %esi
	call	cudaMallocManaged@PLT
	call	cudaDeviceSynchronize@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC0(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	8(%rsp), %r8
	xorl	%ecx, %ecx
	xorl	%edx, %edx
	movq	16(%rsp), %r10
	movq	24(%rsp), %rbx
.L9:
	movl	%edx, %esi
	leaq	(%rbx,%rcx), %r11
	leaq	(%r10,%rcx), %r9
	xorl	%eax, %eax
	leaq	(%r8,%rcx), %rdi
	sall	$10, %esi
.L10:
	leal	(%rsi,%rax), %ebp
	movl	%ebp, (%rdi,%rax,4)
	xorl	%ebp, %ebp
	movl	%ebp, (%r11,%rax,4)
	xorl	%ebp, %ebp
	cmpl	%eax, %edx
	sete	%bpl
	movl	%ebp, (%r9,%rax,4)
	incq	%rax
	cmpq	$1024, %rax
	jne	.L10
	incl	%edx
	addq	$4096, %rcx
	cmpl	$1024, %edx
	jne	.L9
	call	cudaDeviceSynchronize@PLT
	movq	stderr(%rip), %rdi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	leaq	.LC4(%rip), %r13
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L13:
	movq	8(%rsp), %r12
	xorl	%ebp, %ebp
	addq	%rbx, %r12
.L12:
	movl	(%r12,%rbp), %ecx
	movq	stderr(%rip), %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	addq	$4, %rbp
	call	__fprintf_chk@PLT
	cmpq	$40, %rbp
	jne	.L12
	movq	stderr(%rip), %rdi
	leaq	.LC5(%rip), %r12
	movl	$2, %esi
	xorl	%eax, %eax
	movq	%r12, %rdx
	addq	$4096, %rbx
	call	__fprintf_chk@PLT
	cmpq	$40960, %rbx
	jne	.L13
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	leaq	.LC6(%rip), %r14
	movq	%r14, %rdx
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC7(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L15:
	movq	16(%rsp), %r15
	xorl	%ebp, %ebp
	addq	%rbx, %r15
.L14:
	movl	(%r15,%rbp), %ecx
	movq	stderr(%rip), %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	addq	$4, %rbp
	call	__fprintf_chk@PLT
	cmpq	$40, %rbp
	jne	.L14
	movq	stderr(%rip), %rdi
	movq	%r12, %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	addq	$4096, %rbx
	call	__fprintf_chk@PLT
	cmpq	$40960, %rbx
	jne	.L15
	movq	stderr(%rip), %rdi
	movq	%r14, %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$137438953504, %rdi
	movl	$1, %esi
	movl	$1, 40(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z36__device_stub__Z12shared_mmultPiS_S_PiS_S_
.L16:
	call	cudaDeviceSynchronize@PLT
	movq	stderr(%rip), %rdi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	leaq	.LC8(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
.L18:
	movq	24(%rsp), %r14
	xorl	%ebp, %ebp
	addq	%rbx, %r14
.L17:
	movl	(%r14,%rbp), %ecx
	movq	stderr(%rip), %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	addq	$4, %rbp
	call	__fprintf_chk@PLT
	cmpq	$40, %rbp
	jne	.L17
	movq	stderr(%rip), %rdi
	movq	%r12, %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	addq	$4096, %rbx
	call	__fprintf_chk@PLT
	cmpq	$40960, %rbx
	jne	.L18
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_
	.type	_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_, @function
_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12simple_mmultPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L28:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_, .-_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_
	.globl	_Z12simple_mmultPiS_S_
	.type	_Z12simple_mmultPiS_S_, @function
_Z12simple_mmultPiS_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12simple_mmultPiS_S_PiS_S_
	.cfi_endproc
.LFE2055:
	.size	_Z12simple_mmultPiS_S_, .-_Z12simple_mmultPiS_S_
	.section	.rodata.str1.1
.LC9:
	.string	"_Z12simple_mmultPiS_S_"
.LC10:
	.string	"_Z12shared_mmultPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12simple_mmultPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12shared_mmultPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
    Mmult application 
    Written by: Riccardo Fontanini
    Start date: 3 May 2018
    Note:  This program is created to multiply 3 matrix
     R O T A S
     O P E R A
     T E N E T
     A R E P O
     S A T O R

*/

#include <hip/hip_runtime.h>
#include <stdio.h>

#ifndef N
  #define N 1024
#endif

#ifndef BLOCKDIM
  #define BLOCKDIM 32
#endif


void __global__ shared_mmult(int *A, int *B, int *C) {
  __shared__ int s_A [BLOCKDIM * BLOCKDIM];
  __shared__ int s_B [BLOCKDIM * BLOCKDIM];
  int value = 0;
  int block_index = threadIdx.y * BLOCKDIM + threadIdx.x;
  int xa, ya, xb, yb = 0;
  ya = blockIdx.y;
  xb = blockIdx.x;
  /*
  se matrice 3*3 e multipla di 32
  (blockIdx.y; blockIdx.c) == (0, 0) -> siamo nel blocco C00 = A00 * B00 + A01 * B10 + A02 * B20
  (blockIdx.y; blockIdx.x) == (0, 1) -> siamo nel blocco C01 = A00 * B01 + A01 * B11 + A02 * B21
  (blockIdx.y; blockIdx.x) == (1, 0) -> siamo nel blocco C10 = A10 * B00 + A11 * B10 + A12 * B20
  (blockIdx.y; blockIdx.x) == (1, 1) -> siamo nel blocco C11 = A10 * B01 + A11 * B11 + A12 * B21
  e così via...

  */

  for(int i = 0; i < N/BLOCKDIM; i++) {
    //copy global memory Axaya and Bxbyb to shared memory
    xa = i;
    yb = i;
    *(s_A + block_index) = *(A + ( (ya * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + xa * BLOCKDIM));
    *(s_B + block_index) = *(B + ( (yb * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + xb * BLOCKDIM));

    if(blockIdx.y * BLOCKDIM + threadIdx.y >= N || blockIdx.x * BLOCKDIM + threadIdx.x >= N)
      return;

    __syncthreads();

    for (int k = 0; k < BLOCKDIM; k++)
      value += *(s_A + threadIdx.y * BLOCKDIM + k) * *(s_B + k * BLOCKDIM + threadIdx.x);

    __syncthreads();
  }

  *(C + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM)) = value;

}

void __global__ simple_mmult(int *A, int *B, int *C) {
  int value = 0;
  for (int k = 0; k < N; k++)
    value += *(A + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (k + blockIdx.x * BLOCKDIM) ) * *(B + ( (blockIdx.y * BLOCKDIM) + k ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM));
  *(C + ( (blockIdx.y * BLOCKDIM) + threadIdx.y ) * N + (threadIdx.x + blockIdx.x * BLOCKDIM)) =  value;

}


int main () {

  int NN = N * N;
  int *A, *B, *C;
  hipMallocManaged (&A, NN * sizeof (int));
  hipMallocManaged (&B, NN * sizeof (int));
  hipMallocManaged (&C, NN * sizeof (int));
  hipDeviceSynchronize();
  fprintf(stderr, "PRIma\n");
  int *ptrA = A;
  int *ptrB = B;
  int *ptrC = C;
  for (int i = 0; i < N; i++)
    for (int j = 0; j < N; j++, ptrA++, ptrB++, ptrC++) {
      *ptrA = i * N + j;
      *ptrB = *ptrC = 0;
      if (i == j) *ptrB = 1;
    }
  hipDeviceSynchronize();
  fprintf(stderr, "seconda\n");

  fprintf (stderr, "La visualizzazione delle matrici è stata limitata a 10x10\n");
  fprintf (stderr, "Matrix A\n");
  ptrA = A;
  for (int i = 0; i < 10; i++) {
    ptrA = A + i * N;
    for (int j = 0; j < 10; j++, ptrA++)
      fprintf (stderr, "%2d ", *ptrA);
    fprintf (stderr, "\n");
  }
  fprintf (stderr, "\n\n\n");

  fprintf (stderr, "Matrix B\n");
  ptrB = B;
  for (int i = 0; i < 10; i++) {
    ptrB = B + i * N;
    for (int j = 0; j < 10; j++, ptrB++)
      fprintf (stderr, "%2d ", *ptrB);
    fprintf (stderr, "\n");
  }
  fprintf (stderr, "\n\n\n");
  hipDeviceSynchronize ();
  dim3 blocksPerGrid (N/BLOCKDIM, N/BLOCKDIM);
  dim3 threadsPerBlock (BLOCKDIM, BLOCKDIM);
  #ifdef SIMPLE
    simple_mmult <<< blocksPerGrid, threadsPerBlock>>> (A, B, C);
    hipDeviceSynchronize ();
    ptrC = C;
    fprintf (stderr, "Matrix C SIMPLE (not shared memory)\n");
    for (int i = 0; i < 10; i++) {
      ptrC = C + i * N;
      for (int j = 0; j < 10; j++, ptrC++)
        fprintf (stderr, "%2d ", *ptrC);
      fprintf (stderr, "\n");
    }
    fprintf (stderr, "\n\n\n");
  #endif
  int dimSHARED = 3 * ( BLOCKDIM * BLOCKDIM * sizeof(int));
  shared_mmult <<< blocksPerGrid, threadsPerBlock>>> (A, B, C);
  hipDeviceSynchronize ();

  fprintf (stderr, "Matrix C Shared memory\n");
  ptrC = C;
  for (int i = 0; i < 10; i++) {
    ptrC = C + i * N;
    for (int j = 0; j < 10; j++, ptrC++)
      fprintf (stderr, "%2d ", *ptrC);
    fprintf (stderr, "\n");
  }

  return 0;

}

	.text
	.file	"main.hip"
	.globl	_Z27__device_stub__shared_mmultPiS_S_ # -- Begin function _Z27__device_stub__shared_mmultPiS_S_
	.type	_Z27__device_stub__shared_mmultPiS_S_,@function
_Z27__device_stub__shared_mmultPiS_S_:  # @_Z27__device_stub__shared_mmultPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12shared_mmultPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__shared_mmultPiS_S_, .Lfunc_end0-_Z27__device_stub__shared_mmultPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__simple_mmultPiS_S_ # -- Begin function _Z27__device_stub__simple_mmultPiS_S_
	.type	_Z27__device_stub__simple_mmultPiS_S_,@function
_Z27__device_stub__simple_mmultPiS_S_:  # @_Z27__device_stub__simple_mmultPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12simple_mmultPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__simple_mmultPiS_S_, .Lfunc_end1-_Z27__device_stub__simple_mmultPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	16(%rsp), %rbx
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %r14
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r14, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %r15
	movl	$4194304, %esi                  # imm = 0x400000
	movq	%r15, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	callq	hipDeviceSynchronize
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$6, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	(%rbx), %rax
	movq	(%r14), %rcx
	xorl	%edx, %edx
	movq	(%r15), %rsi
	movl	$1024, %edi                     # imm = 0x400
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB2_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	movl	%edx, %r11d
	xorl	%r10d, %r10d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r11d, (%rax,%r10)
	movl	$0, (%rsi,%r10)
	xorl	%ebx, %ebx
	cmpl	%r10d, %r8d
	sete	%bl
	movl	%ebx, (%rcx,%r10)
	addq	$4, %r10
	incl	%r11d
	cmpl	$4096, %r10d                    # imm = 0x1000
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incl	%r9d
	addq	%r10, %rax
	addq	%r10, %rcx
	addq	%r10, %rsi
	addq	$4, %r8
	addl	%edi, %edx
	cmpl	%edi, %r9d
	jne	.LBB2_1
# %bb.4:
	callq	hipDeviceSynchronize
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$8, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$59, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	stderr(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$9, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_5:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movq	16(%rsp), %r15
	addq	%rbx, %r15
	xorl	%r12d, %r12d
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	stderr(%rip), %rdi
	movl	(%r15,%r12,4), %edx
	movl	$.L.str.4, %esi
	xorl	%eax, %eax
	callq	fprintf
	incq	%r12
	cmpl	$10, %r12d
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	movq	stderr(%rip), %rsi
	movl	$10, %edi
	callq	fputc@PLT
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$10, %r14
	jne	.LBB2_5
# %bb.8:
	movq	stderr(%rip), %rcx
	movl	$.L.str.6, %edi
	movl	$3, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	stderr(%rip), %rcx
	movl	$.L.str.7, %edi
	movl	$9, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_9:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_10 Depth 2
	movq	8(%rsp), %r15
	addq	%rbx, %r15
	xorl	%r12d, %r12d
.LBB2_10:                               #   Parent Loop BB2_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	stderr(%rip), %rdi
	movl	(%r15,%r12,4), %edx
	movl	$.L.str.4, %esi
	xorl	%eax, %eax
	callq	fprintf
	incq	%r12
	cmpl	$10, %r12d
	jne	.LBB2_10
# %bb.11:                               #   in Loop: Header=BB2_9 Depth=1
	movq	stderr(%rip), %rsi
	movl	$10, %edi
	callq	fputc@PLT
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$10, %r14
	jne	.LBB2_9
# %bb.12:
	movq	stderr(%rip), %rcx
	movl	$.L.str.6, %edi
	movl	$3, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	callq	hipDeviceSynchronize
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_14
# %bb.13:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	_Z27__device_stub__shared_mmultPiS_S_
.LBB2_14:
	callq	hipDeviceSynchronize
	movq	stderr(%rip), %rcx
	movl	$.L.str.8, %edi
	movl	$23, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_15:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_16 Depth 2
	movq	(%rsp), %r15
	addq	%rbx, %r15
	xorl	%r12d, %r12d
.LBB2_16:                               #   Parent Loop BB2_15 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	stderr(%rip), %rdi
	movl	(%r15,%r12,4), %edx
	movl	$.L.str.4, %esi
	xorl	%eax, %eax
	callq	fprintf
	incq	%r12
	cmpl	$10, %r12d
	jne	.LBB2_16
# %bb.17:                               #   in Loop: Header=BB2_15 Depth=1
	movq	stderr(%rip), %rsi
	movl	$10, %edi
	callq	fputc@PLT
	incq	%r14
	addq	$4096, %rbx                     # imm = 0x1000
	cmpq	$10, %r14
	jne	.LBB2_15
# %bb.18:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12shared_mmultPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12simple_mmultPiS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12shared_mmultPiS_S_,@object  # @_Z12shared_mmultPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z12shared_mmultPiS_S_
	.p2align	3, 0x0
_Z12shared_mmultPiS_S_:
	.quad	_Z27__device_stub__shared_mmultPiS_S_
	.size	_Z12shared_mmultPiS_S_, 8

	.type	_Z12simple_mmultPiS_S_,@object  # @_Z12simple_mmultPiS_S_
	.globl	_Z12simple_mmultPiS_S_
	.p2align	3, 0x0
_Z12simple_mmultPiS_S_:
	.quad	_Z27__device_stub__simple_mmultPiS_S_
	.size	_Z12simple_mmultPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"PRIma\n"
	.size	.L.str, 7

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"seconda\n"
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"La visualizzazione delle matrici \303\250 stata limitata a 10x10\n"
	.size	.L.str.2, 60

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Matrix A\n"
	.size	.L.str.3, 10

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%2d "
	.size	.L.str.4, 5

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\n\n\n"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Matrix B\n"
	.size	.L.str.7, 10

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Matrix C Shared memory\n"
	.size	.L.str.8, 24

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12shared_mmultPiS_S_"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12simple_mmultPiS_S_"
	.size	.L__unnamed_2, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__shared_mmultPiS_S_
	.addrsig_sym _Z27__device_stub__simple_mmultPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12shared_mmultPiS_S_
	.addrsig_sym _Z12simple_mmultPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12shared_mmultPiS_S_  ; -- Begin function _Z12shared_mmultPiS_S_
	.globl	_Z12shared_mmultPiS_S_
	.p2align	8
	.type	_Z12shared_mmultPiS_S_,@function
_Z12shared_mmultPiS_S_:                 ; @_Z12shared_mmultPiS_S_
; %bb.0:
	v_bfe_u32 v7, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v8, 0x3ff, v0
	v_lshlrev_b32_e32 v1, 10, v7
	v_lshlrev_b32_e32 v0, 5, v7
	v_lshl_add_u32 v6, s15, 5, v7
	v_lshlrev_b32_e32 v10, 7, v7
	v_lshl_or_b32 v11, v8, 2, 0x1000
	v_lshl_add_u32 v2, s15, 15, v1
	v_add_lshl_u32 v9, v0, v8, 2
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_lshl_add_u32 v2, s14, 5, v8
	v_add_nc_u32_e32 v12, 0x1000, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_or_b32_e32 v2, v6, v2
	v_mov_b32_e32 v6, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v13, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v15, s0, s6, v4
	v_cmp_gt_u32_e32 vcc_lo, 0x400, v2
	v_add_co_ci_u32_e64 v16, s0, s7, v5, s0
	s_mov_b32 s4, 0
                                        ; implicit-def: $sgpr5
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr6
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_lshl_b32 s0, s4, 5
	s_or_b32 s6, s6, exec_lo
	v_add_nc_u32_e32 v2, s0, v8
	s_or_b32 s7, s7, exec_lo
	v_lshlrev_b64 v[17:18], 2, v[2:3]
	v_add_lshl_u32 v2, s0, v7, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[19:20], 2, v[2:3]
	v_add_co_u32 v17, s0, v13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v18, s0, v14, v18, s0
	v_add_co_u32 v19, s0, v15, v19
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v20, s0, v16, v20, s0
	global_load_b32 v2, v[17:18], off
	global_load_b32 v17, v[19:20], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v12, v17
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v2, v11
	s_mov_b32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v17, s8, v10
	s_add_i32 s8, s8, 4
	ds_load_b32 v19, v2
	ds_load_b32 v20, v17
	v_add_nc_u32_e32 v2, 0x80, v2
	s_cmpk_eq_i32 s8, 0x80
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[17:18], null, v19, v20, v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v6, v17
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 32
	s_barrier
	s_cselect_b32 s8, -1, 0
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_and_not1_b32 s6, s6, exec_lo
	s_or_b32 s7, s7, s8
	buffer_gl0_inv
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s7
	s_or_b32 s1, s0, s1
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s5, s6, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s0, s5
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_1
; %bb.6:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s1
	s_xor_b32 s0, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:                                ; %.critedge
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_8:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12shared_mmultPiS_S_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12shared_mmultPiS_S_, .Lfunc_end0-_Z12shared_mmultPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12simple_mmultPiS_S_  ; -- Begin function _Z12simple_mmultPiS_S_
	.globl	_Z12simple_mmultPiS_S_
	.p2align	8
	.type	_Z12simple_mmultPiS_S_,@function
_Z12simple_mmultPiS_S_:                 ; @_Z12simple_mmultPiS_S_
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v1, 0xffc00, v0
	s_lshl_b32 s2, s15, 15
	v_and_b32_e32 v2, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s2, v1
	s_lshl_b32 s6, s14, 5
	s_mov_b32 s5, 0
	s_mov_b32 s7, 0
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_add_nc_u32_e32 v3, s6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v3, vcc_lo
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s4, s6, s7
	s_mov_b32 s3, s5
	s_lshl_b64 s[8:9], s[4:5], 2
	s_lshl_b64 s[10:11], s[2:3], 2
	v_add_co_u32 v5, vcc_lo, v7, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, v9, s10
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v10, vcc_lo
	s_add_i32 s7, s7, 1
	global_load_b32 v13, v[5:6], off
	global_load_b32 v11, v[11:12], off
	s_addk_i32 s2, 0x400
	s_cmpk_eq_i32 s7, 0x400
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[5:6], null, v11, v13, v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v5
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12simple_mmultPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12simple_mmultPiS_S_, .Lfunc_end1-_Z12simple_mmultPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12shared_mmultPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12shared_mmultPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12simple_mmultPiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12simple_mmultPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
