// #CSCS CUDA Training 
//
// #Example 2.1 - sum vectors, fix number of threads
//
// #Author Ugo Varetto
//
// #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the 
//        size of the output vector.
//
// #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the 
//             domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1)
//
// #Solution: 
//          Given the maximum number of threads to use compute number of blocks 
//          . total number of threads = T
//          . number of threads per block = Tb          
//          The number of blocks is = Tb div T; note that it doesn't matter if the integer division
//          gives a reminder since each GPU thread will iterate over multiple elements and ensure that
//          the entire domain is processed regardless of the number of threads concurrently executed
//
// #Code: typical flow:
//        1) compute launch grid configuration
//        2) allocate data on host(cpu) and device(gpu)
//        3) copy data from host to device
//        4) launch kernel
//        5) read data back
//        6) consume data (in this case print result)
//        7) free memory
//        
// #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2
//
// #Execution: ./sum-vectors-2 
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to 
//        cudaThreadSynchronize() is required to wait for the end of kernel execution from
//        a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
//        kernel execution is guaranteed to be terminated before data are copied   
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
//        are named with C++ convention and the syntax is checked by default against C++ grammar rules 
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and array size from the command line
//        and could be timed to investigate how performance is dependent on single/double precision
//        and thread block size


//#include <cuda_runtime.h> // automatically added by nvcc
#include <vector>
#include <iostream>
#include <iomanip>
#include <sstream>
#include <string>

typedef float real_t;

// In this case the number of GPU threads is smaller than the number of elements in the domain:
//  every iterates over multple elements to ensure than the entire domain is covered
__global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) {
    // compute current thread id
    int xIndex = blockIdx.x * blockDim.x + threadIdx.x;          
    // iterate over vector: grid can be smaller than vector, it is therefore
    // required that each thread iterate over more than one vector element
    while( xIndex < num_elements ) {
        out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ];
        xIndex += gridDim.x * blockDim.x;
    }
}


//------------------------------------------------------------------------------
int main( int , char**  ) {
    
    const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537
    const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5;
    const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes
    const int THREADS_PER_BLOCK = 32; //number of gpu threads per block
    const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; 
   
    // host allocated storage; use std vectors to simplify memory management
    // and initialization
    std::vector< real_t > v1  ( VECTOR_SIZE, 1.f ); //initialize all elements to 1
    std::vector< real_t > v2  ( VECTOR_SIZE, 2.f ); //initialize all elements to 2   
    std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0

    // gpu allocated storage
    real_t* dev_in1 = 0; //vector 1
    real_t* dev_in2 = 0; //vector 2
    real_t* dev_out = 0; //result value
    cudaMalloc( &dev_in1, SIZE );
    cudaMalloc( &dev_in2, SIZE );
    cudaMalloc( &dev_out, SIZE  );
    
    // copy data to GPU
    cudaMemcpy( dev_in1, &v1[ 0 ], SIZE, cudaMemcpyHostToDevice );
    cudaMemcpy( dev_in2, &v2[ 0 ], SIZE, cudaMemcpyHostToDevice );

    // execute kernel with num threads >= num elements
    sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE );
    
    // read back result
    cudaMemcpy( &vout[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost );
    
    // print first and last element of vector
    std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl;

    // free memory
    cudaFree( dev_in1 );
    cudaFree( dev_in2 );
    cudaFree( dev_out );

    return 0;
}

	.file	"tmpxft_0025eee1_00000000-6_002_1_sum-vectors.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4281:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4281:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm
	.type	_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, @function
_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm:
.LFB4303:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11sum_vectorsPKfS0_Pfm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4303:
	.size	_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm, .-_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm
	.globl	_Z11sum_vectorsPKfS0_Pfm
	.type	_Z11sum_vectorsPKfS0_Pfm, @function
_Z11sum_vectorsPKfS0_Pfm:
.LFB4304:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm
	.cfi_endproc
.LFE4304:
	.size	_Z11sum_vectorsPKfS0_Pfm, .-_Z11sum_vectorsPKfS0_Pfm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11sum_vectorsPKfS0_Pfm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4306:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z11sum_vectorsPKfS0_Pfm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4306:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.str1.1,"aMS",@progbits,1
.LC1:
	.string	"cannot create std::vector larger than max_size()"
	.section	.text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKfRKS0_,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.type	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_:
.LFB4627:
	.cfi_startproc
	endbr64
	movabsq	$2305843009213693951, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	pushq	%rcx
	.cfi_def_cfa_offset 48
	cmpq	%rsi, %rax
	jnb	.L11
	leaq	.LC1(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L11:
	movq	%rdx, %r13
	xorl	%edx, %edx
	movq	%rdi, %rbx
	movq	%rsi, %rbp
	movq	%rdx, (%rdi)
	leaq	0(,%rsi,4), %r12
	xorl	%eax, %eax
	movq	%rdx, 8(%rdi)
	movq	%rdx, 16(%rdi)
	testq	%rsi, %rsi
	je	.L12
	movq	%r12, %rdi
	call	_Znwm@PLT
.L12:
	addq	%rax, %r12
	movq	%rax, (%rbx)
	movq	%r12, 16(%rbx)
	testq	%rbp, %rbp
	je	.L13
	movss	0(%r13), %xmm0
.L14:
	cmpq	%rax, %r12
	je	.L13
	movss	%xmm0, (%rax)
	addq	$4, %rax
	jmp	.L14
.L13:
	movq	%rax, 8(%rbx)
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4627:
	.size	_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.weak	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
	.set	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
	.section	.text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
	.align 2
	.weak	_ZNSt6vectorIfSaIfEED2Ev
	.type	_ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4630:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	testq	%rax, %rax
	je	.L22
	movq	16(%rdi), %rsi
	movq	%rax, %rdi
	subq	%rax, %rsi
	jmp	_ZdlPvm@PLT
.L22:
	ret
	.cfi_endproc
.LFE4630:
	.size	_ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
	.weak	_ZNSt6vectorIfSaIfEED1Ev
	.set	_ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
	.section	.rodata.str1.1
.LC5:
	.string	"result: "
.LC6:
	.string	".."
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4278:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA4278
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$65537, %esi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$136, %rsp
	.cfi_def_cfa_offset 176
	leaq	72(%rsp), %r12
	leaq	96(%rsp), %r13
	leaq	48(%rsp), %rbp
	movq	%r12, %rcx
	leaq	36(%rsp), %rbx
	movq	%r13, %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	movq	%rbp, %rdi
	movl	$0x3f800000, 96(%rsp)
.LEHB0:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE0:
	movq	%rbx, %rcx
	movq	%r13, %rdx
	movl	$65537, %esi
	movq	%r12, %rdi
	movl	$0x40000000, 96(%rsp)
.LEHB1:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE1:
	leaq	24(%rsp), %rcx
	movq	%rbx, %rdx
	movl	$65537, %esi
	movq	%r13, %rdi
	movl	$0x00000000, 36(%rsp)
.LEHB2:
	call	_ZNSt6vectorIfSaIfEEC1EmRKfRKS0_
.LEHE2:
	xorl	%eax, %eax
	movq	%rsp, %rdi
	movl	$262148, %esi
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
.LEHB3:
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$262148, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$262148, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$262148, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$262148, %edx
	call	cudaMemcpy@PLT
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdx
	movl	$1, %esi
	movabsq	$4294967705, %rdi
	movl	$1, 44(%rsp)
	movq	%rdx, 36(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movq	16(%rsp), %rdx
	testl	%eax, %eax
	jne	.L25
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$65537, %ecx
	call	_Z38__device_stub__Z11sum_vectorsPKfS0_PfmPKfS0_Pfm
.L25:
	movq	96(%rsp), %rbx
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$262148, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	cvtss2sd	(%rbx), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	leaq	.LC6(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	104(%rsp), %rax
	cvtss2sd	-4(%rax), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
.LEHE3:
	movq	%r13, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	%rbp, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	jmp	.L34
.L33:
	endbr64
	movq	%rax, %rbx
.L26:
	movq	%r13, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L27
.L32:
	endbr64
	movq	%rax, %rbx
.L27:
	movq	%r12, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	jmp	.L28
.L31:
	endbr64
	movq	%rax, %rbx
.L28:
	movq	%rbp, %rdi
	call	_ZNSt6vectorIfSaIfEED1Ev
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L34
	movq	%rbx, %rdi
.LEHB4:
	call	_Unwind_Resume@PLT
.LEHE4:
.L34:
	call	__stack_chk_fail@PLT
.L30:
	addq	$136, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4278:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA4278:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE4278-.LLSDACSB4278
.LLSDACSB4278:
	.uleb128 .LEHB0-.LFB4278
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB4278
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L31-.LFB4278
	.uleb128 0
	.uleb128 .LEHB2-.LFB4278
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L32-.LFB4278
	.uleb128 0
	.uleb128 .LEHB3-.LFB4278
	.uleb128 .LEHE3-.LEHB3
	.uleb128 .L33-.LFB4278
	.uleb128 0
	.uleb128 .LEHB4-.LFB4278
	.uleb128 .LEHE4-.LEHB4
	.uleb128 0
	.uleb128 0
.LLSDACSE4278:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// #CSCS CUDA Training 
//
// #Example 2.1 - sum vectors, fix number of threads
//
// #Author Ugo Varetto
//
// #Goal: compute the scalar product of two 1D vectors using a number of threads lower than the 
//        size of the output vector.
//
// #Rationale: shows how to implement a kernel with a computation/memory configuration independent on the 
//             domain data layout; this is required in case the data is bigger than the computation grid (see exercise 1)
//
// #Solution: 
//          Given the maximum number of threads to use compute number of blocks 
//          . total number of threads = T
//          . number of threads per block = Tb          
//          The number of blocks is = Tb div T; note that it doesn't matter if the integer division
//          gives a reminder since each GPU thread will iterate over multiple elements and ensure that
//          the entire domain is processed regardless of the number of threads concurrently executed
//
// #Code: typical flow:
//        1) compute launch grid configuration
//        2) allocate data on host(cpu) and device(gpu)
//        3) copy data from host to device
//        4) launch kernel
//        5) read data back
//        6) consume data (in this case print result)
//        7) free memory
//        
// #Compilation: nvcc -arch=sm_13 2_1_sum-vectors.cu -o sum-vectors-2
//
// #Execution: ./sum-vectors-2 
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to 
//        cudaThreadSynchronize() is required to wait for the end of kernel execution from
//        a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
//        kernel execution is guaranteed to be terminated before data are copied   
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
//        are named with C++ convention and the syntax is checked by default against C++ grammar rules 
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and array size from the command line
//        and could be timed to investigate how performance is dependent on single/double precision
//        and thread block size


//#include <cuda_runtime.h> // automatically added by nvcc

#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <iomanip>
#include <sstream>
#include <string>

typedef float real_t;

// In this case the number of GPU threads is smaller than the number of elements in the domain:
//  every iterates over multple elements to ensure than the entire domain is covered
__global__ void sum_vectors( const real_t* v1, const real_t* v2, real_t* out, size_t num_elements ) {
    // compute current thread id
    int xIndex = blockIdx.x * blockDim.x + threadIdx.x;          
    // iterate over vector: grid can be smaller than vector, it is therefore
    // required that each thread iterate over more than one vector element
    while( xIndex < num_elements ) {
        out[ xIndex ] = v1[ xIndex ] + v2[ xIndex ];
        xIndex += gridDim.x * blockDim.x;
    }
}


//------------------------------------------------------------------------------
int main( int , char**  ) {
    
    const int VECTOR_SIZE = 0x10000 + 1; //vector size 65537
    const int MAX_NUMBER_OF_THREADS = VECTOR_SIZE / 5;
    const int SIZE = sizeof( real_t ) * VECTOR_SIZE; // total size in bytes
    const int THREADS_PER_BLOCK = 32; //number of gpu threads per block
    const int NUMBER_OF_BLOCKS = MAX_NUMBER_OF_THREADS / THREADS_PER_BLOCK; 
   
    // host allocated storage; use std vectors to simplify memory management
    // and initialization
    std::vector< real_t > v1  ( VECTOR_SIZE, 1.f ); //initialize all elements to 1
    std::vector< real_t > v2  ( VECTOR_SIZE, 2.f ); //initialize all elements to 2   
    std::vector< real_t > vout( VECTOR_SIZE, 0.f ); //initialize all elements to 0

    // gpu allocated storage
    real_t* dev_in1 = 0; //vector 1
    real_t* dev_in2 = 0; //vector 2
    real_t* dev_out = 0; //result value
    hipMalloc( &dev_in1, SIZE );
    hipMalloc( &dev_in2, SIZE );
    hipMalloc( &dev_out, SIZE  );
    
    // copy data to GPU
    hipMemcpy( dev_in1, &v1[ 0 ], SIZE, hipMemcpyHostToDevice );
    hipMemcpy( dev_in2, &v2[ 0 ], SIZE, hipMemcpyHostToDevice );

    // execute kernel with num threads >= num elements
    sum_vectors<<<NUMBER_OF_BLOCKS, THREADS_PER_BLOCK>>>( dev_in1, dev_in2, dev_out, VECTOR_SIZE );
    
    // read back result
    hipMemcpy( &vout[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost );
    
    // print first and last element of vector
    std::cout << "result: " << vout.front() << ".." << vout.back() << std::endl;

    // free memory
    hipFree( dev_in1 );
    hipFree( dev_in2 );
    hipFree( dev_out );

    return 0;
}

	.text
	.file	"002_1_sum-vectors.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__sum_vectorsPKfS0_Pfm # -- Begin function _Z26__device_stub__sum_vectorsPKfS0_Pfm
	.type	_Z26__device_stub__sum_vectorsPKfS0_Pfm,@function
_Z26__device_stub__sum_vectorsPKfS0_Pfm: # @_Z26__device_stub__sum_vectorsPKfS0_Pfm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11sum_vectorsPKfS0_Pfm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z26__device_stub__sum_vectorsPKfS0_Pfm
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:                                # %.noexc
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$262148, %edi                   # imm = 0x40004
	callq	_Znwm
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB1_1:                                # %.lr.ph.i.i.i.i.i.i.i.i.i
                                        # =>This Inner Loop Header: Depth=1
	movl	$1065353216, (%rbx,%rax)        # imm = 0x3F800000
	addq	$4, %rax
	cmpq	$262148, %rax                   # imm = 0x40004
	jne	.LBB1_1
# %bb.2:                                # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit
.Ltmp0:
	movl	$262148, %edi                   # imm = 0x40004
	callq	_Znwm
.Ltmp1:
# %bb.3:                                # %.lr.ph.i.i.i.i.i.i.i.i.i10.preheader
	movq	%rax, %r14
	xorl	%eax, %eax
.LBB1_4:                                # %.lr.ph.i.i.i.i.i.i.i.i.i10
                                        # =>This Inner Loop Header: Depth=1
	movl	$1073741824, (%r14,%rax)        # imm = 0x40000000
	addq	$4, %rax
	cmpq	$262148, %rax                   # imm = 0x40004
	jne	.LBB1_4
# %bb.5:                                # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit14
.Ltmp3:
	movl	$262148, %edi                   # imm = 0x40004
	callq	_Znwm
.Ltmp4:
# %bb.6:                                # %.lr.ph.i.i.i.i.i.i.i.i.i15.preheader
	movq	%rax, %r15
	xorl	%r12d, %r12d
	movl	$262148, %edx                   # imm = 0x40004
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	16(%rsp), %rdi
	movq	%r12, (%rdi)
	movq	%r12, 8(%rsp)
	movq	%r12, (%rsp)
.Ltmp6:
	movl	$262148, %esi                   # imm = 0x40004
	callq	hipMalloc
.Ltmp7:
# %bb.7:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp8:
	leaq	8(%rsp), %rdi
	movl	$262148, %esi                   # imm = 0x40004
	callq	hipMalloc
.Ltmp9:
# %bb.8:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit22
.Ltmp10:
	movq	%rsp, %rdi
	movl	$262148, %esi                   # imm = 0x40004
	callq	hipMalloc
.Ltmp11:
# %bb.9:                                # %_ZL9hipMallocIfE10hipError_tPPT_m.exit24
	movq	16(%rsp), %rdi
.Ltmp12:
	movl	$262148, %edx                   # imm = 0x40004
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp13:
# %bb.10:
	movq	8(%rsp), %rdi
.Ltmp14:
	movl	$262148, %edx                   # imm = 0x40004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp16:
	movabsq	$4294967705, %rdi               # imm = 0x100000199
	movabsq	$4294967328, %rdx               # imm = 0x100000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp17:
# %bb.12:
	testl	%eax, %eax
	jne	.LBB1_14
# %bb.13:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
.Ltmp18:
	movl	$65537, %ecx                    # imm = 0x10001
	callq	_Z26__device_stub__sum_vectorsPKfS0_Pfm
.Ltmp19:
.LBB1_14:
	movq	(%rsp), %rsi
.Ltmp20:
	movl	$262148, %edx                   # imm = 0x40004
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp21:
# %bb.15:
.Ltmp22:
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$8, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.16:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	cvtss2sd	(%r15), %xmm0
.Ltmp24:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.17:                               # %_ZNSolsEf.exit
.Ltmp26:
	movq	%rax, %r12
	movl	$.L.str.1, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp27:
# %bb.18:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit28
	xorps	%xmm0, %xmm0
	cvtss2sd	262144(%r15), %xmm0
.Ltmp28:
	movq	%r12, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp29:
# %bb.19:                               # %_ZNSolsEf.exit30
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
.Ltmp30:
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp31:
# %bb.20:                               # %.noexc47
.Ltmp32:
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
.Ltmp33:
# %bb.21:                               # %.noexc48
.Ltmp34:
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.Ltmp35:
# %bb.22:                               # %_ZNSolsEPFRSoS_E.exit
	movq	16(%rsp), %rdi
.Ltmp36:
	callq	hipFree
.Ltmp37:
# %bb.23:
	movq	8(%rsp), %rdi
.Ltmp38:
	callq	hipFree
.Ltmp39:
# %bb.24:
	movq	(%rsp), %rdi
.Ltmp40:
	callq	hipFree
.Ltmp41:
# %bb.25:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit37
	movq	%r15, %rdi
	callq	_ZdlPv
	movq	%r14, %rdi
	callq	_ZdlPv
	movq	%rbx, %rdi
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_28:
	.cfi_def_cfa_offset 64
.Ltmp5:
	movq	%rax, %r12
	jmp	.LBB1_29
.LBB1_26:
.Ltmp2:
	movq	%rax, %r12
	jmp	.LBB1_30
.LBB1_27:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit
.Ltmp42:
	movq	%rax, %r12
	movq	%r15, %rdi
	callq	_ZdlPv
.LBB1_29:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit39
	movq	%r14, %rdi
	callq	_ZdlPv
.LBB1_30:                               # %_ZNSt6vectorIfSaIfEED2Ev.exit41
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r12, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp1-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp1
	.uleb128 .Ltmp2-.Lfunc_begin0           #     jumps to .Ltmp2
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp3-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp4-.Ltmp3                  #   Call between .Ltmp3 and .Ltmp4
	.uleb128 .Ltmp5-.Lfunc_begin0           #     jumps to .Ltmp5
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp4-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp6-.Ltmp4                  #   Call between .Ltmp4 and .Ltmp6
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp6-.Lfunc_begin0           # >> Call Site 5 <<
	.uleb128 .Ltmp41-.Ltmp6                 #   Call between .Ltmp6 and .Ltmp41
	.uleb128 .Ltmp42-.Lfunc_begin0          #     jumps to .Ltmp42
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp41-.Lfunc_begin0          # >> Call Site 6 <<
	.uleb128 .Lfunc_end1-.Ltmp41            #   Call between .Ltmp41 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11sum_vectorsPKfS0_Pfm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11sum_vectorsPKfS0_Pfm,@object # @_Z11sum_vectorsPKfS0_Pfm
	.section	.rodata,"a",@progbits
	.globl	_Z11sum_vectorsPKfS0_Pfm
	.p2align	3, 0x0
_Z11sum_vectorsPKfS0_Pfm:
	.quad	_Z26__device_stub__sum_vectorsPKfS0_Pfm
	.size	_Z11sum_vectorsPKfS0_Pfm, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"result: "
	.size	.L.str, 9

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	".."
	.size	.L.str.1, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11sum_vectorsPKfS0_Pfm"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__sum_vectorsPKfS0_Pfm
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z11sum_vectorsPKfS0_Pfm
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11sum_vectorsPKfS0_Pfm ; -- Begin function _Z11sum_vectorsPKfS0_Pfm
	.globl	_Z11sum_vectorsPKfS0_Pfm
	.p2align	8
	.type	_Z11sum_vectorsPKfS0_Pfm,@function
_Z11sum_vectorsPKfS0_Pfm:               ; @_Z11sum_vectorsPKfS0_Pfm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s1, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s15, s15, s1
	s_mul_i32 s1, s1, s2
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v0, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[3:4]
	global_load_b32 v0, v[0:1], off
	global_load_b32 v7, v[7:8], off
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_add_co_u32 v4, s0, s8, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
	v_add_nc_u32_e32 v3, s1, v3
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v7
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11sum_vectorsPKfS0_Pfm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11sum_vectorsPKfS0_Pfm, .Lfunc_end0-_Z11sum_vectorsPKfS0_Pfm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11sum_vectorsPKfS0_Pfm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11sum_vectorsPKfS0_Pfm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
