/*
        ***** vecadd.cu *****

CUDA program to add two vectors.

Compile:    nvcc -o vecadd vecadd.cu
Usage:      vecadd [N], where N is vector length

Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.

Modifications:
*/

#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;


// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
    for ( int i = 0; i < n; i++ )
        c[i] = a[i] + b[i];
}

// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
    int i = threadIdx.x + blockIdx.x * blockDim.x;
    if ( i < n ) c[i] = a[i] + b[i];
}

// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
    for ( int i = 0; i < n; i++ )
        array[i] = rand() % n;
}

int main( int argc, char** argv )
{
    int n = 1024;
    if ( argc > 1 ) n = atoi( argv[1] );

    // alloc host memory for vectors a, b, c
    int size = n * sizeof( int );
    int *a = ( int * )malloc( size );
    int *b = ( int * )malloc( size );
    int *c_seq = ( int * )malloc( size );
    int *c_par = ( int * )malloc( size );

    // fill arrays a and b with random ints
    srand( time( NULL ) );
    random_ints( a, n );
    random_ints( b, n );

    // add vectors sequentially
    auto c = chrono::system_clock::now();
    add_seq( a, b, c_seq, n );
    chrono::duration<double> d_cpu = chrono::system_clock::now() - c;

    // alloc device  memory for vectors a, b, c
    int *d_a, *d_b, *d_c;
    cudaMalloc( ( void ** )&d_a, size );
    cudaMalloc( ( void ** )&d_b, size );
    cudaMalloc( ( void ** )&d_c, size );

    // copy vectors a and b to device
    cudaMemcpy( d_a, a, size, cudaMemcpyHostToDevice );
    cudaMemcpy( d_b, b, size, cudaMemcpyHostToDevice );

    // launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
    int nThreads = 64;                              // should be multiple of 32 (up to 1024)
    int nBlocks = ( n + nThreads - 1 ) / nThreads;
    c = chrono::system_clock::now();
    add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
    chrono::duration<double> d_gpu = chrono::system_clock::now() - c;

    // copy vector sum back to host
    cudaMemcpy( c_par, d_c, size, cudaMemcpyDeviceToHost );

    #if 0
    cout << "\na:    ";
    for ( int i = 0; i < n; i++ ) cout << " " << a[i];
    cout << "\nb:    ";
    for ( int i = 0; i < n; i++ ) cout << " " << b[i];
    cout << "\nc_seq:";
    for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
    cout << "\nc_par:";
    for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
    #endif

    cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";

    // cleanup
    free( a ); free( b ); free( c_seq ); free( c_par );
    cudaFree( d_a ); cudaFree( d_b ); cudaFree( d_c );
    return 0;
}

	.file	"tmpxft_0021c18a_00000000-6_vecadd.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3741:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3741:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7add_seqPiS_S_i
	.type	_Z7add_seqPiS_S_i, @function
_Z7add_seqPiS_S_i:
.LFB3734:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %ecx
	jle	.L6
	movl	(%rsi,%rax,4), %r8d
	addl	(%rdi,%rax,4), %r8d
	movl	%r8d, (%rdx,%rax,4)
	incq	%rax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE3734:
	.size	_Z7add_seqPiS_S_i, .-_Z7add_seqPiS_S_i
	.globl	_Z11random_intsPii
	.type	_Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3735:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%esi, %ebx
.L8:
	cmpl	%ebp, %ebx
	jle	.L11
	call	rand@PLT
	cltd
	idivl	%ebx
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L8
.L11:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3735:
	.size	_Z11random_intsPii, .-_Z11random_intsPii
	.globl	_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
	.type	_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, @function
_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i:
.LFB3763:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7add_parPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3763:
	.size	_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i, .-_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
	.globl	_Z7add_parPiS_S_i
	.type	_Z7add_parPiS_S_i, @function
_Z7add_parPiS_S_i:
.LFB3764:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3764:
	.size	_Z7add_parPiS_S_i, .-_Z7add_parPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\n\nBenchmarks: CPU "
.LC2:
	.string	" sec, GPU "
.LC3:
	.string	" sec\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3736:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	$1024, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jle	.L18
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ebp
.L18:
	leal	0(,%rbp,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, (%rsp)
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movl	%ebp, %esi
	movq	%r13, %rdi
	call	_Z11random_intsPii
	movl	%ebp, %esi
	movq	%r12, %rdi
	call	_Z11random_intsPii
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	%ebp, %ecx
	movq	%r14, %rdx
	movq	%r12, %rsi
	movq	%r13, %rdi
	movq	%rax, %r15
	call	_Z7add_seqPiS_S_i
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	subq	%r15, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC0(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movl	$64, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, %r15
	leal	63(%rbp), %eax
	cltd
	idivl	%ecx
	movl	$67108865, %edx
	movl	$1, %ecx
	salq	$6, %rdx
	movl	%eax, 48(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 52(%rsp)
	movq	48(%rsp), %rdi
	movl	56(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%ebp, %ecx
	movq	24(%rsp), %rdi
	call	_Z31__device_stub__Z7add_parPiS_S_iPiS_S_i
.L19:
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	subq	%r15, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC0(%rip), %xmm0
	movq	%xmm0, %rbp
	call	cudaMemcpy@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	8(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3736:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z7add_parPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3766:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7add_parPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3766:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
        ***** vecadd.cu *****

CUDA program to add two vectors.

Compile:    nvcc -o vecadd vecadd.cu
Usage:      vecadd [N], where N is vector length

Author: John M. Weiss, Ph.D.
CSC433/533 Computer Graphics - Fall 2016.

Modifications:
*/


#include <hip/hip_runtime.h>
#include <chrono>
#include <ctime>
#include <cmath>
#include <iostream>
using namespace std;


// sequential vector addition (on the host)
void add_seq( int *a, int *b, int *c, int n )
{
    for ( int i = 0; i < n; i++ )
        c[i] = a[i] + b[i];
}

// CUDA kernel: add two ints in parallel
__global__ void add_par( int *a, int *b, int *c, int n )
{
    int i = threadIdx.x + blockIdx.x * blockDim.x;
    if ( i < n ) c[i] = a[i] + b[i];
}

// generate array of random ints with values between 0 and n-1
void random_ints( int array[], int n )
{
    for ( int i = 0; i < n; i++ )
        array[i] = rand() % n;
}

int main( int argc, char** argv )
{
    int n = 1024;
    if ( argc > 1 ) n = atoi( argv[1] );

    // alloc host memory for vectors a, b, c
    int size = n * sizeof( int );
    int *a = ( int * )malloc( size );
    int *b = ( int * )malloc( size );
    int *c_seq = ( int * )malloc( size );
    int *c_par = ( int * )malloc( size );

    // fill arrays a and b with random ints
    srand( time( NULL ) );
    random_ints( a, n );
    random_ints( b, n );

    // add vectors sequentially
    auto c = chrono::system_clock::now();
    add_seq( a, b, c_seq, n );
    chrono::duration<double> d_cpu = chrono::system_clock::now() - c;

    // alloc device  memory for vectors a, b, c
    int *d_a, *d_b, *d_c;
    hipMalloc( ( void ** )&d_a, size );
    hipMalloc( ( void ** )&d_b, size );
    hipMalloc( ( void ** )&d_c, size );

    // copy vectors a and b to device
    hipMemcpy( d_a, a, size, hipMemcpyHostToDevice );
    hipMemcpy( d_b, b, size, hipMemcpyHostToDevice );

    // launch add() kernel on GPU with M threads per block, (N+M-1)/M blocks
    int nThreads = 64;                              // should be multiple of 32 (up to 1024)
    int nBlocks = ( n + nThreads - 1 ) / nThreads;
    c = chrono::system_clock::now();
    add_par<<< nBlocks, nThreads >>>(d_a, d_b, d_c, n);
    chrono::duration<double> d_gpu = chrono::system_clock::now() - c;

    // copy vector sum back to host
    hipMemcpy( c_par, d_c, size, hipMemcpyDeviceToHost );

    #if 0
    cout << "\na:    ";
    for ( int i = 0; i < n; i++ ) cout << " " << a[i];
    cout << "\nb:    ";
    for ( int i = 0; i < n; i++ ) cout << " " << b[i];
    cout << "\nc_seq:";
    for ( int i = 0; i < n; i++ ) cout << " " << c_seq[i];
    cout << "\nc_par:";
    for ( int i = 0; i < n; i++ ) cout << " " << c_par[i];
    #endif

    cout << "\n\nBenchmarks: CPU " << d_cpu.count() << " sec, GPU " << d_gpu.count() << " sec\n\n";

    // cleanup
    free( a ); free( b ); free( c_seq ); free( c_par );
    hipFree( d_a ); hipFree( d_b ); hipFree( d_c );
    return 0;
}

	.text
	.file	"vecadd.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z7add_seqPiS_S_i               # -- Begin function _Z7add_seqPiS_S_i
	.type	_Z7add_seqPiS_S_i,@function
_Z7add_seqPiS_S_i:                      # @_Z7add_seqPiS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ecx, %eax
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rsi,%rcx,4), %r8d
	addl	(%rdi,%rcx,4), %r8d
	movl	%r8d, (%rdx,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z7add_seqPiS_S_i, .Lfunc_end0-_Z7add_seqPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__add_parPiS_S_i # -- Begin function _Z22__device_stub__add_parPiS_S_i
	.type	_Z22__device_stub__add_parPiS_S_i,@function
_Z22__device_stub__add_parPiS_S_i:      # @_Z22__device_stub__add_parPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7add_parPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__add_parPiS_S_i, .Lfunc_end1-_Z22__device_stub__add_parPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11random_intsPii              # -- Begin function _Z11random_intsPii
	.type	_Z11random_intsPii,@function
_Z11random_intsPii:                     # @_Z11random_intsPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB2_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	movl	%esi, %r15d
	xorl	%r12d, %r12d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB2_2
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r14
	.cfi_restore %r15
.LBB2_4:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1024, %r13d                    # imm = 0x400
	cmpl	$2, %edi
	jl	.LBB3_2
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %r13d
.LBB3_2:
	leal	(,%r13,4), %eax
	movslq	%eax, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	testl	%r13d, %r13d
	jle	.LBB3_7
# %bb.3:                                # %.lr.ph.preheader.i
	movl	%r13d, %r15d
	xorl	%ebp, %ebp
.LBB3_4:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%r13d
	movl	%edx, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	%rbp, %r15
	jne	.LBB3_4
# %bb.5:                                # %.lr.ph.i38.preheader
	xorl	%ebp, %ebp
.LBB3_6:                                # %.lr.ph.i38
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%r13d
	movl	%edx, (%r14,%rbp,4)
	incq	%rbp
	cmpq	%rbp, %r15
	jne	.LBB3_6
.LBB3_7:                                # %_Z7add_seqPiS_S_i.exit
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, (%rsp)                    # 8-byte Spill
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %r15
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	63(%r13), %eax
	leal	126(%r13), %ebp
	testl	%eax, %eax
	cmovnsl	%eax, %ebp
	sarl	$6, %ebp
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	btsq	$32, %rbp
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movq	%rbp, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.8:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%r13d, %ecx
	callq	_Z22__device_stub__add_parPiS_S_i
.LBB3_9:
	subq	(%rsp), %r15                    # 8-byte Folded Reload
	cvtsi2sd	%r15, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movsd	%xmm0, 32(%rsp)                 # 8-byte Spill
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	subq	40(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	movq	8(%rsp), %rsi
	movq	48(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$18, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	32(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.1, %esi
	movl	$10, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.2, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7add_parPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7add_parPiS_S_i,@object       # @_Z7add_parPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z7add_parPiS_S_i
	.p2align	3, 0x0
_Z7add_parPiS_S_i:
	.quad	_Z22__device_stub__add_parPiS_S_i
	.size	_Z7add_parPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n\nBenchmarks: CPU "
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" sec, GPU "
	.size	.L.str.1, 11

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" sec\n\n"
	.size	.L.str.2, 7

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7add_parPiS_S_i"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__add_parPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7add_parPiS_S_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7add_parPiS_S_i       ; -- Begin function _Z7add_parPiS_S_i
	.globl	_Z7add_parPiS_S_i
	.p2align	8
	.type	_Z7add_parPiS_S_i,@function
_Z7add_parPiS_S_i:                      ; @_Z7add_parPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7add_parPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7add_parPiS_S_i, .Lfunc_end0-_Z7add_parPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7add_parPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7add_parPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
