#include "includes.h"
__global__ void box_encode_kernel(float * targets_dx, float * targets_dy, float * targets_dw, float * targets_dh, float4 * boxes, float4 * anchors, float wx, float wy, float ww, float wh, size_t gt, size_t idxJump) {

int idx = blockIdx.x*blockDim.x + threadIdx.x;
size_t row_offset;
float anchors_x1,anchors_x2, anchors_y1, anchors_y2,
boxes_x1, boxes_x2, boxes_y1, boxes_y2, ex_w, ex_h,
ex_ctr_x, ex_ctr_y, gt_w, gt_h, gt_ctr_x, gt_ctr_y;

for (int i=idx; i<gt; i+=idxJump){
row_offset = i;
anchors_x1 = anchors[row_offset].x;
anchors_y1 = anchors[row_offset].y;
anchors_x2 = anchors[row_offset].z;
anchors_y2 = anchors[row_offset].w;

boxes_x1 = boxes[row_offset].x;
boxes_y1 = boxes[row_offset].y;
boxes_x2 = boxes[row_offset].z;
boxes_y2 = boxes[row_offset].w;

ex_w = anchors_x2 - anchors_x1 + 1;
ex_h = anchors_y2 - anchors_y1 + 1;
ex_ctr_x = anchors_x1 + 0.5 * ex_w;
ex_ctr_y = anchors_y1 + 0.5 * ex_h;

gt_w = boxes_x2 - boxes_x1 + 1;
gt_h = boxes_y2 -  boxes_y1 + 1;
gt_ctr_x = boxes_x1 + 0.5 * gt_w;
gt_ctr_y = boxes_y1 + 0.5 * gt_h;

targets_dx[i] = wx * (gt_ctr_x-ex_ctr_x)/ex_w;
targets_dy[i] = wy * (gt_ctr_y-ex_ctr_y)/ex_h;
targets_dw[i] = ww * log(gt_w/ex_w);
targets_dh[i] = wh * log(gt_h/ex_h);
}

}
	.file	"tmpxft_003683ab_00000000-6_box_encode_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm
	.type	_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm, @function
_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 200(%rsp)
	movq	%rsp, %rax
	movq	%rax, 208(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L2:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm, .-_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm
	.globl	_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm
	.type	_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm, @function
_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmmPfS_S_S_P6float4S1_ffffmm
	.cfi_endproc
.LFE2033:
	.size	_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm, .-_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17box_encode_kernelPfS_S_S_P6float4S1_ffffmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void box_encode_kernel(float * targets_dx, float * targets_dy, float * targets_dw, float * targets_dh, float4 * boxes, float4 * anchors, float wx, float wy, float ww, float wh, size_t gt, size_t idxJump) {

int idx = blockIdx.x*blockDim.x + threadIdx.x;
size_t row_offset;
float anchors_x1,anchors_x2, anchors_y1, anchors_y2,
boxes_x1, boxes_x2, boxes_y1, boxes_y2, ex_w, ex_h,
ex_ctr_x, ex_ctr_y, gt_w, gt_h, gt_ctr_x, gt_ctr_y;

for (int i=idx; i<gt; i+=idxJump){
row_offset = i;
anchors_x1 = anchors[row_offset].x;
anchors_y1 = anchors[row_offset].y;
anchors_x2 = anchors[row_offset].z;
anchors_y2 = anchors[row_offset].w;

boxes_x1 = boxes[row_offset].x;
boxes_y1 = boxes[row_offset].y;
boxes_x2 = boxes[row_offset].z;
boxes_y2 = boxes[row_offset].w;

ex_w = anchors_x2 - anchors_x1 + 1;
ex_h = anchors_y2 - anchors_y1 + 1;
ex_ctr_x = anchors_x1 + 0.5 * ex_w;
ex_ctr_y = anchors_y1 + 0.5 * ex_h;

gt_w = boxes_x2 - boxes_x1 + 1;
gt_h = boxes_y2 -  boxes_y1 + 1;
gt_ctr_x = boxes_x1 + 0.5 * gt_w;
gt_ctr_y = boxes_y1 + 0.5 * gt_h;

targets_dx[i] = wx * (gt_ctr_x-ex_ctr_x)/ex_w;
targets_dy[i] = wy * (gt_ctr_y-ex_ctr_y)/ex_h;
targets_dw[i] = ww * log(gt_w/ex_w);
targets_dh[i] = wh * log(gt_h/ex_h);
}

}
	.text
	.file	"box_encode_kernel.hip"
	.globl	_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm # -- Begin function _Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.type	_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm,@function
_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm: # @_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	movq	%rsp, %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm, .Lfunc_end0-_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm,@object # @_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.section	.rodata,"a",@progbits
	.globl	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.p2align	3, 0x0
_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm:
	.quad	_Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.size	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm"
	.size	.L__unnamed_1, 64

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm ; -- Begin function _Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.globl	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
	.p2align	8
	.type	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm,@function
_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm: ; @_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b128 s[20:23], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[20:21], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_add_nc_u32_e32 v3, s22, v1
	s_mov_b32 s3, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_lshlrev_b64 v[4:5], 4, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	global_load_b128 v[4:7], v[6:7], off
	global_load_b128 v[8:11], v[8:9], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v12, v7, v5 :: v_dual_sub_f32 v13, v10, v8
	v_sub_f32_e32 v0, v6, v4
	v_sub_f32_e32 v14, v11, v9
	v_cvt_f64_f32_e32 v[10:11], v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v20, 1.0, v12 :: v_dual_add_f32 v21, 1.0, v13
	v_add_f32_e32 v0, 1.0, v0
	v_cvt_f64_f32_e32 v[6:7], v4
	v_cvt_f64_f32_e32 v[4:5], v5
	v_add_f32_e32 v22, 1.0, v14
	v_cvt_f64_f32_e32 v[16:17], v21
	v_cvt_f64_f32_e32 v[12:13], v0
	v_cvt_f64_f32_e32 v[14:15], v20
	v_cvt_f64_f32_e32 v[8:9], v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], v[16:17], 0.5, v[10:11]
	v_fma_f64 v[6:7], v[12:13], 0.5, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[14:15], 0.5, v[4:5]
	v_div_scale_f32 v5, null, v0, v0, v21
	v_ashrrev_i32_e32 v4, 31, v3
	v_rcp_f32_e32 v17, v5
	v_cvt_f32_f64_e32 v10, v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v5, v17, 1.0
	v_cvt_f32_f64_e32 v6, v[6:7]
	v_cvt_f32_f64_e32 v7, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v11, v17
	v_div_scale_f32 v14, s0, v21, v0, v21
	v_mul_f32_e32 v11, v14, v17
	v_cvt_f64_f32_e32 v[18:19], v22
	v_div_scale_f32 v15, null, v20, v20, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v5, v11, v14
	v_dual_fmac_f32 v11, v13, v17 :: v_dual_sub_f32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v5, v11, v14
	v_mul_f32_e32 v14, s16, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, v0, v0, v14
	v_fma_f64 v[8:9], v[18:19], 0.5, v[8:9]
	v_rcp_f32_e32 v10, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v6, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v19, v10
	v_cvt_f32_f64_e32 v8, v[8:9]
	v_rcp_f32_e32 v9, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v15, v9, 1.0
	v_fmac_f32_e32 v9, v12, v9
	v_div_scale_f32 v16, s1, v22, v20, v22
	v_sub_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v16, v9
	v_div_scale_f32 v8, vcc_lo, v14, v0, v14
	v_fma_f32 v18, -v15, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, v8, v10 :: v_dual_fmac_f32 v12, v18, v9
	v_fma_f32 v24, -v6, v19, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v15, v12, v16
	v_mul_f32_e32 v15, s17, v7
	v_div_scale_f32 v7, null, v20, v20, v15
	v_div_scale_f32 v18, s2, v15, v20, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v7, v16, 1.0
	v_fmac_f32_e32 v16, v23, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v18, v16
	v_fma_f32 v25, -v7, v23, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v23, v25, v16
	v_fmac_f32_e32 v19, v24, v10
	v_fma_f32 v7, -v7, v23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v6, v19, v8
	v_div_fmas_f32 v18, v6, v10, v19
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v16, v7, v16, v23
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v5, v5, v17, v11
	s_mov_b32 vcc_lo, s1
	v_cmp_le_u64_e64 s1, s[20:21], v[3:4]
	v_div_fmas_f32 v6, v13, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v7, v5, v0, v21
	v_div_fixup_f32 v0, v18, v0, v14
	v_div_fixup_f32 v8, v6, v20, v22
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v7
	v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
	v_cmp_gt_f32_e64 s0, 0x800000, v8
	s_or_b32 s3, s1, s3
	v_cndmask_b32_e64 v9, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v23, 0, 0x41b17218, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, 1.0, 0x4f800000, s0
	v_cndmask_b32_e64 v24, 0, 0x41b17218, s0
	v_dual_mul_f32 v7, v7, v9 :: v_dual_mul_f32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_log_f32_e32 v4, v7
	v_add_co_u32 v7, s2, s4, v5
	v_log_f32_e32 v13, v8
	v_add_co_ci_u32_e64 v8, s2, s5, v6, s2
	v_add_co_u32 v9, s2, s6, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s2, s7, v6, s2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v17, 0x3f317217, v4
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_add_co_u32 v11, s2, s8, v5
	v_mul_f32_e32 v19, 0x3f317217, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v21, 0x3f317217, v4, -v17
	v_cmp_gt_f32_e64 s0, 0x7f800000, |v13|
	v_add_co_ci_u32_e64 v12, s2, s9, v6, s2
	v_fma_f32 v22, 0x3f317217, v13, -v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, 0x3377d1cf, v4
	v_dual_fmac_f32 v22, 0x3377d1cf, v13 :: v_dual_add_nc_u32 v3, s22, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v17, v21
	v_add_f32_e32 v19, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v17, v4, v17, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v6, vcc_lo
	v_cndmask_b32_e64 v13, v13, v19, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v23
	v_div_fixup_f32 v6, v16, v20, v15
	v_dual_sub_f32 v13, v13, v24 :: v_dual_mul_f32 v14, s18, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v13, s19, v13
	global_store_b32 v[7:8], v0, off
	global_store_b32 v[9:10], v6, off
	global_store_b32 v[11:12], v14, off
	global_store_b32 v[4:5], v13, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow102
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 26
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm, .Lfunc_end0-_Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1060
; NumSgprs: 26
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 26
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z17box_encode_kernelPfS_S_S_P15HIP_vector_typeIfLj4EES2_ffffmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     26
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
