#define ulong unsigned long long
#define uint unsigned int

#define MOD_P0 469762049LL
#define MOD_P1 1811939329LL
#define MOD_P2 2013265921LL


//Ř݂ɑfP^̂ŁAꂼ̗]肩猳̒l𕜌
//̂ƂP͑SČŒȂ̂ŏ]vZ͑Sߑłł

//E0`E2́AE3ɏo
//Jオl
//arrayLength2=arrayE3̔zTCY
__global__ void GarnerGPU(uint *arrayE0,uint *arrayE1,uint *arrayE2,uint *arrayE3,uint arrayLength2 ) {
	int idx = threadIdx.x+blockIdx.x*256;
	
	ulong ar=arrayE0[idx];
	ulong br=arrayE1[idx];
	ulong cr=arrayE2[idx];
	
	ulong x=ar;
	ulong brx=br-x+MOD_P1;
	if (brx>=MOD_P1)brx-=MOD_P1;
	x=x+(brx*1540148431)%MOD_P1*MOD_P0;
	//1540148431=modinv(MOD_P0,MOD_P1)
	//̎_xMOD_P1*MOD_P0ȉł邱Ƃۏ؂Ă

	ulong crx=cr+MOD_P2-x%MOD_P2;
	if (crx>=MOD_P2)crx-=MOD_P2;
	ulong w1=(crx*1050399624)%MOD_P2;
	//1050399624=modinv(MOD_P0,MOD_P2) *modinv(MOD_P1,MOD_P2)%MOD_P2
	ulong w2=MOD_P0*MOD_P1;
	ulong out_lo=w1*w2;
	ulong out_hi=__umul64hi(w1,w2);
	
	if (out_lo>(out_lo+x)){
		out_hi++;
	}
	out_lo+=x;
	
	//Jオ菈
	uint ui00_32=(uint)(out_lo%(1ULL<<32ULL));
	uint ui32_64=(uint)(out_lo/(1ULL<<32ULL));
	uint ui64_96=(uint)(out_hi%(1ULL<<32ULL));
	
	uint lastE3_0 = atomicAdd( &arrayE3[idx+0], ui00_32 );
	if ((lastE3_0+ui00_32)<lastE3_0){//Jオl
		ui32_64++;
		if (ui32_64==0)ui64_96++;
	}
	
	if (ui32_64!=0){
		uint lastE3_1 = atomicAdd( &arrayE3[idx+1], ui32_64 );
		if ((lastE3_1+ui32_64)<lastE3_1){//Jオl
			ui64_96++;//I[o[t[邱Ƃ͐΂ɂȂ
		}
	}
	
	uint upflg=0;
	if (ui64_96!=0){
		uint lastE3_2 = atomicAdd( &arrayE3[idx+2], ui64_96 );
		if ((lastE3_2+ui64_96)<lastE3_2){//Jオl
			upflg++;
		}
	}
	
	uint lastE3_i;
	for(int i=idx+3;i<arrayLength2;i++){ //9999999+1݂ȂƂp
		if (upflg==0)break;
		lastE3_i = atomicAdd( &arrayE3[i], upflg );
		if (lastE3_i==4294967295){
			upflg=1;
		}else{
			upflg=0;
		}
	}
}
	.file	"tmpxft_0027e940_00000000-6_garner_win.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j
	.type	_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j, @function
_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z9GarnerGPUPjS_S_S_j(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j, .-_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j
	.globl	_Z9GarnerGPUPjS_S_S_j
	.type	_Z9GarnerGPUPjS_S_S_j, @function
_Z9GarnerGPUPjS_S_S_j:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z9GarnerGPUPjS_S_S_jPjS_S_S_j
	.cfi_endproc
.LFE2033:
	.size	_Z9GarnerGPUPjS_S_S_j, .-_Z9GarnerGPUPjS_S_S_j
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9GarnerGPUPjS_S_S_j"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9GarnerGPUPjS_S_S_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define ulong unsigned long long
#define uint unsigned int

#define MOD_P0 469762049LL
#define MOD_P1 1811939329LL
#define MOD_P2 2013265921LL


//Ř݂ɑfP^̂ŁAꂼ̗]肩猳̒l𕜌
//̂ƂP͑SČŒȂ̂ŏ]vZ͑Sߑłł

//E0`E2́AE3ɏo
//Jオl
//arrayLength2=arrayE3̔zTCY
__global__ void GarnerGPU(uint *arrayE0,uint *arrayE1,uint *arrayE2,uint *arrayE3,uint arrayLength2 ) {
	int idx = threadIdx.x+blockIdx.x*256;
	
	ulong ar=arrayE0[idx];
	ulong br=arrayE1[idx];
	ulong cr=arrayE2[idx];
	
	ulong x=ar;
	ulong brx=br-x+MOD_P1;
	if (brx>=MOD_P1)brx-=MOD_P1;
	x=x+(brx*1540148431)%MOD_P1*MOD_P0;
	//1540148431=modinv(MOD_P0,MOD_P1)
	//̎_xMOD_P1*MOD_P0ȉł邱Ƃۏ؂Ă

	ulong crx=cr+MOD_P2-x%MOD_P2;
	if (crx>=MOD_P2)crx-=MOD_P2;
	ulong w1=(crx*1050399624)%MOD_P2;
	//1050399624=modinv(MOD_P0,MOD_P2) *modinv(MOD_P1,MOD_P2)%MOD_P2
	ulong w2=MOD_P0*MOD_P1;
	ulong out_lo=w1*w2;
	ulong out_hi=__umul64hi(w1,w2);
	
	if (out_lo>(out_lo+x)){
		out_hi++;
	}
	out_lo+=x;
	
	//Jオ菈
	uint ui00_32=(uint)(out_lo%(1ULL<<32ULL));
	uint ui32_64=(uint)(out_lo/(1ULL<<32ULL));
	uint ui64_96=(uint)(out_hi%(1ULL<<32ULL));
	
	uint lastE3_0 = atomicAdd( &arrayE3[idx+0], ui00_32 );
	if ((lastE3_0+ui00_32)<lastE3_0){//Jオl
		ui32_64++;
		if (ui32_64==0)ui64_96++;
	}
	
	if (ui32_64!=0){
		uint lastE3_1 = atomicAdd( &arrayE3[idx+1], ui32_64 );
		if ((lastE3_1+ui32_64)<lastE3_1){//Jオl
			ui64_96++;//I[o[t[邱Ƃ͐΂ɂȂ
		}
	}
	
	uint upflg=0;
	if (ui64_96!=0){
		uint lastE3_2 = atomicAdd( &arrayE3[idx+2], ui64_96 );
		if ((lastE3_2+ui64_96)<lastE3_2){//Jオl
			upflg++;
		}
	}
	
	uint lastE3_i;
	for(int i=idx+3;i<arrayLength2;i++){ //9999999+1݂ȂƂp
		if (upflg==0)break;
		lastE3_i = atomicAdd( &arrayE3[i], upflg );
		if (lastE3_i==4294967295){
			upflg=1;
		}else{
			upflg=0;
		}
	}
}
	.text
	.file	"garner_win.hip"
	.globl	_Z24__device_stub__GarnerGPUPjS_S_S_j # -- Begin function _Z24__device_stub__GarnerGPUPjS_S_S_j
	.type	_Z24__device_stub__GarnerGPUPjS_S_S_j,@function
_Z24__device_stub__GarnerGPUPjS_S_S_j:  # @_Z24__device_stub__GarnerGPUPjS_S_S_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9GarnerGPUPjS_S_S_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__GarnerGPUPjS_S_S_j, .Lfunc_end0-_Z24__device_stub__GarnerGPUPjS_S_S_j
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9GarnerGPUPjS_S_S_j, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9GarnerGPUPjS_S_S_j,@object   # @_Z9GarnerGPUPjS_S_S_j
	.section	.rodata,"a",@progbits
	.globl	_Z9GarnerGPUPjS_S_S_j
	.p2align	3, 0x0
_Z9GarnerGPUPjS_S_S_j:
	.quad	_Z24__device_stub__GarnerGPUPjS_S_S_j
	.size	_Z9GarnerGPUPjS_S_S_j, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9GarnerGPUPjS_S_S_j"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__GarnerGPUPjS_S_S_j
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9GarnerGPUPjS_S_S_j
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9GarnerGPUPjS_S_S_j   ; -- Begin function _Z9GarnerGPUPjS_S_S_j
	.globl	_Z9GarnerGPUPjS_S_S_j
	.p2align	8
	.type	_Z9GarnerGPUPjS_S_S_j,@function
_Z9GarnerGPUPjS_S_S_j:                  ; @_Z9GarnerGPUPjS_S_S_j
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 8, v0
	s_movk_i32 s2, 0x67a
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s2, 0x134, s2
	s_addc_u32 s3, 0, 0
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v7, s2, 0x5ed09000, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s2, 0
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	v_readfirstlane_b32 s4, v7
	global_load_b32 v3, v[3:4], off
	global_load_b32 v6, v[5:6], off
	v_add_co_u32 v4, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v2, vcc_lo
	s_addc_u32 s5, s3, 2
	s_mov_b32 s2, 0x93ffffff
	s_mov_b32 s3, -1
	global_load_b32 v13, v[4:5], off
	s_mul_hi_u32 s7, s4, 0x93ffffff
	s_mul_i32 s6, s5, 0x93ffffff
	s_sub_i32 s7, s7, s4
	s_mul_i32 s8, s4, 0x93ffffff
	s_add_i32 s7, s7, s6
	s_mul_hi_u32 s9, s4, s8
	s_mul_hi_u32 s12, s5, s8
	s_mul_hi_u32 s6, s5, s7
	s_waitcnt vmcnt(1)
	v_sub_co_u32 v4, s13, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e64 v5, null, 0, 0, s13
	v_add_co_u32 v6, vcc_lo, 0x6c000001, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[4:5]
	s_mul_hi_u32 s3, s4, s7
	s_mul_i32 s4, s4, s7
	s_mul_i32 s2, s5, s8
	s_add_u32 s4, s9, s4
	s_addc_u32 s3, 0, s3
	v_cndmask_b32_e32 v6, v6, v4, vcc_lo
	v_cndmask_b32_e32 v8, v8, v5, vcc_lo
	s_add_u32 s2, s4, s2
	s_mul_i32 s7, s5, s7
	s_addc_u32 s2, s3, s12
	v_mad_u64_u32 v[4:5], null, 0x5bcccccf, v6, 0
	s_addc_u32 s3, s6, 0
	s_add_u32 s2, s2, s7
	s_addc_u32 s3, 0, s3
	v_add_co_u32 v11, s2, v7, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s2, 0
	v_mad_u64_u32 v[6:7], null, 0x5bcccccf, v8, v[5:6]
	s_addc_u32 s2, s5, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v5, v4, v11
	v_mad_u64_u32 v[7:8], null, v4, s2, 0
	v_mad_u64_u32 v[9:10], null, v6, v11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v8, vcc_lo
	v_mad_u64_u32 v[7:8], null, v6, s2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v5, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v10, vcc_lo
	s_add_u32 s2, 0, 0
	s_addc_u32 s3, 0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v7
	v_add_co_u32 v14, s2, 0x2222221d, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_mad_u64_u32 v[7:8], null, 0x6c000001, v5, 0
	s_cmp_lg_u32 s2, 0
	s_addc_u32 s3, s3, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v5, v8
	v_mad_u64_u32 v[8:9], null, 0x6c000001, v10, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v5, vcc_lo, v4, v7
	v_sub_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v6, vcc_lo, 0x6c000001, v5
	v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_lt_u32_e32 vcc_lo, 0x6c000000, v6
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x6c000000, v5
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_dual_cndmask_b32 v7, -1, v8 :: v_dual_add_nc_u32 v8, 0x93ffffff, v6
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v9, -1, v9
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v5, v6, vcc_lo
	v_mad_u64_u32 v[5:6], null, 0x1c000001, v7, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, v5, s3, 0
	v_mul_hi_u32 v3, v5, v14
	v_mad_u64_u32 v[9:10], null, v6, v14, 0
	v_mad_u64_u32 v[11:12], null, v6, s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v7, v10, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
	v_mad_u64_u32 v[7:8], null, 0x78000001, v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v8
	v_mad_u64_u32 v[8:9], null, 0x78000001, v10, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v5, v7
	v_sub_co_ci_u32_e32 v7, vcc_lo, v6, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v8, vcc_lo, 0x78000001, v3
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x78000000, v8
	v_cmp_eq_u32_e64 s2, 0, v7
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x78000000, v3
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, -1, v10, vcc_lo
	v_subrev_co_u32 v12, vcc_lo, 0x78000001, v8
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v10, -1, v11, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v12
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_cndmask_b32_e32 v3, v3, v8, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v3, vcc_lo, v13, v3
	v_sub_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, 0x78000001, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, 0x78000000, v[7:8]
	v_dual_cndmask_b32 v10, v8, v9 :: v_dual_cndmask_b32 v3, v7, v3
	v_mad_u64_u32 v[7:8], null, 0x3e9bd388, v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v8
	v_mad_u64_u32 v[8:9], null, 0x3e9bd388, v10, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v7, s3, 0
	v_mul_hi_u32 v3, v7, v14
	v_mad_u64_u32 v[11:12], null, v8, v14, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v10, vcc_lo
	v_mad_u64_u32 v[9:10], null, v8, s3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v11
	v_add_co_ci_u32_e32 v3, vcc_lo, v13, v12, vcc_lo
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v3, vcc_lo, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v10, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0x78000001, v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v10
	v_mad_u64_u32 v[10:11], null, 0x78000001, v12, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v7, v9
	v_sub_co_ci_u32_e32 v7, vcc_lo, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_u32 v8, vcc_lo, 0x78000001, v3
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0x78000000, v8
	v_cmp_eq_u32_e64 s2, 0, v7
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0x78000000, v3
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, -1, v10, vcc_lo
	v_subrev_co_u32 v12, vcc_lo, 0x78000001, v8
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v9, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v10, -1, v11, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v8, v12 :: v_dual_cndmask_b32 v9, v9, v13
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v3, v8, vcc_lo
	v_cndmask_b32_e32 v9, v7, v9, vcc_lo
	v_add_co_u32 v1, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[7:8], null, 0x88000001, v11, 0
	v_mul_lo_u32 v3, 0x88000001, v9
	v_mul_lo_u32 v10, 0xbd00000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v7
	v_add3_u32 v10, v8, v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v9, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
	global_atomic_add_u32 v3, v[1:2], v5, off glc
	v_add_co_u32 v12, s2, v6, 1
	s_waitcnt vmcnt(0)
	v_not_b32_e32 v7, v3
	v_mov_b32_e32 v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, v7, v5
	v_mad_u64_u32 v[7:8], null, 0xbd00000, v11, v[3:4]
	s_and_b32 s2, vcc_lo, s2
	v_cndmask_b32_e32 v4, v6, v12, vcc_lo
	v_cmp_lt_u64_e32 vcc_lo, v[5:6], v[9:10]
	v_cndmask_b32_e64 v3, 0, 1, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v8, vcc_lo
	v_cmpx_ne_u32_e32 0, v4
	s_cbranch_execz .LBB0_2
; %bb.1:
	global_atomic_add_u32 v5, v[1:2], v4, off offset:4 glc
	s_waitcnt vmcnt(0)
	v_not_b32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, v4, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b32 s2, s[0:1], 0x20
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v3
	s_cbranch_execz .LBB0_4
; %bb.3:
	global_atomic_add_u32 v1, v[1:2], v3, off offset:8 glc
	s_waitcnt vmcnt(0)
	v_not_b32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, v3, v1
	s_or_not1_b32 s3, vcc_lo, exec_lo
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, 3, v0
	s_xor_b32 s0, s3, -1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_b32 s0, s0, vcc_lo
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.5:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v2, 4, v0
	v_add_co_u32 v0, vcc_lo, s10, v3
	v_mov_b32_e32 v3, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v4, vcc_lo
.LBB0_6:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_atomic_add_u32 v4, v[0:1], v3, off glc
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	v_add_co_u32 v0, s1, v0, 4
	v_add_nc_u32_e32 v2, 1, v2
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s0, -1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, vcc_lo
	v_add_co_ci_u32_e64 v1, vcc_lo, 0, v1, s1
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s3, s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_6
.LBB0_7:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9GarnerGPUPjS_S_S_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9GarnerGPUPjS_S_S_j, .Lfunc_end0-_Z9GarnerGPUPjS_S_S_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1684
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9GarnerGPUPjS_S_S_j
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9GarnerGPUPjS_S_S_j.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
