#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <assert.h>
//#include "benchmark.h"

//Macros
#define min(a, b) ( (a)<(b)? (a): (b) )
#define max(a, b) ( (a)>(b)? (a): (b) )

//Constants
#define MAX_VECTOR_COUNT 5

//Vector structure
typedef struct {
	float e[3];
}Vec3f;

//Global array
Vec3f vecArray[MAX_VECTOR_COUNT];
Vec3f newvecArray[MAX_VECTOR_COUNT];

//forward declarations
__global__ void reduce(Vec3f *input, Vec3f *output);

int 
main(int argc, char** argv){

	vecArray[0].e[0] =   1.0; vecArray[0].e[1] =   2.0; vecArray[0].e[2] =   3.0;
	vecArray[1].e[0] =   4.0; vecArray[1].e[1] =   5.0; vecArray[1].e[2] =   6.0;
	vecArray[2].e[0] =   7.0; vecArray[2].e[1] =   8.0; vecArray[2].e[2] =   9.0;
	vecArray[3].e[0] =  10.0; vecArray[3].e[1] =  11.0; vecArray[3].e[2] =  12.0;
	vecArray[4].e[0] =  13.0; vecArray[4].e[1] =  14.0; vecArray[4].e[2] =  15.0;
	// NOTE:  the data being operated on are Vec3f's and frange from 0 (black) to 10ish for each rgb.  
	//I think they are the intesities.

	//--------------------------------------------------------------------------------
	//allocate device mem
	Vec3f *ddata, *dbuffer;

	cudaMalloc( &ddata,     MAX_VECTOR_COUNT * sizeof(Vec3f) );
	cudaMalloc( &dbuffer,   MAX_VECTOR_COUNT * sizeof(Vec3f) );   
	cudaMemset( dbuffer, 0, MAX_VECTOR_COUNT * sizeof(Vec3f) );    

	cudaMemcpy( ddata, vecArray, MAX_VECTOR_COUNT * sizeof(Vec3f), cudaMemcpyHostToDevice );

	dim3 gridDim(1,1);
	dim3 blockDim(5,1);

	//Check verArray values going into kernel function
	for (int i = 0 ; i < 5 ; i++){
		for (int j = 0 ; j < 3 ; j ++)
	        	printf("vecArray[%d][%d] = %.3f\n", j,i,vecArray[i].e[j]);
    	}
	printf("\n\n");

	//call the reduction function
	reduce<<< gridDim, blockDim >>> ( ddata, dbuffer );

	//ZERO out newvecArray
    	memset(newvecArray, 0, MAX_VECTOR_COUNT * sizeof(Vec3f));
	cudaMemcpy( newvecArray, dbuffer, MAX_VECTOR_COUNT * sizeof(Vec3f), cudaMemcpyDeviceToHost );
	//Check to see if copied over to newvecArry

	//Check to see if copied over to newvecArry
	printf("Check to see if copied over to newvecArry\n");
	for (int i = 0 ; i < 5 ; i++){
		for (int j = 0 ; j < 3 ; j ++)
	        	printf("newvecArray[%d][%d] = %.3f\n", j,i,newvecArray[i].e[j]);
    	}

	//free device mem
	cudaFree( &ddata );

	//--------------------------------------------------------------------------------
	return 0;
}

__global__ void 
reduce(Vec3f *input, Vec3f *output){
	extern __shared__ Vec3f sdata[];

	// each thread loadsome element from global to shared mem
	unsigned int tid = threadIdx.x;
	unsigned int i   = threadIdx.x + blockIdx.x * blockDim.x;
	sdata[tid] = input[i];
	__syncthreads();

	//perform reduction in shared mem
	for(unsigned int s=1; s < blockDim.x; s *= 2) {
		//int s = 2;
		if(tid % (2*s) == 0){

			sdata[tid].e[0] += sdata[tid + s].e[0];	//summing
			sdata[tid].e[1] += sdata[tid + s].e[1];
			sdata[tid].e[2] += sdata[tid + s].e[2];
/*
			sdata[tid].e[0] = min( sdata[tid].e[0], sdata[tid + s].e[0] );	//min
			sdata[tid].e[1] = min( sdata[tid].e[1], sdata[tid + s].e[1] );
			sdata[tid].e[2] = min( sdata[tid].e[2], sdata[tid + s].e[2] );

			sdata[tid].e[0] = max( sdata[tid].e[0], sdata[tid + s].e[0] );	//max
			sdata[tid].e[1] = max( sdata[tid].e[1], sdata[tid + s].e[1] );
			sdata[tid].e[2] = max( sdata[tid].e[2], sdata[tid + s].e[2] );
*/
		}
		__syncthreads();
	}

	// write result for this block to global mem
	if(tid == 0) output[blockIdx.x] = sdata[0];
}

	.file	"tmpxft_003294c1_00000000-6_reduction_algorithm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_
	.type	_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_, @function
_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z6reduceP5Vec3fS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_, .-_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_
	.globl	_Z6reduceP5Vec3fS0_
	.type	_Z6reduceP5Vec3fS0_, @function
_Z6reduceP5Vec3fS0_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_
	.cfi_endproc
.LFE2053:
	.size	_Z6reduceP5Vec3fS0_, .-_Z6reduceP5Vec3fS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"vecArray[%d][%d] = %.3f\n"
.LC2:
	.string	"\n\n"
.LC3:
	.string	"Check to see if copied over to newvecArry\n"
.LC4:
	.string	"newvecArray[%d][%d] = %.3f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$60, %esi
	leaq	.LC1(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	vecArray(%rip), %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %r12
	movabsq	$4611686019492741120, %rax
	movl	$0x41700000, 56+vecArray(%rip)
	movq	%rax, vecArray(%rip)
	movq	%r12, %rdi
	movabsq	$4647714816524288000, %rax
	movq	%rax, 8+vecArray(%rip)
	movabsq	$4665729215040061440, %rax
	movq	%rax, 16+vecArray(%rip)
	movabsq	$4683743613553737728, %rax
	movq	%rax, 24+vecArray(%rip)
	movabsq	$4692750812811624448, %rax
	movq	%rax, 32+vecArray(%rip)
	movabsq	$4701758012068462592, %rax
	movq	%rax, 40+vecArray(%rip)
	movabsq	$4710765211325300736, %rax
	movq	%rax, 48+vecArray(%rip)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$60, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$60, %edx
	xorl	%esi, %esi
	call	cudaMemset@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$60, %edx
	call	cudaMemcpy@PLT
	movl	$1, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 16(%rsp)
	addq	$4, %rax
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
.L9:
	xorl	%ebp, %ebp
.L10:
	movl	%ebp, %edx
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	movl	%r13d, %ecx
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$3, %rbp
	jne	.L10
	incl	%r13d
	addq	$12, %rbx
	cmpl	$5, %r13d
	jne	.L9
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	36(%rsp), %ecx
	movl	24(%rsp), %esi
	xorl	%r9d, %r9d
	movq	28(%rsp), %rdx
	movq	16(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z33__device_stub__Z6reduceP5Vec3fS0_P5Vec3fS0_
.L12:
	movq	8(%rsp), %rsi
	xorl	%eax, %eax
	movl	$15, %ecx
	xorl	%r13d, %r13d
	leaq	newvecArray(%rip), %rbx
	movl	$60, %edx
	leaq	.LC4(%rip), %r14
	movq	%rbx, %rdi
	rep stosl
	movl	$2, %ecx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L13:
	xorl	%ebp, %ebp
.L14:
	movl	%ebp, %edx
	cvtss2sd	(%rbx,%rbp,4), %xmm0
	movl	%r13d, %ecx
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$3, %rbp
	jne	.L14
	incl	%r13d
	addq	$12, %rbx
	cmpl	$5, %r13d
	jne	.L13
	movq	%r12, %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z6reduceP5Vec3fS0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6reduceP5Vec3fS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	newvecArray
	.bss
	.align 32
	.type	newvecArray, @object
	.size	newvecArray, 60
newvecArray:
	.zero	60
	.globl	vecArray
	.align 32
	.type	vecArray, @object
	.size	vecArray, 60
vecArray:
	.zero	60
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <assert.h>
//#include "benchmark.h"

//Macros
#define min(a, b) ( (a)<(b)? (a): (b) )
#define max(a, b) ( (a)>(b)? (a): (b) )

//Constants
#define MAX_VECTOR_COUNT 5

//Vector structure
typedef struct {
	float e[3];
}Vec3f;

//Global array
Vec3f vecArray[MAX_VECTOR_COUNT];
Vec3f newvecArray[MAX_VECTOR_COUNT];

//forward declarations
__global__ void reduce(Vec3f *input, Vec3f *output);

int 
main(int argc, char** argv){

	vecArray[0].e[0] =   1.0; vecArray[0].e[1] =   2.0; vecArray[0].e[2] =   3.0;
	vecArray[1].e[0] =   4.0; vecArray[1].e[1] =   5.0; vecArray[1].e[2] =   6.0;
	vecArray[2].e[0] =   7.0; vecArray[2].e[1] =   8.0; vecArray[2].e[2] =   9.0;
	vecArray[3].e[0] =  10.0; vecArray[3].e[1] =  11.0; vecArray[3].e[2] =  12.0;
	vecArray[4].e[0] =  13.0; vecArray[4].e[1] =  14.0; vecArray[4].e[2] =  15.0;
	// NOTE:  the data being operated on are Vec3f's and frange from 0 (black) to 10ish for each rgb.  
	//I think they are the intesities.

	//--------------------------------------------------------------------------------
	//allocate device mem
	Vec3f *ddata, *dbuffer;

	hipMalloc( &ddata,     MAX_VECTOR_COUNT * sizeof(Vec3f) );
	hipMalloc( &dbuffer,   MAX_VECTOR_COUNT * sizeof(Vec3f) );   
	hipMemset( dbuffer, 0, MAX_VECTOR_COUNT * sizeof(Vec3f) );    

	hipMemcpy( ddata, vecArray, MAX_VECTOR_COUNT * sizeof(Vec3f), hipMemcpyHostToDevice );

	dim3 gridDim(1,1);
	dim3 blockDim(5,1);

	//Check verArray values going into kernel function
	for (int i = 0 ; i < 5 ; i++){
		for (int j = 0 ; j < 3 ; j ++)
	        	printf("vecArray[%d][%d] = %.3f\n", j,i,vecArray[i].e[j]);
    	}
	printf("\n\n");

	//call the reduction function
	reduce<<< gridDim, blockDim >>> ( ddata, dbuffer );

	//ZERO out newvecArray
    	memset(newvecArray, 0, MAX_VECTOR_COUNT * sizeof(Vec3f));
	hipMemcpy( newvecArray, dbuffer, MAX_VECTOR_COUNT * sizeof(Vec3f), hipMemcpyDeviceToHost );
	//Check to see if copied over to newvecArry

	//Check to see if copied over to newvecArry
	printf("Check to see if copied over to newvecArry\n");
	for (int i = 0 ; i < 5 ; i++){
		for (int j = 0 ; j < 3 ; j ++)
	        	printf("newvecArray[%d][%d] = %.3f\n", j,i,newvecArray[i].e[j]);
    	}

	//free device mem
	hipFree( &ddata );

	//--------------------------------------------------------------------------------
	return 0;
}

__global__ void 
reduce(Vec3f *input, Vec3f *output){
	extern __shared__ Vec3f sdata[];

	// each thread loadsome element from global to shared mem
	unsigned int tid = threadIdx.x;
	unsigned int i   = threadIdx.x + blockIdx.x * blockDim.x;
	sdata[tid] = input[i];
	__syncthreads();

	//perform reduction in shared mem
	for(unsigned int s=1; s < blockDim.x; s *= 2) {
		//int s = 2;
		if(tid % (2*s) == 0){

			sdata[tid].e[0] += sdata[tid + s].e[0];	//summing
			sdata[tid].e[1] += sdata[tid + s].e[1];
			sdata[tid].e[2] += sdata[tid + s].e[2];
/*
			sdata[tid].e[0] = min( sdata[tid].e[0], sdata[tid + s].e[0] );	//min
			sdata[tid].e[1] = min( sdata[tid].e[1], sdata[tid + s].e[1] );
			sdata[tid].e[2] = min( sdata[tid].e[2], sdata[tid + s].e[2] );

			sdata[tid].e[0] = max( sdata[tid].e[0], sdata[tid + s].e[0] );	//max
			sdata[tid].e[1] = max( sdata[tid].e[1], sdata[tid + s].e[1] );
			sdata[tid].e[2] = max( sdata[tid].e[2], sdata[tid + s].e[2] );
*/
		}
		__syncthreads();
	}

	// write result for this block to global mem
	if(tid == 0) output[blockIdx.x] = sdata[0];
}

	.text
	.file	"reduction_algorithm.hip"
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI0_0:
	.long	0x3f800000                      # float 1
	.long	0x40000000                      # float 2
	.long	0x40400000                      # float 3
	.long	0x40800000                      # float 4
.LCPI0_1:
	.long	0x40a00000                      # float 5
	.long	0x40c00000                      # float 6
	.long	0x40e00000                      # float 7
	.long	0x41000000                      # float 8
.LCPI0_2:
	.long	0x41100000                      # float 9
	.long	0x41200000                      # float 10
	.long	0x41300000                      # float 11
	.long	0x41400000                      # float 12
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movaps	.LCPI0_0(%rip), %xmm0           # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
	movaps	%xmm0, vecArray(%rip)
	movl	$vecArray, %r15d
	movaps	.LCPI0_1(%rip), %xmm0           # xmm0 = [5.0E+0,6.0E+0,7.0E+0,8.0E+0]
	movaps	%xmm0, vecArray+16(%rip)
	movaps	.LCPI0_2(%rip), %xmm0           # xmm0 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1]
	movaps	%xmm0, vecArray+32(%rip)
	movabsq	$4710765211325300736, %rax      # imm = 0x4160000041500000
	movq	%rax, vecArray+48(%rip)
	movl	$1097859072, vecArray+56(%rip)  # imm = 0x41700000
	leaq	8(%rsp), %r14
	movl	$60, %esi
	movq	%r14, %rdi
	callq	hipMalloc
	movq	%rsp, %rbx
	movl	$60, %esi
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	xorl	%ebx, %ebx
	movl	$60, %edx
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%r14), %rdi
	movl	$vecArray, %esi
	movl	$60, %edx
	movl	$1, %ecx
	callq	hipMemcpy
.LBB0_1:                                # %.preheader29
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	xorl	%r14d, %r14d
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r14,4), %xmm0
	movl	$.L.str, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB0_2
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rbx
	addq	$12, %r15
	cmpq	$5, %rbx
	jne	.LBB0_1
# %bb.4:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	4(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z21__device_stub__reduceP5Vec3fS0_
.LBB0_6:
	xorps	%xmm0, %xmm0
	movups	%xmm0, newvecArray+44(%rip)
	movaps	%xmm0, newvecArray+32(%rip)
	movaps	%xmm0, newvecArray+16(%rip)
	movaps	%xmm0, newvecArray(%rip)
	movl	$newvecArray, %r15d
	movq	(%rsp), %rsi
	movl	$newvecArray, %edi
	movl	$60, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
.LBB0_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_8 Depth 2
	xorl	%r14d, %r14d
.LBB0_8:                                #   Parent Loop BB0_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r14,4), %xmm0
	movl	$.L.str.3, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movb	$1, %al
	callq	printf
	incq	%r14
	cmpq	$3, %r14
	jne	.LBB0_8
# %bb.9:                                #   in Loop: Header=BB0_7 Depth=1
	incq	%rbx
	addq	$12, %r15
	cmpq	$5, %rbx
	jne	.LBB0_7
# %bb.10:
	leaq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__reduceP5Vec3fS0_ # -- Begin function _Z21__device_stub__reduceP5Vec3fS0_
	.type	_Z21__device_stub__reduceP5Vec3fS0_,@function
_Z21__device_stub__reduceP5Vec3fS0_:    # @_Z21__device_stub__reduceP5Vec3fS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6reduceP5Vec3fS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__reduceP5Vec3fS0_, .Lfunc_end1-_Z21__device_stub__reduceP5Vec3fS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6reduceP5Vec3fS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	vecArray,@object                # @vecArray
	.bss
	.globl	vecArray
	.p2align	4, 0x0
vecArray:
	.zero	60
	.size	vecArray, 60

	.type	newvecArray,@object             # @newvecArray
	.globl	newvecArray
	.p2align	4, 0x0
newvecArray:
	.zero	60
	.size	newvecArray, 60

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"vecArray[%d][%d] = %.3f\n"
	.size	.L.str, 25

	.type	_Z6reduceP5Vec3fS0_,@object     # @_Z6reduceP5Vec3fS0_
	.section	.rodata,"a",@progbits
	.globl	_Z6reduceP5Vec3fS0_
	.p2align	3, 0x0
_Z6reduceP5Vec3fS0_:
	.quad	_Z21__device_stub__reduceP5Vec3fS0_
	.size	_Z6reduceP5Vec3fS0_, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"newvecArray[%d][%d] = %.3f\n"
	.size	.L.str.3, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6reduceP5Vec3fS0_"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\n"
	.size	.Lstr, 2

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Check to see if copied over to newvecArry"
	.size	.Lstr.1, 42

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__reduceP5Vec3fS0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym vecArray
	.addrsig_sym newvecArray
	.addrsig_sym _Z6reduceP5Vec3fS0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6reduceP5Vec3fS0_     ; -- Begin function _Z6reduceP5Vec3fS0_
	.globl	_Z6reduceP5Vec3fS0_
	.p2align	8
	.type	_Z6reduceP5Vec3fS0_,@function
_Z6reduceP5Vec3fS0_:                    ; @_Z6reduceP5Vec3fS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_cmp_lt_u32 s4, 2
	v_mad_u64_u32 v[2:3], null, v1, 12, s[0:1]
	v_mad_u32_u24 v1, v0, 12, 0
	global_load_b96 v[2:4], v[2:3], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b32 v1, v2, v3 offset1:1
	ds_store_b32 v1, v4 offset:8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph
	s_mov_b32 s5, 1
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s5, 1
	s_add_i32 s1, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, s1, v0
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[2:3], null, s5, 12, v[1:2]
	ds_load_2addr_b32 v[3:4], v2 offset1:1
	ds_load_2addr_b32 v[5:6], v1 offset1:1
	ds_load_b32 v7, v1 offset:8
	ds_load_b32 v2, v2 offset:8
	s_waitcnt lgkmcnt(2)
	v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v7
	ds_store_2addr_b32 v1, v3, v4 offset1:1
	ds_store_b32 v1, v2 offset:8
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_ge_u32 s0, s4
	s_mov_b32 s5, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_mov_b32_e32 v3, 0
	s_mul_i32 s0, s15, 12
	s_mul_hi_u32 s1, s15, 12
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v2, v3 offset:8
	ds_load_2addr_b32 v[0:1], v3 offset1:1
	s_waitcnt lgkmcnt(0)
	global_store_b96 v3, v[0:2], s[0:1]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6reduceP5Vec3fS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6reduceP5Vec3fS0_, .Lfunc_end0-_Z6reduceP5Vec3fS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 16
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6reduceP5Vec3fS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z6reduceP5Vec3fS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
