
/* This is a automatically generated test. Do not modify */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float* var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
  if (comp > (var_2 + -1.5747E-35f)) {
    comp += coshf((+0.0f / +1.3473E-43f));
if (comp >= -1.3494E36f - (-0.0f * (+1.7416E-44f - var_5))) {
  comp += asinf((var_6 + var_7));
float tmp_1 = -0.0f + (+0.0f * var_8);
float tmp_2 = -1.9823E34f / +0.0f - var_9;
comp = tmp_2 * tmp_1 + (var_10 * var_11);
}
for (int i=0; i < var_3; ++i) {
  var_12[i] = var_13 + var_14 * fabsf((var_15 - var_16 * ldexpf(floorf(tanhf((-1.9774E-35f * var_17 + var_18))), 2)));
float tmp_3 = +1.5409E26f;
comp = tmp_3 / var_12[i] / -1.2900E-35f + var_19 / (var_20 / (-1.3379E-15f - -1.8224E-35f - var_21));
}
for (int i=0; i < var_4; ++i) {
  var_22[i] = sinhf(acosf(var_24 + +1.4771E-35f));
var_23[i] = +1.8351E-35f * (-1.0405E10f * (var_25 / (var_26 * fmodf((-1.5535E35f + -1.3174E-24f * -1.2706E-41f - (-1.4619E-35f - var_27)), (var_28 + (var_29 - (var_30 / ceilf(+1.0588E-43f))))))));
comp += var_23[i] + var_22[i] + powf(var_31 - (var_32 / -1.1886E34f * -0.0f - (var_33 - +0.0f)), -1.0284E-35f);
}
}
}
   printf("%.17g\n", comp);

}

float* initPointer(float v) {
  float *ret = (float*) malloc(sizeof(float)*10);
  for(int i=0; i < 10; ++i)
    ret[i] = v;
  return ret;
}

int main(int argc, char** argv) {
/* Program variables */

  float tmp_1 = atof(argv[1]);
  int tmp_2 = atoi(argv[2]);
  float tmp_3 = atof(argv[3]);
  int tmp_4 = atoi(argv[4]);
  int tmp_5 = atoi(argv[5]);
  float tmp_6 = atof(argv[6]);
  float tmp_7 = atof(argv[7]);
  float tmp_8 = atof(argv[8]);
  float tmp_9 = atof(argv[9]);
  float tmp_10 = atof(argv[10]);
  float tmp_11 = atof(argv[11]);
  float tmp_12 = atof(argv[12]);
  float* tmp_13 = initPointer( atof(argv[13]) );
  float tmp_14 = atof(argv[14]);
  float tmp_15 = atof(argv[15]);
  float tmp_16 = atof(argv[16]);
  float tmp_17 = atof(argv[17]);
  float tmp_18 = atof(argv[18]);
  float tmp_19 = atof(argv[19]);
  float tmp_20 = atof(argv[20]);
  float tmp_21 = atof(argv[21]);
  float tmp_22 = atof(argv[22]);
  float* tmp_23 = initPointer( atof(argv[23]) );
  float* tmp_24 = initPointer( atof(argv[24]) );
  float tmp_25 = atof(argv[25]);
  float tmp_26 = atof(argv[26]);
  float tmp_27 = atof(argv[27]);
  float tmp_28 = atof(argv[28]);
  float tmp_29 = atof(argv[29]);
  float tmp_30 = atof(argv[30]);
  float tmp_31 = atof(argv[31]);
  float tmp_32 = atof(argv[32]);
  float tmp_33 = atof(argv[33]);
  float tmp_34 = atof(argv[34]);

  compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
  cudaDeviceSynchronize();

  return 0;
}

	.file	"tmpxft_00299895_00000000-6_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11initPointerf
	.type	_Z11initPointerf, @function
_Z11initPointerf:
.LFB2027:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$40, %edi
	movss	%xmm0, 12(%rsp)
	call	malloc@PLT
	movss	12(%rsp), %xmm0
	xorl	%edx, %edx
.L3:
	movss	%xmm0, (%rax,%rdx,4)
	incq	%rdx
	cmpq	$10, %rdx
	jne	.L3
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11initPointerf, .-_Z11initPointerf
	.globl	_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff
	.type	_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff, @function
_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$440, %rsp
	.cfi_def_cfa_offset 448
	movl	%edi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movl	%edx, 60(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 76(%rsp)
	movss	%xmm1, 68(%rsp)
	movss	%xmm2, 56(%rsp)
	movss	%xmm3, 52(%rsp)
	movss	%xmm4, 48(%rsp)
	movss	%xmm5, 44(%rsp)
	movss	%xmm6, 40(%rsp)
	movss	%xmm7, 36(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 424(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	480(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	488(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	496(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	504(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	512(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	520(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	528(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	536(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	544(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	552(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	560(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	568(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	576(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	584(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	592(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	600(%rsp), %rax
	movq	%rax, 416(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	96(%rsp)
	.cfi_def_cfa_offset 456
	leaq	_Z7computefifiifffffffPffffffffffS_S_ffffffffff(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 464
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 456
	popq	%rdx
	.cfi_def_cfa_offset 448
.L7:
	movq	424(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$440, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff, .-_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff
	.globl	_Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.type	_Z7computefifiifffffffPffffffffffS_S_ffffffffff, @function
_Z7computefifiifffffffPffffffffffS_S_ffffffffff:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff
	.cfi_endproc
.LFE2054:
	.size	_Z7computefifiifffffffPffffffffffS_S_ffffffffff, .-_Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	8(%rsi), %rdi
	call	atof@PLT
	movq	16(%rbx), %rdi
	movsd	%xmm0, 232(%rsp)
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, 116(%rsp)
	call	atof@PLT
	movq	32(%rbx), %rdi
	movsd	%xmm0, 224(%rsp)
	call	atoi@PLT
	movq	40(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movq	48(%rbx), %rdi
	movl	%eax, %r12d
	call	atof@PLT
	movq	56(%rbx), %rdi
	movsd	%xmm0, 216(%rsp)
	call	atof@PLT
	movq	64(%rbx), %rdi
	movsd	%xmm0, 208(%rsp)
	call	atof@PLT
	movq	72(%rbx), %rdi
	movsd	%xmm0, 200(%rsp)
	call	atof@PLT
	movq	80(%rbx), %rdi
	movsd	%xmm0, 192(%rsp)
	call	atof@PLT
	movq	88(%rbx), %rdi
	movsd	%xmm0, 184(%rsp)
	call	atof@PLT
	movq	96(%rbx), %rdi
	movsd	%xmm0, 176(%rsp)
	call	atof@PLT
	movsd	%xmm0, 8(%rsp)
	movq	104(%rbx), %rdi
	call	atof@PLT
	cvtsd2ss	%xmm0, %xmm0
	call	_Z11initPointerf
	movq	112(%rbx), %rdi
	movq	%rax, %r13
	call	atof@PLT
	movq	120(%rbx), %rdi
	movsd	%xmm0, 16(%rsp)
	call	atof@PLT
	movq	128(%rbx), %rdi
	movsd	%xmm0, 24(%rsp)
	call	atof@PLT
	movq	136(%rbx), %rdi
	movsd	%xmm0, 32(%rsp)
	call	atof@PLT
	movq	144(%rbx), %rdi
	movsd	%xmm0, 40(%rsp)
	call	atof@PLT
	movq	152(%rbx), %rdi
	movsd	%xmm0, 48(%rsp)
	call	atof@PLT
	movq	160(%rbx), %rdi
	movsd	%xmm0, 56(%rsp)
	call	atof@PLT
	movq	168(%rbx), %rdi
	movsd	%xmm0, 64(%rsp)
	call	atof@PLT
	movq	176(%rbx), %rdi
	movsd	%xmm0, 72(%rsp)
	call	atof@PLT
	movq	184(%rbx), %rdi
	movsd	%xmm0, 80(%rsp)
	call	atof@PLT
	cvtsd2ss	%xmm0, %xmm0
	call	_Z11initPointerf
	movq	192(%rbx), %rdi
	movq	%rax, %r14
	call	atof@PLT
	cvtsd2ss	%xmm0, %xmm0
	call	_Z11initPointerf
	movq	200(%rbx), %rdi
	movq	%rax, %r15
	call	atof@PLT
	movq	208(%rbx), %rdi
	movsd	%xmm0, 88(%rsp)
	call	atof@PLT
	movq	216(%rbx), %rdi
	movsd	%xmm0, 96(%rsp)
	call	atof@PLT
	movq	224(%rbx), %rdi
	movsd	%xmm0, 104(%rsp)
	call	atof@PLT
	movq	232(%rbx), %rdi
	movsd	%xmm0, 168(%rsp)
	call	atof@PLT
	movq	240(%rbx), %rdi
	movsd	%xmm0, 160(%rsp)
	call	atof@PLT
	movq	248(%rbx), %rdi
	movsd	%xmm0, 152(%rsp)
	call	atof@PLT
	movq	256(%rbx), %rdi
	movsd	%xmm0, 144(%rsp)
	call	atof@PLT
	movq	264(%rbx), %rdi
	movsd	%xmm0, 136(%rsp)
	call	atof@PLT
	movq	272(%rbx), %rdi
	movsd	%xmm0, 128(%rsp)
	call	atof@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movsd	%xmm0, 120(%rsp)
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	movsd	120(%rsp), %xmm14
	movsd	128(%rsp), %xmm13
	movsd	136(%rsp), %xmm12
	testl	%eax, %eax
	movsd	144(%rsp), %xmm11
	movsd	152(%rsp), %xmm10
	movsd	160(%rsp), %xmm9
	movsd	168(%rsp), %xmm8
	movsd	176(%rsp), %xmm7
	movsd	184(%rsp), %xmm6
	movsd	192(%rsp), %xmm5
	movsd	200(%rsp), %xmm4
	movsd	208(%rsp), %xmm3
	movsd	216(%rsp), %xmm2
	movsd	224(%rsp), %xmm1
	movsd	232(%rsp), %xmm15
	jne	.L13
	subq	$160, %rsp
	.cfi_def_cfa_offset 496
	cvtsd2ss	%xmm14, %xmm14
	cvtsd2ss	%xmm13, %xmm13
	cvtsd2ss	%xmm12, %xmm12
	cvtsd2ss	%xmm11, %xmm11
	movq	%r15, %r9
	movq	%r14, %r8
	movq	%r13, %rcx
	movss	%xmm14, 152(%rsp)
	movl	%r12d, %edx
	movl	%ebp, %esi
	cvtsd2ss	%xmm10, %xmm10
	cvtsd2ss	%xmm9, %xmm9
	movss	%xmm10, 120(%rsp)
	cvtsd2ss	%xmm8, %xmm8
	cvtsd2ss	%xmm15, %xmm0
	movss	%xmm9, 112(%rsp)
	cvtsd2ss	%xmm7, %xmm7
	cvtsd2ss	%xmm6, %xmm6
	cvtsd2ss	%xmm5, %xmm5
	movss	%xmm8, 104(%rsp)
	cvtsd2ss	%xmm4, %xmm4
	cvtsd2ss	%xmm3, %xmm3
	cvtsd2ss	264(%rsp), %xmm8
	movss	%xmm8, 96(%rsp)
	cvtsd2ss	%xmm2, %xmm2
	cvtsd2ss	%xmm1, %xmm1
	cvtsd2ss	256(%rsp), %xmm8
	movss	%xmm13, 144(%rsp)
	movss	%xmm12, 136(%rsp)
	movss	%xmm11, 128(%rsp)
	movss	%xmm8, 88(%rsp)
	cvtsd2ss	248(%rsp), %xmm8
	movss	%xmm8, 80(%rsp)
	cvtsd2ss	240(%rsp), %xmm8
	movss	%xmm8, 72(%rsp)
	cvtsd2ss	232(%rsp), %xmm8
	movss	%xmm8, 64(%rsp)
	cvtsd2ss	224(%rsp), %xmm8
	movss	%xmm8, 56(%rsp)
	cvtsd2ss	216(%rsp), %xmm8
	movss	%xmm8, 48(%rsp)
	cvtsd2ss	208(%rsp), %xmm8
	movss	%xmm8, 40(%rsp)
	cvtsd2ss	200(%rsp), %xmm8
	movss	%xmm8, 32(%rsp)
	cvtsd2ss	192(%rsp), %xmm8
	movss	%xmm8, 24(%rsp)
	cvtsd2ss	184(%rsp), %xmm8
	movss	%xmm8, 16(%rsp)
	cvtsd2ss	176(%rsp), %xmm8
	movss	%xmm8, 8(%rsp)
	cvtsd2ss	168(%rsp), %xmm8
	movl	276(%rsp), %edi
	movss	%xmm8, (%rsp)
	call	_Z61__device_stub__Z7computefifiifffffffPffffffffffS_S_fffffffffffifiifffffffPffffffffffS_S_ffffffffff
	addq	$160, %rsp
	.cfi_def_cfa_offset 336
.L13:
	call	cudaDeviceSynchronize@PLT
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7computefifiifffffffPffffffffffS_S_ffffffffff"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7computefifiifffffffPffffffffffS_S_ffffffffff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


/* This is a automatically generated test. Do not modify */


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

__global__
void compute(float comp, int var_1,float var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float* var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float* var_22,float* var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
for (int i=0; i < var_1; ++i) {
  if (comp > (var_2 + -1.5747E-35f)) {
    comp += coshf((+0.0f / +1.3473E-43f));
if (comp >= -1.3494E36f - (-0.0f * (+1.7416E-44f - var_5))) {
  comp += asinf((var_6 + var_7));
float tmp_1 = -0.0f + (+0.0f * var_8);
float tmp_2 = -1.9823E34f / +0.0f - var_9;
comp = tmp_2 * tmp_1 + (var_10 * var_11);
}
for (int i=0; i < var_3; ++i) {
  var_12[i] = var_13 + var_14 * fabsf((var_15 - var_16 * ldexpf(floorf(tanhf((-1.9774E-35f * var_17 + var_18))), 2)));
float tmp_3 = +1.5409E26f;
comp = tmp_3 / var_12[i] / -1.2900E-35f + var_19 / (var_20 / (-1.3379E-15f - -1.8224E-35f - var_21));
}
for (int i=0; i < var_4; ++i) {
  var_22[i] = sinhf(acosf(var_24 + +1.4771E-35f));
var_23[i] = +1.8351E-35f * (-1.0405E10f * (var_25 / (var_26 * fmodf((-1.5535E35f + -1.3174E-24f * -1.2706E-41f - (-1.4619E-35f - var_27)), (var_28 + (var_29 - (var_30 / ceilf(+1.0588E-43f))))))));
comp += var_23[i] + var_22[i] + powf(var_31 - (var_32 / -1.1886E34f * -0.0f - (var_33 - +0.0f)), -1.0284E-35f);
}
}
}
   printf("%.17g\n", comp);

}

float* initPointer(float v) {
  float *ret = (float*) malloc(sizeof(float)*10);
  for(int i=0; i < 10; ++i)
    ret[i] = v;
  return ret;
}

int main(int argc, char** argv) {
/* Program variables */

  float tmp_1 = atof(argv[1]);
  int tmp_2 = atoi(argv[2]);
  float tmp_3 = atof(argv[3]);
  int tmp_4 = atoi(argv[4]);
  int tmp_5 = atoi(argv[5]);
  float tmp_6 = atof(argv[6]);
  float tmp_7 = atof(argv[7]);
  float tmp_8 = atof(argv[8]);
  float tmp_9 = atof(argv[9]);
  float tmp_10 = atof(argv[10]);
  float tmp_11 = atof(argv[11]);
  float tmp_12 = atof(argv[12]);
  float* tmp_13 = initPointer( atof(argv[13]) );
  float tmp_14 = atof(argv[14]);
  float tmp_15 = atof(argv[15]);
  float tmp_16 = atof(argv[16]);
  float tmp_17 = atof(argv[17]);
  float tmp_18 = atof(argv[18]);
  float tmp_19 = atof(argv[19]);
  float tmp_20 = atof(argv[20]);
  float tmp_21 = atof(argv[21]);
  float tmp_22 = atof(argv[22]);
  float* tmp_23 = initPointer( atof(argv[23]) );
  float* tmp_24 = initPointer( atof(argv[24]) );
  float tmp_25 = atof(argv[25]);
  float tmp_26 = atof(argv[26]);
  float tmp_27 = atof(argv[27]);
  float tmp_28 = atof(argv[28]);
  float tmp_29 = atof(argv[29]);
  float tmp_30 = atof(argv[30]);
  float tmp_31 = atof(argv[31]);
  float tmp_32 = atof(argv[32]);
  float tmp_33 = atof(argv[33]);
  float tmp_34 = atof(argv[34]);

  compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
  hipDeviceSynchronize();

  return 0;
}

	.text
	.file	"test.hip"
	.globl	_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff # -- Begin function _Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
	.type	_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff,@function
_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff: # @_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$408, %rsp                      # imm = 0x198
	.cfi_def_cfa_offset 464
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	52(%rsp), %r11
	movl	%edi, (%r11)
	leaq	48(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	44(%rsp), %r14
	movl	%esi, (%r14)
	leaq	40(%rsp), %rdi
	movl	%edx, (%rdi)
	leaq	36(%rsp), %rsi
	movss	%xmm2, (%rsi)
	leaq	32(%rsp), %r15
	movss	%xmm3, (%r15)
	leaq	28(%rsp), %r12
	movss	%xmm4, (%r12)
	leaq	24(%rsp), %r13
	movss	%xmm5, (%r13)
	leaq	20(%rsp), %rbp
	movss	%xmm6, (%rbp)
	leaq	16(%rsp), %rax
	movss	%xmm7, (%rax)
	leaq	88(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rcx
	movq	%r8, (%rcx)
	movq	%rcx, %r8
	leaq	72(%rsp), %rcx
	movq	%r9, (%rcx)
	leaq	128(%rsp), %rbx
	leaq	12(%rsp), %r9
	movq	%r9, (%rbx)
	movq	%r11, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%r14, 24(%rbx)
	movq	%rdi, 32(%rbx)
	movq	%rsi, 40(%rbx)
	movq	%r15, 48(%rbx)
	movq	%r12, 56(%rbx)
	movq	%r13, 64(%rbx)
	movq	%rbp, 72(%rbx)
	movq	%rax, 80(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%rdx, 96(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	512(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	520(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	528(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	536(%rsp), %rax
	movq	%rax, 168(%rbx)
	movq	%r8, 176(%rbx)
	movq	%rcx, 184(%rbx)
	leaq	544(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	552(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	560(%rsp), %rax
	movq	%rax, 208(%rbx)
	leaq	568(%rsp), %rax
	movq	%rax, 216(%rbx)
	leaq	576(%rsp), %rax
	movq	%rax, 224(%rbx)
	leaq	584(%rsp), %rax
	movq	%rax, 232(%rbx)
	leaq	592(%rsp), %rax
	movq	%rax, 240(%rbx)
	leaq	600(%rsp), %rax
	movq	%rax, 248(%rbx)
	leaq	608(%rsp), %rax
	movq	%rax, 256(%rbx)
	leaq	616(%rsp), %rax
	movq	%rax, 264(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	64(%rsp), %r12
	leaq	56(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7computefifiifffffffPffffffffffS_S_ffffffffff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$424, %rsp                      # imm = 0x1A8
	.cfi_adjust_cfa_offset -424
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff, .Lfunc_end0-_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
	.cfi_endproc
                                        # -- End function
	.globl	_Z11initPointerf                # -- Begin function _Z11initPointerf
	.type	_Z11initPointerf,@function
_Z11initPointerf:                       # @_Z11initPointerf
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	xorl	%ecx, %ecx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%rax,%rcx,4)
	incq	%rcx
	cmpq	$10, %rcx
	jne	.LBB1_1
# %bb.2:
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z11initPointerf, .Lfunc_end1-_Z11initPointerf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$392, %rsp                      # imm = 0x188
	.cfi_def_cfa_offset 448
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r15
	movq	8(%rsi), %rdi
	callq	atof
	movsd	%xmm0, 384(%rsp)                # 8-byte Spill
	movq	16(%r15), %rdi
	callq	atoi
	movl	%eax, 260(%rsp)                 # 4-byte Spill
	movq	24(%r15), %rdi
	callq	atof
	movsd	%xmm0, 376(%rsp)                # 8-byte Spill
	movq	32(%r15), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	40(%r15), %rdi
	callq	atoi
	movl	%eax, %r14d
	movq	48(%r15), %rdi
	callq	atof
	movsd	%xmm0, 368(%rsp)                # 8-byte Spill
	movq	56(%r15), %rdi
	callq	atof
	movsd	%xmm0, 248(%rsp)                # 8-byte Spill
	movq	64(%r15), %rdi
	callq	atof
	movsd	%xmm0, 240(%rsp)                # 8-byte Spill
	movq	72(%r15), %rdi
	callq	atof
	movsd	%xmm0, 232(%rsp)                # 8-byte Spill
	movq	80(%r15), %rdi
	callq	atof
	movsd	%xmm0, 224(%rsp)                # 8-byte Spill
	movq	88(%r15), %rdi
	callq	atof
	movsd	%xmm0, 360(%rsp)                # 8-byte Spill
	movq	96(%r15), %rdi
	callq	atof
	movsd	%xmm0, 216(%rsp)                # 8-byte Spill
	movq	104(%r15), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 160(%rsp)                # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	160(%rsp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %r12
	xorl	%eax, %eax
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_1
# %bb.2:                                # %_Z11initPointerf.exit
	movq	112(%r15), %rdi
	callq	atof
	movsd	%xmm0, 208(%rsp)                # 8-byte Spill
	movq	120(%r15), %rdi
	callq	atof
	movsd	%xmm0, 200(%rsp)                # 8-byte Spill
	movq	128(%r15), %rdi
	callq	atof
	movsd	%xmm0, 192(%rsp)                # 8-byte Spill
	movq	136(%r15), %rdi
	callq	atof
	movsd	%xmm0, 184(%rsp)                # 8-byte Spill
	movq	144(%r15), %rdi
	callq	atof
	movsd	%xmm0, 176(%rsp)                # 8-byte Spill
	movq	152(%r15), %rdi
	callq	atof
	movsd	%xmm0, 168(%rsp)                # 8-byte Spill
	movq	160(%r15), %rdi
	callq	atof
	movsd	%xmm0, 352(%rsp)                # 8-byte Spill
	movq	168(%r15), %rdi
	callq	atof
	movsd	%xmm0, 344(%rsp)                # 8-byte Spill
	movq	176(%r15), %rdi
	callq	atof
	movsd	%xmm0, 336(%rsp)                # 8-byte Spill
	movq	184(%r15), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 160(%rsp)                # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	160(%rsp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %r13
	xorl	%eax, %eax
.LBB2_3:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%r13,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_3
# %bb.4:                                # %_Z11initPointerf.exit72
	movq	192(%r15), %rdi
	callq	atof
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 160(%rsp)                # 4-byte Spill
	movl	$40, %edi
	callq	malloc
	movss	160(%rsp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.LBB2_5
# %bb.6:                                # %_Z11initPointerf.exit76
	movq	200(%r15), %rdi
	callq	atof
	movsd	%xmm0, 160(%rsp)                # 8-byte Spill
	movq	208(%r15), %rdi
	callq	atof
	movsd	%xmm0, 328(%rsp)                # 8-byte Spill
	movq	216(%r15), %rdi
	callq	atof
	movsd	%xmm0, 320(%rsp)                # 8-byte Spill
	movq	224(%r15), %rdi
	callq	atof
	movsd	%xmm0, 312(%rsp)                # 8-byte Spill
	movq	232(%r15), %rdi
	callq	atof
	movsd	%xmm0, 304(%rsp)                # 8-byte Spill
	movq	240(%r15), %rdi
	callq	atof
	movsd	%xmm0, 296(%rsp)                # 8-byte Spill
	movq	248(%r15), %rdi
	callq	atof
	movsd	%xmm0, 288(%rsp)                # 8-byte Spill
	movq	256(%r15), %rdi
	callq	atof
	movsd	%xmm0, 280(%rsp)                # 8-byte Spill
	movq	264(%r15), %rdi
	callq	atof
	movsd	%xmm0, 272(%rsp)                # 8-byte Spill
	movq	272(%r15), %rdi
	callq	atof
	movsd	%xmm0, 264(%rsp)                # 8-byte Spill
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	cvtsd2ss	264(%rsp), %xmm8                # 8-byte Folded Reload
	cvtsd2ss	272(%rsp), %xmm9                # 8-byte Folded Reload
	cvtsd2ss	280(%rsp), %xmm10               # 8-byte Folded Reload
	cvtsd2ss	288(%rsp), %xmm11               # 8-byte Folded Reload
	cvtsd2ss	296(%rsp), %xmm12               # 8-byte Folded Reload
	cvtsd2ss	304(%rsp), %xmm13               # 8-byte Folded Reload
	cvtsd2ss	312(%rsp), %xmm14               # 8-byte Folded Reload
	cvtsd2ss	320(%rsp), %xmm15               # 8-byte Folded Reload
	cvtsd2ss	328(%rsp), %xmm3                # 8-byte Folded Reload
	cvtsd2ss	160(%rsp), %xmm4                # 8-byte Folded Reload
	cvtsd2ss	336(%rsp), %xmm5                # 8-byte Folded Reload
	cvtsd2ss	344(%rsp), %xmm6                # 8-byte Folded Reload
	cvtsd2ss	352(%rsp), %xmm7                # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsd2ss	168(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 168(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	176(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 176(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	184(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 184(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	192(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 192(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	200(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 200(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	208(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 208(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	216(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 216(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	360(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 160(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	224(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 224(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	232(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 232(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	240(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 240(%rsp)                # 4-byte Spill
	xorps	%xmm0, %xmm0
	cvtsd2ss	248(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm0, 248(%rsp)                # 4-byte Spill
	cvtsd2ss	368(%rsp), %xmm2                # 8-byte Folded Reload
	cvtsd2ss	376(%rsp), %xmm1                # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsd2ss	384(%rsp), %xmm0                # 8-byte Folded Reload
	movss	%xmm8, 152(%rsp)
	movss	%xmm9, 144(%rsp)
	movss	%xmm10, 136(%rsp)
	movss	%xmm11, 128(%rsp)
	movss	%xmm12, 120(%rsp)
	movss	%xmm13, 112(%rsp)
	movss	%xmm14, 104(%rsp)
	movss	%xmm15, 96(%rsp)
	movss	%xmm3, 88(%rsp)
	movss	%xmm4, 80(%rsp)
	movss	%xmm5, 72(%rsp)
	movss	%xmm6, 64(%rsp)
	movss	%xmm7, 56(%rsp)
	movss	168(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 48(%rsp)
	movss	176(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 40(%rsp)
	movss	184(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 32(%rsp)
	movss	192(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 24(%rsp)
	movss	200(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 16(%rsp)
	movss	208(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, 8(%rsp)
	movss	216(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	%xmm3, (%rsp)
	movl	260(%rsp), %edi                 # 4-byte Reload
	movl	%ebp, %esi
	movl	%r14d, %edx
	movss	248(%rsp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	240(%rsp), %xmm4                # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	232(%rsp), %xmm5                # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	movss	224(%rsp), %xmm6                # 4-byte Reload
                                        # xmm6 = mem[0],zero,zero,zero
	movss	160(%rsp), %xmm7                # 4-byte Reload
                                        # xmm7 = mem[0],zero,zero,zero
	movq	%r12, %rcx
	movq	%r13, %r8
	movq	%rbx, %r9
	callq	_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
.LBB2_8:
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	addq	$392, %rsp                      # imm = 0x188
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7computefifiifffffffPffffffffffS_S_ffffffffff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7computefifiifffffffPffffffffffS_S_ffffffffff,@object # @_Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.section	.rodata,"a",@progbits
	.globl	_Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.p2align	3, 0x0
_Z7computefifiifffffffPffffffffffS_S_ffffffffff:
	.quad	_Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
	.size	_Z7computefifiifffffffPffffffffffS_S_ffffffffff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7computefifiifffffffPffffffffffS_S_ffffffffff"
	.size	.L__unnamed_1, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__computefifiifffffffPffffffffffS_S_ffffffffff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7computefifiifffffffPffffffffffS_S_ffffffffff ; -- Begin function _Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.globl	_Z7computefifiifffffffPffffffffffS_S_ffffffffff
	.p2align	8
	.type	_Z7computefifiifffffffPffffffffffS_S_ffffffffff,@function
_Z7computefifiifffffffPffffffffffS_S_ffffffffff: ; @_Z7computefifiifffffffPffffffffffS_S_ffffffffff
; %bb.0:
	s_load_b128 s[24:27], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v31, s24
	s_cmp_lt_i32 s25, 1
	s_cbranch_scc1 .LBB0_14
; %bb.1:                                ; %.lr.ph103
	s_clause 0x4
	s_load_b32 s2, s[0:1], 0x58
	s_load_b256 s[16:23], s[0:1], 0x38
	s_load_b128 s[28:31], s[0:1], 0x60
	s_load_b256 s[8:15], s[0:1], 0x70
	s_load_b64 s[4:5], s[0:1], 0x90
	s_mov_b32 s3, 0x3d1c21a7
	s_cmp_gt_i32 s27, 0
	s_load_b64 s[36:37], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v0, 0xa6c0cfcc, s2
	s_mov_b32 s2, 0xf812819a
	v_add_f32_e64 v18, 0x59b74b4, s11
	v_sub_f32_e64 v20, s13, s14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, v0, v0, s23
	v_div_scale_f32 v4, vcc_lo, s23, v0, s23
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v2
	v_mul_f32_e32 v3, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v1, v3, v4
	v_fmac_f32_e32 v3, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v3, v4
	v_div_fmas_f32 v1, v1, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v4, v1, v0, s23
	v_add_f32_e64 v0, 0x59d127d, s8
	v_div_scale_f32 v1, null, s2, s2, s4
	s_mov_b32 s8, 0x3e76c4e1
	v_div_scale_f32 v2, null, v4, v4, s22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v3, |v0|, -0.5, 0.5
	v_mul_f32_e32 v5, v0, v0
	v_cmp_gt_f32_e64 s2, |v0|, 0.5
	v_rcp_f32_e32 v6, v2
	v_div_scale_f32 v11, vcc_lo, s22, v4, s22
	v_rcp_f32_e32 v7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v5, v3, s2
	v_sqrt_f32_e32 v12, v3
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v9, -v2, v6, 1.0
	v_fmaak_f32 v5, s3, v3, 0x3c5fc5da
	v_div_scale_f32 v8, s3, s4, 0xf812819a, s4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v1, v7, 1.0
	v_dual_fmac_f32 v6, v9, v6 :: v_dual_fmaak_f32 v5, v3, v5, 0x3d034c3c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, v11, v6
	v_fmaak_f32 v5, v3, v5, 0x3d3641b1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v2, v9, v11
	v_fmaak_f32 v5, v3, v5, 0x3d999bc8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v13, v6
	v_fmaak_f32 v5, v3, v5, 0x3e2aaaac
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v2, v9, v11
	v_mul_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v6, v2, v6, v9
	v_fmac_f32_e32 v12, v12, v3
	v_fmac_f32_e32 v7, v10, v7
	s_mov_b32 vcc_lo, s3
	s_mov_b32 s3, 0x3ab42872
	v_div_fixup_f32 v6, v6, v4, s22
	v_add_f32_e32 v2, v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v8, v7 :: v_dual_sub_f32 v5, 0x40490fdb, v2
	v_fma_f32 v14, -v1, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v14, v7
	v_fma_f32 v1, -v1, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v1, v1, v7, v10
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_fmac_f32_e32 v0, v0, v3
	v_div_fixup_f32 v1, v1, 0xf812819a, s4
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v0, 0x3fc90fdb, v0
	v_fma_f32 v1, 0x80000000, v1, -s5
	s_clause 0x1
	s_load_b64 s[34:35], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x20
	v_cndmask_b32_e64 v2, v0, v2, s2
	s_mov_b32 s2, 0xbbbac73d
	v_sub_f32_e32 v1, s15, v1
	s_cselect_b32 s15, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e64 v3, 0xbf317218, |v2|
	v_frexp_mant_f32_e64 v0, |v1|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e64 v7, v3, |v2|
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s34, 0
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_cselect_b32 s11, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f32 v0, v0, v5
	v_sub_f32_e32 v5, v7, v3
	v_dual_add_f32 v7, 0x3f317218, v7 :: v_dual_add_f32 v8, 1.0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e64 v5, |v2|, v5
	v_dual_add_f32 v12, -1.0, v8 :: v_dual_sub_f32 v5, v5, v7
	v_add_f32_e32 v7, -1.0, v0
	v_rcp_f32_e32 v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v0, v12 :: v_dual_add_f32 v5, 0x3102e308, v5
	v_add_f32_e32 v11, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fb8aa3b, v11
	v_sub_f32_e32 v3, v3, v11
	v_rndne_f32_e32 v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v3, v5, v3
	v_fmamk_f32 v5, v12, 0xbf317200, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, 0x35bfbc00, v12 :: v_dual_add_f32 v15, v3, v5
	v_sub_f32_e32 v17, v15, v14
	v_sub_f32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v17
	v_add_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v15, v14
	v_sub_f32_e64 v15, 0xff800000, s5
	v_add_f32_e32 v5, v3, v5
	v_mul_f32_e64 v3, s6, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v17, v5
	v_dual_mul_f32 v10, v7, v9 :: v_dual_sub_f32 v17, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v8, v10
	v_fma_f32 v8, v10, v8, -v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v10, v0
	v_add_f32_e64 v0, 0x85a77369, s26
	v_add_f32_e32 v11, v13, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v7, v11
	v_sub_f32_e32 v13, v11, v13
	v_sub_f32_e32 v7, v7, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v8, v13, v8
	v_mul_f32_e32 v13, 0x2ea39ef3, v12
	v_cvt_i32_f32_e32 v12, v12
	v_sub_f32_e32 v7, v7, v11
	v_mul_f32_e64 v11, s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v8, v7
	v_fmac_f32_e32 v3, v11, v15
	v_sub_f32_e64 v8, 12, s35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v16, v7 :: v_dual_sub_f32 v16, v14, v13
	v_mul_f32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v9, s21 :: v_dual_sub_f32 v14, v14, v16
	v_add_f32_e32 v19, v10, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmamk_f32 v9, s20, 0x85d245f3, v9
	v_dual_sub_f32 v13, v14, v13 :: v_dual_add_f32 v14, 0xf9ef5ac5, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v19, v10
	v_add_f32_e64 v18, |v9|, |v9|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e64 v27, |v14|
	v_frexp_exp_i32_f32_e32 v23, v14
	v_sub_f32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v32, 0x3fb8aa3b, v18 :: v_dual_add_f32 v17, v5, v17
	v_readfirstlane_b32 s4, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v17, v13
	v_add_f32_e32 v15, v16, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v31, s24 :: v_dual_mul_f32 v22, v15, v15
	v_sub_f32_e32 v16, v16, v15
	v_fma_f32 v25, v15, v15, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v16
	v_fmaak_f32 v16, s3, v15, 0x3c091de6
	v_add_f32_e32 v26, v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v16, v15, v16, 0x3d2aadcc
	v_fmac_f32_e32 v25, v15, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v16, v15, v16, 0x3e2aaa47
	v_add_f32_e32 v30, v22, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v16, v15, v16, 0x3efffffc
	v_sub_f32_e32 v22, v30, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v33, v16, v30
	v_sub_f32_e32 v22, v25, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v25, v30, v16, -v33
	v_rndne_f32_e32 v30, v32
	v_dual_fmaak_f32 v5, 0, v8, 0xfb81f147 :: v_dual_mul_f32 v8, v19, v19
	v_dual_fmac_f32 v25, v22, v16 :: v_dual_sub_f32 v16, v32, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v19, v19, -v8
	v_dual_add_f32 v36, v33, v25 :: v_dual_add_f32 v13, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v19, v13
	v_add_f32_e32 v21, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v24, s8, v21, 0x3e91f4c4
	v_sub_f32_e32 v8, v21, v8
	v_fmaak_f32 v24, v21, v24, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v11, v8
	v_mul_f32_e32 v26, v21, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v21, v24, -v26
	v_fmac_f32_e32 v11, v8, v24
	v_fma_f32 v24, 0x3fb8aa3b, v18, -v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v35, v26, v11 :: v_dual_fmac_f32 v24, 0x32a5705f, v18
	v_sub_f32_e32 v22, v35, v26
	v_dual_add_f32 v26, 0x3f2aaaaa, v35 :: v_dual_add_f32 v17, s12, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v16, v16, v24
	v_bfi_b32 v20, 0x7fffffff, 0, v14
	v_sub_f32_e32 v11, v11, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v22, 0xbf2aaaaa, v26 :: v_dual_mul_f32 v13, v9, v9
	v_exp_f32_e32 v16, v16
	v_cmp_gt_f32_e64 s14, |v14|, |v17|
	v_frexp_exp_i32_f32_e32 v28, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v22, v35, v22
	v_fmaak_f32 v34, s2, v13, 0x3ca908c9
	v_mul_f32_e32 v32, v19, v21
	v_add_f32_e32 v37, v15, v36
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v18
	v_frexp_mant_f32_e64 v29, |v17|
	v_fmaak_f32 v34, v13, v34, 0xbd5c1c4e
	v_fma_f32 v24, v21, v19, -v32
	v_sub_f32_e32 v15, v37, v15
	v_cmp_o_f32_e64 s3, v17, v17
	v_cmp_class_f32_e64 s12, v14, 0x1f8
	v_readfirstlane_b32 s5, v28
	v_fmac_f32_e32 v24, v21, v7
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v24, v8, v19
	v_add_f32_e32 v11, 0x31739010, v11
	v_sub_f32_e32 v8, v36, v15
	v_ldexp_f32 v19, v19, 1
	v_fmaak_f32 v15, v13, v34, 0x3e088382
	v_dual_add_f32 v11, v11, v22 :: v_dual_add_f32 v22, v32, v24
	v_sub_f32_e32 v33, v36, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v25, v33
	v_cvt_i32_f32_e32 v25, v30
	v_sub_f32_e32 v30, v22, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v21
	v_ldexp_f32 v16, v16, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v24, v30
	v_add_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, v16, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v18
	v_fmaak_f32 v10, v13, v15, 0xbeaaaa99
	v_add_f32_e32 v25, v37, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v10, |v9|, v10
	v_add_f32_e32 v32, 1.0, v25
	v_dual_sub_f32 v18, v25, v37 :: v_dual_add_f32 v21, v26, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v13, v10, |v9|
	v_dual_sub_f32 v8, v8, v18 :: v_dual_sub_f32 v15, v26, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v26, v22, v21 :: v_dual_add_f32 v11, v11, v15
	v_fma_f32 v15, v22, v21, -v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v15, v22, v11
	v_cndmask_b32_e64 v11, 0x7f800000, v16, s2
	v_frexp_exp_i32_f32_e32 v16, v1
	v_add_f32_e32 v22, -1.0, v32
	v_cmp_eq_f32_e64 s2, 0, v17
	v_add_f32_e32 v11, 1.0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_sub_f32_e32 v18, v25, v22
	v_cmp_gt_f32_e64 vcc_lo, 0x3f200000, |v9|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v11, v11
	v_cvt_f32_i32_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v18
	v_add_f32_e32 v25, v32, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, v11, -2.0, 1.0
	v_dual_fmac_f32 v15, v24, v21 :: v_dual_mul_f32 v24, 0x3f317218, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v11, v10 :: v_dual_add_f32 v21, v26, v15
	v_cmp_eq_f32_e64 vcc_lo, |v14|, |v17|
	v_add_f32_e32 v18, v19, v21
	v_sub_f32_e32 v22, v21, v26
	v_fma_f32 v26, 0x3f317218, v16, -v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v18, v19
	v_dual_sub_f32 v15, v15, v22 :: v_dual_fmamk_f32 v16, v16, 0xb102e308, v26
	v_ldexp_f32 v22, v25, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v21, v19
	v_add_f32_e32 v15, v7, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v13, v24, v16
	v_rcp_f32_e32 v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v15, v19
	v_sub_f32_e32 v19, v25, v32
	v_add_f32_e32 v25, v18, v15
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v8, v8, v19 :: v_dual_mul_f32 v19, v22, v21
	v_sub_f32_e32 v18, v25, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ldexp_f32 v26, v8, v12
	v_bfi_b32 v8, 0x7fffffff, v10, v9
	v_sub_f32_e32 v10, v13, v24
	v_fma_f32 v12, v21, v22, -v19
	v_floor_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v16, v10 :: v_dual_add_f32 v11, v13, v25
	v_fmac_f32_e32 v12, v21, v26
	v_and_b32_e32 v7, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v8, v8, 2
	v_sub_f32_e32 v9, v11, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v19, v12
	v_fma_f32 v8, -v8, s19, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v11, v9
	v_sub_f32_e32 v9, v25, v9
	v_fma_f32 v8, |v8|, s17, s16
	s_sub_i32 s16, s4, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v24
	s_cmp_gt_i32 s16, 12
	s_cselect_b32 s17, -1, 0
	s_and_b32 s3, s12, s3
	v_add_f32_e32 v9, v9, v13
	v_sub_f32_e32 v13, v16, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v13, v12 :: v_dual_sub_f32 v15, v15, v18
	v_sub_f32_e32 v18, 1.0, v16
	v_dual_add_f32 v24, v10, v15 :: v_dual_sub_f32 v19, 1.0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v24, v10
	v_add_f32_e32 v9, v24, v9
	v_dual_sub_f32 v13, v19, v16 :: v_dual_sub_f32 v16, v24, v25
	v_div_scale_f32 v24, null, v8, v8, 0xeafeeba7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v13, v12, v13
	v_sub_f32_e32 v12, v15, v25
	v_dual_sub_f32 v10, v10, v16 :: v_dual_add_f32 v19, v11, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v15, v24
	v_add_f32_e32 v16, v18, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v12, v12, v10 :: v_dual_sub_f32 v11, v19, v11
	v_ldexp_f32 v10, v27, 12
	v_sub_f32_e32 v25, v9, v11
	v_cndmask_b32_e32 v9, v14, v20, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v1
	v_mul_f32_e32 v14, v21, v16
	s_delay_alu instid0(TRANS32_DEP_1)
	v_fma_f32 v20, -v24, v15, 1.0
	v_add_f32_e32 v17, v12, v25
	v_ldexp_f32 v12, v29, 1
	v_cndmask_b32_e64 v27, 0x855ab76c, 1.0, vcc_lo
	v_mul_f32_e32 v23, v22, v14
	v_div_scale_f32 v29, vcc_lo, 0xeafeeba7, v8, 0xeafeeba7
	v_add_f32_e32 v25, v19, v17
	v_fmac_f32_e32 v15, v20, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v30, v14, v22, -v23
	v_add_nc_u32_e32 v11, -1, v28
	v_dual_sub_f32 v19, v25, v19 :: v_dual_mul_f32 v32, v27, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v14, v26
	v_mul_f32_e32 v20, v29, v15
	v_sub_f32_e32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v19, v27, v25, -v32
	v_add_f32_e32 v25, v23, v30
	v_cmp_class_f32_e64 s4, v32, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, v27, v17
	v_fma_f32 v17, -v24, v20, v29
	v_sub_f32_e32 v28, v16, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v4, v32, v19
	v_dual_fmac_f32 v20, v17, v15 :: v_dual_sub_f32 v17, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v16, v28
	v_cndmask_b32_e64 v18, v4, v32, s4
	v_sub_f32_e32 v4, v4, v32
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v24, -v24, v20, v29
	v_add_f32_e32 v13, v13, v17
	v_sub_f32_e32 v17, v25, v23
	v_cmp_eq_f32_e64 s4, 0x42b17218, v18
	v_sub_f32_e32 v4, v19, v4
	v_cmp_neq_f32_e64 s8, 0x7f800000, |v18|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v16, v16, v25 :: v_dual_sub_f32 v17, v17, v30
	v_cndmask_b32_e64 v23, 0, 0x37000000, s4
	v_cmp_eq_f32_e64 s4, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, 0, v4, s8
	v_dual_add_f32 v13, v13, v16 :: v_dual_sub_f32 v16, v18, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v4, v23, v4
	v_div_fmas_f32 v15, v24, v15, v20
	v_add_f32_e32 v20, v21, v14
	v_add_f32_e32 v13, v17, v13
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	v_cmp_gt_f32_e32 vcc_lo, 0, v27
	v_div_fixup_f32 v15, v15, v8, 0xeafeeba7
	v_sub_f32_e32 v25, v20, v21
	v_add_f32_e32 v13, v28, v13
	v_fma_f32 v28, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v29, v17
	v_div_scale_f32 v24, null, 0x5892d24, 0x5892d24, v15
	v_sub_f32_e32 v14, v14, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v13, v21, v13 :: v_dual_fmac_f32 v28, 0x32a5705f, v16
	v_rcp_f32_e32 v30, v24
	v_sub_f32_e32 v17, v17, v29
	v_trunc_f32_e32 v21, v27
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v13, v14, v13
	v_mul_f32_e32 v25, 0.5, v27
	v_cmp_ngt_f32_e64 s8, 0xc2ce8ed0, v16
	v_add_f32_e32 v14, v17, v28
	v_cmp_eq_f32_e64 s5, v21, v27
	v_add_f32_e32 v27, v20, v13
	v_trunc_f32_e32 v17, v25
	v_fma_f32 v21, -v24, v30, 1.0
	v_exp_f32_e32 v14, v14
	v_div_scale_f32 v28, s6, v15, 0x5892d24, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f32_e64 s7, v17, v25
	v_fmac_f32_e32 v30, v21, v30
	v_cvt_i32_f32_e32 v21, v29
	v_ldexp_f32 v29, v27, -2
	v_sub_f32_e32 v18, v27, v20
	s_and_b32 s7, s5, s7
	v_mul_f32_e32 v17, v28, v30
	s_delay_alu instid0(TRANS32_DEP_1)
	v_ldexp_f32 v14, v14, v21
	v_sub_f32_e32 v19, v22, v29
	v_sub_f32_e32 v13, v13, v18
	v_cndmask_b32_e64 v18, 1.0, v1, s7
	v_cndmask_b32_e64 v21, 0, v1, s7
	v_cndmask_b32_e64 v14, 0, v14, s8
	v_sub_f32_e32 v20, v22, v19
	v_cmp_nlt_f32_e64 s8, 0x42b17218, v16
	v_ldexp_f32 v13, v13, -2
	v_cmp_class_f32_e64 s7, v1, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v20, v29
	v_cndmask_b32_e64 v14, 0x7f800000, v14, s8
	v_fma_f32 v20, -v24, v17, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v26, v16
	v_fma_f32 v4, v14, v4, v14
	v_cmp_eq_f32_e64 s8, 0x7f800000, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v17, v20, v30
	v_sub_f32_e32 v13, v16, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v14, s8
	v_fma_f32 v16, -v24, v17, v28
	s_xor_b32 s8, s4, vcc_lo
	s_mov_b32 vcc_lo, s6
	v_add_f32_e32 v13, v19, v13
	v_bfi_b32 v4, 0x7fffffff, v4, v18
	v_div_fmas_f32 v16, v16, v30, v17
	v_cmp_nlt_f32_e64 vcc_lo, 0x42b2d4fc, |v2|
	v_cndmask_b32_e64 v14, 0x7f800000, 0, s8
	s_mov_b32 s8, 0
	v_cndmask_b32_e64 v18, 0x7fc00000, v4, s5
	v_cmp_gt_f32_e64 s5, 0x39800000, |v2|
	v_cndmask_b32_e32 v13, 0x7f800000, v13, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v1
	v_bfi_b32 v14, 0x7fffffff, v14, v21
	v_div_fixup_f32 v15, v16, 0x5892d24, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, |v2|, s5
	v_cndmask_b32_e32 v4, v4, v18, vcc_lo
	s_or_b32 vcc_lo, s4, s7
	v_add_f32_e32 v6, v6, v15
	s_mov_b32 s5, 0
	v_bfi_b32 v2, 0x7fffffff, v13, v2
	v_cndmask_b32_e32 v14, v4, v14, vcc_lo
	v_rcp_f32_e32 v4, v12
	v_cmp_o_f32_e32 vcc_lo, v1, v1
	v_mov_b32_e32 v13, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v1, 0x7fc00000, v14, vcc_lo
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_10 Depth 3
	v_cmp_ngt_f32_e32 vcc_lo, v31, v0
	s_cbranch_vccnz .LBB0_13
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_f32_e32 v14, 1.0, v31
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_mov_b64 s[6:7], s[36:37]
	s_mov_b32 s12, s27
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nge_f32_e64 s4, v14, v5
	s_cbranch_vccnz .LBB0_5
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s12, s12, -1
	v_mov_b32_e32 v31, v6
	global_store_b32 v13, v8, s[6:7]
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s12, 0
	s_cbranch_scc0 .LBB0_4
	s_branch .LBB0_6
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v31, v3, v14, s4
.LBB0_6:                                ; %.preheader76
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_13
; %bb.7:                                ; %.lr.ph100.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s4, 0
.LBB0_8:                                ; %.lr.ph100
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_10 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[4:5], 2
	v_mov_b32_e32 v14, v9
	s_add_u32 s6, s28, s12
	s_addc_u32 s7, s29, s13
	s_and_not1_b32 vcc_lo, exec_lo, s14
	global_store_b32 v13, v2, s[6:7]
	s_cbranch_vccnz .LBB0_12
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=2
	v_mov_b32_e32 v14, v10
	s_and_not1_b32 vcc_lo, exec_lo, s17
	s_mov_b32 s18, s16
	s_cbranch_vccnz .LBB0_11
.LBB0_10:                               ; %.preheader.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v4, v14
	s_mov_b32 s19, s18
	s_add_i32 s18, s18, -12
	s_cmp_gt_u32 s19, 24
	v_rndne_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v15, v12, v14
	v_cmp_gt_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v15, 0x80000000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v14, v15
	v_ldexp_f32 v14, v14, 12
	s_cbranch_scc1 .LBB0_10
.LBB0_11:                               ; %.loopexit.i.i
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_add_i32 s18, s18, -11
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v14, v14, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v4, v14
	v_rndne_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v15, v12, v14
	v_cmp_gt_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v15, 0x80000000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v14, v15
	v_ldexp_f32 v14, v14, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v14, v7, v14
.LBB0_12:                               ; %_ZL5fmodfff.exit
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v14, v14, 0x7fc00000, s2
	s_add_u32 s12, s30, s12
	s_addc_u32 s13, s31, s13
	s_add_i32 s4, s4, 1
	s_cmp_lg_u32 s4, s34
	v_cndmask_b32_e64 v14, 0x7fc00000, v14, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, s10, v14
	v_div_scale_f32 v15, null, v14, v14, s9
	v_div_scale_f32 v18, vcc_lo, s9, v14, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v15, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v16
	v_fma_f32 v19, -v15, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v16
	v_fma_f32 v15, -v15, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v15, v15, v16, v17
	v_div_fixup_f32 v14, v15, v14, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, 0xd01b0bed, v14
	v_mul_f32_e32 v15, 0x5c3242c, v14
	global_store_b32 v13, v15, s[12:13]
	global_load_b32 v15, v13, s[6:7]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v15, 0x5c3242c, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v1, v15
	v_add_f32_e32 v31, v31, v14
	s_cbranch_scc1 .LBB0_8
.LBB0_13:                               ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s8, s25
	s_cbranch_scc0 .LBB0_2
.LBB0_14:                               ; %._crit_edge
	s_load_b64 s[2:3], s[0:1], 0xe8
	v_mbcnt_lo_u32_b32 v28, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v28
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_20
; %bb.15:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[5:6], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB0_19
; %bb.16:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_17:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[2:3] offset:40
	global_load_b64 v[10:11], v0, s[2:3]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %Flow513
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_19:                               ; %Flow515
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_20:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s4, v6
	v_readfirstlane_b32 s5, v7
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[2:3] offset:40
	global_load_b128 v[0:3], v5, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_30
; %bb.23:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s5, v3
	v_and_b32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB0_26
; %bb.24:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_25:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_25
.LBB0_26:                               ; %Flow511
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v5, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v4, s10, 0
	global_load_b64 v[2:3], v5, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_28
; %bb.27:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_30
; %bb.29:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_30:                               ; %Flow512
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_31:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_31 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_33:                               ;   in Loop: Header=BB0_31 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_31 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_31 Depth=1
	s_mov_b32 s1, -1
.LBB0_36:                               ; %Flow506
                                        ;   in Loop: Header=BB0_31 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_31
; %bb.37:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_41
; %bb.38:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_41
; %bb.39:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_40:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_40
.LBB0_41:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_127
; %bb.42:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v32, 2, v0
	v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v7, 1
	v_and_b32_e32 v2, -3, v0
	v_mov_b32_e32 v6, 2
	s_mov_b64 s[6:7], 7
.LBB0_43:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_46 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_77 Depth 2
                                        ;     Child Loop BB0_85 Depth 2
                                        ;     Child Loop BB0_93 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_109 Depth 2
                                        ;     Child Loop BB0_115 Depth 2
                                        ;     Child Loop BB0_124 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_48
; %bb.44:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_47
; %bb.45:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB0_46:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB0_46
.LBB0_47:                               ; %Flow482
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB0_48:                               ; %Flow484
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[10:11], v30, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_50:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_55
; %bb.51:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_54
; %bb.52:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_53:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB0_53
.LBB0_54:                               ; %Flow477
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_56
.LBB0_55:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr14
.LBB0_56:                               ; %Flow479
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[12:13], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_58:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_63
; %bb.59:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_62
; %bb.60:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_61:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB0_61
.LBB0_62:                               ; %Flow472
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_64
.LBB0_63:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_64:                               ; %Flow474
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[14:15], v30, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_66:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_71
; %bb.67:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_70
; %bb.68:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_69:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB0_69
.LBB0_70:                               ; %Flow467
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_72
.LBB0_71:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr14
.LBB0_72:                               ; %Flow469
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[16:17], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_74:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_79
; %bb.75:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_78
; %bb.76:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_77:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB0_77
.LBB0_78:                               ; %Flow462
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_80:                               ; %Flow464
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[18:19], v30, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_82:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_87
; %bb.83:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_86
; %bb.84:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_85:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v4, v30, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB0_85
.LBB0_86:                               ; %Flow457
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_88
.LBB0_87:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr14
.LBB0_88:                               ; %Flow459
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_90
; %bb.89:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[20:21], v30, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_90:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_95
; %bb.91:                               ;   in Loop: Header=BB0_43 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_94
; %bb.92:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB0_93:                               ; %.preheader.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v30, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v29, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s10, v[29:30]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB0_93
.LBB0_94:                               ; %Flow452
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB0_96
.LBB0_95:                               ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s10, -1
.LBB0_96:                               ; %Flow454
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[22:23], v30, s[0:1]
.LBB0_98:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v29, v28 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v29
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_104
; %bb.99:                               ;   in Loop: Header=BB0_43 Depth=1
	global_load_b64 v[26:27], v30, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	global_load_b64 v[8:9], v30, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB0_103
; %bb.100:                              ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s11, 0
.LBB0_101:                              ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[2:3] offset:40
	global_load_b64 v[24:25], v30, s[2:3]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v30, v[24:27], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_101
; %bb.102:                              ; %Flow447
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_103:                              ; %Flow449
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_104:                              ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v30, s[2:3] offset:40
	global_load_b128 v[24:27], v30, s[2:3]
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v8
	v_readfirstlane_b32 s13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_43 Depth=1
	v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, v30
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s16, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_106:                              ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v32
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[29:30]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s12
	v_add_co_ci_u32_e32 v27, vcc_lo, s13, v27, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s16
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_114
; %bb.107:                              ;   in Loop: Header=BB0_43 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v30, s[2:3] offset:32 glc
	global_load_b64 v[2:3], v30, s[2:3] offset:40
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v2
	v_readfirstlane_b32 s17, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v8, vcc_lo, v24, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v25, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v30, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB0_110
; %bb.108:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s16, 0
.LBB0_109:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v30, v[2:5], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_109
.LBB0_110:                              ; %Flow445
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[2:3], v30, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v4, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_112
; %bb.111:                              ;   in Loop: Header=BB0_43 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v29, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[29:30], off offset:8
.LBB0_112:                              ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_43 Depth=1
	global_load_b32 v29, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v29
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[29:30], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_114:                              ; %Flow446
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v24, s15
	v_add_co_ci_u32_e32 v3, vcc_lo, s14, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_115:                              ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_117
; %bb.116:                              ;   in Loop: Header=BB0_115 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB0_117:                              ;   in Loop: Header=BB0_115 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_119
; %bb.118:                              ;   in Loop: Header=BB0_115 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_120
.LBB0_119:                              ;   in Loop: Header=BB0_115 Depth=2
	s_mov_b32 s1, -1
.LBB0_120:                              ; %Flow440
                                        ;   in Loop: Header=BB0_115 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_115
; %bb.121:                              ;   in Loop: Header=BB0_43 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_125
; %bb.122:                              ;   in Loop: Header=BB0_43 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v30, s[2:3] offset:40
	global_load_b64 v[12:13], v30, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v30, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v30, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_125
; %bb.123:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_mov_b32 s0, 0
.LBB0_124:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_43 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v30, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_124
.LBB0_125:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_43 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB0_43
; %bb.126:                              ; %Flow485
	s_mov_b32 s0, 0
	s_branch .LBB0_128
.LBB0_127:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_128:                              ; %Flow500
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_157
; %bb.129:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v28
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_135
; %bb.130:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_134
; %bb.131:                              ; %.preheader3.i.i.i68.preheader
	s_mov_b32 s5, 0
.LBB0_132:                              ; %.preheader3.i.i.i68
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_132
; %bb.133:                              ; %Flow497
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_134:                              ; %Flow499
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_135:                              ; %.loopexit4.i.i.i63
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_137
; %bb.136:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_137:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_145
; %bb.138:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
	v_mov_b32_e32 v12, s5
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v8, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_141
; %bb.139:                              ; %.preheader1.i.i.i66.preheader
	s_mov_b32 s10, 0
.LBB0_140:                              ; %.preheader1.i.i.i66
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_140
.LBB0_141:                              ; %Flow495
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_143
; %bb.142:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_143:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_145
; %bb.144:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_145:                              ; %Flow496
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_146:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_148
; %bb.147:                              ;   in Loop: Header=BB0_146 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_148:                              ;   in Loop: Header=BB0_146 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_150
; %bb.149:                              ;   in Loop: Header=BB0_146 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_151
.LBB0_150:                              ;   in Loop: Header=BB0_146 Depth=1
	s_mov_b32 s1, -1
.LBB0_151:                              ; %Flow490
                                        ;   in Loop: Header=BB0_146 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_146
; %bb.152:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_156
; %bb.153:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_156
; %bb.154:                              ; %.preheader.i.i.i65.preheader
	s_mov_b32 s0, 0
.LBB0_155:                              ; %.preheader.i.i.i65
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_155
.LBB0_156:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_157:                              ; %__ockl_printf_append_string_n.exit
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v28
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v28
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_163
; %bb.158:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[7:8], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[2:3] offset:40
	global_load_b64 v[5:6], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v9, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v9, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[7:8]
	s_cbranch_execz .LBB0_162
; %bb.159:                              ; %.preheader3.i.i.i75.preheader
	s_mov_b32 s5, 0
.LBB0_160:                              ; %.preheader3.i.i.i75
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[9:10], v4, s[2:3]
	v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[1:2]
	v_mov_b32_e32 v1, v5
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[7:8]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_160
; %bb.161:                              ; %Flow433
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_162:                              ; %Flow435
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_163:                              ; %.loopexit4.i.i.i69
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v29, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[4:5], v29, s[2:3] offset:40
	global_load_b128 v[6:9], v29, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v4
	v_readfirstlane_b32 s7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_165
; %bb.164:
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, v29
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB0_165:
	s_or_b32 exec_lo, exec_lo, s11
	v_cvt_f64_f32_e32 v[4:5], v31
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[28:29]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v2, 0xffffff1d, v2, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[2:5], off
	global_store_b128 v[0:1], v[8:11], off offset:16
	global_store_b128 v[0:1], v[8:11], off offset:32
	global_store_b128 v[0:1], v[8:11], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_173
; %bb.166:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v4, vcc_lo, v6, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_169
; %bb.167:                              ; %.preheader1.i.i.i73.preheader
	s_mov_b32 s10, 0
.LBB0_168:                              ; %.preheader1.i.i.i73
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_168
.LBB0_169:                              ; %Flow431
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_171
; %bb.170:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_171:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_173
; %bb.172:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_173:                              ; %Flow432
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v6, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_174:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_176
; %bb.175:                              ;   in Loop: Header=BB0_174 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_176:                              ;   in Loop: Header=BB0_174 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_178
; %bb.177:                              ;   in Loop: Header=BB0_174 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_179
.LBB0_178:                              ;   in Loop: Header=BB0_174 Depth=1
	s_mov_b32 s1, -1
.LBB0_179:                              ; %Flow426
                                        ;   in Loop: Header=BB0_174 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_174
; %bb.180:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_184
; %bb.181:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_184
; %bb.182:                              ; %.preheader.i.i.i72.preheader
	s_mov_b32 s0, 0
.LBB0_183:                              ; %.preheader.i.i.i72
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_183
.LBB0_184:                              ; %__ockl_printf_append_args.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7computefifiifffffffPffffffffffS_S_ffffffffff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 408
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 38
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7computefifiifffffffPffffffffffS_S_ffffffffff, .Lfunc_end0-_Z7computefifiifffffffPffffffffffS_S_ffffffffff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10300
; NumSgprs: 40
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 40
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%.17g\n"
	.size	.str, 7

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         124
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     by_value
      - .offset:         132
        .size:           4
        .value_kind:     by_value
      - .offset:         136
        .size:           4
        .value_kind:     by_value
      - .offset:         140
        .size:           4
        .value_kind:     by_value
      - .offset:         144
        .size:           4
        .value_kind:     by_value
      - .offset:         148
        .size:           4
        .value_kind:     by_value
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         156
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         160
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         164
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         166
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         168
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         170
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         172
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         174
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         208
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         216
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         232
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 408
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7computefifiifffffffPffffffffffS_S_ffffffffff
    .private_segment_fixed_size: 0
    .sgpr_count:     40
    .sgpr_spill_count: 0
    .symbol:         _Z7computefifiifffffffPffffffffffS_S_ffffffffff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
