extern "C"

__device__ float vxd(const float m,float Vy, float w, float ZpTei, float Xr, float Kvx)
{
	if (Vy > 0) {
            return ((m * Vy * w - Xr + ZpTei) * Kvx);
        } else {
            return ((m * Vy * w * 1.09f - Xr + ZpTei) * Kvx);//Vx*1.061 ;N0=3;k11=580.91f Ubuntu
            //return ((m * Vy * w  - Xr + ZpTei) * Kvx);
        }//*1.1045; k11=5.91f windows ; 1.09; k11=580.91f
}

extern "C"

__device__ float vyd(const float m,float Vx, float w, float ZpYri, float Yr, float Kvy) {
        if (Vx > 0) {
            return ((Yr - ZpYri - m * Vx * w * 1.0165f) * Kvy);//Vx*1.0179
            //return ((Yr - ZpYri - m * Vx * w) * Kvy);
        } else {//*1.0165; k11=5.91f windows
            return ((Yr - ZpYri - m * Vx * w) * Kvy);
        }
    }
extern "C"

__device__ float wd(const float lr,float Mr, float ZpYri, float Yr, float Kw) {
        return ((Mr + lr * ZpYri) * Kw);
    }
	
extern "C"

__global__ void modelCalc(float* VX, float* VY, float* ww, float* X, float* Y,
float* W, float* Xobs, float* Yobs, float T, float L, float B,float m,float lr,float Vx, float Vy,
float v,float w, const int size,const int nShips) 
{ 
int j = blockDim.x * blockIdx.x + threadIdx.x; 
if (j<nShips){
		float k11, k22, k66, k26;
        
        const float delta = 0.7f;//  
        float c1, c2, c3, m1, m2;// ..
        float w_ = 0.0f;// 						approx
        float betta_d = 0.0f;//     (rad)
        float Cxr, Cyr, Cmr;// Cxr,  , 
        //	float L1=B,T1=L/2;//,    ????????????????????
        const float p = 1000.0f;// 
        float Xr, Yr, Mr;// 
        float ZpTei = 0;//       =R+Xa
        float Jz;//      Gz
        float ZpYri;//   
        const float a66 = 0.31f;// 
        //float Ramp = 0.0f;//  
        const float lyamdaR = 1.4f;// c 335 //0.5--1.4 //1
        
        const float deltaR = 0.349f;//    - 20% //0.349f
        
//	float Va;//    
        float Yri, Ysi;//   
        const float Ar = 6.0f;// //5  
        const float D = 1.5f;//  //2  
        const float Cta = 10.0f, Ctt = 50.0f;//c 334 //Cta<=20, 0.5--30, Ctt<=20, 1--50 UP!!!
        //Ctt =30
        float Kvx, Kvy, Kw;//  
        const float No = 3.0f;//  ////3 
        const float Re = 5000000.0f;//  >5E8
        float K_betta;
        float fit;
        const float xk = 1.0f;
        const float bettar = 0.9f;
        const float fik = 0.95f;
        float ld_;//   c228
        float betta_D;// 
        float fiD;//c 338
        float CyD1;
        float CyD;
        float A0;//  
        float xD;//c 339
        float viv = 0.0f;//      27 ch3_2
		float Rmatr[3][3]={cosf(viv),-sinf(viv),0.0f,sinf(viv),cosf(viv),0.0f,0.0f,0.0f,1.0f};
		 //------------------------------------------------------------
//c 330         5.91- , 580.91 -  
        k11 = (580.91f * (float) pow(B / L, 2.0f) + 7.76f * (B / L) - 0.259f) / (48.4f - 6.89f * (B / T) + 1.47f * (float) pow(B / T, 2.0f) - 0.0475f * (float) pow(B / T, 3.0f));

        k22 = ((0.722f + 0.224f * delta) * (1.022f - (float) pow(B / L, 2.0f))) / (0.264f + 0.368f * (B / T));
        k66 = (2.0f * T / B) * (2.59f + 0.781f * delta) * (0.357f - 1.77f * (float) pow(B / L, 2.0f));
        k26 = k22;
        //k26=0;       
//c 323
        c1 = 3.14f * (T / L) * (float) pow((0.63f / delta), (5.0f / 2.0f)) * (float) pow(L / (6.0f * B), (1.0f / 3.0f)) - 0.032f;
        c2 = -2.0f * k11 * delta * (B / L);
        c3 = 1.35f * (float) pow(T / B, (1.0f / 2.0f)) * (float) pow((0.63f / delta), (3.0f / 2.0f)) - 0.029f;
        m1 = 1.67f * (T / L) - 0.56f * delta + 0.43f;
        m2 = -0.44f * (T / L) - 0.0375f;
        // System.out.printf("c1=%f\tc2=%f\tc3=%f\tm1=%f\tm2=%f\n", c1, c2, c3, m1, m2);
        Jz = (m * (float) pow(L, 2.0f) / 12.4f) * (0.463f + 0.574f * (float) pow(delta, a66) + (float) pow(B / L, 2.0f));//c 330
        
        Kvx = 1 / (m * (1 + k11));
        Kvy = 1 / (m * (1 + k22));
        Kw = 1 / (Jz * (1 + k66));//????? m        
//----------------------------------------------------------------
        float k1, k2, k3, k4;
        float q1, q2, q3, q4;
        float z1, z2, z3, z4;
        float j1, j2, j3, j4;
        //t = 0.0f; //  		
        int t = 0;
        float h = 1.0f;		
		for (int i = 0; i < size; i++) {	//16550
                v = (float) sqrt((float) pow(Vx, 2.0f) + (float) pow(Vy, 2.0f));
                //assert(Vx==0);
                if (Vx != 0) {
				//c 353 ?????????????????????????
                    w_ = w * L / v;//??????????????????????
                    betta_d = -(float) atan(Vy / Vx);//c 350
                } else {
                    w_ = w * L / v;
                    //betta_d = 0;
                    betta_d = -(float) atan(Vy / Vx);//c 350
                }
                
                Cxr = 0.01f * (1.0f + 170.0f * (T / L));//   c 119
                Cyr = c1 * betta_d + c2 * w_ + c3 * betta_d * abs(betta_d);//c 323
                Cmr = m1 * betta_d + m2 * w_;

                Xr = Cxr * L * T * (float) pow(v, 2.0f) * p / 2.0f;//c 320
                Yr = Cyr * L * T * (float) pow(v, 2.0f) * p / 2.0f;
                Mr = Cmr * L * T * (float) pow(v, 2.0f) * p / 2.0f;

                K_betta = 0.43f * (float) pow(Ctt, -0.6f);
                fit = (float) pow(1.0f + Ctt, 0.508f);
                //IMPORTANT!!!  deltaR
                Yri = 3.14f * (deltaR - K_betta * xk * (betta_d + lr * w_)) * p * Ar * (float) pow(v * fik * fit, 2.0f) / (1.0f + 2.2f / (float) pow(lyamdaR, 2.0f / 3.0f));

                ld_ = 0.77f - 0.125f * (float) sqrt(Ctt) / (1.65f * (float) sqrt(Ctt) - 1.0f);
                betta_D = 1.22f - 0.0563f * (float) sqrt(Ctt) / (1.65f * (float) sqrt(Ctt) - 1.0f);
                fiD = 0.5f * ((float) sqrt(1.0f + 2.0f * Ctt / betta_D) + 1.0f);

                CyD1 = 12.0f * ld_ / (1.0f + 1.56f * ld_);
                CyD = CyD1 + 2.0f * betta_D * (float) pow(fiD, 2.0f);
                xD = xk * (CyD1 + 2.0f * betta_D * fiD) / (CyD1 + 2.0f * betta_D * (float) pow(fiD, 2.0f));
                A0 = 3.14f * (float) pow(D, 2.0f) / 4.0f;
                Ysi = CyD * (xD - 0.02f * xk) * (betta_d + lr * w_) * (p / 2.0f) * A0 * (float) pow(v, 2.0f) * (float) pow(fik, 2.0f);                
                ZpTei = 1000000.0f * (9.740f * (float) pow(No, 2.0f) - 2.23f * v); ////9.740f                
                ZpYri = 2.0f * (Yri - Ysi);//2 
               
                k1 = h * vxd(m,Vy, w, ZpTei, Xr, Kvx);
                q1 = h * vyd(m,Vx, w, ZpYri, Yr, Kvy);
                z1 = h * wd(lr,Mr, ZpTei, Yr, Kw);

                k2 = h * vxd(m,Vy + q1 / 2.0f, w + z1 / 2.0f, ZpTei, Xr, Kvx);
                q2 = h * vyd(m,Vx + k1 / 2.0f, w + z1 / 2.0f, ZpYri, Yr, Kvy);
                z2 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k3 = h * vxd(m,Vy + q2 / 2.0f, w + z2 / 2.0f, ZpTei, Xr, Kvx);
                q3 = h * vyd(m,Vx + k2 / 2.0f, w + z2 / 2.0f, ZpYri, Yr, Kvy);
                z3 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k4 = h * vxd(m,Vy + q3, w + z3, ZpTei, Xr, Kvx);
                q4 = h * vyd(m,Vx + k3, w + z3, ZpYri, Yr, Kvy);
                z4 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                Vx = Vx + (1.0f / 6.0f) * (k1 + 2.0f * k2 + 2.0f * k3 + k4);
                //VX[t] = Vx / 1.24f;
                VX[t] = Vx;
                Vy = Vy + (1.0f / 6.0f) * (q1 + 2.0f * q2 + 2.0f * q3 + q4);
                VY[t] = Vy;
                w = w + (1.0f / 6.0f) * (z1 + 2.0f * z2 + 2.0f * z3 + z4);
                ww[t] = w;

//--- -----------------------------------------
                k1 = h * vxd(m,Vy, w, ZpTei, Xr, Kvx);
                q1 = h * vyd(m,Vx, w, ZpYri, Yr, Kvy);
                z1 = h * wd(lr,Mr, ZpTei, Yr, Kw);

                k2 = h * vxd(m,Vy + q1 / 2.0f, w + z1 / 2.0f, ZpTei, Xr, Kvx);
                q2 = h * vyd(m,Vx + k1 / 2.0f, w + z1 / 2.0f, ZpYri, Yr, Kvy);
                z2 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k3 = h * vxd(m,Vy + q2 / 2.0f, w + z2 / 2.0f, ZpTei, Xr, Kvx);
                q3 = h * vyd(m,Vx + k2 / 2.0f, w + z2 / 2.0f, ZpYri, Yr, Kvy);
                z3 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k4 = h * vxd(m,Vy + q3, w + z3, ZpTei, Xr, Kvx);
                q4 = h * vyd(m,Vx + k3, w + z3, ZpYri, Yr, Kvy);
                z4 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                X[t] = Vx + (1.0f / 6.0f) * (k1 + 2.0f * k2 + 2.0f * k3 + k4);
                Y[t] = Vy + (1.0f / 6.0f) * (q1 + 2.0f * q2 + 2.0f * q3 + q4);
                W[t] = w + (1.0f / 6.0f) * (z1 + 2.0f * z2 + 2.0f * z3 + z4);                
                //                    
                viv = W[t];                                
                //-------
                Rmatr[0][0] = (float)cos(viv);
                Rmatr[0][1] = -(float)sin(viv);
                Rmatr[1][0] = (float)sin(viv);
                Rmatr[1][1] = (float)cos(viv);
                Xobs[t] = Rmatr[0][0] * X[t] + Rmatr[0][1] * Y[t];
                Yobs[t] = Rmatr[1][0] * X[t] + Rmatr[1][1] * Y[t];                
                //----------
                t++;               
                       
        }
	}
}
	.file	"tmpxft_002cf325_00000000-6_modelCalc.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2013:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2013:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	vxd
	.type	vxd, @function
vxd:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	vxd, .-vxd
	.globl	vyd
	.type	vyd, @function
vyd:
.LFB2155:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2155:
	.size	vyd, .-vyd
	.globl	wd
	.type	wd, @function
wd:
.LFB2010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2010:
	.size	wd, .-wd
	.globl	_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii
	.type	_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii, @function
_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$328, %rsp
	.cfi_def_cfa_offset 336
	movq	336(%rsp), %rax
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rax, 40(%rsp)
	movq	344(%rsp), %rax
	movq	%rdx, 72(%rsp)
	leaq	96(%rsp), %rdx
	movq	%rcx, 64(%rsp)
	leaq	104(%rsp), %rcx
	movq	%r8, 56(%rsp)
	movq	%r9, 48(%rsp)
	movq	%rax, 32(%rsp)
	movss	%xmm0, 28(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 20(%rsp)
	movss	%xmm3, 16(%rsp)
	movss	%xmm4, 12(%rsp)
	movss	%xmm5, 8(%rsp)
	movss	%xmm6, 4(%rsp)
	movss	%xmm7, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 312(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 272(%rsp)
	movq	%rsp, %rax
	movq	%rax, 280(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 304(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	104(%rsp)
	.cfi_def_cfa_offset 344
	leaq	modelCalc(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 352
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 344
	popq	%rdx
	.cfi_def_cfa_offset 336
.L8:
	movq	312(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$328, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii, .-_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii
	.globl	modelCalc
	.type	modelCalc, @function
modelCalc:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z9modelCalcPfS_S_S_S_S_S_S_fffffffffiiPfS_S_S_S_S_S_S_fffffffffii
	.cfi_endproc
.LFE2036:
	.size	modelCalc, .-modelCalc
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"modelCalc"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	modelCalc(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"

__device__ float vxd(const float m,float Vy, float w, float ZpTei, float Xr, float Kvx)
{
	if (Vy > 0) {
            return ((m * Vy * w - Xr + ZpTei) * Kvx);
        } else {
            return ((m * Vy * w * 1.09f - Xr + ZpTei) * Kvx);//Vx*1.061 ;N0=3;k11=580.91f Ubuntu
            //return ((m * Vy * w  - Xr + ZpTei) * Kvx);
        }//*1.1045; k11=5.91f windows ; 1.09; k11=580.91f
}

extern "C"

__device__ float vyd(const float m,float Vx, float w, float ZpYri, float Yr, float Kvy) {
        if (Vx > 0) {
            return ((Yr - ZpYri - m * Vx * w * 1.0165f) * Kvy);//Vx*1.0179
            //return ((Yr - ZpYri - m * Vx * w) * Kvy);
        } else {//*1.0165; k11=5.91f windows
            return ((Yr - ZpYri - m * Vx * w) * Kvy);
        }
    }
extern "C"

__device__ float wd(const float lr,float Mr, float ZpYri, float Yr, float Kw) {
        return ((Mr + lr * ZpYri) * Kw);
    }
	
extern "C"

__global__ void modelCalc(float* VX, float* VY, float* ww, float* X, float* Y,
float* W, float* Xobs, float* Yobs, float T, float L, float B,float m,float lr,float Vx, float Vy,
float v,float w, const int size,const int nShips) 
{ 
int j = blockDim.x * blockIdx.x + threadIdx.x; 
if (j<nShips){
		float k11, k22, k66, k26;
        
        const float delta = 0.7f;//  
        float c1, c2, c3, m1, m2;// ..
        float w_ = 0.0f;// 						approx
        float betta_d = 0.0f;//     (rad)
        float Cxr, Cyr, Cmr;// Cxr,  , 
        //	float L1=B,T1=L/2;//,    ????????????????????
        const float p = 1000.0f;// 
        float Xr, Yr, Mr;// 
        float ZpTei = 0;//       =R+Xa
        float Jz;//      Gz
        float ZpYri;//   
        const float a66 = 0.31f;// 
        //float Ramp = 0.0f;//  
        const float lyamdaR = 1.4f;// c 335 //0.5--1.4 //1
        
        const float deltaR = 0.349f;//    - 20% //0.349f
        
//	float Va;//    
        float Yri, Ysi;//   
        const float Ar = 6.0f;// //5  
        const float D = 1.5f;//  //2  
        const float Cta = 10.0f, Ctt = 50.0f;//c 334 //Cta<=20, 0.5--30, Ctt<=20, 1--50 UP!!!
        //Ctt =30
        float Kvx, Kvy, Kw;//  
        const float No = 3.0f;//  ////3 
        const float Re = 5000000.0f;//  >5E8
        float K_betta;
        float fit;
        const float xk = 1.0f;
        const float bettar = 0.9f;
        const float fik = 0.95f;
        float ld_;//   c228
        float betta_D;// 
        float fiD;//c 338
        float CyD1;
        float CyD;
        float A0;//  
        float xD;//c 339
        float viv = 0.0f;//      27 ch3_2
		float Rmatr[3][3]={cosf(viv),-sinf(viv),0.0f,sinf(viv),cosf(viv),0.0f,0.0f,0.0f,1.0f};
		 //------------------------------------------------------------
//c 330         5.91- , 580.91 -  
        k11 = (580.91f * (float) pow(B / L, 2.0f) + 7.76f * (B / L) - 0.259f) / (48.4f - 6.89f * (B / T) + 1.47f * (float) pow(B / T, 2.0f) - 0.0475f * (float) pow(B / T, 3.0f));

        k22 = ((0.722f + 0.224f * delta) * (1.022f - (float) pow(B / L, 2.0f))) / (0.264f + 0.368f * (B / T));
        k66 = (2.0f * T / B) * (2.59f + 0.781f * delta) * (0.357f - 1.77f * (float) pow(B / L, 2.0f));
        k26 = k22;
        //k26=0;       
//c 323
        c1 = 3.14f * (T / L) * (float) pow((0.63f / delta), (5.0f / 2.0f)) * (float) pow(L / (6.0f * B), (1.0f / 3.0f)) - 0.032f;
        c2 = -2.0f * k11 * delta * (B / L);
        c3 = 1.35f * (float) pow(T / B, (1.0f / 2.0f)) * (float) pow((0.63f / delta), (3.0f / 2.0f)) - 0.029f;
        m1 = 1.67f * (T / L) - 0.56f * delta + 0.43f;
        m2 = -0.44f * (T / L) - 0.0375f;
        // System.out.printf("c1=%f\tc2=%f\tc3=%f\tm1=%f\tm2=%f\n", c1, c2, c3, m1, m2);
        Jz = (m * (float) pow(L, 2.0f) / 12.4f) * (0.463f + 0.574f * (float) pow(delta, a66) + (float) pow(B / L, 2.0f));//c 330
        
        Kvx = 1 / (m * (1 + k11));
        Kvy = 1 / (m * (1 + k22));
        Kw = 1 / (Jz * (1 + k66));//????? m        
//----------------------------------------------------------------
        float k1, k2, k3, k4;
        float q1, q2, q3, q4;
        float z1, z2, z3, z4;
        float j1, j2, j3, j4;
        //t = 0.0f; //  		
        int t = 0;
        float h = 1.0f;		
		for (int i = 0; i < size; i++) {	//16550
                v = (float) sqrt((float) pow(Vx, 2.0f) + (float) pow(Vy, 2.0f));
                //assert(Vx==0);
                if (Vx != 0) {
				//c 353 ?????????????????????????
                    w_ = w * L / v;//??????????????????????
                    betta_d = -(float) atan(Vy / Vx);//c 350
                } else {
                    w_ = w * L / v;
                    //betta_d = 0;
                    betta_d = -(float) atan(Vy / Vx);//c 350
                }
                
                Cxr = 0.01f * (1.0f + 170.0f * (T / L));//   c 119
                Cyr = c1 * betta_d + c2 * w_ + c3 * betta_d * abs(betta_d);//c 323
                Cmr = m1 * betta_d + m2 * w_;

                Xr = Cxr * L * T * (float) pow(v, 2.0f) * p / 2.0f;//c 320
                Yr = Cyr * L * T * (float) pow(v, 2.0f) * p / 2.0f;
                Mr = Cmr * L * T * (float) pow(v, 2.0f) * p / 2.0f;

                K_betta = 0.43f * (float) pow(Ctt, -0.6f);
                fit = (float) pow(1.0f + Ctt, 0.508f);
                //IMPORTANT!!!  deltaR
                Yri = 3.14f * (deltaR - K_betta * xk * (betta_d + lr * w_)) * p * Ar * (float) pow(v * fik * fit, 2.0f) / (1.0f + 2.2f / (float) pow(lyamdaR, 2.0f / 3.0f));

                ld_ = 0.77f - 0.125f * (float) sqrt(Ctt) / (1.65f * (float) sqrt(Ctt) - 1.0f);
                betta_D = 1.22f - 0.0563f * (float) sqrt(Ctt) / (1.65f * (float) sqrt(Ctt) - 1.0f);
                fiD = 0.5f * ((float) sqrt(1.0f + 2.0f * Ctt / betta_D) + 1.0f);

                CyD1 = 12.0f * ld_ / (1.0f + 1.56f * ld_);
                CyD = CyD1 + 2.0f * betta_D * (float) pow(fiD, 2.0f);
                xD = xk * (CyD1 + 2.0f * betta_D * fiD) / (CyD1 + 2.0f * betta_D * (float) pow(fiD, 2.0f));
                A0 = 3.14f * (float) pow(D, 2.0f) / 4.0f;
                Ysi = CyD * (xD - 0.02f * xk) * (betta_d + lr * w_) * (p / 2.0f) * A0 * (float) pow(v, 2.0f) * (float) pow(fik, 2.0f);                
                ZpTei = 1000000.0f * (9.740f * (float) pow(No, 2.0f) - 2.23f * v); ////9.740f                
                ZpYri = 2.0f * (Yri - Ysi);//2 
               
                k1 = h * vxd(m,Vy, w, ZpTei, Xr, Kvx);
                q1 = h * vyd(m,Vx, w, ZpYri, Yr, Kvy);
                z1 = h * wd(lr,Mr, ZpTei, Yr, Kw);

                k2 = h * vxd(m,Vy + q1 / 2.0f, w + z1 / 2.0f, ZpTei, Xr, Kvx);
                q2 = h * vyd(m,Vx + k1 / 2.0f, w + z1 / 2.0f, ZpYri, Yr, Kvy);
                z2 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k3 = h * vxd(m,Vy + q2 / 2.0f, w + z2 / 2.0f, ZpTei, Xr, Kvx);
                q3 = h * vyd(m,Vx + k2 / 2.0f, w + z2 / 2.0f, ZpYri, Yr, Kvy);
                z3 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k4 = h * vxd(m,Vy + q3, w + z3, ZpTei, Xr, Kvx);
                q4 = h * vyd(m,Vx + k3, w + z3, ZpYri, Yr, Kvy);
                z4 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                Vx = Vx + (1.0f / 6.0f) * (k1 + 2.0f * k2 + 2.0f * k3 + k4);
                //VX[t] = Vx / 1.24f;
                VX[t] = Vx;
                Vy = Vy + (1.0f / 6.0f) * (q1 + 2.0f * q2 + 2.0f * q3 + q4);
                VY[t] = Vy;
                w = w + (1.0f / 6.0f) * (z1 + 2.0f * z2 + 2.0f * z3 + z4);
                ww[t] = w;

//--- -----------------------------------------
                k1 = h * vxd(m,Vy, w, ZpTei, Xr, Kvx);
                q1 = h * vyd(m,Vx, w, ZpYri, Yr, Kvy);
                z1 = h * wd(lr,Mr, ZpTei, Yr, Kw);

                k2 = h * vxd(m,Vy + q1 / 2.0f, w + z1 / 2.0f, ZpTei, Xr, Kvx);
                q2 = h * vyd(m,Vx + k1 / 2.0f, w + z1 / 2.0f, ZpYri, Yr, Kvy);
                z2 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k3 = h * vxd(m,Vy + q2 / 2.0f, w + z2 / 2.0f, ZpTei, Xr, Kvx);
                q3 = h * vyd(m,Vx + k2 / 2.0f, w + z2 / 2.0f, ZpYri, Yr, Kvy);
                z3 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                k4 = h * vxd(m,Vy + q3, w + z3, ZpTei, Xr, Kvx);
                q4 = h * vyd(m,Vx + k3, w + z3, ZpYri, Yr, Kvy);
                z4 = h * wd(lr,Mr, ZpYri, Yr, Kw);

                X[t] = Vx + (1.0f / 6.0f) * (k1 + 2.0f * k2 + 2.0f * k3 + k4);
                Y[t] = Vy + (1.0f / 6.0f) * (q1 + 2.0f * q2 + 2.0f * q3 + q4);
                W[t] = w + (1.0f / 6.0f) * (z1 + 2.0f * z2 + 2.0f * z3 + z4);                
                //                    
                viv = W[t];                                
                //-------
                Rmatr[0][0] = (float)cos(viv);
                Rmatr[0][1] = -(float)sin(viv);
                Rmatr[1][0] = (float)sin(viv);
                Rmatr[1][1] = (float)cos(viv);
                Xobs[t] = Rmatr[0][0] * X[t] + Rmatr[0][1] * Y[t];
                Yobs[t] = Rmatr[1][0] * X[t] + Rmatr[1][1] * Y[t];                
                //----------
                t++;               
                       
        }
	}
}
	.text
	.file	"modelCalc.hip"
	.globl	__device_stub__modelCalc        # -- Begin function __device_stub__modelCalc
	.type	__device_stub__modelCalc,@function
__device_stub__modelCalc:               # @__device_stub__modelCalc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	28(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	24(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	20(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	16(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	12(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	8(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	4(%rsp), %r13
	movss	%xmm6, (%r13)
	movq	%rsp, %rbp
	movss	%xmm7, (%rbp)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	movq	%r14, 88(%rbx)
	movq	%r15, 96(%rbx)
	movq	%r12, 104(%rbx)
	movq	%r13, 112(%rbx)
	movq	%rbp, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$modelCalc, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$296, %rsp                      # imm = 0x128
	.cfi_adjust_cfa_offset -296
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__modelCalc, .Lfunc_end0-__device_stub__modelCalc
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$modelCalc, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	modelCalc,@object               # @modelCalc
	.section	.rodata,"a",@progbits
	.globl	modelCalc
	.p2align	3, 0x0
modelCalc:
	.quad	__device_stub__modelCalc
	.size	modelCalc, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"modelCalc"
	.size	.L__unnamed_1, 10

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__modelCalc
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym modelCalc
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	modelCalc               ; -- Begin function modelCalc
	.globl	modelCalc
	.p2align	8
	.type	modelCalc,@function
modelCalc:                              ; @modelCalc
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x7c
	s_load_b128 s[36:39], s[0:1], 0x60
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s38, v1
	s_cbranch_execz .LBB0_23
; %bb.1:
	s_cmp_lt_i32 s37, 1
	s_cbranch_scc1 .LBB0_23
; %bb.2:                                ; %.lr.ph
	s_load_b256 s[24:31], s[0:1], 0x40
	s_mov_b32 s7, 0xc0dc7ae1
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s31, 0x3e76c4e1
	s_mov_b32 s13, 0x3ebc6a7f
	v_div_scale_f32 v1, null, s25, s25, s26
	v_div_scale_f32 v5, null, s24, s24, s26
	v_div_scale_f32 v8, vcc_lo, s26, s25, s26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v6, v1
	v_rcp_f32_e32 v7, v5
	v_div_scale_f32 v9, s3, s26, s24, s26
	v_div_scale_f32 v3, null, s25, s25, s24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v0, -v1, v6, 1.0
	v_fma_f32 v2, -v5, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v6, v0, v6 :: v_dual_fmac_f32 v7, v2, v7
	v_add_f32_e64 v0, s24, s24
	v_dual_mul_f32 v10, v8, v6 :: v_dual_mul_f32 v11, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v14, null, s26, s26, v0
	v_div_scale_f32 v15, s5, v0, s26, v0
	v_fma_f32 v2, -v1, v10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v5, v11, v9
	v_dual_fmac_f32 v10, v2, v6 :: v_dual_fmac_f32 v11, v4, v7
	v_mul_f32_e64 v2, 0x40c00000, s26
	v_div_scale_f32 v4, s2, s24, s25, s24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v1, -v1, v10, v8
	v_fma_f32 v5, -v5, v11, v9
	v_frexp_mant_f32_e64 v8, |s25|
	v_div_scale_f32 v16, null, v2, v2, s25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v1, v1, v6, v10
	s_mov_b32 vcc_lo, s3
	v_cmp_gt_f32_e64 s4, 0x3f2aaaab, v8
	v_div_fmas_f32 v7, v5, v7, v11
	v_rcp_f32_e32 v10, v3
	v_div_fixup_f32 v1, v1, s25, s26
	v_div_scale_f32 v5, null, s26, s26, s24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v7, v7, s24, s26
	v_cndmask_b32_e64 v19, 0, 1, s4
	v_frexp_mant_f32_e64 v9, |v1|
	v_div_scale_f32 v17, s6, s25, v2, s25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e64 v11, |v7|
	v_ldexp_f32 v8, v8, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_f32_e64 s8, 0x3f2aaaab, v9
	v_fma_f32 v22, -v3, v10, 1.0
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v1
	v_cmp_gt_f32_e64 s9, 0x3f2aaaab, v11
	v_cmp_eq_f32_e64 s10, 1.0, v7
	v_cndmask_b32_e64 v12, 0, 1, s8
	v_frexp_exp_i32_f32_e32 v39, v7
	v_div_scale_f32 v6, s3, s24, s26, s24
	v_cndmask_b32_e64 v13, 0, 1, s9
	s_delay_alu instid0(VALU_DEP_4)
	v_ldexp_f32 v18, v9, v12
	v_rcp_f32_e32 v9, v5
	v_add_f32_e32 v25, -1.0, v8
	v_rcp_f32_e32 v12, v14
	v_ldexp_f32 v13, v11, v13
	v_add_f32_e32 v26, -1.0, v18
	v_add_f32_e32 v20, 1.0, v18
	v_add_f32_e32 v28, 1.0, v8
	v_rcp_f32_e32 v11, v16
	v_add_f32_e32 v21, 1.0, v13
	v_add_f32_e32 v27, -1.0, v13
	v_rcp_f32_e32 v19, v20
	v_fma_f32 v23, -v5, v9, 1.0
	v_fma_f32 v29, -v14, v12, 1.0
	v_rcp_f32_e32 v24, v21
	v_fmac_f32_e32 v10, v22, v10
	v_subrev_co_ci_u32_e64 v39, s9, 0, v39, s9
	v_add_f32_e32 v33, -1.0, v21
	v_fma_f32 v22, -v16, v11, 1.0
	v_cndmask_b32_e64 v49, 0x40400000, 1.0, s10
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
	v_mul_f32_e32 v30, v26, v19
	v_cmp_class_f32_e64 s14, v1, 0x204
	v_fmac_f32_e32 v9, v23, v9
	v_mul_f32_e32 v31, v27, v24
	v_add_f32_e32 v32, -1.0, v20
	v_dual_mul_f32 v34, v20, v30 :: v_dual_sub_f32 v13, v13, v33
	v_cmp_class_f32_e64 s15, v7, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v35, v21, v31 :: v_dual_sub_f32 v18, v18, v32
	v_fma_f32 v20, v30, v20, -v34
	v_rcp_f32_e32 v32, v28
	v_add_f32_e32 v33, -1.0, v28
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v23, v31, v21, -v35
	v_fmac_f32_e32 v12, v29, v12
	v_fmac_f32_e32 v20, v30, v18
	v_mul_f32_e32 v21, v4, v10
	v_fmac_f32_e32 v11, v22, v11
	v_fmac_f32_e32 v23, v31, v13
	v_sub_f32_e32 v8, v8, v33
	v_add_f32_e32 v18, v34, v20
	v_dual_mul_f32 v36, v25, v32 :: v_dual_mul_f32 v13, v6, v9
	v_mul_f32_e32 v22, v15, v12
	v_add_f32_e32 v29, v35, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v33, v26, v18 :: v_dual_mul_f32 v38, v28, v36
	v_dual_sub_f32 v34, v18, v34 :: v_dual_sub_f32 v37, v27, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v35, v29, v35 :: v_dual_sub_f32 v26, v26, v33
	v_fma_f32 v28, v36, v28, -v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v20, v34, v20 :: v_dual_sub_f32 v27, v27, v37
	v_sub_f32_e32 v18, v26, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v26, v27, v29
	v_fma_f32 v27, -v3, v21, v4
	v_fmac_f32_e32 v28, v36, v8
	v_add_f32_e32 v8, v20, v18
	v_frexp_exp_i32_f32_e32 v29, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v21, v27, v10 :: v_dual_add_f32 v20, v38, v28
	v_sub_f32_e32 v34, v35, v23
	v_add_f32_e32 v8, v33, v8
	v_cndmask_b32_e64 v27, 2.0, 1.0, vcc_lo
	v_subrev_co_ci_u32_e64 v29, s8, 0, v29, s8
	v_sub_f32_e32 v33, v20, v38
	v_add_f32_e32 v18, v34, v26
	v_cndmask_b32_e64 v38, 2.0, 1.0, s10
	v_cmp_eq_f32_e32 vcc_lo, 0, v1
	v_mul_f32_e32 v23, v17, v11
	v_fma_f32 v26, -v14, v22, v15
	v_add_f32_e32 v18, v37, v18
	v_trunc_f32_e32 v46, v38
	v_fmaak_f32 v37, s7, v7, 0x4241999a
	v_cmp_eq_f32_e64 s7, 0, v7
	v_fmac_f32_e32 v22, v26, v12
	v_mul_f32_e32 v18, v24, v18
	v_cmp_eq_f32_e64 s9, v46, v38
	v_fma_f32 v3, -v3, v21, v4
	v_cndmask_b32_e64 v44, 0x7f800000, 0, s7
	v_fma_f32 v15, -v14, v22, v15
	v_dual_add_f32 v35, v31, v18 :: v_dual_sub_f32 v34, v25, v20
	v_dual_sub_f32 v28, v33, v28 :: v_dual_mul_f32 v47, 0.5, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v31, v35, v31
	v_dual_sub_f32 v25, v25, v34 :: v_dual_sub_f32 v18, v18, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v20, v25, v20 :: v_dual_add_f32 v43, v18, v18
	v_mul_f32_e32 v8, v19, v8
	v_cndmask_b32_e64 v19, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s14
	v_add_f32_e32 v24, v30, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v30, v24, v30
	v_sub_f32_e32 v8, v8, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v30, v35, v35 :: v_dual_add_f32 v41, v8, v8
	v_fma_f32 v42, v35, v35, -v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v42, v35, v43
	v_dual_mul_f32 v40, v24, v24 :: v_dual_mul_f32 v43, 0.5, v27
	v_add_f32_e32 v33, v30, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, v24, v24, -v40
	v_mul_f32_e32 v55, v35, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v31, v24, v41
	v_trunc_f32_e32 v41, v27
	v_fma_f32 v59, v33, v35, -v55
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v45, v40, v31
	v_cmp_eq_f32_e64 s8, v41, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v48, s31, v45, 0x3e91f4c4
	v_dual_sub_f32 v40, v45, v40 :: v_dual_mul_f32 v53, v24, v45
	v_fmaak_f32 v48, v45, v48, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v25, v31, v40
	v_fma_f32 v57, v45, v24, -v53
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v51, v45, v48
	v_fma_f32 v31, v45, v48, -v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v25, v48
	v_fmac_f32_e32 v57, v45, v8
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v46, v51, v31 :: v_dual_fmac_f32 v57, v25, v24
	v_cvt_f32_i32_e32 v25, v29
	v_ldexp_f32 v24, v24, 1
	v_dual_sub_f32 v51, v46, v51 :: v_dual_fmaak_f32 v50, s31, v33, 0x3e91f4c4
	v_add_f32_e32 v56, 0x3f2aaaaa, v46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v30, v33, v30 :: v_dual_sub_f32 v31, v31, v51
	v_fmaak_f32 v41, v33, v50, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v51, 0xbf2aaaaa, v56 :: v_dual_sub_f32 v30, v42, v30
	v_dual_mul_f32 v48, 0.5, v49 :: v_dual_fmac_f32 v59, v33, v18
	v_mul_f32_e32 v52, v33, v41
	v_trunc_f32_e32 v50, v43
	v_add_f32_e32 v31, 0x31739010, v31
	v_trunc_f32_e32 v42, v47
	v_fmac_f32_e32 v59, v30, v35
	v_fma_f32 v40, v33, v41, -v52
	v_add_f32_e32 v33, v53, v57
	v_cmp_neq_f32_e64 s10, v50, v43
	v_ldexp_f32 v35, v35, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v43, v55, v59 :: v_dual_fmac_f32 v40, v30, v41
	v_sub_f32_e32 v50, v33, v53
	v_cmp_neq_f32_e64 s11, v42, v47
	v_ldexp_f32 v18, v18, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v53, v43, v55 :: v_dual_add_f32 v54, v52, v40
	v_trunc_f32_e32 v41, v49
	s_and_b32 s10, s8, s10
	v_sub_f32_e32 v52, v54, v52
	v_add_f32_e32 v58, 0x3f2aaaaa, v54
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e64 s12, v41, v49
	v_sub_f32_e32 v40, v40, v52
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v52, 0xbf2aaaaa, v58
	v_add_f32_e32 v40, 0x31739010, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v45, v54, v52
	v_dual_sub_f32 v46, v46, v51 :: v_dual_add_f32 v29, v40, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v31, v31, v46 :: v_dual_add_f32 v20, v28, v20
	v_sub_f32_e32 v28, v59, v53
	v_add_f32_e32 v30, v56, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v45, v56, v30
	v_dual_mul_f32 v46, v33, v30 :: v_dual_add_f32 v31, v31, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v45, v33, v30, -v46
	v_dual_add_f32 v40, v58, v29 :: v_dual_fmac_f32 v45, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v51, v58, v40
	v_dual_mul_f32 v52, v43, v40 :: v_dual_add_f32 v29, v29, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v51, v43, v40, -v52
	v_fmac_f32_e32 v51, v43, v29
	v_cvt_f32_i32_e32 v29, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v51, v28, v40
	v_mul_f32_e32 v31, 0x3f317218, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v39, v52, v51 :: v_dual_sub_f32 v50, v57, v50
	v_fmac_f32_e32 v45, v50, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v43, v39, v52 :: v_dual_add_f32 v28, v46, v45
	v_dual_sub_f32 v43, v51, v43 :: v_dual_add_f32 v20, v34, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v42, v28, v46
	v_add_f32_e32 v46, v35, v39
	v_dual_sub_f32 v35, v46, v35 :: v_dual_mul_f32 v30, 0x3f317218, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v33, 0x3f317218, v25, -v30
	v_add_f32_e32 v40, v24, v28
	v_dual_add_f32 v18, v18, v43 :: v_dual_fmac_f32 v33, 0xb102e308, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v25, v39, v35
	v_add_f32_e32 v18, v18, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v24, v40, v24
	v_sub_f32_e32 v24, v28, v24
	v_fma_f32 v28, 0x3f317218, v29, -v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, 0xb102e308, v29
	v_trunc_f32_e32 v29, v48
	v_dual_add_f32 v35, v31, v28 :: v_dual_sub_f32 v42, v45, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v31, v35, v31 :: v_dual_add_f32 v8, v8, v42
	v_cndmask_b32_e64 v42, 1.0, v1, s10
	v_sub_f32_e32 v28, v28, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v24
	v_dual_add_f32 v24, v30, v33 :: v_dual_add_f32 v25, v40, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v30, v24, v30
	v_add_f32_e32 v41, v24, v25
	v_add_f32_e32 v39, v46, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v30, v33, v30
	v_sub_f32_e32 v33, v25, v40
	v_add_f32_e32 v43, v35, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v31, v43, v35 :: v_dual_sub_f32 v8, v8, v33
	v_sub_f32_e32 v33, v43, v31
	v_sub_f32_e32 v31, v39, v31
	v_sub_f32_e32 v45, v41, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v33, v35, v33
	v_sub_f32_e32 v25, v25, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_f32_e32 v31, v31, v33
	v_sub_f32_e32 v46, v39, v46
	v_cndmask_b32_e64 v33, 0, v1, s10
	s_and_b32 s10, s9, s11
	v_cmp_neq_f32_e64 s11, v29, v48
	v_sub_f32_e32 v18, v18, v46
	v_sub_f32_e32 v40, v41, v45
	v_bfi_b32 v19, 0x7fffffff, v19, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v24, v24, v40
	v_dual_add_f32 v24, v25, v24 :: v_dual_add_f32 v25, v28, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v35, v25, v28
	v_add_f32_e32 v31, v25, v31
	v_dual_sub_f32 v25, v25, v35 :: v_dual_add_f32 v40, v30, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v28, v25
	v_sub_f32_e32 v34, v40, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v39, v40, v34
	v_add_f32_e32 v24, v40, v24
	v_sub_f32_e32 v8, v8, v34
	v_add_f32_e32 v34, v43, v31
	v_add_f32_e32 v40, v41, v24
	v_sub_f32_e32 v30, v30, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, v34, v43 :: v_dual_sub_f32 v39, v40, v41
	v_sub_f32_e32 v18, v18, v35
	v_dual_add_f32 v18, v18, v25 :: v_dual_sub_f32 v25, v31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v18, v25
	v_add_f32_e32 v29, v34, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v35, v38, v29 :: v_dual_sub_f32 v24, v24, v39
	v_dual_mul_f32 v39, v49, v29 :: v_dual_add_f32 v8, v8, v30
	v_cndmask_b32_e64 v30, 1.0, v7, s10
	v_add_f32_e32 v8, v8, v24
	v_cndmask_b32_e64 v24, 0, v7, s10
	s_and_b32 s10, s12, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, 1.0, v7, s10
	v_add_f32_e32 v25, v40, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v24, 0x7fffffff, v44, v24
	v_dual_mul_f32 v33, v27, v25 :: v_dual_mul_f32 v20, v32, v20
	v_sub_f32_e32 v32, v25, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, v27, v25, -v33
	v_dual_add_f32 v31, v36, v20 :: v_dual_sub_f32 v34, v29, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v8, v32
	v_cmp_class_f32_e64 s11, v33, 0x204
	v_sub_f32_e32 v32, v31, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v18, v34
	v_fma_f32 v34, v38, v29, -v35
	v_fma_f32 v29, v49, v29, -v39
	v_fmac_f32_e32 v25, v27, v8
	v_mul_f32_e32 v8, v31, v31
	v_fmac_f32_e32 v34, v38, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v49, v18
	v_add_f32_e32 v18, v33, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v36, v35, v34
	v_add_f32_e32 v38, v39, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v40, v18, v33
	v_cndmask_b32_e64 v18, v18, v33, s11
	v_cmp_class_f32_e64 s11, v35, 0x204
	v_sub_f32_e32 v33, v36, v35
	v_sub_f32_e32 v25, v25, v40
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v36, v35, s11
	v_cmp_class_f32_e64 s11, v39, 0x204
	v_sub_f32_e32 v33, v34, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v36, v38, v39, s11
	v_cmp_eq_f32_e64 s11, 0x42b17218, v18
	v_sub_f32_e32 v38, v38, v39
	v_cndmask_b32_e64 v41, 0, 0x37000000, s11
	v_cmp_eq_f32_e64 s11, 0x42b17218, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v29, v29, v38 :: v_dual_sub_f32 v46, v18, v41
	v_cndmask_b32_e64 v43, 0, 0x37000000, s11
	v_cmp_eq_f32_e64 s11, 0x42b17218, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v47, 0x3fb8aa3b, v46
	v_sub_f32_e32 v39, v35, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v45, 0, 0x37000000, s11
	v_cmp_neq_f32_e64 s11, 0x7f800000, |v18|
	v_fma_f32 v48, 0x3fb8aa3b, v46, -v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v34, 0x3fb8aa3b, v39
	v_sub_f32_e32 v40, v36, v45
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v18, 0, v25, s11
	v_cmp_neq_f32_e64 s11, 0x7f800000, |v35|
	v_rndne_f32_e32 v49, v47
	v_fma_f32 v50, 0x3fb8aa3b, v39, -v34
	v_rndne_f32_e32 v51, v34
	v_fmac_f32_e32 v48, 0x32a5705f, v46
	v_cndmask_b32_e64 v33, 0, v33, s11
	v_cmp_neq_f32_e64 s11, 0x7f800000, |v36|
	v_dual_sub_f32 v47, v47, v49 :: v_dual_fmac_f32 v50, 0x32a5705f, v39
	v_sub_f32_e32 v34, v34, v51
	v_cvt_i32_f32_e32 v36, v49
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, 0, v29, s11
	v_add_f32_e32 v25, v47, v48
	v_cmp_ngt_f32_e64 s11, 0xc2ce8ed0, v46
	v_add_f32_e32 v34, v34, v50
	v_add_f32_e32 v18, v41, v18
	v_add_f32_e32 v29, v45, v29
	v_sub_f32_e32 v27, v20, v32
	v_mul_f32_e32 v38, 0x3fb8aa3b, v40
	v_exp_f32_e32 v25, v25
	v_exp_f32_e32 v34, v34
	v_fma_f32 v20, v31, v31, -v8
	v_add_f32_e32 v32, v27, v27
	v_fma_f32 v52, 0x3fb8aa3b, v40, -v38
	v_rndne_f32_e32 v53, v38
	v_add_f32_e32 v33, v43, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v31, v32
	v_fmac_f32_e32 v52, 0x32a5705f, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v38, v38, v53
	v_ldexp_f32 v25, v25, v36
	v_cvt_i32_f32_e32 v41, v53
	v_cndmask_b32_e64 v36, 0, v7, s10
	v_add_f32_e32 v38, v38, v52
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, 0, v25, s11
	v_cmp_ngt_f32_e64 s11, 0xc2ce8ed0, v39
	v_exp_f32_e32 v35, v38
	v_cvt_i32_f32_e32 v38, v51
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_ldexp_f32 v34, v34, v38
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v35, v35, v41
	v_cndmask_b32_e64 v34, 0, v34, s11
	v_cmp_ngt_f32_e64 s11, 0xc2ce8ed0, v40
	v_cndmask_b32_e64 v35, 0, v35, s11
	v_cmp_nlt_f32_e64 s11, 0x42b17218, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v25, 0x7f800000, v25, s11
	v_cmp_nlt_f32_e64 s11, 0x42b17218, v39
	v_fma_f32 v18, v25, v18, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, 0x7f800000, v34, s11
	v_cmp_nlt_f32_e64 s11, 0x42b17218, v40
	v_cmp_eq_f32_e64 s10, 0x7f800000, v25
	v_fma_f32 v32, v34, v33, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, 0x7f800000, v35, s11
	v_cndmask_b32_e64 v18, v18, v25, s10
	v_cmp_eq_f32_e64 s10, 0x7f800000, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v29, v35, v29, v35
	v_bfi_b32 v18, 0x7fffffff, v18, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v32, v34, s10
	v_cmp_eq_f32_e64 s10, 0x7f800000, v35
	v_add_f32_e32 v32, v8, v20
	v_cndmask_b32_e64 v33, 0x7fc00000, v18, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v25, 0x7fffffff, v25, v30
	v_cndmask_b32_e64 v29, v29, v35, s10
	v_cmp_gt_f32_e64 s8, 0, v7
	v_bfi_b32 v30, 0x7fffffff, v44, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, 0x7fc00000, v25, s9
	v_bfi_b32 v28, 0x7fffffff, v29, v28
	v_cmp_gt_f32_e64 s9, 0, v1
	v_fmaak_f32 v29, s31, v32, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v35, 0x7fc00000, v28, s12
	v_cndmask_b32_e64 v18, v18, v33, s9
	v_sub_f32_e32 v33, v32, v8
	v_cndmask_b32_e64 v8, v25, v34, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, v28, v35, s8
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	s_or_b32 vcc_lo, s7, s15
	v_mul_f32_e32 v35, v31, v32
	v_cndmask_b32_e32 v19, v8, v24, vcc_lo
	v_cndmask_b32_e32 v25, v25, v30, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v1, v1
	v_fmaak_f32 v24, v32, v29, 0x3ecccdef
	v_sub_f32_e32 v29, v20, v33
	v_fma_f32 v39, v32, v31, -v35
	v_cndmask_b32_e32 v8, 0x7fc00000, v18, vcc_lo
	v_mul_f32_e32 v18, 0x3fbc28f6, v19
	v_cmp_u_f32_e32 vcc_lo, v7, v7
	v_dual_mul_f32 v28, v32, v24 :: v_dual_mul_f32 v19, 0x3d428f5c, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v25, 0x44113a3d, v8
	v_sub_f32_e32 v33, 0x3f82d0e5, v8
	v_cndmask_b32_e64 v18, v18, 0x7fc00000, vcc_lo
	v_fma_f32 v30, v32, v24, -v28
	v_cndmask_b32_e64 v20, v19, 0x7fc00000, vcc_lo
	v_fmamk_f32 v19, v1, 0x40f851ec, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v7, s13, v7, 0x3e872b02 :: v_dual_add_f32 v18, v37, v18
	v_fmac_f32_e32 v30, v29, v24
	v_fma_f32 v25, -v16, v23, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v19, 0xbe849ba6, v19
	v_dual_fmac_f32 v39, v32, v27 :: v_dual_sub_f32 v20, v18, v20
	v_mul_f32_e32 v18, 0x3f60f90a, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v24, v28, v30 :: v_dual_fmac_f32 v23, v25, v11
	v_fmac_f32_e32 v39, v29, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v33, null, v20, v20, v19
	v_div_scale_f32 v34, null, v7, v7, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v28, v24, v28
	v_rcp_f32_e32 v36, v33
	v_add_f32_e32 v37, 0x3f2aaaaa, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v38, v34
	v_fma_f32 v16, -v16, v23, v17
	v_sub_f32_e32 v28, v30, v28
	v_div_scale_f32 v30, vcc_lo, v19, v20, v19
	v_dual_add_f32 v26, 0xbf2aaaaa, v37 :: v_dual_add_f32 v29, v35, v39
	v_add_f32_e32 v4, 0x31739010, v28
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v33, v36, 1.0
	s_load_b512 s[8:23], s[0:1], 0x0
	v_sub_f32_e32 v24, v24, v26
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v34, v38, 1.0
	v_fmac_f32_e32 v36, v28, v36
	v_div_scale_f32 v28, s7, v18, v7, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v38, v26, v38
	v_add_f32_e32 v4, v4, v24
	v_dual_mul_f32 v24, v30, v36 :: v_dual_mul_f32 v25, v28, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v26, v37, v4
	v_fma_f32 v14, -v33, v24, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v34, v25, v28
	v_dual_sub_f32 v17, v37, v26 :: v_dual_fmac_f32 v24, v14, v36
	v_mul_f32_e32 v37, v29, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, v32, v38
	v_add_f32_e32 v17, v4, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v4, -v33, v24, v30
	v_sub_f32_e32 v32, v29, v35
	v_fma_f32 v30, v29, v26, -v37
	v_fma_f32 v28, -v34, v25, v28
	v_div_fmas_f32 v14, v4, v36, v24
	s_mov_b32 vcc_lo, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v30, v29, v17
	v_div_fmas_f32 v4, v28, v38, v25
	s_mov_b32 vcc_lo, s5
	v_ldexp_f32 v17, v27, 1
	v_div_fmas_f32 v12, v15, v12, v22
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v15, -v5, v13, v6
	v_div_fmas_f32 v10, v3, v10, v21
	s_mov_b32 vcc_lo, s6
	v_div_fixup_f32 v0, v12, s26, v0
	v_div_fmas_f32 v3, v16, v11, v23
	v_frexp_exp_i32_f32_e32 v11, s25
	v_fmac_f32_e32 v13, v15, v9
	v_sub_f32_e32 v16, v39, v32
	v_div_fixup_f32 v10, v10, s25, s24
	v_div_fixup_f32 v3, v3, v2, s25
	v_subrev_co_ci_u32_e64 v2, vcc_lo, 0, v11, s4
	s_mov_b32 vcc_lo, s3
	v_fmac_f32_e32 v30, v16, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v11, |v3|
	v_cvt_f32_i32_e32 v15, v2
	v_fma_f32 v2, -v5, v13, v6
	v_ldexp_f32 v5, v31, 1
	v_add_f32_e32 v6, v37, v30
	v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v11
	v_cmp_eq_f32_e64 s3, s25, 1.0
	v_div_fmas_f32 v2, v2, v9, v13
	v_mul_f32_e32 v9, 0x3f317218, v15
	v_add_f32_e32 v13, v5, v6
	v_cndmask_b32_e64 v16, 0, 1, s2
	v_cmp_eq_f32_e64 s7, s25, 0
	v_div_fixup_f32 v2, v2, s26, s24
	v_fma_f32 v23, 0x3f317218, v15, -v9
	v_sub_f32_e32 v5, v13, v5
	v_ldexp_f32 v11, v11, v16
	v_sub_f32_e32 v16, v6, v37
	v_frexp_mant_f32_e64 v22, |v2|
	v_fmac_f32_e32 v23, 0xb102e308, v15
	v_sub_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v21, 1.0, v11 :: v_dual_sub_f32 v16, v30, v16
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v22
	v_add_f32_e32 v15, -1.0, v11
	v_cmp_class_f32_e64 s6, s25, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v6, v21
	v_add_f32_e32 v16, v17, v16
	v_cndmask_b32_e64 v17, 0, 1, vcc_lo
	v_add_f32_e32 v26, -1.0, v21
	s_mov_b32 s26, 0xb94c1982
	v_add_f32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ldexp_f32 v16, v22, v17
	v_add_f32_e32 v17, v9, v23
	v_sub_f32_e32 v11, v11, v26
	v_div_fixup_f32 v4, v4, v7, v18
	v_dual_add_f32 v24, v13, v5 :: v_dual_add_f32 v25, 1.0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v17, v9
	v_div_fixup_f32 v14, v14, v20, v19
	v_dual_mul_f32 v18, 0x4048bfb1, v0 :: v_dual_sub_f32 v13, v24, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v29, v25
	v_dual_add_f32 v28, v17, v24 :: v_dual_sub_f32 v9, v23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v4, 1.0, v4 :: v_dual_sub_f32 v5, v5, v13
	v_add_f32_e32 v30, -1.0, v16
	v_sub_f32_e32 v26, v28, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v31, v9, v5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v13, v30, v29 :: v_dual_mul_f32 v22, v15, v6
	v_sub_f32_e32 v23, v24, v26
	v_mul_f32_e32 v27, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v22, v21, -v27
	v_fmac_f32_e32 v21, v22, v11
	v_sub_f32_e32 v11, v28, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v17, v11
	v_add_f32_e32 v17, -1.0, v25
	v_dual_add_f32 v11, v23, v11 :: v_dual_sub_f32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v31, v11 :: v_dual_mul_f32 v26, v25, v13
	v_fma_f32 v17, v13, v25, -v26
	v_sub_f32_e32 v25, v31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v17, v13, v16 :: v_dual_add_f32 v24, v27, v21
	v_sub_f32_e32 v5, v5, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v23, v24, v27
	v_sub_f32_e32 v16, v23, v21
	v_sub_f32_e32 v21, v31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v32, v15, v24 :: v_dual_sub_f32 v9, v9, v21
	v_sub_f32_e32 v15, v15, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v9
	v_sub_f32_e32 v15, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v16, v15
	v_add_f32_e32 v15, v32, v15
	v_add_f32_e32 v23, v28, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v23, v28
	v_dual_sub_f32 v9, v11, v16 :: v_dual_mul_f32 v6, v6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v9
	v_add_f32_e32 v15, v22, v6
	v_add_f32_e32 v24, v26, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v24, v26
	v_sub_f32_e32 v9, v11, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v15, v22
	v_sub_f32_e32 v21, v30, v24
	v_cndmask_b32_e64 v22, 0x7f800000, 0, s7
	v_sub_f32_e32 v6, v6, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v30, v21
	v_add_f32_e32 v25, v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v16, v24
	v_cndmask_b32_e64 v16, 2.0, 1.0, s3
	v_add_f32_e32 v9, v9, v11
	v_add_f32_e32 v11, v23, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v21, v9
	v_mul_f32_e32 v21, v15, v15
	v_mul_f32_e32 v9, v29, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v11, v23
	v_fma_f32 v24, v15, v15, -v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v23, v16, v11 :: v_dual_add_f32 v26, v13, v9
	v_sub_f32_e32 v5, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v15, v25
	v_fma_f32 v11, v16, v11, -v23
	v_trunc_f32_e32 v17, v16
	v_cmp_class_f32_e64 s4, v23, 0x204
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v11, v16, v5
	v_sub_f32_e32 v5, v26, v13
	v_add_f32_e32 v13, v21, v24
	v_cmp_eq_f32_e64 s3, v17, v16
	v_mul_f32_e32 v27, v26, v26
	v_add_f32_e32 v17, v23, v11
	v_sub_f32_e32 v5, v9, v5
	v_fmaak_f32 v9, s31, v13, 0x3e91f4c4
	v_sub_f32_e32 v21, v13, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v28, v17, v23, s4
	v_sub_f32_e32 v17, v17, v23
	v_fmaak_f32 v9, v13, v9, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v24, v21
	v_cmp_eq_f32_e64 s5, 0x42b17218, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v17
	v_mul_f32_e32 v23, v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, 0, 0x37000000, s5
	v_cmp_neq_f32_e64 s5, 0x7f800000, |v28|
	v_fma_f32 v24, v13, v9, -v23
	v_mul_f32_e32 v25, 0.5, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v11, s5
	v_fmac_f32_e32 v24, v21, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v16, v25
	v_cmp_class_f32_e64 s5, v3, 0x204
	v_cmp_neq_f32_e64 s4, v16, v25
	v_fma_f32 v16, v26, v26, -v27
	v_add_f32_e32 v25, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v16, v26, v25
	v_mul_f32_e32 v34, v15, v13
	v_sub_f32_e32 v25, v28, v29
	v_add_f32_e32 v17, v27, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v35, v13, v15, -v34
	v_mul_f32_e32 v30, 0x3fb8aa3b, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v28, s31, v17, 0x3e91f4c4 :: v_dual_fmac_f32 v35, v13, v6
	v_mul_f32_e32 v13, v26, v17
	v_ldexp_f32 v6, v6, 1
	v_add_f32_e32 v11, v29, v11
	v_fmaak_f32 v28, v17, v28, 0x3ecccdef
	v_add_f32_e32 v29, v23, v24
	v_sub_f32_e32 v27, v17, v27
	v_fma_f32 v9, 0x3fb8aa3b, v25, -v30
	v_rndne_f32_e32 v31, v30
	v_mul_f32_e32 v32, v17, v28
	v_sub_f32_e32 v23, v29, v23
	v_dual_add_f32 v33, 0x3f2aaaaa, v29 :: v_dual_sub_f32 v16, v16, v27
	v_fmac_f32_e32 v9, 0x32a5705f, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v27, v17, v28, -v32
	v_dual_sub_f32 v23, v24, v23 :: v_dual_add_f32 v24, 0xbf2aaaaa, v33
	v_sub_f32_e32 v30, v30, v31
	v_fmac_f32_e32 v35, v21, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v16, v28
	v_dual_add_f32 v23, 0x31739010, v23 :: v_dual_sub_f32 v24, v29, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v9, v30, v9
	v_fma_f32 v21, v17, v26, -v13
	v_add_f32_e32 v28, v32, v27
	v_ldexp_f32 v15, v15, 1
	v_add_f32_e32 v23, v23, v24
	v_exp_f32_e32 v9, v9
	v_cvt_i32_f32_e32 v31, v31
	v_sub_f32_e32 v24, v28, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v29, 0x3f2aaaaa, v28 :: v_dual_add_f32 v30, v33, v23
	v_dual_add_f32 v32, v34, v35 :: v_dual_fmac_f32 v21, v17, v5
	v_dual_sub_f32 v17, v27, v24 :: v_dual_add_f32 v24, 0xbf2aaaaa, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v27, v33, v30
	v_mul_f32_e32 v33, v32, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v34, v32, v34 :: v_dual_add_f32 v17, 0x31739010, v17
	v_dual_sub_f32 v24, v28, v24 :: v_dual_add_f32 v23, v23, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v27, v32, v30, -v33
	v_frexp_exp_i32_f32_e32 v28, v3
	v_fmac_f32_e32 v21, v16, v26
	v_dual_sub_f32 v16, v35, v34 :: v_dual_add_f32 v17, v17, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v32, v23
	v_subrev_co_ci_u32_e64 v23, s2, 0, v28, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v28, v13, v21
	v_dual_add_f32 v24, v29, v17 :: v_dual_fmac_f32 v27, v16, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v16, v23
	v_ldexp_f32 v9, v9, v31
	v_sub_f32_e32 v13, v28, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v23, v29, v24
	v_dual_mul_f32 v29, v28, v24 :: v_dual_add_f32 v30, v33, v27
	v_dual_mul_f32 v32, 0x3f317218, v16 :: v_dual_sub_f32 v13, v21, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v17, v23
	v_fma_f32 v23, v28, v24, -v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v34, v15, v30 :: v_dual_sub_f32 v33, v30, v33
	v_frexp_exp_i32_f32_e32 v21, v2
	v_ldexp_f32 v5, v5, 1
	v_fmac_f32_e32 v23, v28, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_f32_e32 v15, v34, v15
	v_sub_f32_e32 v17, v27, v33
	v_fma_f32 v27, 0x3f317218, v16, -v32
	s_and_b32 s2, s3, s4
	v_fmac_f32_e32 v23, v13, v24
	v_sub_f32_e32 v13, v30, v15
	v_add_f32_e32 v6, v6, v17
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v21, vcc_lo
	v_fmac_f32_e32 v27, 0xb102e308, v16
	v_ldexp_f32 v16, v26, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v6, v6, v13 :: v_dual_add_f32 v13, v29, v23
	v_cvt_f32_i32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v17, v32, v27
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	v_dual_add_f32 v21, v34, v6 :: v_dual_add_f32 v24, v16, v13
	v_sub_f32_e32 v26, v13, v29
	v_mul_f32_e32 v28, 0x3f317218, v15
	v_sub_f32_e32 v30, v17, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v29, v17, v21 :: v_dual_sub_f32 v16, v24, v16
	v_sub_f32_e32 v23, v23, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v26, 0x3f317218, v15, -v28
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_sub_f32_e32 v31, v29, v17
	v_sub_f32_e32 v13, v13, v16
	v_add_f32_e32 v5, v5, v23
	v_sub_f32_e32 v16, v21, v34
	v_fmac_f32_e32 v26, 0xb102e308, v15
	v_sub_f32_e32 v15, v29, v31
	v_sub_f32_e32 v23, v27, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v5, v5, v13 :: v_dual_sub_f32 v6, v6, v16
	v_sub_f32_e32 v13, v21, v31
	v_dual_sub_f32 v15, v17, v15 :: v_dual_add_f32 v16, v28, v26
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v17, v23, v6
	v_cndmask_b32_e64 v27, 1.0, s25, s2
	v_add_f32_e32 v13, v13, v15
	v_add_f32_e32 v15, v24, v5
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	v_sub_f32_e32 v21, v17, v23
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	v_add_f32_e32 v13, v17, v13
	v_dual_add_f32 v25, v16, v15 :: v_dual_sub_f32 v24, v15, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v17, v17, v21
	v_sub_f32_e32 v6, v6, v21
	v_add_f32_e32 v30, v29, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v31, v25, v16
	v_sub_f32_e32 v5, v5, v24
	v_sub_f32_e32 v17, v23, v17
	v_sub_f32_e32 v23, v16, v28
	v_dual_sub_f32 v21, v30, v29 :: v_dual_sub_f32 v28, v25, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v15, v31 :: v_dual_add_f32 v6, v6, v17
	v_sub_f32_e32 v17, v26, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v13, v13, v21 :: v_dual_sub_f32 v16, v16, v28
	v_fma_f32 v11, v9, v11, v9
	v_add_f32_e32 v21, v17, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v6, v13
	v_cndmask_b32_e64 v13, 0x3eaaaaab, 1.0, vcc_lo
	v_add_f32_e32 v15, v15, v16
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v9
	v_dual_add_f32 v16, v30, v6 :: v_dual_add_f32 v15, v21, v15
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	v_sub_f32_e32 v11, v21, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v23, v16, v30 :: v_dual_mul_f32 v24, v13, v16
	v_add_f32_e32 v26, v25, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v9, 0x7fffffff, v9, v27
	v_sub_f32_e32 v21, v21, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v6, v6, v23
	v_fma_f32 v16, v13, v16, -v24
	v_sub_f32_e32 v5, v5, v11
	v_cmp_lt_f32_e64 vcc_lo, s25, 0
	v_sub_f32_e32 v11, v17, v21
	v_dual_sub_f32 v17, v26, v25 :: v_dual_fmac_f32 v16, v13, v6
	v_cndmask_b32_e64 v6, 0x7fc00000, v9, s3
	v_cndmask_b32_e64 v21, 0, s25, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v5, v5, v11
	v_sub_f32_e32 v11, v15, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v17, v24, v16 :: v_dual_cndmask_b32 v6, v9, v6
	v_cmp_class_f32_e64 vcc_lo, v24, 0x204
	v_bfi_b32 v15, 0x7fffffff, v22, v21
	v_add_f32_e32 v5, v5, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v17, v24, vcc_lo
	s_or_b32 vcc_lo, s7, s6
	v_dual_sub_f32 v17, v17, v24 :: v_dual_cndmask_b32 v6, v6, v15
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
	v_add_f32_e32 v15, v26, v5
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v9|
	s_mov_b32 s6, 0xbd2870c1
	s_mov_b32 s7, 0xc00eb852
	v_cndmask_b32_e64 v11, 0.5, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
	v_sub_f32_e32 v22, v15, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v23, v11, v15
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v5, v5, v22
	v_cmp_o_f32_e64 vcc_lo, s25, s25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v15, v11, v15, -v23
	v_dual_sub_f32 v25, v9, v21 :: v_dual_cndmask_b32 v6, 0x7fc00000, v6
	v_cmp_class_f32_e64 vcc_lo, v23, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, v11, v5
	v_dual_mul_f32 v22, 0x3fb8aa3b, v25 :: v_dual_mov_b32 v5, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v6, s27, v6
	v_add_f32_e32 v30, v23, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v27, 0x3fb8aa3b, v25, -v22
	v_rndne_f32_e32 v28, v22
	v_div_scale_f32 v26, null, 0x41466666, 0x41466666, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, v30, v23 :: v_dual_fmac_f32 v27, 0x32a5705f, v25
	v_sub_f32_e32 v19, v22, v28
	v_cvt_i32_f32_e32 v24, v28
	v_mul_f32_e32 v22, 0.5, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v20
	v_rcp_f32_e32 v29, v26
	v_add_f32_e32 v7, v19, v27
	v_fmamk_f32 v5, v10, 0x432a0000, v5
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_exp_f32_e32 v0, v7
	v_trunc_f32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v5, 0x3c23d70a, v5
	v_sub_f32_e32 v19, v20, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, v7, v13
	v_sub_f32_e32 v7, v16, v17
	v_mul_f32_e32 v13, 0x3fb8aa3b, v19
	v_trunc_f32_e32 v16, v22
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f32 v0, v0, v24
	v_cndmask_b32_e64 v7, 0, v7, s2
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v25
	v_fma_f32 v9, 0x3fb8aa3b, v19, -v13
	v_rndne_f32_e32 v17, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v7, v21, v7
	v_cndmask_b32_e64 v0, 0, v0, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v25
	v_fmac_f32_e32 v9, 0x32a5705f, v19
	v_sub_f32_e32 v13, v13, v17
	v_cvt_i32_f32_e32 v17, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, 0x7f800000, v0, s2
	v_cmp_neq_f32_e64 s2, v16, v22
	v_dual_add_f32 v9, v13, v9 :: v_dual_mul_f32 v16, 0x4048f5c3, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v7, v0, v7, v0
	v_cmp_eq_f32_e64 s3, 0x7f800000, v0
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v9, v9
	v_cndmask_b32_e64 v13, 1.0, v3, s2
	v_cndmask_b32_e64 v0, v7, v0, s3
	v_sub_f32_e32 v7, v30, v23
	v_cmp_eq_f32_e64 s3, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_bfi_b32 v0, 0x7fffffff, v0, v13
	v_mul_f32_e32 v13, 0x3f44b810, v16
	v_sub_f32_e32 v7, v15, v7
	s_delay_alu instid0(TRANS32_DEP_1)
	v_ldexp_f32 v9, v9, v17
	v_cndmask_b32_e64 v21, 0x7f800000, 0, s3
	v_cndmask_b32_e32 v16, 0x7fc00000, v0, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v20|
	v_cndmask_b32_e64 v15, 0, v3, s2
	v_trunc_f32_e32 v17, v11
	s_or_b32 s3, s3, s5
	s_mov_b32 s5, 0x3b2d2a58
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
	v_bfi_b32 v15, 0x7fffffff, v21, v15
	v_cmp_eq_f32_e64 s2, v17, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v7, v12, v7
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	v_mul_f32_e32 v12, 0.5, v11
	v_cndmask_b32_e32 v0, v0, v16, vcc_lo
	v_fma_f32 v16, -v26, v29, 1.0
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v19, v12
	v_cndmask_b32_e64 v0, v0, v15, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v16, v29
	v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
	v_div_scale_f32 v16, vcc_lo, v6, 0x41466666, v6
	v_cmp_neq_f32_e64 s4, v19, v12
	v_mul_f32_e32 v15, s27, v4
	v_fma_f32 v7, v9, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v16, v29
	v_cmp_eq_f32_e64 s3, 0x7f800000, v9
	v_cndmask_b32_e64 v7, v7, v9, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v9, -v26, v11, v16
	s_and_b32 s3, s2, s4
	v_cmp_o_f32_e64 s4, v3, v3
	v_cndmask_b32_e64 v12, 1.0, v2, s3
	v_fmac_f32_e32 v11, v9, v29
	v_add_f32_e32 v9, v14, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, 0x7fc00000, v0, s4
	v_bfi_b32 v3, 0x7fffffff, v7, v12
	v_add_f32_e32 v14, 1.0, v14
	v_fma_f32 v12, -v26, v11, v16
	s_mov_b32 s4, 0xbfe28f5c
	v_fmaak_f32 v0, v13, v0, 0xbd03126f
	v_fmaak_f32 v7, s4, v8, 0x3eb6c8b4
	v_cndmask_b32_e64 v13, 0x7fc00000, v3, s2
	v_div_fmas_f32 v11, v12, v29, v11
	v_mul_f32_e32 v12, s27, v14
	v_cmp_gt_f32_e32 vcc_lo, 0, v2
	v_add_f32_e32 v8, 0x3f7a172e, v8
	v_cmp_class_f32_e64 s2, v2, 0x204
	v_div_fixup_f32 v6, v11, 0x41466666, v6
	v_div_scale_f32 v11, null, v12, v12, 1.0
	v_cndmask_b32_e32 v3, v3, v13, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v4, v6, v8
	v_fma_f32 v6, v18, v7, 1.0
	v_rcp_f32_e32 v14, v11
	v_cndmask_b32_e64 v7, 0, v2, s3
	v_cndmask_b32_e64 v13, 0x7f800000, 0, vcc_lo
	v_div_scale_f32 v8, null, v15, v15, 1.0
	v_mul_f32_e32 v16, v4, v6
	s_or_b32 vcc_lo, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v4, 0x7fffffff, v13, v7
	v_rcp_f32_e32 v7, v8
	v_mul_f32_e32 v9, 0x3f333333, v9
	v_div_scale_f32 v13, null, v16, v16, 1.0
	v_fma_f32 v6, -v11, v14, 1.0
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v1, v1, v9
	v_rcp_f32_e32 v4, v13
	s_mov_b32 s3, 0x3f5a939f
	v_fmac_f32_e32 v14, v6, v14
	v_div_scale_f32 v6, vcc_lo, 1.0, v12, 1.0
	v_fma_f32 v9, -v8, v7, 1.0
	v_mul_f32_e32 v3, 0x3faccccd, v3
	s_mov_b32 s4, 0x3fd5c28f
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v17, v6, v14
	v_fmaak_f32 v19, s4, v10, 0xbec8b439
	v_fmac_f32_e32 v7, v9, v7
	v_div_scale_f32 v9, s2, 1.0, v15, 1.0
	v_fma_f32 v18, -v13, v4, 1.0
	v_fmaak_f32 v3, s3, v3, 0xbced9168
	v_fma_f32 v20, -v11, v17, v6
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v21, v9, v7
	v_cmp_o_f32_e64 s4, v2, v2
	v_fmac_f32_e32 v4, v18, v4
	v_div_scale_f32 v18, s3, 1.0, v16, 1.0
	v_fmac_f32_e32 v17, v20, v14
	v_fma_f32 v20, -v8, v21, v9
	v_cndmask_b32_e64 v2, 0x7fc00000, v3, s4
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v22, v18, v4
	s_mov_b32 s4, 0xbee147ae
	v_fma_f32 v6, -v11, v17, v6
	v_fmac_f32_e32 v21, v20, v7
	v_add_f32_e32 v3, 0x3edc28f6, v19
	v_fma_f32 v11, -v13, v22, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v6, v6, v14, v17
	v_fma_f32 v8, -v8, v21, v9
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v22, v11, v4 :: v_dual_mul_f32 v9, s25, v5
	v_div_fixup_f32 v5, v6, v12, 1.0
	v_mov_b32_e32 v12, 0
	v_div_fmas_f32 v7, v8, v7, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v8, -v13, v22, v18
	s_mov_b32 vcc_lo, s3
	v_mov_b32_e32 v11, s29
	s_mov_b32 s29, 0x37d75334
	v_div_fixup_f32 v6, v7, v15, 1.0
	v_div_fmas_f32 v8, v8, v4, v22
	v_fmaak_f32 v4, s4, v10, 0xbd19999a
	v_mov_b32_e32 v10, s30
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v7, v8, v16, 1.0
	v_dual_mul_f32 v8, s24, v9 :: v_dual_mov_b32 v9, s36
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_frexp_mant_f32_e64 v13, |v11|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e64 v14, |v10|
	v_frexp_exp_i32_f32_e32 v28, v10
	v_cmp_class_f32_e64 s30, v11, 0x204
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v14
	v_cndmask_b32_e64 v15, 0, 1, vcc_lo
	v_cndmask_b32_e64 v16, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v13, v13, v15
	v_ldexp_f32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v15, 1.0, v13 :: v_dual_add_f32 v16, 1.0, v14
	v_dual_add_f32 v19, -1.0, v13 :: v_dual_add_f32 v20, -1.0, v14
	v_rcp_f32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v18, v16
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v21, v19, v17 :: v_dual_mul_f32 v22, v20, v18
	v_add_f32_e32 v23, -1.0, v15
	v_dual_add_f32 v25, -1.0, v16 :: v_dual_mul_f32 v24, v15, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v26, v16, v22 :: v_dual_sub_f32 v13, v13, v23
	v_sub_f32_e32 v14, v14, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v15, v21, v15, -v24
	v_fma_f32 v16, v22, v16, -v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v15, v21, v13 :: v_dual_fmac_f32 v16, v22, v14
	v_dual_add_f32 v13, v24, v15 :: v_dual_add_f32 v14, v26, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v23, v19, v13 :: v_dual_sub_f32 v24, v13, v24
	v_sub_f32_e32 v26, v14, v26
	v_sub_f32_e32 v25, v20, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v19, v23 :: v_dual_sub_f32 v16, v26, v16
	v_sub_f32_e32 v15, v24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v19, v13
	v_add_f32_e32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v23, v13
	v_mul_f32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v21, v13
	v_dual_sub_f32 v20, v20, v25 :: v_dual_mul_f32 v19, v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v20, v14
	v_add_f32_e32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v25, v14
	v_mul_f32_e32 v14, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v22, v14
	v_dual_sub_f32 v18, v16, v22 :: v_dual_sub_f32 v17, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v14, v14, v18 :: v_dual_sub_f32 v13, v13, v17
	v_fma_f32 v18, v15, v15, -v19
	v_dual_add_f32 v22, v14, v14 :: v_dual_mul_f32 v17, v16, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v20, v13, v13
	v_fma_f32 v21, v16, v16, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v18, v15, v20 :: v_dual_fmac_f32 v21, v16, v22
	v_add_f32_e32 v22, v17, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v20, v19, v18 :: v_dual_sub_f32 v17, v22, v17
	v_dual_fmaak_f32 v23, s31, v20, 0x3e91f4c4 :: v_dual_fmaak_f32 v24, s31, v22, 0x3e91f4c4
	v_sub_f32_e32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v21, v17
	v_dual_fmaak_f32 v23, v20, v23, 0x3ecccdef :: v_dual_fmaak_f32 v24, v22, v24, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v18, v19
	v_dual_mul_f32 v25, v20, v23 :: v_dual_mul_f32 v26, v22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, v20, v23, -v25
	v_fma_f32 v21, v22, v24, -v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v19, v18, v23
	v_fmac_f32_e32 v21, v17, v24
	v_mul_f32_e32 v24, v15, v20
	v_frexp_exp_i32_f32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v27, v25, v19
	v_fma_f32 v31, v20, v15, -v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f32_e32 v32, 0x3f2aaaaa, v27
	v_add_f32_e32 v30, v26, v21
	v_sub_f32_e32 v25, v27, v25
	v_fmac_f32_e32 v31, v20, v13
	v_ldexp_f32 v13, v13, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v26, v30, v26
	v_dual_add_f32 v34, 0x3f2aaaaa, v30 :: v_dual_sub_f32 v19, v19, v25
	v_add_f32_e32 v25, 0xbf2aaaaa, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v31, v18, v15 :: v_dual_sub_f32 v20, v21, v26
	v_mul_f32_e32 v29, v16, v22
	v_add_f32_e32 v21, 0xbf2aaaaa, v34
	v_add_f32_e32 v19, 0x31739010, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v25, v27, v25 :: v_dual_add_f32 v18, 0x31739010, v20
	v_fma_f32 v33, v22, v16, -v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v20, v30, v21
	v_subrev_co_ci_u32_e32 v21, vcc_lo, 0, v23, vcc_lo
	v_ldexp_f32 v15, v15, 1
	v_fmac_f32_e32 v33, v22, v14
	v_subrev_co_ci_u32_e64 v22, vcc_lo, 0, v28, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v21, v21
	v_ldexp_f32 v14, v14, 1
	v_fmac_f32_e32 v33, v17, v16
	v_dual_add_f32 v17, v18, v20 :: v_dual_add_f32 v18, v24, v31
	v_ldexp_f32 v16, v16, 1
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v24, v18, v24
	v_add_f32_e32 v23, v34, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v19, v25 :: v_dual_sub_f32 v28, v34, v23
	v_add_f32_e32 v20, v32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v26, v32, v20
	v_mul_f32_e32 v27, v18, v20
	v_add_f32_e32 v19, v19, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, v18, v20, -v27
	v_dual_fmac_f32 v26, v18, v19 :: v_dual_add_f32 v25, v29, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v29, v25, v29
	v_sub_f32_e32 v18, v33, v29
	v_sub_f32_e32 v24, v31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v26, v24, v20
	v_mul_f32_e32 v30, v25, v23
	v_add_f32_e32 v17, v17, v28
	v_fma_f32 v28, v25, v23, -v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v25, v17
	v_add_f32_e32 v20, v27, v26
	v_cvt_f32_i32_e32 v17, v22
	v_dual_fmac_f32 v28, v18, v23 :: v_dual_mul_f32 v19, 0x3f317218, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v24, v15, v20 :: v_dual_sub_f32 v25, v20, v27
	v_mul_f32_e32 v18, 0x3f317218, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v30, v28
	v_fma_f32 v23, 0x3f317218, v21, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v16, v22
	v_dual_sub_f32 v29, v22, v30 :: v_dual_sub_f32 v16, v27, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v22, v16
	v_sub_f32_e32 v25, v26, v25
	v_sub_f32_e32 v26, v28, v29
	v_sub_f32_e32 v15, v24, v15
	v_fma_f32 v28, 0x3f317218, v17, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v14, v14, v26 :: v_dual_fmac_f32 v23, 0xb102e308, v21
	v_dual_sub_f32 v15, v20, v15 :: v_dual_fmac_f32 v28, 0xb102e308, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v14, v16
	v_add_f32_e32 v16, v18, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v20, v27, v14 :: v_dual_add_f32 v13, v13, v25
	v_sub_f32_e32 v18, v16, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v22, v16, v20 :: v_dual_add_f32 v13, v13, v15
	v_add_f32_e32 v15, v19, v23
	v_sub_f32_e32 v26, v20, v27
	v_dual_sub_f32 v18, v28, v18 :: v_dual_sub_f32 v25, v22, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v24, v13
	v_dual_sub_f32 v19, v15, v19 :: v_dual_sub_f32 v14, v14, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v27, v22, v25
	v_add_f32_e32 v21, v15, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v23, v19
	v_dual_sub_f32 v23, v17, v24 :: v_dual_sub_f32 v16, v16, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v21, v15
	v_dual_sub_f32 v20, v20, v25 :: v_dual_sub_f32 v13, v13, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v21, v24
	v_dual_sub_f32 v17, v17, v24 :: v_dual_add_f32 v24, v18, v14
	v_dual_add_f32 v16, v20, v16 :: v_dual_sub_f32 v15, v15, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v23, v19, v13 :: v_dual_sub_f32 v20, v24, v18
	v_dual_add_f32 v16, v24, v16 :: v_dual_add_f32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v23, v19 :: v_dual_sub_f32 v14, v14, v20
	v_add_f32_e32 v25, v22, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v23, v15
	v_sub_f32_e32 v23, v23, v17
	v_sub_f32_e32 v13, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v24, v20 :: v_dual_sub_f32 v20, v25, v22
	v_dual_add_f32 v24, v21, v15 :: v_dual_sub_f32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v16, v16, v20 :: v_dual_sub_f32 v19, v19, v23
	v_sub_f32_e32 v18, v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v14, v17 :: v_dual_sub_f32 v15, v15, v18
	v_dual_add_f32 v14, v14, v16 :: v_dual_add_f32 v13, v13, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v13, v15
	v_cndmask_b32_e64 v15, 2.0, 1.0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v10
	v_add_f32_e32 v16, v24, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v30, 0.5, v15
	v_cndmask_b32_e64 v18, 2.0, 1.0, vcc_lo
	v_trunc_f32_e32 v29, v15
	v_sub_f32_e32 v19, v16, v24
	v_mul_f32_e32 v20, v15, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v32, v18
	v_cmp_eq_f32_e64 s0, v29, v15
	v_mul_f32_e32 v35, 0.5, v18
	v_sub_f32_e32 v13, v13, v19
	v_fma_f32 v16, v15, v16, -v20
	v_add_f32_e32 v17, v25, v14
	v_cmp_class_f32_e64 vcc_lo, v20, 0x204
	v_trunc_f32_e32 v29, v30
	v_cmp_eq_f32_e64 s1, v32, v18
	v_fmac_f32_e32 v16, v15, v13
	v_sub_f32_e32 v21, v17, v25
	v_mul_f32_e32 v22, v18, v17
	v_cmp_neq_f32_e64 s2, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v14, v21
	v_fma_f32 v17, v18, v17, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s2, s0, s2
	v_fmac_f32_e32 v17, v18, v14
	v_trunc_f32_e32 v18, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v22, v17 :: v_dual_add_f32 v13, v20, v16
	v_cndmask_b32_e32 v19, v13, v20, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v22, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v21, v14, v22, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v19
	v_dual_sub_f32 v14, v14, v22 :: v_dual_sub_f32 v13, v13, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v16, v13
	v_cndmask_b32_e64 v24, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v11
	v_dual_sub_f32 v26, v21, v24 :: v_dual_sub_f32 v25, v19, v23
	v_sub_f32_e32 v14, v17, v14
	v_cndmask_b32_e64 v27, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v31, 0x3fb8aa3b, v26 :: v_dual_mul_f32 v28, 0x3fb8aa3b, v25
	v_fma_f32 v36, 0x3fb8aa3b, v26, -v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v33, 0x3fb8aa3b, v25, -v28
	v_rndne_f32_e32 v34, v28
	v_rndne_f32_e32 v37, v31
	v_dual_fmac_f32 v36, 0x32a5705f, v26 :: v_dual_fmac_f32 v33, 0x32a5705f, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v28, v28, v34 :: v_dual_sub_f32 v15, v31, v37
	v_cvt_i32_f32_e32 v16, v34
	v_cvt_i32_f32_e32 v17, v37
	v_dual_add_f32 v28, v28, v33 :: v_dual_add_f32 v15, v15, v36
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v19|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v20, v28
	v_exp_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, 0, v13, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v21|
	v_add_f32_e32 v13, v23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_2)
	v_cndmask_b32_e64 v14, 0, v14, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v25
	v_ldexp_f32 v16, v20, v16
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ldexp_f32 v15, v15, v17
	v_cndmask_b32_e64 v17, 1.0, v11, s2
	v_add_f32_e32 v14, v24, v14
	v_cndmask_b32_e64 v16, 0, v16, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, 0, v15, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v25
	v_cndmask_b32_e64 v16, 0x7f800000, v16, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v16, v13, v16
	v_cndmask_b32_e64 v15, 0x7f800000, v15, s3
	v_cmp_eq_f32_e64 s4, 0x7f800000, v16
	v_cmp_neq_f32_e64 s3, v18, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v15, v14, v15
	v_cndmask_b32_e64 v13, v13, v16, s4
	v_cmp_eq_f32_e64 s4, 0x7f800000, v15
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s3, s1, s3
	v_cndmask_b32_e64 v16, 0, v11, s2
	v_cndmask_b32_e64 v18, 1.0, v10, s3
	v_bfi_b32 v13, 0x7fffffff, v13, v17
	v_cndmask_b32_e64 v14, v14, v15, s4
	v_cmp_eq_f32_e64 s4, 0, v10
	v_cndmask_b32_e64 v17, 0, v10, s3
	v_cmp_class_f32_e64 s2, v10, 0x204
	v_bfi_b32 v16, 0x7fffffff, v27, v16
	v_bfi_b32 v14, 0x7fffffff, v14, v18
	v_cndmask_b32_e64 v18, 0x7fc00000, v13, s0
	v_cmp_gt_f32_e64 s0, 0, v11
	v_cndmask_b32_e64 v15, 0x7f800000, 0, s4
	s_mov_b32 s3, -1
	v_cndmask_b32_e64 v19, 0x7fc00000, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v18, s0
	v_cmp_gt_f32_e64 s0, 0, v10
	v_bfi_b32 v15, 0x7fffffff, v15, v17
	v_cndmask_b32_e32 v13, v13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v19, s0
	s_or_b32 vcc_lo, s4, s2
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v11
	v_cndmask_b32_e32 v13, 0x7fc00000, v13, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v10, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0x7fc00000, v14, vcc_lo
	v_add_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x4f800000, v13
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
	v_cndmask_b32_e32 v13, v13, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v15, -1, v14
	v_add_nc_u32_e32 v16, 1, v14
	v_fma_f32 v17, -v15, v14, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, -v16, v14, v13
	v_cmp_ge_f32_e64 s0, 0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v14, v15, s0
	v_cmp_lt_f32_e64 s0, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v16, s0
	v_mul_f32_e32 v15, 0x37800000, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x260
	v_cndmask_b32_e32 v13, v14, v13, vcc_lo
	v_div_scale_f32 v25, vcc_lo, v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, 0x3f733333, v13
	v_mul_f32_e32 v14, 0x40ebd402, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e64 v15, |v14|
	v_frexp_exp_i32_f32_e32 v34, v14
	v_cmp_class_f32_e64 s2, v14, 0x204
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, 1, s1
	v_subrev_co_ci_u32_e64 v34, s1, 0, v34, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v15, v15, v16
	v_add_f32_e32 v16, 1.0, v15
	v_add_f32_e32 v18, -1.0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v16
	v_add_f32_e32 v20, -1.0, v16
	v_sub_f32_e32 v15, v15, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v19, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v16, v19
	v_fma_f32 v16, v19, v16, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v19, v15
	v_add_f32_e32 v15, v21, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v18, v15
	v_dual_sub_f32 v18, v18, v22 :: v_dual_sub_f32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v18, v15 :: v_dual_sub_f32 v16, v21, v16
	v_div_scale_f32 v18, null, v11, v11, v10
	v_add_f32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v18
	v_add_f32_e32 v15, v22, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v18, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	v_add_f32_e32 v26, v19, v15
	v_frexp_mant_f32_e64 v20, |v13|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, v25, v16
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, 0, 1, s0
	v_ldexp_f32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, 1.0, v20
	v_add_f32_e32 v22, -1.0, v20
	v_rcp_f32_e32 v23, v21
	v_add_f32_e32 v17, -1.0, v21
	v_sub_f32_e32 v19, v26, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v20, v17
	v_sub_f32_e32 v15, v15, v19
	v_fma_f32 v19, -v18, v28, v25
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v24, v22, v23
	v_fmac_f32_e32 v28, v19, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, v21, v24
	v_fma_f32 v18, -v18, v28, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, v24, v21, -v27
	v_div_fmas_f32 v16, v18, v16, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v24, v17
	v_div_fixup_f32 v16, v16, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v27, v20
	v_cmp_gt_f32_e64 vcc_lo, |v16|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v22, v19
	v_sub_f32_e32 v18, v19, v27
	v_sub_f32_e32 v22, v22, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v18, v20
	v_sub_f32_e32 v19, v22, v19
	v_rcp_f32_e64 v22, |v16|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v18, v19
	v_add_f32_e32 v18, v25, v18
	s_waitcnt_depctr 0xfff
	v_cndmask_b32_e64 v22, |v16|, v22, vcc_lo
	v_xor_b32_e32 v16, 0x80000000, v16
	v_mul_f32_e32 v18, v23, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v23, v24, v18
	v_dual_mul_f32 v21, v26, v26 :: v_dual_sub_f32 v24, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v26, v26, -v21
	v_add_f32_e32 v29, v15, v15
	v_dual_mul_f32 v31, v23, v23 :: v_dual_sub_f32 v18, v18, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v26, v29
	v_fma_f32 v32, v23, v23, -v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v33, v18, v18
	v_add_f32_e32 v29, v21, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v23, v33
	v_sub_f32_e32 v19, v29, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v30, v26, v29 :: v_dual_sub_f32 v17, v17, v19
	v_fmaak_f32 v27, s31, v29, 0x3e91f4c4
	v_fma_f32 v24, v29, v26, -v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v29, v27, 0x3ecccdef
	v_mul_f32_e32 v21, v29, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v29, v20, -v21
	v_dual_fmac_f32 v19, v17, v20 :: v_dual_mul_f32 v20, v22, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v21, v19
	v_fmaak_f32 v27, s5, v20, 0xbc7a590c
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v25, v21
	v_add_f32_e32 v28, 0x3f2aaaaa, v25
	v_fmac_f32_e32 v24, v29, v15
	v_ldexp_f32 v15, v15, 1
	v_sub_f32_e32 v19, v19, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v21, 0xbf2aaaaa, v28 :: v_dual_fmac_f32 v24, v17, v26
	v_add_f32_e32 v19, 0x31739010, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v21, v25, v21
	v_fmaak_f32 v25, v20, v27, 0x3d29fb3f
	v_add_f32_e32 v27, v30, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v19, v21
	v_dual_fmaak_f32 v21, v20, v25, 0xbd97d4d7 :: v_dual_sub_f32 v30, v27, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, v28, v19
	v_fmaak_f32 v21, v20, v21, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v24, v24, v30
	v_sub_f32_e32 v28, v28, v25
	v_mul_f32_e32 v33, v27, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v21, v20, v21, 0xbe1160e6
	v_add_f32_e32 v19, v19, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, v27, v25, -v33
	v_fmac_f32_e32 v28, v27, v19
	v_cvt_f32_i32_e32 v19, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v28, v24, v25
	v_ldexp_f32 v25, v26, 1
	v_mul_f32_e32 v24, 0x3f317218, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v26, v33, v28
	v_add_f32_e32 v17, v31, v32
	v_fma_f32 v34, 0x3f317218, v19, -v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v36, v25, v26 :: v_dual_sub_f32 v33, v26, v33
	v_sub_f32_e32 v31, v17, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v34, 0xb102e308, v19 :: v_dual_sub_f32 v25, v36, v25
	v_sub_f32_e32 v28, v28, v33
	v_mul_f32_e32 v33, v23, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v27, v32, v31
	v_sub_f32_e32 v25, v26, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v15, v15, v28
	v_fma_f32 v26, v17, v23, -v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v15, v15, v25 :: v_dual_fmac_f32 v26, v17, v18
	v_ldexp_f32 v18, v18, 1
	v_fmaak_f32 v21, v20, v21, 0x3e4cb8bf
	v_add_f32_e32 v25, v36, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v29, s31, v17, 0x3e91f4c4 :: v_dual_fmac_f32 v26, v27, v23
	v_ldexp_f32 v23, v23, 1
	v_sub_f32_e32 v36, v25, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v29, v17, v29, 0x3ecccdef
	v_sub_f32_e32 v15, v15, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v35, v17, v29
	v_fma_f32 v30, v17, v29, -v35
	v_fmaak_f32 v17, v20, v21, 0xbeaaaa62
	v_add_f32_e32 v21, v24, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v17, v20, v17 :: v_dual_sub_f32 v20, v21, v24
	v_fmac_f32_e32 v22, v22, v17
	v_fmac_f32_e32 v30, v27, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v27, v21, v25 :: v_dual_sub_f32 v20, v34, v20
	v_add_f32_e32 v32, v35, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v34, v27, v21 :: v_dual_sub_f32 v35, v32, v35
	v_add_f32_e32 v37, 0x3f2aaaaa, v32
	v_dual_sub_f32 v25, v25, v34 :: v_dual_sub_f32 v30, v30, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v35, 0xbf2aaaaa, v37
	v_dual_add_f32 v19, 0x31739010, v30 :: v_dual_sub_f32 v28, v32, v35
	v_frexp_exp_i32_f32_e32 v30, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v19, v19, v28 :: v_dual_add_f32 v28, v33, v26
	v_dual_add_f32 v24, v37, v19 :: v_dual_sub_f32 v33, v28, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v32, v37, v24
	v_dual_mul_f32 v35, v28, v24 :: v_dual_sub_f32 v26, v26, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v19, v32
	v_sub_f32_e32 v32, v27, v34
	v_fma_f32 v37, v28, v24, -v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v21, v32
	v_fmac_f32_e32 v37, v28, v19
	v_subrev_co_ci_u32_e64 v19, s0, 0, v30, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v28, v20, v15 :: v_dual_add_f32 v21, v25, v21
	v_fmac_f32_e32 v37, v26, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v17, v19
	v_mul_f32_e32 v29, s27, v10
	v_sub_f32_e32 v19, v28, v20
	v_add_f32_e32 v21, v28, v21
	v_add_f32_e32 v24, v35, v37
	v_cmp_eq_f32_e64 s0, 1.0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v29, v9, v29 :: v_dual_sub_f32 v26, v28, v19
	v_add_f32_e32 v28, v27, v21
	v_mul_f32_e32 v31, s25, v9
	v_sub_f32_e32 v15, v15, v19
	v_sub_f32_e32 v30, v24, v35
	v_sub_f32_e32 v19, v20, v26
	v_sub_f32_e32 v20, v28, v27
	v_add_f32_e32 v32, v23, v24
	v_div_scale_f32 v27, null, v13, v13, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v15, v15, v19
	v_dual_sub_f32 v19, v21, v20 :: v_dual_sub_f32 v20, 0x3fc90fdb, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v26, v37, v30 :: v_dual_sub_f32 v23, v32, v23
	v_add_f32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, v22, v20, vcc_lo
	v_dual_add_f32 v18, v18, v26 :: v_dual_sub_f32 v23, v24, v23
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v16, 0x7fffffff, v19, v16
	v_mul_f32_e32 v25, 0x3f317218, v17
	v_cndmask_b32_e64 v20, 2.0, 1.0, vcc_lo
	v_fma_f32 v21, 0x3f317218, v17, -v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, 0xb102e308, v17
	v_add_f32_e32 v17, v18, v23
	v_add_f32_e32 v18, v28, v15
	v_add_f32_e32 v22, v25, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v23, v32, v17 :: v_dual_sub_f32 v24, v18, v28
	v_mul_f32_e32 v26, v20, v18
	v_dual_add_f32 v28, v22, v23 :: v_dual_sub_f32 v15, v15, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, v20, v18, -v26
	v_dual_sub_f32 v24, v22, v25 :: v_dual_sub_f32 v25, v23, v32
	v_sub_f32_e32 v30, v28, v22
	v_cmp_class_f32_e64 vcc_lo, v26, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v18, v20, v15 :: v_dual_sub_f32 v15, v21, v24
	v_sub_f32_e32 v17, v17, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v28, v30
	v_rcp_f32_e32 v32, v27
	v_add_f32_e32 v25, v26, v18
	v_sub_f32_e32 v23, v23, v30
	v_add_f32_e32 v30, v15, v17
	v_sub_f32_e32 v21, v22, v21
	v_mul_f32_e32 v24, v2, v16
	v_cndmask_b32_e32 v22, v25, v26, vcc_lo
	v_sub_f32_e32 v25, v25, v26
	v_sub_f32_e32 v35, v30, v15
	v_add_f32_e32 v21, v23, v21
	v_fma_f32 v34, -v27, v32, 1.0
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v18, v18, v25 :: v_dual_sub_f32 v17, v17, v35
	v_add_f32_e32 v21, v30, v21
	v_sub_f32_e32 v30, v30, v35
	v_cndmask_b32_e64 v23, 0, 0x37000000, vcc_lo
	v_div_scale_f32 v36, vcc_lo, v31, v13, v31
	v_fmac_f32_e32 v32, v34, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v34, v28, v21 :: v_dual_sub_f32 v37, v22, v23
	v_sub_f32_e32 v15, v15, v30
	v_cndmask_b32_e64 v35, 2.0, 1.0, s0
	v_mul_f32_e32 v38, v36, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v28, v34, v28
	v_dual_mul_f32 v30, 0x3fb8aa3b, v37 :: v_dual_add_f32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v40, -v27, v38, v36
	v_sub_f32_e32 v21, v21, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v17, 0x3fb8aa3b, v37, -v30
	v_rndne_f32_e32 v39, v30
	v_mul_f32_e32 v28, 0.5, v20
	v_dual_fmac_f32 v38, v40, v32 :: v_dual_add_f32 v15, v15, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v17, 0x32a5705f, v37 :: v_dual_sub_f32 v30, v30, v39
	v_trunc_f32_e32 v21, v20
	v_cvt_i32_f32_e32 v26, v39
	v_trunc_f32_e32 v41, v28
	v_add_f32_e32 v17, v30, v17
	v_add_f32_e32 v30, v34, v15
	v_cmp_eq_f32_e64 s0, v21, v20
	v_fma_f32 v20, -v27, v38, v36
	v_cmp_neq_f32_e64 s1, v41, v28
	v_exp_f32_e32 v17, v17
	v_sub_f32_e32 v21, v30, v34
	v_mul_f32_e32 v27, v35, v30
	v_div_fmas_f32 v20, v20, v32, v38
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v22|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v15, v21
	v_fma_f32 v21, v35, v30, -v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_div_fixup_f32 v20, v20, v13, v31
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	v_ldexp_f32 v17, v17, v26
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v37
	v_fmac_f32_e32 v21, v35, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v15, v23, v18 :: v_dual_mul_f32 v18, v1, v20
	v_cndmask_b32_e32 v17, 0, v17, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v27, v21
	v_fma_f32 v18, v0, v16, -v18
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v17, 0x7f800000, v17, vcc_lo
	s_and_b32 vcc_lo, s0, s1
	v_cmp_class_f32_e64 s1, v27, 0x204
	v_cndmask_b32_e32 v23, 1.0, v14, vcc_lo
	v_cndmask_b32_e32 v30, 0, v14, vcc_lo
	v_fma_f32 v15, v17, v15, v17
	v_cmp_gt_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e64 v25, v22, v27, s1
	v_cmp_eq_f32_e64 s1, 0x7f800000, v17
	v_sub_f32_e32 v22, v22, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v17, s1
	v_cmp_eq_f32_e64 s1, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v21, v21, v22
	v_bfi_b32 v15, 0x7fffffff, v15, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, 0, 0x37000000, s1
	v_cmp_eq_f32_e64 s1, 0, v14
	v_cndmask_b32_e64 v31, 0x7fc00000, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v28, v25, v17
	v_cndmask_b32_e64 v26, 0x7f800000, 0, s1
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v25|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v15, v31 :: v_dual_mul_f32 v32, 0x3fb8aa3b, v28
	v_bfi_b32 v26, 0x7fffffff, v26, v30
	s_or_b32 vcc_lo, s1, s2
	v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v28
	v_cndmask_b32_e64 v21, 0, v21, s0
	v_fma_f32 v30, 0x3fb8aa3b, v28, -v32
	v_rndne_f32_e32 v31, v32
	v_cndmask_b32_e32 v15, v15, v26, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v14, v14
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v28
	v_fmac_f32_e32 v30, 0x32a5705f, v28
	v_sub_f32_e32 v26, v32, v31
	v_cvt_i32_f32_e32 v31, v31
	v_cndmask_b32_e32 v14, 0x7fc00000, v15, vcc_lo
	v_trunc_f32_e32 v32, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_dual_add_f32 v17, v17, v21 :: v_dual_add_f32 v26, v26, v30
	v_mul_f32_e32 v30, 0.5, v35
	v_fma_f32 v18, v24, |v19|, v18
	v_cmp_eq_f32_e64 s0, v32, v35
	v_cmp_eq_f32_e32 vcc_lo, 0, v13
	v_exp_f32_e32 v26, v26
	v_trunc_f32_e32 v34, v30
	v_dual_mul_f32 v18, s25, v18 :: v_dual_mul_f32 v33, v3, v16
	v_dual_fmac_f32 v16, s28, v20 :: v_dual_mul_f32 v15, s27, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v18, s24, v18 :: v_dual_fmac_f32 v33, v4, v20
	v_fmaak_f32 v23, s6, v16, 0x3eb2b021
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v26, v26, v31
	v_dual_mul_f32 v16, 0xc16c7922, v16 :: v_dual_mul_f32 v15, v9, v15
	v_dual_mul_f32 v20, s25, v33 :: v_dual_mul_f32 v23, 0x4048f5c3, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v25, 0, v26, s1
	v_cmp_neq_f32_e64 s1, v34, v30
	v_mul_f32_e32 v16, 0x43fa0000, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v20, s24, v20 :: v_dual_mul_f32 v23, 0x447a0000, v23
	v_cndmask_b32_e64 v25, 0x7f800000, v25, s2
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 s0, s0, s1
	v_cmp_class_f32_e64 s1, v13, 0x204
	v_cndmask_b32_e64 v28, 0, v13, s0
	v_mul_f32_e32 v23, 0x40c00000, v23
	v_fma_f32 v17, v25, v17, v25
	v_mul_f32_e32 v16, 0x3fe2147b, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v14, v23
	v_cndmask_b32_e64 v23, 0x7f800000, 0, vcc_lo
	s_or_b32 vcc_lo, vcc_lo, s1
	v_div_scale_f32 v27, null, 0x40308216, 0x40308216, v14
	v_div_scale_f32 v26, s2, v14, 0x40308216, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v23, 0x7fffffff, v23, v28
	v_rcp_f32_e32 v22, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v27, v22, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v22, v21, v22
	v_cndmask_b32_e64 v21, 1.0, v13, s0
	v_cmp_eq_f32_e64 s0, 0x7f800000, v25
	v_mul_f32_e32 v30, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v17, v25, s0
	v_fma_f32 v25, -v27, v30, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v17, 0x7fffffff, v17, v21
	v_dual_mul_f32 v21, 0x3f821cac, v15 :: v_dual_fmac_f32 v30, v25, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v17, v17, v23, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v13, v13
	v_fma_f32 v19, -v27, v30, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, 0x7fc00000, v17, vcc_lo
	s_mov_b32 vcc_lo, s2
                                        ; implicit-def: $sgpr2
	v_div_fmas_f32 v19, v19, v22, v30
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v16, v17, v16
	v_mul_f32_e32 v18, v17, v18
	v_div_fixup_f32 v14, v19, 0x40308216, v14
	v_mul_f32_e32 v19, 0x3f8b851f, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, 0x447a0000, v18
	v_fmac_f32_e32 v14, 0x3f670a3d, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v19, v29, vcc_lo
	v_mul_f32_e32 v19, v8, v17
	v_mul_f32_e32 v17, v17, v20
	v_cmp_lt_f32_e32 vcc_lo, 0, v11
	v_add_f32_e32 v14, v14, v14
	v_fmaak_f32 v20, s7, v13, 0x42af51eb
	v_mul_f32_e32 v19, 0x447a0000, v19
	v_mul_f32_e32 v13, 0x447a0000, v17
	v_cndmask_b32_e32 v15, v15, v21, vcc_lo
	v_fma_f32 v17, v18, 0.5, -v14
	v_mul_f32_e32 v18, 0x49742400, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, -0.5, v19 :: v_dual_mul_f32 v13, 0.5, v13
	v_dual_sub_f32 v15, v17, v15 :: v_dual_fmac_f32 v16, 0x49742400, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v18, s28, v18, v13
	v_fmac_f32_e32 v13, s28, v14
	v_dual_mul_f32 v15, v6, v15 :: v_dual_mul_f32 v16, v5, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v7, v18
	v_fma_f32 v21, 0.5, v15, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v22, 0.5, v16, v11
	v_fma_f32 v23, 0.5, v18, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, s27, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v21
	v_dual_mul_f32 v25, s27, v22 :: v_dual_mul_f32 v24, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, v25, v23
	v_mul_f32_e32 v25, 0x3f8b851f, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v26, 0x3f821cac, v23 :: v_dual_cndmask_b32 v21, v25, v24
	v_cmp_lt_f32_e32 vcc_lo, 0, v22
	v_dual_fmac_f32 v21, -0.5, v19 :: v_dual_cndmask_b32 v22, v23, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v21, 0x49742400, v20 :: v_dual_sub_f32 v22, v17, v22
	v_dual_mul_f32 v21, v5, v21 :: v_dual_mul_f32 v14, v6, v22
	v_mul_f32_e32 v22, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v24, 0.5, v21, v11
	v_fma_f32 v23, 0.5, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v25, 0.5, v22, v9
	v_dual_fmac_f32 v15, 2.0, v14 :: v_dual_fmac_f32 v16, 2.0, v21
	v_dual_mul_f32 v27, s27, v24 :: v_dual_mul_f32 v26, s27, v23
	v_cmp_lt_f32_e32 vcc_lo, 0, v23
	v_fma_f32 v21, 2.0, v22, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v26, v25, v26
	v_mul_f32_e32 v25, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, 2.0, v22
	v_mul_f32_e32 v27, 0x3f8b851f, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, 0x3f821cac, v25
	v_fmac_f32_e32 v21, v7, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v27, v26, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v24
	v_fma_f32 v27, v7, v13, v9
	v_fmac_f32_e32 v9, 0x3e2aaaab, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v23, -0.5, v19 :: v_dual_cndmask_b32 v24, v25, v28
	v_fma_f32 v18, 0.5, v18, v9
	v_fma_f32 v22, 0.5, v22, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v23, 0x49742400, v20
	v_sub_f32_e32 v24, v17, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, v5, v23, v11
	v_fma_f32 v25, v6, v24, v10
	v_dual_mul_f32 v24, v6, v24 :: v_dual_mul_f32 v23, v5, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v29, s27, v26 :: v_dual_mul_f32 v28, s27, v25
	v_cmp_lt_f32_e32 vcc_lo, 0, v25
	v_dual_fmac_f32 v15, 2.0, v24 :: v_dual_fmac_f32 v16, 2.0, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v28, v27, v28
	v_mul_f32_e32 v27, v27, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, 0x3f8b851f, v28
	v_dual_mul_f32 v14, 0x3f821cac, v27 :: v_dual_cndmask_b32 v25, v29, v28
	v_cmp_lt_f32_e32 vcc_lo, 0, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v25, -0.5, v19 :: v_dual_cndmask_b32 v14, v27, v14
	v_dual_fmac_f32 v25, 0x49742400, v20 :: v_dual_sub_f32 v14, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v5, v25 :: v_dual_fmac_f32 v15, v6, v14
	v_dual_fmac_f32 v11, 0x3e2aaaab, v16 :: v_dual_fmac_f32 v10, 0x3e2aaaab, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, s27, v11 :: v_dual_mul_f32 v14, s27, v10
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_mul_f32_e32 v15, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v14, v9, v14 :: v_dual_mul_f32 v23, 0x3f821cac, v15
	v_mul_f32_e32 v16, 0x3f8b851f, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v16, v14, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v11
	v_fmac_f32_e32 v14, -0.5, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v15, v15, v23 :: v_dual_fmac_f32 v14, 0x49742400, v20
	v_sub_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, v5, v14 :: v_dual_mul_f32 v15, v6, v15
	v_fma_f32 v23, 0.5, v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, 0.5, v15, v10
	v_dual_mul_f32 v25, s27, v23 :: v_dual_mul_f32 v24, s27, v14
	v_cmp_lt_f32_e32 vcc_lo, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v18, v24
	v_dual_mul_f32 v18, v18, v25 :: v_dual_mul_f32 v25, 0x3f8b851f, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, 0x3f821cac, v18
	v_cndmask_b32_e32 v14, v25, v24, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v14, -0.5, v19
	v_cndmask_b32_e32 v18, v18, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, 0x49742400, v20
	v_sub_f32_e32 v18, v17, v18
	v_fma_f32 v13, v7, v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v5, v14
	v_mul_f32_e32 v18, v6, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, 0.5, v14, v11
	v_fma_f32 v23, 0.5, v18, v10
	v_fmac_f32_e32 v15, 2.0, v18
	v_fmac_f32_e32 v16, 2.0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v26, s27, v24 :: v_dual_mul_f32 v25, s27, v23
	v_cmp_lt_f32_e32 vcc_lo, 0, v23
	v_mul_f32_e32 v25, v22, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, v22, v26
	v_mul_f32_e32 v26, 0x3f8b851f, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, 0x3f821cac, v22
	v_cndmask_b32_e32 v23, v26, v25, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, -0.5, v19
	v_dual_cndmask_b32 v22, v22, v27 :: v_dual_fmac_f32 v23, 0x49742400, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v17, v22
	v_fma_f32 v25, v5, v23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, v6, v22, v10
	v_dual_mul_f32 v14, v5, v23 :: v_dual_mul_f32 v27, s27, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v26, s27, v24
	v_cmp_lt_f32_e32 vcc_lo, 0, v24
	v_fmac_f32_e32 v16, 2.0, v14
                                        ; implicit-def: $vgpr14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, v13, v26
	v_mul_f32_e32 v13, v13, v27
	v_mul_f32_e32 v27, 0x3f8b851f, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, 0x3f821cac, v13
	v_cndmask_b32_e32 v24, v27, v26, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v24, -0.5, v19
	v_cndmask_b32_e32 v18, v13, v18, vcc_lo
	v_mul_f32_e32 v19, v6, v22
	v_fmamk_f32 v13, v21, 0x3e2aaaab, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v24, 0x49742400, v20 :: v_dual_sub_f32 v17, v17, v18
	v_fmac_f32_e32 v15, 2.0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v13
	v_cmp_ngt_f32_e64 s1, 0x48000000, |v13|
	v_dual_fmac_f32 v16, v5, v24 :: v_dual_fmac_f32 v15, v6, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_bitset0_b32 s0, 31
	s_and_b32 vcc_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_fmamk_f32 v16, v16, 0x3e2aaaab, v11 :: v_dual_fmamk_f32 v15, v15, 0x3e2aaaab, v10
	s_waitcnt lgkmcnt(0)
	s_clause 0x5
	global_store_b32 v12, v11, s[8:9]
	global_store_b32 v12, v10, s[10:11]
	global_store_b32 v12, v9, s[12:13]
	global_store_b32 v12, v16, s[14:15]
	global_store_b32 v12, v15, s[16:17]
	global_store_b32 v12, v13, s[18:19]
	s_cbranch_vccz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 s2, s0, 0x7fffff
	s_lshr_b32 s3, s0, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s4, s2, 0xfe5163ab
	s_mul_i32 s30, s2, 0x3c439041
	s_mul_hi_u32 s33, s2, 0x3c439041
	s_add_u32 s4, s4, s30
	s_addc_u32 s30, 0, s33
	s_mul_i32 s33, s2, 0xdb629599
	s_mul_hi_u32 s34, s2, 0xdb629599
	s_add_u32 s30, s30, s33
	s_addc_u32 s33, 0, s34
	s_mul_i32 s34, s2, 0xf534ddc0
	s_mul_hi_u32 s35, s2, 0xf534ddc0
	s_add_u32 s33, s33, s34
	s_addc_u32 s34, 0, s35
	s_mul_i32 s35, s2, 0xfc2757d1
	s_mul_hi_u32 s36, s2, 0xfc2757d1
	s_add_u32 s34, s34, s35
	s_addc_u32 s35, 0, s36
	s_mul_i32 s36, s2, 0x4e441529
	s_mul_hi_u32 s38, s2, 0x4e441529
	s_add_u32 s35, s35, s36
	s_addc_u32 s36, 0, s38
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s38, s2, 0xfe5163ab
	s_mul_hi_u32 s39, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s40, s30, s34
	s_cselect_b32 s4, s4, s33
	s_cselect_b32 s30, s38, s30
	s_add_u32 s2, s36, s2
	s_addc_u32 s36, 0, s39
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s38, 0xffffffc0, 0
	s_cselect_b32 s33, s33, s35
	s_cselect_b32 s2, s34, s2
	s_cselect_b32 s34, s35, s36
	s_add_i32 s38, s38, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s38, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s35, s33, s2
	s_cselect_b32 s2, s2, s34
	s_cselect_b32 s33, s40, s33
	s_cselect_b32 s34, s4, s40
	s_cselect_b32 s4, s30, s4
	s_add_i32 s3, s3, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s30, 0xffffffe0, 0
	s_cselect_b32 s2, s35, s2
	s_cselect_b32 s35, s33, s35
	s_cselect_b32 s33, s34, s33
	s_cselect_b32 s4, s4, s34
	s_add_i32 s30, s30, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s30
	s_cmp_eq_u32 s30, 0
	v_mov_b32_e32 v14, s3
	s_cselect_b32 s30, -1, 0
	v_alignbit_b32 v15, s2, s35, v14
	v_alignbit_b32 v16, s35, s33, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v15
	v_cndmask_b32_e64 v15, v16, s35, s30
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v16, s2, v15, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s34, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v16, s34, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v17, v16
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v19, 23, v17
	v_alignbit_b32 v14, s33, s4, v14
	v_sub_nc_u32_e32 v18, 31, v17
	v_cndmask_b32_e64 v14, v14, s33, s30
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v15, v15, v14, 30
	v_alignbit_b32 v14, v14, s4, 30
	s_lshr_b32 s4, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s4, s4, 31
	v_xor_b32_e32 v15, s34, v15
	v_xor_b32_e32 v14, s34, v14
	s_or_b32 s30, s4, 0.5
	s_add_i32 s2, s3, s2
	v_sub_nc_u32_e32 v19, s30, v19
	v_alignbit_b32 v16, v16, v15, v18
	v_alignbit_b32 v14, v15, v14, v18
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v16, v14, 9
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v20, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v15, v14, v20
	v_or_b32_e32 v15, v16, v19
	v_add_nc_u32_e32 v17, v18, v17
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v17, 0x3fc90fda, v15 :: v_dual_lshlrev_b32 v16, 23, v17
	v_sub_nc_u32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, 0x3fc90fda, v15, -v17
	v_add_nc_u32_e32 v14, 0x33000000, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, 0x33a22168, v15
	v_or_b32_e32 v14, s4, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0x3fc90fda, v14
	v_add_f32_e32 v14, v17, v16
.LBB0_5:                                ; %Flow526
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v15, s2
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f32_e64 v14, 0x3f22f983, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v15, v14
	v_fma_f32 v14, 0xbfc90fda, v15, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0xb3a22168, v15
	v_fmac_f32_e32 v14, 0xa7c234c4, v15
	v_cvt_i32_f32_e32 v15, v15
.LBB0_7:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 s2, s0, 0x7fffff
	s_lshr_b32 s3, s0, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s4, s2, 0xfe5163ab
	s_mul_i32 s30, s2, 0x3c439041
	s_mul_hi_u32 s33, s2, 0x3c439041
	s_add_u32 s4, s4, s30
	s_addc_u32 s30, 0, s33
	s_mul_i32 s33, s2, 0xdb629599
	s_mul_hi_u32 s34, s2, 0xdb629599
	s_add_u32 s30, s30, s33
	s_addc_u32 s33, 0, s34
	s_mul_i32 s34, s2, 0xf534ddc0
	s_mul_hi_u32 s35, s2, 0xf534ddc0
	s_add_u32 s33, s33, s34
	s_addc_u32 s34, 0, s35
	s_mul_i32 s35, s2, 0xfc2757d1
	s_mul_hi_u32 s36, s2, 0xfc2757d1
	s_add_u32 s34, s34, s35
	s_addc_u32 s35, 0, s36
	s_mul_i32 s36, s2, 0x4e441529
	s_mul_hi_u32 s38, s2, 0x4e441529
	s_add_u32 s35, s35, s36
	s_addc_u32 s36, 0, s38
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s38, s2, 0xfe5163ab
	s_mul_hi_u32 s39, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s40, s30, s34
	s_cselect_b32 s4, s4, s33
	s_cselect_b32 s30, s38, s30
	s_add_u32 s2, s36, s2
	s_addc_u32 s36, 0, s39
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s38, 0xffffffc0, 0
	s_cselect_b32 s33, s33, s35
	s_cselect_b32 s2, s34, s2
	s_cselect_b32 s34, s35, s36
	s_add_i32 s38, s38, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s38, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s35, s33, s2
	s_cselect_b32 s2, s2, s34
	s_cselect_b32 s33, s40, s33
	s_cselect_b32 s34, s4, s40
	s_cselect_b32 s4, s30, s4
	s_add_i32 s3, s3, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s30, 0xffffffe0, 0
	s_cselect_b32 s2, s35, s2
	s_cselect_b32 s35, s33, s35
	s_cselect_b32 s33, s34, s33
	s_cselect_b32 s4, s4, s34
	s_add_i32 s30, s30, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s30
	s_cmp_eq_u32 s30, 0
	v_mov_b32_e32 v16, s3
	s_cselect_b32 s30, -1, 0
	v_alignbit_b32 v17, s2, s35, v16
	v_alignbit_b32 v18, s35, s33, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v17
	v_cndmask_b32_e64 v17, v18, s35, s30
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v18, s2, v17, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s34, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v18, s34, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v19, v18
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v21, 23, v19
	v_alignbit_b32 v16, s33, s4, v16
	v_sub_nc_u32_e32 v20, 31, v19
	v_cndmask_b32_e64 v16, v16, s33, s30
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v17, v17, v16, 30
	v_alignbit_b32 v16, v16, s4, 30
	s_lshr_b32 s4, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s4, s4, 31
	v_xor_b32_e32 v17, s34, v17
	v_xor_b32_e32 v16, s34, v16
	s_or_b32 s30, s4, 0.5
	s_add_i32 s3, s3, s2
	v_sub_nc_u32_e32 v21, s30, v21
	v_alignbit_b32 v18, v18, v17, v20
	v_alignbit_b32 v16, v17, v16, v20
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v18, v16, 9
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v22, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v17, v16, v22
	v_or_b32_e32 v17, v18, v21
	v_add_nc_u32_e32 v19, v20, v19
	v_lshrrev_b32_e32 v16, 9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, 0x3fc90fda, v17 :: v_dual_lshlrev_b32 v18, 23, v19
	v_sub_nc_u32_e32 v16, v16, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v17, -v19
	v_add_nc_u32_e32 v16, 0x33000000, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, 0x33a22168, v17
	v_or_b32_e32 v16, s4, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, 0x3fc90fda, v16
	v_add_f32_e32 v16, v19, v18
	s_branch .LBB0_10
.LBB0_9:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr16
.LBB0_10:                               ; %Flow525
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v17, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f32_e64 v16, 0x3f22f983, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v17, v16
	v_fma_f32 v16, 0xbfc90fda, v17, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, 0xb3a22168, v17
	v_fmac_f32_e32 v16, 0xa7c234c4, v17
	v_cvt_i32_f32_e32 v17, v17
.LBB0_12:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 s2, s0, 0x7fffff
	s_lshr_b32 s3, s0, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s4, s2, 0xfe5163ab
	s_mul_i32 s30, s2, 0x3c439041
	s_mul_hi_u32 s33, s2, 0x3c439041
	s_add_u32 s4, s4, s30
	s_addc_u32 s30, 0, s33
	s_mul_i32 s33, s2, 0xdb629599
	s_mul_hi_u32 s34, s2, 0xdb629599
	s_add_u32 s30, s30, s33
	s_addc_u32 s33, 0, s34
	s_mul_i32 s34, s2, 0xf534ddc0
	s_mul_hi_u32 s35, s2, 0xf534ddc0
	s_add_u32 s33, s33, s34
	s_addc_u32 s34, 0, s35
	s_mul_i32 s35, s2, 0xfc2757d1
	s_mul_hi_u32 s36, s2, 0xfc2757d1
	s_add_u32 s34, s34, s35
	s_addc_u32 s35, 0, s36
	s_mul_i32 s36, s2, 0x4e441529
	s_mul_hi_u32 s38, s2, 0x4e441529
	s_add_u32 s35, s35, s36
	s_addc_u32 s36, 0, s38
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s38, s2, 0xfe5163ab
	s_mul_hi_u32 s39, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s40, s30, s34
	s_cselect_b32 s4, s4, s33
	s_cselect_b32 s30, s38, s30
	s_add_u32 s2, s36, s2
	s_addc_u32 s36, 0, s39
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s38, 0xffffffc0, 0
	s_cselect_b32 s33, s33, s35
	s_cselect_b32 s2, s34, s2
	s_cselect_b32 s34, s35, s36
	s_add_i32 s38, s38, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s38, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s35, s33, s2
	s_cselect_b32 s2, s2, s34
	s_cselect_b32 s33, s40, s33
	s_cselect_b32 s34, s4, s40
	s_cselect_b32 s4, s30, s4
	s_add_i32 s3, s3, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s30, 0xffffffe0, 0
	s_cselect_b32 s2, s35, s2
	s_cselect_b32 s35, s33, s35
	s_cselect_b32 s33, s34, s33
	s_cselect_b32 s4, s4, s34
	s_add_i32 s30, s30, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s30
	s_cmp_eq_u32 s30, 0
	v_mov_b32_e32 v18, s3
	s_cselect_b32 s30, -1, 0
	v_alignbit_b32 v19, s2, s35, v18
	v_alignbit_b32 v20, s35, s33, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v19
	v_cndmask_b32_e64 v19, v20, s35, s30
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v20, s2, v19, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s34, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v20, s34, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v21, v20
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v23, 23, v21
	v_alignbit_b32 v18, s33, s4, v18
	v_sub_nc_u32_e32 v22, 31, v21
	v_cndmask_b32_e64 v18, v18, s33, s30
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v19, v19, v18, 30
	v_alignbit_b32 v18, v18, s4, 30
	s_lshr_b32 s4, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s4, s4, 31
	v_xor_b32_e32 v19, s34, v19
	v_xor_b32_e32 v18, s34, v18
	s_or_b32 s30, s4, 0.5
	s_add_i32 s3, s3, s2
	v_sub_nc_u32_e32 v23, s30, v23
	v_alignbit_b32 v20, v20, v19, v22
	v_alignbit_b32 v18, v19, v18, v22
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v19, v20, v18, 9
	v_lshrrev_b32_e32 v20, 9, v20
	v_clz_i32_u32_e32 v22, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v22, 32, v22
	v_sub_nc_u32_e32 v24, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v19, v18, v24
	v_or_b32_e32 v19, v20, v23
	v_add_nc_u32_e32 v21, v22, v21
	v_lshrrev_b32_e32 v18, 9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v21, 0x3fc90fda, v19 :: v_dual_lshlrev_b32 v20, 23, v21
	v_sub_nc_u32_e32 v18, v18, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, 0x3fc90fda, v19, -v21
	v_add_nc_u32_e32 v18, 0x33000000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, 0x33a22168, v19
	v_or_b32_e32 v18, s4, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0x3fc90fda, v18
	v_add_f32_e32 v18, v21, v20
	s_branch .LBB0_15
.LBB0_14:                               ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr18
.LBB0_15:                               ; %Flow524
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v19, s3
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f32_e64 v18, 0x3f22f983, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v19, v18
	v_fma_f32 v18, 0xbfc90fda, v19, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, 0xb3a22168, v19
	v_fmac_f32_e32 v18, 0xa7c234c4, v19
	v_cvt_i32_f32_e32 v19, v19
.LBB0_17:                               ; %_ZL3sinf.exit390
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_3 Depth=1
	s_and_b32 s1, s0, 0x7fffff
	s_lshr_b32 s2, s0, 23
	s_bitset1_b32 s1, 23
	s_addk_i32 s2, 0xff88
	s_mul_hi_u32 s3, s1, 0xfe5163ab
	s_mul_i32 s4, s1, 0x3c439041
	s_mul_hi_u32 s30, s1, 0x3c439041
	s_add_u32 s3, s3, s4
	s_addc_u32 s4, 0, s30
	s_mul_i32 s30, s1, 0xdb629599
	s_mul_hi_u32 s33, s1, 0xdb629599
	s_add_u32 s4, s4, s30
	s_addc_u32 s30, 0, s33
	s_mul_i32 s33, s1, 0xf534ddc0
	s_mul_hi_u32 s34, s1, 0xf534ddc0
	s_add_u32 s30, s30, s33
	s_addc_u32 s33, 0, s34
	s_mul_i32 s34, s1, 0xfc2757d1
	s_mul_hi_u32 s35, s1, 0xfc2757d1
	s_add_u32 s33, s33, s34
	s_addc_u32 s34, 0, s35
	s_mul_i32 s35, s1, 0x4e441529
	s_mul_hi_u32 s36, s1, 0x4e441529
	s_add_u32 s34, s34, s35
	s_addc_u32 s35, 0, s36
	s_cmp_gt_u32 s2, 63
	s_mul_i32 s36, s1, 0xfe5163ab
	s_mul_hi_u32 s38, s1, 0xa2f9836e
	s_mul_i32 s1, s1, 0xa2f9836e
	s_cselect_b32 s39, s4, s33
	s_cselect_b32 s3, s3, s30
	s_cselect_b32 s4, s36, s4
	s_add_u32 s1, s35, s1
	s_addc_u32 s35, 0, s38
	s_cmp_gt_u32 s2, 63
	s_cselect_b32 s36, 0xffffffc0, 0
	s_cselect_b32 s30, s30, s34
	s_cselect_b32 s1, s33, s1
	s_cselect_b32 s33, s34, s35
	s_add_i32 s36, s36, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s36, 31
	s_cselect_b32 s2, 0xffffffe0, 0
	s_cselect_b32 s34, s30, s1
	s_cselect_b32 s1, s1, s33
	s_cselect_b32 s30, s39, s30
	s_cselect_b32 s33, s3, s39
	s_cselect_b32 s3, s4, s3
	s_add_i32 s2, s2, s36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s2, 31
	s_cselect_b32 s4, 0xffffffe0, 0
	s_cselect_b32 s1, s34, s1
	s_cselect_b32 s34, s30, s34
	s_cselect_b32 s30, s33, s30
	s_cselect_b32 s3, s3, s33
	s_add_i32 s4, s4, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s2, 32, s4
	s_cmp_eq_u32 s4, 0
	v_mov_b32_e32 v20, s2
	s_cselect_b32 s4, -1, 0
	v_alignbit_b32 v21, s1, s34, v20
	v_alignbit_b32 v22, s34, s30, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v21
	v_cndmask_b32_e64 v21, v22, s34, s4
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v22, s1, v21, 30
	s_bfe_u32 s2, s1, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s33, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v22, s33, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v23, v22
	v_min_u32_e32 v23, 32, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v25, 23, v23
	v_alignbit_b32 v20, s30, s3, v20
	v_sub_nc_u32_e32 v24, 31, v23
	v_cndmask_b32_e64 v20, v20, s30, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v21, v21, v20, 30
	v_alignbit_b32 v20, v20, s3, 30
	s_lshr_b32 s3, s1, 29
	s_lshr_b32 s1, s1, 30
	s_lshl_b32 s3, s3, 31
	v_xor_b32_e32 v21, s33, v21
	v_xor_b32_e32 v20, s33, v20
	s_or_b32 s4, s3, 0.5
	s_add_i32 s2, s2, s1
	v_sub_nc_u32_e32 v25, s4, v25
	v_alignbit_b32 v22, v22, v21, v24
	v_alignbit_b32 v20, v21, v20, v24
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v21, v22, v20, 9
	v_lshrrev_b32_e32 v22, 9, v22
	v_clz_i32_u32_e32 v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v24, 32, v24
	v_sub_nc_u32_e32 v26, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v21, v20, v26
	v_or_b32_e32 v21, v22, v25
	v_add_nc_u32_e32 v23, v24, v23
	v_lshrrev_b32_e32 v20, 9, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v23, 0x3fc90fda, v21 :: v_dual_lshlrev_b32 v22, 23, v23
	v_sub_nc_u32_e32 v20, v20, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3fc90fda, v21, -v23
	v_add_nc_u32_e32 v20, 0x33000000, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x33a22168, v21
	v_or_b32_e32 v20, s3, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, 0x3fc90fda, v20
	v_add_f32_e32 v20, v23, v22
	s_branch .LBB0_20
.LBB0_19:                               ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr20
.LBB0_20:                               ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_mov_b32_e32 v21, s2
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f32_e64 v20, 0x3f22f983, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v21, v20
	v_fma_f32 v20, 0xbfc90fda, v21, |v13|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, 0xb3a22168, v21
	v_fmac_f32_e32 v20, 0xa7c234c4, v21
	v_cvt_i32_f32_e32 v21, v21
.LBB0_22:                               ; %_ZL3cosf.exit396
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b32 v22, v12, s[16:17]
	global_load_b32 v23, v12, s[14:15]
	v_dual_mul_f32 v24, v18, v18 :: v_dual_and_b32 v25, 1, v19
	v_dual_mul_f32 v26, v16, v16 :: v_dual_lshlrev_b32 v19, 30, v19
	v_dual_mul_f32 v28, v14, v14 :: v_dual_and_b32 v27, 1, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v30, s26, v24, 0x3c0881c4 :: v_dual_lshlrev_b32 v17, 30, v17
	v_dual_fmaak_f32 v32, s26, v26, 0x3c0881c4 :: v_dual_and_b32 v29, 1, v15
	v_cmp_eq_u32_e32 vcc_lo, 0, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v34, s26, v28, 0x3c0881c4 :: v_dual_lshlrev_b32 v15, 30, v15
	v_fmaak_f32 v30, v24, v30, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v32, v26, v32, 0xbe2aaa9d
	v_fmaak_f32 v31, s29, v24, 0xbab64f3b
	v_and_b32_e32 v19, 0x80000000, v19
	v_fmaak_f32 v34, v28, v34, 0xbe2aaa9d
	v_mul_f32_e32 v30, v24, v30
	v_dual_mul_f32 v32, v26, v32 :: v_dual_fmaak_f32 v33, s29, v26, 0xbab64f3b
	v_fmaak_f32 v35, s29, v28, 0xbab64f3b
	v_xor_b32_e32 v19, s0, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v18, v18, v30
	v_dual_fmac_f32 v16, v16, v32 :: v_dual_fmaak_f32 v33, v26, v33, 0x3d2aabf7
	v_and_b32_e32 v15, 0x80000000, v15
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_add_u32 s10, s10, 4
	v_fmaak_f32 v33, v26, v33, 0xbf000004
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v26, v26, v33, 1.0
	v_fmaak_f32 v31, v24, v31, 0x3d2aabf7
	v_fmaak_f32 v31, v24, v31, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v24, v31, 1.0
	v_cndmask_b32_e32 v18, v24, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v18, v19, v18
	v_dual_cndmask_b32 v16, v26, v16 :: v_dual_and_b32 v19, 1, v21
	v_lshlrev_b32_e32 v21, 30, v21
	v_dual_mul_f32 v34, v28, v34 :: v_dual_and_b32 v17, 0x80000000, v17
	v_fmaak_f32 v35, v28, v35, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v17, s0, v17
	v_fmac_f32_e32 v14, v14, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v30, v28, v35, 0xbf000004
	v_cmp_eq_u32_e64 s0, 0, v19
	v_xor_b32_e32 v16, v17, v16
	v_xor_b32_e32 v17, v18, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v24, v28, v30, 1.0
	v_xor_b32_e32 v16, v16, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, -v14, v24, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x1f8
	v_xor_b32_e32 v13, v15, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, 0x7fc00000, v16, vcc_lo
	v_dual_mul_f32 v16, v20, v20 :: v_dual_cndmask_b32 v13, 0x7fc00000, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v15, v22
	s_waitcnt vmcnt(0)
	v_fma_f32 v13, v13, v23, -v15
	global_store_b32 v12, v13, s[20:21]
	s_clause 0x1
	global_load_b32 v13, v12, s[16:17]
	global_load_b32 v15, v12, s[14:15]
	v_cndmask_b32_e32 v14, 0x7fc00000, v17, vcc_lo
	v_fmaak_f32 v17, s26, v16, 0x3c0881c4
	s_add_u32 s14, s14, 4
	s_addc_u32 s15, s15, 0
	s_add_u32 s16, s16, 4
	s_addc_u32 s17, s17, 0
	v_fmaak_f32 v17, v16, v17, 0xbe2aaa9d
	v_fmaak_f32 v18, s29, v16, 0xbab64f3b
	s_add_u32 s18, s18, 4
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 4
	v_mul_f32_e32 v17, v16, v17
	v_fmaak_f32 v18, v16, v18, 0x3d2aabf7
	s_addc_u32 s21, s21, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v20, v17
	v_fmaak_f32 v18, v16, v18, 0xbf000004
	v_and_b32_e32 v17, 0x80000000, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, v16, v18, 1.0
	v_cndmask_b32_e64 v16, -v20, v16, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v16, v17, v16
	v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v13, v16
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v13, v14, v15
	global_store_b32 v12, v13, s[22:23]
	s_add_u32 s22, s22, 4
	s_addc_u32 s23, s23, 0
	s_add_i32 s37, s37, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s37, 0
	s_cbranch_scc1 .LBB0_3
.LBB0_23:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel modelCalc
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 60
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	modelCalc, .Lfunc_end0-modelCalc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 16464
; NumSgprs: 43
; NumVgprs: 60
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 60
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           modelCalc
    .private_segment_fixed_size: 0
    .sgpr_count:     43
    .sgpr_spill_count: 0
    .symbol:         modelCalc.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     60
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
