/************************************************************
*	ECE408 Parallel Programming - Final Project				*
*															*
*	Topic: Terrain Generation								*
*	Members: Lai,Haoming; Ma,Yunhan; Wang,Bangqi			*
*															*
************************************************************/

/* 
* Terrain Generation:
* Algorithmn: Diamond Square Algorithmn.
* Version:
*			0. Serial version: 1 * square loop + 4 * diamond loop;
*			1. Parallel version: 1 * sdsfsdfsdf + 4 * diamond kernel; 
*			2. Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex);
*			3. Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			4. One Kernel Version: 1 * square_diamond kernel combined; (based on version 2)
*			5. Kernel Device Version: 1 * kernel + 1 * square device + 1 * diamond device;
*			6. Less Threads Version: 1 * kernel + 1 * square device + 1 * diamond device (only active threads we need);
*			7. Shared Memory Version: 1 * kernel + 1 * square device + 1 * diamond device (use share memory);
*
*			8. 2D Smarter Kernel Versio: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*/

#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <stdio.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <time.h>
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include <math.h>

/* Set the parameter */
/* Choose the version to use */
//#define VERSION 0
/* Set the length of each edge. please put power of 2 */
#define SIZE 512
/* Set number of array */
#define N (SIZE+1)*(SIZE+1)
/* Set the roughness for terrain */
#define ROUGHNESS 10
/* Set the height for each corner */
#define CORNER 0

/* main function for different version */
int version_0 (void);
int version_1 (void);
int version_2 (void);
int version_3 (bool print, int block_size);
int version_4 (bool print);
int version_5 (void);
int version_6 (void);
int version_7 (void);
int version_8 (bool print, int block_size);
int version_9 (bool print, int block_size);

/* main function */
int main (void){
	int VERSION;
	int p;
	int block_size; 

	bool print= false;
	printf("what version do you want: ");
	scanf("%d", &VERSION);
	printf("print? (0/1): ");
	scanf("%d", &p);
	printf("please define block_size(max = 32): ");
	scanf("%d", &block_size);
	if(p)
		print = true; 

	switch(VERSION){
		/* test version 0 */
		case 0:
			version_0();
			break;
		case 1:
		/* test version 1 */
			version_1();
			break;
		case 2:
		/* test version 2 */
			version_2();
			break;
		case 3:
		/* test version 3 */
			version_3(print, block_size);
			break;
		case 4:
		/* test version 4 */
			version_4(print);
			break;
		case 5:
		/* test version 5 */
			version_5();
			break;
		case 6:
		/* test version 5 */
			version_6();
			break;
		case 7:
		/* test version 5 */
			version_7();
			break;
		case 8:
		/* test version 5 */
			version_8(print, block_size);
			break;
		case 9:
		/* test version 5 */
			version_9(print, block_size);
			break;
		default:
		/* test version 0 */
			version_0();
			return 0;
	}
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 0.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 0.0: 
*			0.0 Serial version: 1 * square loop + 4 * loop;  
*			
*/

/* host code for serial version */
int version_0 (void) {
	clock_t start, end;
	double runTime;
	float heightMap[SIZE+1][SIZE+1];
	for(int i=0; i<SIZE; i++){
		for(int j=0; j<SIZE; j++){
			heightMap[i][j] = 0.0;
		}
	}

	//initial the first four points
	heightMap[0][0] = 0; 
	heightMap[SIZE][0] = 0; 
	heightMap[0][SIZE] = 0; 
	heightMap[SIZE][SIZE] = 0;  

	start = clock();
	int stride = SIZE;
	while(stride>=2){
		for(int i = 0; i<(SIZE/stride); i++){
			for(int j = 0; j<(SIZE/stride); j++){
				int leftbottom_x = i* stride;
				int leftbottom_y = j* stride;
				float average =  heightMap[leftbottom_x][leftbottom_y] + heightMap[leftbottom_x + stride][leftbottom_y] + heightMap[leftbottom_x][leftbottom_y+stride] + heightMap[leftbottom_x + stride][leftbottom_y +stride];
				average = average /4 ;
				heightMap[leftbottom_x + stride/2][leftbottom_y + stride/2]= average + rand() %10 - 5; 


				heightMap[leftbottom_x + stride/2 ][leftbottom_y] = (average + heightMap[leftbottom_x][leftbottom_y]  + heightMap[leftbottom_x + stride][leftbottom_y] ) /3 + rand() %10 -5; 
				heightMap[leftbottom_x][leftbottom_y + stride/2] = (average + heightMap[leftbottom_x][leftbottom_y]  + heightMap[leftbottom_x][leftbottom_y + stride] ) /3 + rand() %10 -5 ; 
				heightMap[leftbottom_x + stride][leftbottom_y+ stride/2] = (average + heightMap[leftbottom_x + stride ][leftbottom_y]  + heightMap[leftbottom_x + stride][leftbottom_y + stride] ) /3 +rand() %10-5; 
				heightMap[leftbottom_x+ stride/2][leftbottom_y+ stride] = (average + heightMap[leftbottom_x][leftbottom_y + stride]  + heightMap[leftbottom_x + stride][leftbottom_y + stride] ) /3 +rand() %10-5; 
			}


		}
		printf("%d \n", stride);
		stride = stride/2;
	}

 	for (int i=0; i<=SIZE; i++){
 		for(int j=0; j<=SIZE; j++){
	 		printf("%d: x = %d, y = %d; hm = %f\n", i*j, i, j, heightMap[i][j]);
		}
	}

	end = clock();
 	runTime = (double)(end - start)/CLOCKS_PER_SEC;

	printf("Run time for Version_0: %f\n", runTime);
	printf("Version 0\n");
	return 0;
}



///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 1.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 1.0: 
*			1.0 Parallel version: 1 * square kernel + 4 * diamond kernel;  
*			This parallel function parallelize the serial code directly. it change the one square loop to
*			one square kernel and change four diamond loop to four different diamond kernel.	1
*/

/* square kernel to calculate the middle point */
__global__ void Square_1(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();
  	}
}

/* diamond kernel 1_1 to calcualte middle bottom point */
__global__ void Diamond_1_1(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, mi, j;
		int pmi_b, pmj_b;
		float hm_b;
		int num_b;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		mi = i + half;

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand1 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
  }

/* diamond kernel 1_2 to calcualte left point */
__global__ void Diamond_1_2(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, mj;
		int pmi_l, pmj_l;
		float hm_l;
		int num_l;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		mj = j + half;

		/* find 4 diamond vertex */
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;

		/* set the value */
		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand2 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;

		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* diamond kernel 1_3 to calcualte right point */
__global__ void Diamond_1_3(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, mj;
		int pmi_r, pmj_r;
		float hm_r;
		int num_r;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		mj = j + half;

		/* find 4 diamond vertex */
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;

		/* set the value */
		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand3 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* diamond kernel 1_4 to calcualte middle top point */
__global__ void Diamond_1_4(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, mi, nj;
		int pmi_t, pmj_t;
		float hm_t;
		int num_t;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		nj = j + rect;
		mi = i + half;

		/* find 4 diamond vertex */
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand4 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* host code for version 1.0 */
int version_1 (void) {
	printf("Version 1: square kernel + 4 diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_1_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_1_2<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_1_3<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_1_4<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_1: %f\n", runTime);
	return EXIT_SUCCESS;
}




///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 2.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 2.0:
*			2.0 Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex); 
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/

/* combined diamond kernel to calculate the four point in each thread */
__global__ void Diamond_2(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int pmi_b, pmj_b, pmi_l, pmj_l, pmi_r, pmj_r, pmi_t, pmj_t;
		float hm_b, hm_l, hm_r, hm_t;
		int num_b, num_l, num_r, num_t;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		check1[idx] = hm_l;
		check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand1 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand2 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand3 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand4 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}


/* the host code for version 2: 1 square kernel + 1 stupid diamond kernel */
int version_2 (void) {
	printf("Version 2: square kernel + stupid diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_2<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_2: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}




///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 3.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 3.0:
*			3.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex.
*/

/* smart diamond kernel calculate the diamond vertex and each thread only calculate one vertex */
__global__ void Diamond_3(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p + rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 3: 1 square kernel + 1 smart diamond kernel */
int version_3 (bool print, int block_size) {
	printf("Version 3: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	int size = block_size * block_size;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/size),size>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_3<<<ceil((float)N/size),size>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
	// for (int i=0; i<N; i++){
	//   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
	// }

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_3: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 4.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 4.0:
*			4.0 Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex); 
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/
/* combined diamond kernel to calculate the four point in each thread */
__global__ void Square_Diamond_4(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
  		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int pmi_b, pmj_b, pmi_l, pmj_l, pmi_r, pmj_r, pmi_t, pmj_t;
		float hm_b, hm_l, hm_r, hm_t;
		int num_b, num_l, num_r, num_t;
		int squareInRow = SIZE/rect;

  		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		check1[idx] = hm_l;
		check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
	    float rand1 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand2 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand3 = v1 + (v2 - v1) * curand_uniform(&localState);
	    float rand4 = v1 + (v2 - v1) * curand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}


/* the host code for version 2: 1 square kernel + 1 stupid diamond kernel */
int version_4 (bool print) {
	printf("Version 2: square kernel + stupid diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_Diamond_4<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_4: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}

int version_5 (void) {
	printf("5\n");
	return 0;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 6.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 6.0:
*			6. Less Threads Version: 1 * kernel + 1 * square device + 1 * diamond device (only active threads we need);
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/

/* square kernel to calculate the middle point */
__global__ void Square_6(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int squareInRow = SIZE/rect;
  	if (idx < squareInRow * squareInRow){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();
  	}
}

/* smart diamond kernel calculate the diamond vertex and each thread only calculate one vertex */
__global__ void Diamond_6(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int squareInRow = SIZE/rect;
  	if (idx < 4 * squareInRow * squareInRow){
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p + rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 3: 1 square kernel + 1 smart diamond kernel */
int version_6 (void) {
	printf("Version 6: square kernel + smart diamond kernel (active less threads) \n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_6<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_6<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}
	// printf("\n");	
	// for (int i=0; i<N; i++){
	//   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
	// }

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_6: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


int version_7 (void) {
	printf("7\n");
	return 0;
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 8.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 8.0:
*			8.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex. (A simple revised 2D version of version 3)
*/
__global__ void Square_8(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 +rand;
		__syncthreads();
  	}
}

__global__ void Diamond_8(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p +rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 8: 2D + 1 square kernel + 1 smart diamond kernel. */
int version_8 (bool print, int block_size) {
	printf("Version 8: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = 1;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = 2;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = 3;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = 4;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
	dim3 DimGrid(ceil(((float)SIZE)/block_size),ceil(((float)SIZE)/block_size), 1); 
	dim3 DimBlock(block_size,block_size,1);
 	for (int i=SIZE; i>1; i=i/2){
		Square_8<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_8<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
//	for (int i=0; i<SIZE+1; i++){
//	   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
//	}

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_8: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 9.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 9.0:
*			9.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex. (A simple revised 2D version of version 3)
*/
__global__ void Square_9(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 +rand;
		__syncthreads();
  	}
}

__global__ void Diamond_9(curandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		curandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * curand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p +rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 8: 2D + 1 square kernel + 1 smart diamond kernel. */
int version_9 (bool print, int block_size) {
	printf("Version 8: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = 1;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = 2;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = 3;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = 4;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	curandState* rng;
	/* allocate memory for device */
	cudaMalloc(&rng, N * sizeof(curandState));
	cudaMalloc((void**)&dev_heightMap, N * sizeof(float));
	cudaMalloc((void**)&dev_check1, N * sizeof(float));
	cudaMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	cudaMemcpy(dev_heightMap, heightMap, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check1, check1, N * sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(dev_check2, check2, N * sizeof(float), cudaMemcpyHostToDevice);

	start = clock();
	/* run kernel */
	dim3 DimGrid(ceil(((float)SIZE)/block_size),ceil(((float)SIZE)/block_size), 1); 
	dim3 DimBlock(block_size,block_size,1);
 	for (int i=SIZE; i>1; i=i/2){
		Square_9<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
		Diamond_9<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		cudaDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	cudaMemcpy(heightMap, dev_heightMap, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check1, dev_check1, N * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy(check2, dev_check2, N * sizeof(float), cudaMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
//	for (int i=0; i<SIZE+1; i++){
//	   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
//	}

	// printf("%f\n", cpu_time_used);
	cudaFree(dev_heightMap);
	cudaFree(dev_check1);
	cudaFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_8: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}

	.file	"tmpxft_00292e29_00000000-6_tg.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3993:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3993:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB4682:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE4682:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"%d \n"
.LC5:
	.string	"%d: x = %d, y = %d; hm = %f\n"
.LC7:
	.string	"Run time for Version_0: %f\n"
.LC8:
	.string	"Version 0\n"
	.text
	.globl	_Z9version_0v
	.type	_Z9version_0v, @function
_Z9version_0v:
.LFB3981:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-1052672(%rsp), %r11
	.cfi_def_cfa 11, 1052728
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 1052832
	movq	%fs:40, %rax
	movq	%rax, 1052760(%rsp)
	xorl	%eax, %eax
	leaq	84(%rsp), %r12
	leaq	1050708(%rsp), %rsi
	movq	%r12, %rdx
.L4:
	movq	%rdx, %rdi
	movl	$512, %ecx
	addq	$2052, %rdx
	rep stosl
	cmpq	%rsi, %rdx
	jne	.L4
	movl	$0x00000000, 84(%rsp)
	movl	$0x00000000, 1050708(%rsp)
	movl	$0x00000000, 2132(%rsp)
	movl	$0x00000000, 1052756(%rsp)
	call	clock@PLT
	movl	$9, 28(%rsp)
	movq	%rax, 32(%rsp)
	movl	$512, 12(%rsp)
.L5:
	movl	$512, %eax
	movslq	12(%rsp), %r15
	movq	%r12, %rbx
	xorl	%edi, %edi
	cltd
	idivl	12(%rsp)
	movl	%r15d, 16(%rsp)
	sarl	12(%rsp)
	movslq	12(%rsp), %r14
	imulq	$2052, %r15, %r11
	leaq	0(,%r15,4), %r8
	movl	%eax, 20(%rsp)
	imulq	$2052, %r14, %rax
	movq	%rax, 40(%rsp)
.L9:
	cmpl	%edi, 20(%rsp)
	je	.L19
	movq	40(%rsp), %rax
	leaq	(%rbx,%r11), %r10
	xorl	%r9d, %r9d
	movq	%r10, %rbp
	leaq	(%rbx,%rax), %r13
.L6:
	movss	(%rbx), %xmm0
	addss	0(%rbp), %xmm0
	movq	%r10, 72(%rsp)
	addss	(%rbx,%r15,4), %xmm0
	addss	0(%rbp,%r15,4), %xmm0
	movq	%r11, 64(%rsp)
	mulss	.LC1(%rip), %xmm0
	movq	%r8, 56(%rsp)
	movl	%r9d, 52(%rsp)
	movl	%edi, 48(%rsp)
	movss	%xmm0, 8(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	addss	8(%rsp), %xmm0
	subss	.LC2(%rip), %xmm0
	movss	%xmm0, 0(%r13,%r14,4)
	movss	8(%rsp), %xmm0
	addss	(%rbx), %xmm0
	addss	0(%rbp), %xmm0
	divss	.LC3(%rip), %xmm0
	movss	%xmm0, 24(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	addss	24(%rsp), %xmm0
	subss	.LC2(%rip), %xmm0
	movss	%xmm0, 0(%r13)
	movss	8(%rsp), %xmm0
	addss	(%rbx), %xmm0
	addss	(%rbx,%r15,4), %xmm0
	divss	.LC3(%rip), %xmm0
	movss	%xmm0, 24(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	addss	24(%rsp), %xmm0
	subss	.LC2(%rip), %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	movss	8(%rsp), %xmm0
	addss	0(%rbp), %xmm0
	addss	0(%rbp,%r15,4), %xmm0
	divss	.LC3(%rip), %xmm0
	movss	%xmm0, 24(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	addss	24(%rsp), %xmm0
	subss	.LC2(%rip), %xmm0
	movss	%xmm0, 0(%rbp,%r14,4)
	movss	8(%rsp), %xmm0
	addss	(%rbx,%r15,4), %xmm0
	addss	0(%rbp,%r15,4), %xmm0
	divss	.LC3(%rip), %xmm0
	movss	%xmm0, 8(%rsp)
	call	rand@PLT
	movl	$10, %ecx
	movq	56(%rsp), %r8
	movl	52(%rsp), %r9d
	cltd
	movl	48(%rsp), %edi
	movq	64(%rsp), %r11
	idivl	%ecx
	movq	72(%rsp), %r10
	incl	%r9d
	addq	%r8, %rbx
	addq	%r8, %rbp
	cvtsi2ssl	%edx, %xmm0
	addss	8(%rsp), %xmm0
	subss	.LC2(%rip), %xmm0
	movss	%xmm0, 0(%r13,%r15,4)
	addq	%r8, %r13
	cmpl	%r9d, 20(%rsp)
	jne	.L6
	incl	%edi
	movq	%r10, %rbx
	jmp	.L9
.L19:
	movl	16(%rsp), %edx
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC4(%rip), %rsi
	call	__printf_chk@PLT
	decl	28(%rsp)
	jne	.L5
	xorl	%ebp, %ebp
	leaq	.LC5(%rip), %r14
.L8:
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
.L10:
	movl	%ebx, %r8d
	movl	%r13d, %edx
	cvtss2sd	(%r12,%rbx,4), %xmm0
	movl	%ebp, %ecx
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	incq	%rbx
	call	__printf_chk@PLT
	addl	%ebp, %r13d
	cmpq	$513, %rbx
	jne	.L10
	incl	%ebp
	addq	$2052, %r12
	cmpl	$513, %ebp
	jne	.L8
	call	clock@PLT
	movq	32(%rsp), %rsi
	movl	$2, %edi
	subq	%rsi, %rax
	leaq	.LC7(%rip), %rsi
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC8(%rip), %rsi
	call	__printf_chk@PLT
	movq	1052760(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$1052776, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3981:
	.size	_Z9version_0v, .-_Z9version_0v
	.section	.rodata.str1.1
.LC9:
	.string	"5\n"
	.text
	.globl	_Z9version_5v
	.type	_Z9version_5v, @function
_Z9version_5v:
.LFB3986:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3986:
	.size	_Z9version_5v, .-_Z9version_5v
	.section	.rodata.str1.1
.LC10:
	.string	"7\n"
	.text
	.globl	_Z9version_7v
	.type	_Z9version_7v, @function
_Z9version_7v:
.LFB3988:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3988:
	.size	_Z9version_7v, .-_Z9version_7v
	.globl	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4015:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8Square_1P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L24:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4015:
	.size	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z8Square_1P17curandStateXORWOWPfiS1_S1_
	.type	_Z8Square_1P17curandStateXORWOWPfiS1_S1_, @function
_Z8Square_1P17curandStateXORWOWPfiS1_S1_:
.LFB4016:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4016:
	.size	_Z8Square_1P17curandStateXORWOWPfiS1_S1_, .-_Z8Square_1P17curandStateXORWOWPfiS1_S1_
	.globl	_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4017:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4017:
	.size	_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_
	.type	_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_, @function
_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_:
.LFB4018:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4018:
	.size	_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_, .-_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_
	.globl	_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4019:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L34:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4019:
	.size	_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_
	.type	_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_, @function
_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_:
.LFB4020:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4020:
	.size	_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_, .-_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_
	.globl	_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4021:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L39:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4021:
	.size	_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_
	.type	_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_, @function
_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_:
.LFB4022:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4022:
	.size	_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_, .-_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_
	.globl	_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4023:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L44:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4023:
	.size	_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_
	.type	_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_, @function
_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_:
.LFB4024:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4024:
	.size	_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_, .-_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC11:
	.string	"Version 1: square kernel + 4 diamond kernel\n"
.LC12:
	.string	"heightMap_corner0: %f\n"
.LC14:
	.string	"heightMap_corner1: %f\n"
.LC15:
	.string	"heightMap_corner3: %f\n"
.LC16:
	.string	"heightMap_corner2: %f\n"
.LC17:
	.string	"Run time for Version_1: %f\n"
	.text
	.globl	_Z9version_1v
	.type	_Z9version_1v, @function
_Z9version_1v:
.LFB3982:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL1:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL1
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	movl	$16777217, %ebx
	movl	$9, %r15d
	movl	$512, %r12d
	salq	$8, %rbx
	movabsq	$4294968325, %rbp
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	leaq	2105428(%rsp), %r13
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%r13, %rdi
	rep stosl
	xorps	%xmm0, %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC14(%rip), %rsi
	movl	$0x00000000, 2107476(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC15(%rip), %rsi
	movl	$0x00000000, 3156052(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movl	$0x00000000, 3158100(%rsp)
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	leaq	76(%rsp), %rax
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	movq	%rax, %r14
.L55:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rbp, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r12d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L50:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rbp, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r12d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z58__device_stub__Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L51:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rbp, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r12d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z58__device_stub__Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L52:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rbp, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L53
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r12d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z58__device_stub__Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L53:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rbp, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r12d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z58__device_stub__Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L54:
	call	cudaDeviceSynchronize@PLT
	sarl	%r12d
	decl	%r15d
	jne	.L55
	call	clock@PLT
	movq	16(%rsp), %rsi
	movq	%r13, %rdi
	xorl	%ebp, %ebp
	movl	$2, %ecx
	movl	$1052676, %edx
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	leaq	.LC5(%rip), %r12
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
.L56:
	movl	%ebp, %eax
	movl	$513, %edi
	cvtss2sd	0(%r13,%rbp,4), %xmm0
	movq	%r12, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%ebp, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%rbp
	cmpq	$263169, %rbp
	jne	.L56
	movq	16(%rsp), %rdi
	subq	%r14, %rbx
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbx, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L57
	call	__stack_chk_fail@PLT
.L57:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3982:
	.size	_Z9version_1v, .-_Z9version_1v
	.globl	_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4025:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L61:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4025:
	.size	_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_
	.type	_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_, @function
_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_:
.LFB4026:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4026:
	.size	_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_, .-_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC18:
	.string	"Version 2: square kernel + stupid diamond kernel\n"
.LC19:
	.string	"Run time for Version_2: %0.20f\n"
	.text
	.globl	_Z9version_2v
	.type	_Z9version_2v, @function
_Z9version_2v:
.LFB3983:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL2:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL2
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	movl	$512, %ebp
	movabsq	$4294967552, %r12
	movl	$9, %r15d
	movabsq	$4294968325, %r13
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	leaq	2105428(%rsp), %rbx
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%rbx, %rdi
	rep stosl
	xorps	%xmm0, %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC14(%rip), %rsi
	movl	$0x00000000, 2107476(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC15(%rip), %rsi
	movl	$0x00000000, 3156052(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movl	$0x00000000, 3158100(%rsp)
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	leaq	76(%rsp), %rax
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	movq	%rax, %r14
.L69:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%r13, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L67
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L67:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%r13, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L68
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z55__device_stub__Z9Diamond_2P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L68:
	call	cudaDeviceSynchronize@PLT
	sarl	%ebp
	decl	%r15d
	jne	.L69
	call	clock@PLT
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movl	$2, %ecx
	movl	$1052676, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	leaq	.LC5(%rip), %r13
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
.L70:
	movl	%r12d, %eax
	movl	$513, %edi
	cvtss2sd	(%rbx,%r12,4), %xmm0
	movq	%r13, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%r12d, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r12
	cmpq	$263169, %r12
	jne	.L70
	movq	16(%rsp), %rdi
	subq	%r14, %rbp
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbp, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3983:
	.size	_Z9version_2v, .-_Z9version_2v
	.globl	_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4027:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L75
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L75:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L77
	call	__stack_chk_fail@PLT
.L77:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4027:
	.size	_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_
	.type	_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_, @function
_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_:
.LFB4028:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4028:
	.size	_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_, .-_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC20:
	.string	"Version 3: square kernel + smart diamond kernel\n"
.LC22:
	.string	"Run time for Version_3: %0.20f\n"
	.text
	.globl	_Z9version_3bi
	.type	_Z9version_3bi, @function
_Z9version_3bi:
.LFB3984:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL3:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL3
	.cfi_def_cfa_register 7
	subq	$120, %rsp
	.cfi_def_cfa_offset 3158192
	movl	$9, %r14d
	movl	$512, %ebp
	movabsq	$4294967297, %r12
	movq	%fs:40, %rax
	movq	%rax, 3158120(%rsp)
	xorl	%eax, %eax
	movl	%esi, %ebx
	movl	%edi, %r13d
	leaq	.LC20(%rip), %rsi
	movl	$2, %edi
	imull	%ebx, %ebx
	call	__printf_chk@PLT
	leaq	2105444(%rsp), %rax
	xorps	%xmm0, %xmm0
	movl	$263169, %ecx
	movq	%rax, (%rsp)
	movq	(%rsp), %rdi
	xorl	%eax, %eax
	leaq	.LC12(%rip), %rsi
	rep stosl
	movl	$2, %edi
	movb	$1, %al
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC14(%rip), %rsi
	movl	$0x00000000, 2107492(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC15(%rip), %rsi
	movl	$0x00000000, 3156068(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movl	$0x00000000, 3158116(%rsp)
	call	__printf_chk@PLT
	leaq	56(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	leaq	92(%rsp), %rax
	movq	40(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052768(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	cvtsi2ssl	%ebx, %xmm1
	movss	.LC21(%rip), %xmm0
	movq	%rax, 24(%rsp)
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	cvttss2siq	%xmm0, %r15
.L83:
	movq	%r12, 84(%rsp)
	movl	88(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, 72(%rsp)
	movl	76(%rsp), %esi
	movl	%ebx, 80(%rsp)
	movq	80(%rsp), %rdx
	movl	%r15d, 68(%rsp)
	movq	68(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movl	%ebp, %edx
	movq	32(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_1P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L81:
	call	cudaDeviceSynchronize@PLT
	movq	%r12, 84(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, 72(%rsp)
	movl	88(%rsp), %ecx
	movl	%ebx, 80(%rsp)
	movl	76(%rsp), %esi
	movl	%r15d, 68(%rsp)
	movq	80(%rsp), %rdx
	movq	68(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	movq	48(%rsp), %r8
	movq	40(%rsp), %rcx
	movl	%ebp, %edx
	movq	32(%rsp), %rsi
	movq	56(%rsp), %rdi
	call	_Z55__device_stub__Z9Diamond_3P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L82:
	call	cudaDeviceSynchronize@PLT
	sarl	%ebp
	decl	%r14d
	jne	.L83
	call	clock@PLT
	movq	32(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	testb	%r13b, %r13b
	je	.L84
	xorl	%ebp, %ebp
	leaq	.LC5(%rip), %r12
.L85:
	movq	(%rsp), %rax
	movl	$513, %edi
	movq	%r12, %rsi
	cvtss2sd	(%rax,%rbp,4), %xmm0
	movl	%ebp, %eax
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%ebp, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%rbp
	cmpq	$263169, %rbp
	jne	.L85
.L84:
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rax
	movl	$2, %edi
	leaq	.LC22(%rip), %rsi
	subq	%rax, %rbx
	movb	$1, %al
	cvtsi2sdq	%rbx, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L86
	call	__stack_chk_fail@PLT
.L86:
	addq	$3158136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3984:
	.size	_Z9version_3bi, .-_Z9version_3bi
	.globl	_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4029:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L90:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4029:
	.size	_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_
	.type	_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_, @function
_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_:
.LFB4030:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4030:
	.size	_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_, .-_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC23:
	.string	"Run time for Version_4: %0.20f\n"
	.text
	.globl	_Z9version_4b
	.type	_Z9version_4b, @function
_Z9version_4b:
.LFB3985:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL4:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL4
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	leaq	.LC18(%rip), %rsi
	movl	$9, %r13d
	movl	$512, %r14d
	movabsq	$4294967552, %r15
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	leaq	2105428(%rsp), %rbx
	movl	%edi, %r12d
	movl	$2, %edi
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%rbx, %rdi
	rep stosl
	xorps	%xmm0, %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC14(%rip), %rsi
	movl	$0x00000000, 2107476(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC15(%rip), %rsi
	movl	$0x00000000, 3156052(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movl	$0x00000000, 3158100(%rsp)
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	leaq	76(%rsp), %rax
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	movq	%rax, %rbp
.L97:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r15, %rdx
	movl	$1, %ecx
	movabsq	$4294968325, %rdi
	movl	$1, %esi
	movq	%r15, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rdi, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%r14d, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z63__device_stub__Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L96:
	call	cudaDeviceSynchronize@PLT
	sarl	%r14d
	decl	%r13d
	jne	.L97
	call	clock@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1052676, %edx
	movq	%rax, %r13
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	testb	%r12b, %r12b
	je	.L98
	xorl	%r12d, %r12d
	leaq	.LC5(%rip), %r14
.L99:
	movl	%r12d, %eax
	movl	$513, %edi
	cvtss2sd	(%rbx,%r12,4), %xmm0
	movq	%r14, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%r12d, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r12
	cmpq	$263169, %r12
	jne	.L99
.L98:
	movq	16(%rsp), %rdi
	subq	%rbp, %r13
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC23(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%r13, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L100
	call	__stack_chk_fail@PLT
.L100:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3985:
	.size	_Z9version_4b, .-_Z9version_4b
	.globl	_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4031:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8Square_6P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L104:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4031:
	.size	_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z8Square_6P17curandStateXORWOWPfiS1_S1_
	.type	_Z8Square_6P17curandStateXORWOWPfiS1_S1_, @function
_Z8Square_6P17curandStateXORWOWPfiS1_S1_:
.LFB4032:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4032:
	.size	_Z8Square_6P17curandStateXORWOWPfiS1_S1_, .-_Z8Square_6P17curandStateXORWOWPfiS1_S1_
	.globl	_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4033:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L109
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L109:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L111
	call	__stack_chk_fail@PLT
.L111:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4033:
	.size	_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_
	.type	_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_, @function
_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_:
.LFB4034:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4034:
	.size	_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_, .-_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC24:
	.string	"Version 6: square kernel + smart diamond kernel (active less threads) \n"
.LC25:
	.string	"Run time for Version_6: %0.20f\n"
	.text
	.globl	_Z9version_6v
	.type	_Z9version_6v, @function
_Z9version_6v:
.LFB3987:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL5:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL5
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	leaq	.LC24(%rip), %rsi
	movl	$2, %edi
	movl	$512, %ebp
	movabsq	$4294967552, %r12
	movl	$9, %r15d
	movabsq	$4294968325, %r13
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	leaq	2105428(%rsp), %rbx
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%rbx, %rdi
	rep stosl
	xorps	%xmm0, %xmm0
	leaq	.LC12(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC14(%rip), %rsi
	movl	$0x00000000, 2107476(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC15(%rip), %rsi
	movl	$0x00000000, 3156052(%rsp)
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC16(%rip), %rsi
	movl	$0x00000000, 3158100(%rsp)
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	leaq	76(%rsp), %rax
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	movq	%rax, %r14
.L117:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%r13, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L115
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L115:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r12, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%r13, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L116
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z55__device_stub__Z9Diamond_6P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L116:
	call	cudaDeviceSynchronize@PLT
	sarl	%ebp
	decl	%r15d
	jne	.L117
	call	clock@PLT
	movq	16(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r12d, %r12d
	movl	$2, %ecx
	movl	$1052676, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	leaq	.LC5(%rip), %r13
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
.L118:
	movl	%r12d, %eax
	movl	$513, %edi
	cvtss2sd	(%rbx,%r12,4), %xmm0
	movq	%r13, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%r12d, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r12
	cmpq	$263169, %r12
	jne	.L118
	movq	16(%rsp), %rdi
	subq	%r14, %rbp
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC25(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbp, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L119
	call	__stack_chk_fail@PLT
.L119:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3987:
	.size	_Z9version_6v, .-_Z9version_6v
	.globl	_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L123
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8Square_8P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L123:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L125
	call	__stack_chk_fail@PLT
.L125:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4035:
	.size	_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z8Square_8P17curandStateXORWOWPfiS1_S1_
	.type	_Z8Square_8P17curandStateXORWOWPfiS1_S1_, @function
_Z8Square_8P17curandStateXORWOWPfiS1_S1_:
.LFB4036:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4036:
	.size	_Z8Square_8P17curandStateXORWOWPfiS1_S1_, .-_Z8Square_8P17curandStateXORWOWPfiS1_S1_
	.globl	_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4037:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L128
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L128:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L130
	call	__stack_chk_fail@PLT
.L130:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4037:
	.size	_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_
	.type	_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_, @function
_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_:
.LFB4038:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4038:
	.size	_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_, .-_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_
	.section	.rodata.str1.1
.LC26:
	.string	"Version 8: square kernel + smart diamond kernel\n"
.LC35:
	.string	"Run time for Version_8: %0.20f\n"
	.text
	.globl	_Z9version_8bi
	.type	_Z9version_8bi, @function
_Z9version_8bi:
.LFB3989:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL6:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL6
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	movl	$9, %r14d
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	movl	%esi, %ebp
	leaq	2105428(%rsp), %rbx
	movl	%edi, %r13d
	leaq	.LC26(%rip), %rsi
	movl	$2, %edi
	leaq	76(%rsp), %r15
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%rbx, %rdi
	movsd	.LC28(%rip), %xmm0
	leaq	.LC12(%rip), %rsi
	rep stosl
	movl	$2, %edi
	movb	$1, %al
	movl	$0x3f800000, 2105428(%rsp)
	call	__printf_chk@PLT
	movsd	.LC30(%rip), %xmm0
	leaq	.LC14(%rip), %rsi
	movb	$1, %al
	movl	$0x40000000, 2107476(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC31(%rip), %xmm0
	leaq	.LC15(%rip), %rsi
	movb	$1, %al
	movl	$0x40400000, 3156052(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC33(%rip), %xmm0
	leaq	.LC16(%rip), %rsi
	movb	$1, %al
	movl	$0x40800000, 3158100(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	cvtsi2ssl	%ebp, %xmm1
	movss	.LC34(%rip), %xmm0
	movq	%rax, %r12
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movl	$1, 60(%rsp)
	cvttss2siq	%xmm0, %rax
	movl	$1, 72(%rsp)
	movl	%ebp, 64(%rsp)
	movl	%ebp, 68(%rsp)
	movl	$512, %ebp
	movl	%eax, 52(%rsp)
	movl	%eax, 56(%rsp)
.L136:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L134
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L134:
	call	cudaDeviceSynchronize@PLT
	movl	72(%rsp), %ecx
	movl	60(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	52(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L135
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z55__device_stub__Z9Diamond_8P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L135:
	call	cudaDeviceSynchronize@PLT
	sarl	%ebp
	decl	%r14d
	jne	.L136
	call	clock@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1052676, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r15, %rdi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	testb	%r13b, %r13b
	je	.L137
	xorl	%r13d, %r13d
	leaq	.LC5(%rip), %r14
.L138:
	movl	%r13d, %eax
	movl	$513, %edi
	cvtss2sd	(%rbx,%r13,4), %xmm0
	movq	%r14, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%r13d, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r13
	cmpq	$263169, %r13
	jne	.L138
.L137:
	movq	16(%rsp), %rdi
	subq	%r12, %rbp
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC35(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbp, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L139
	call	__stack_chk_fail@PLT
.L139:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3989:
	.size	_Z9version_8bi, .-_Z9version_8bi
	.globl	_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4039:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L143
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8Square_9P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L143:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L145
	call	__stack_chk_fail@PLT
.L145:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4039:
	.size	_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z8Square_9P17curandStateXORWOWPfiS1_S1_
	.type	_Z8Square_9P17curandStateXORWOWPfiS1_S1_, @function
_Z8Square_9P17curandStateXORWOWPfiS1_S1_:
.LFB4040:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4040:
	.size	_Z8Square_9P17curandStateXORWOWPfiS1_S1_, .-_Z8Square_9P17curandStateXORWOWPfiS1_S1_
	.globl	_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.type	_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, @function
_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_:
.LFB4041:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L148
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L148:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L150
	call	__stack_chk_fail@PLT
.L150:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4041:
	.size	_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_, .-_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_
	.type	_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_, @function
_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_:
.LFB4042:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
	.cfi_endproc
.LFE4042:
	.size	_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_, .-_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_
	.globl	_Z9version_9bi
	.type	_Z9version_9bi, @function
_Z9version_9bi:
.LFB3990:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-3158016(%rsp), %r11
	.cfi_def_cfa 11, 3158072
.LPSRL7:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL7
	.cfi_def_cfa_register 7
	subq	$104, %rsp
	.cfi_def_cfa_offset 3158176
	movl	$9, %r14d
	movq	%fs:40, %rax
	movq	%rax, 3158104(%rsp)
	xorl	%eax, %eax
	movl	%esi, %ebp
	leaq	2105428(%rsp), %rbx
	movl	%edi, %r13d
	leaq	.LC26(%rip), %rsi
	movl	$2, %edi
	leaq	76(%rsp), %r15
	call	__printf_chk@PLT
	xorl	%eax, %eax
	movl	$263169, %ecx
	movq	%rbx, %rdi
	movsd	.LC28(%rip), %xmm0
	leaq	.LC12(%rip), %rsi
	rep stosl
	movl	$2, %edi
	movb	$1, %al
	movl	$0x3f800000, 2105428(%rsp)
	call	__printf_chk@PLT
	movsd	.LC30(%rip), %xmm0
	leaq	.LC14(%rip), %rsi
	movb	$1, %al
	movl	$0x40000000, 2107476(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC31(%rip), %xmm0
	leaq	.LC15(%rip), %rsi
	movb	$1, %al
	movl	$0x40400000, 3156052(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	.LC33(%rip), %xmm0
	leaq	.LC16(%rip), %rsi
	movb	$1, %al
	movl	$0x40800000, 3158100(%rsp)
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	40(%rsp), %rdi
	movl	$12632112, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$1052676, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r15, %rsi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	leaq	1052752(%rsp), %rax
	movl	$1052676, %edx
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMemcpy@PLT
	call	clock@PLT
	cvtsi2ssl	%ebp, %xmm1
	movss	.LC34(%rip), %xmm0
	movq	%rax, %r12
	divss	%xmm1, %xmm0
	call	ceilf@PLT
	movl	$1, 60(%rsp)
	cvttss2siq	%xmm0, %rax
	movl	$1, 72(%rsp)
	movl	%ebp, 64(%rsp)
	movl	%ebp, 68(%rsp)
	movl	$512, %ebp
	movl	%eax, 52(%rsp)
	movl	%eax, 56(%rsp)
.L156:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L154
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z54__device_stub__Z8Square_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L154:
	call	cudaDeviceSynchronize@PLT
	movl	72(%rsp), %ecx
	movl	60(%rsp), %esi
	xorl	%r9d, %r9d
	movq	64(%rsp), %rdx
	movq	52(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L155
	movq	32(%rsp), %r8
	movq	24(%rsp), %rcx
	movl	%ebp, %edx
	movq	16(%rsp), %rsi
	movq	40(%rsp), %rdi
	call	_Z55__device_stub__Z9Diamond_9P17curandStateXORWOWPfiS1_S1_P17curandStateXORWOWPfiS1_S1_
.L155:
	call	cudaDeviceSynchronize@PLT
	sarl	%ebp
	decl	%r14d
	jne	.L156
	call	clock@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$1052676, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r15, %rdi
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1052676, %edx
	call	cudaMemcpy@PLT
	testb	%r13b, %r13b
	je	.L157
	xorl	%r13d, %r13d
	leaq	.LC5(%rip), %r14
.L158:
	movl	%r13d, %eax
	movl	$513, %edi
	cvtss2sd	(%rbx,%r13,4), %xmm0
	movq	%r14, %rsi
	cltd
	idivl	%edi
	movl	$2, %edi
	movl	%edx, %ecx
	movl	%eax, %r8d
	movl	%r13d, %edx
	movb	$1, %al
	call	__printf_chk@PLT
	incq	%r13
	cmpq	$263169, %r13
	jne	.L158
.L157:
	movq	16(%rsp), %rdi
	subq	%r12, %rbp
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC35(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%rbp, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	3158104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L159
	call	__stack_chk_fail@PLT
.L159:
	addq	$3158120, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3990:
	.size	_Z9version_9bi, .-_Z9version_9bi
	.section	.rodata.str1.1
.LC36:
	.string	"what version do you want: "
.LC37:
	.string	"%d"
.LC38:
	.string	"print? (0/1): "
.LC39:
	.string	"please define block_size(max = 32): "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3980:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC36(%rip), %rsi
	leaq	.LC37(%rip), %rbx
	movl	$2, %edi
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	12(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC38(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	16(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC39(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	xorl	%eax, %eax
	leaq	20(%rsp), %rsi
	call	__isoc23_scanf@PLT
	movl	12(%rsp), %eax
	cmpl	$0, 16(%rsp)
	setne	%dil
	decl	%eax
	cmpl	$8, %eax
	ja	.L164
	leaq	.L166(%rip), %rdx
	movslq	(%rdx,%rax,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata
	.align 4
	.align 4
.L166:
	.long	.L174-.L166
	.long	.L173-.L166
	.long	.L172-.L166
	.long	.L171-.L166
	.long	.L170-.L166
	.long	.L169-.L166
	.long	.L168-.L166
	.long	.L167-.L166
	.long	.L165-.L166
	.section	.text.startup
.L164:
	call	_Z9version_0v
	jmp	.L175
.L174:
	call	_Z9version_1v
	jmp	.L175
.L173:
	call	_Z9version_2v
	jmp	.L175
.L172:
	movl	20(%rsp), %esi
	movzbl	%dil, %edi
	call	_Z9version_3bi
	jmp	.L175
.L171:
	movzbl	%dil, %edi
	call	_Z9version_4b
	jmp	.L175
.L170:
	call	_Z9version_5v
	jmp	.L175
.L169:
	call	_Z9version_6v
	jmp	.L175
.L168:
	call	_Z9version_7v
	jmp	.L175
.L167:
	movl	20(%rsp), %esi
	movzbl	%dil, %edi
	call	_Z9version_8bi
	jmp	.L175
.L165:
	movl	20(%rsp), %esi
	movzbl	%dil, %edi
	call	_Z9version_9bi
.L175:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L176
	call	__stack_chk_fail@PLT
.L176:
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3980:
	.size	main, .-main
	.section	.rodata.str1.1
.LC40:
	.string	"_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_"
.LC41:
	.string	"_Z8Square_9P17curandStateXORWOWPfiS1_S1_"
.LC42:
	.string	"_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_"
.LC43:
	.string	"_Z8Square_8P17curandStateXORWOWPfiS1_S1_"
.LC44:
	.string	"_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_"
.LC45:
	.string	"_Z8Square_6P17curandStateXORWOWPfiS1_S1_"
.LC46:
	.string	"_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_"
.LC47:
	.string	"_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_"
.LC48:
	.string	"_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_"
.LC49:
	.string	"_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_"
.LC50:
	.string	"_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_"
.LC51:
	.string	"_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_"
.LC52:
	.string	"_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_"
.LC53:
	.string	"_Z8Square_1P17curandStateXORWOWPfiS1_S1_"
.LC54:
	.string	"precalc_xorwow_matrix"
.LC55:
	.string	"precalc_xorwow_offset_matrix"
.LC56:
	.string	"mrg32k3aM1"
.LC57:
	.string	"mrg32k3aM2"
.LC58:
	.string	"mrg32k3aM1SubSeq"
.LC59:
	.string	"mrg32k3aM2SubSeq"
.LC60:
	.string	"mrg32k3aM1Seq"
.LC61:
	.string	"mrg32k3aM2Seq"
.LC62:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4044:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9Diamond_9P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8Square_9P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9Diamond_8P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8Square_8P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9Diamond_6P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8Square_6P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z16Square_Diamond_4P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9Diamond_3P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC48(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z9Diamond_2P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11Diamond_1_4P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11Diamond_1_3P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC51(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11Diamond_1_2P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11Diamond_1_1P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8Square_1P17curandStateXORWOWPfiS1_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC54(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4044:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1048576000
	.align 4
.LC2:
	.long	1084227584
	.align 4
.LC3:
	.long	1077936128
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC6:
	.long	0
	.long	1093567616
	.section	.rodata.cst4
	.align 4
.LC21:
	.long	1216380960
	.section	.rodata.cst8
	.align 8
.LC28:
	.long	0
	.long	1072693248
	.align 8
.LC30:
	.long	0
	.long	1073741824
	.align 8
.LC31:
	.long	0
	.long	1074266112
	.align 8
.LC33:
	.long	0
	.long	1074790400
	.section	.rodata.cst4
	.align 4
.LC34:
	.long	1140850688
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/************************************************************
*	ECE408 Parallel Programming - Final Project				*
*															*
*	Topic: Terrain Generation								*
*	Members: Lai,Haoming; Ma,Yunhan; Wang,Bangqi			*
*															*
************************************************************/

/* 
* Terrain Generation:
* Algorithmn: Diamond Square Algorithmn.
* Version:
*			0. Serial version: 1 * square loop + 4 * diamond loop;
*			1. Parallel version: 1 * sdsfsdfsdf + 4 * diamond kernel; 
*			2. Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex);
*			3. Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			4. One Kernel Version: 1 * square_diamond kernel combined; (based on version 2)
*			5. Kernel Device Version: 1 * kernel + 1 * square device + 1 * diamond device;
*			6. Less Threads Version: 1 * kernel + 1 * square device + 1 * diamond device (only active threads we need);
*			7. Shared Memory Version: 1 * kernel + 1 * square device + 1 * diamond device (use share memory);
*
*			8. 2D Smarter Kernel Versio: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*/

#include "hip/hip_runtime.h"

#include <hip/device_functions.h>
#include <stdio.h>

#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <time.h>
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include <math.h>

/* Set the parameter */
/* Choose the version to use */
//#define VERSION 0
/* Set the length of each edge. please put power of 2 */
#define SIZE 512
/* Set number of array */
#define N (SIZE+1)*(SIZE+1)
/* Set the roughness for terrain */
#define ROUGHNESS 10
/* Set the height for each corner */
#define CORNER 0

/* main function for different version */
int version_0 (void);
int version_1 (void);
int version_2 (void);
int version_3 (bool print, int block_size);
int version_4 (bool print);
int version_5 (void);
int version_6 (void);
int version_7 (void);
int version_8 (bool print, int block_size);
int version_9 (bool print, int block_size);

/* main function */
int main (void){
	int VERSION;
	int p;
	int block_size; 

	bool print= false;
	printf("what version do you want: ");
	scanf("%d", &VERSION);
	printf("print? (0/1): ");
	scanf("%d", &p);
	printf("please define block_size(max = 32): ");
	scanf("%d", &block_size);
	if(p)
		print = true; 

	switch(VERSION){
		/* test version 0 */
		case 0:
			version_0();
			break;
		case 1:
		/* test version 1 */
			version_1();
			break;
		case 2:
		/* test version 2 */
			version_2();
			break;
		case 3:
		/* test version 3 */
			version_3(print, block_size);
			break;
		case 4:
		/* test version 4 */
			version_4(print);
			break;
		case 5:
		/* test version 5 */
			version_5();
			break;
		case 6:
		/* test version 5 */
			version_6();
			break;
		case 7:
		/* test version 5 */
			version_7();
			break;
		case 8:
		/* test version 5 */
			version_8(print, block_size);
			break;
		case 9:
		/* test version 5 */
			version_9(print, block_size);
			break;
		default:
		/* test version 0 */
			version_0();
			return 0;
	}
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 0.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 0.0: 
*			0.0 Serial version: 1 * square loop + 4 * loop;  
*			
*/

/* host code for serial version */
int version_0 (void) {
	clock_t start, end;
	double runTime;
	float heightMap[SIZE+1][SIZE+1];
	for(int i=0; i<SIZE; i++){
		for(int j=0; j<SIZE; j++){
			heightMap[i][j] = 0.0;
		}
	}

	//initial the first four points
	heightMap[0][0] = 0; 
	heightMap[SIZE][0] = 0; 
	heightMap[0][SIZE] = 0; 
	heightMap[SIZE][SIZE] = 0;  

	start = clock();
	int stride = SIZE;
	while(stride>=2){
		for(int i = 0; i<(SIZE/stride); i++){
			for(int j = 0; j<(SIZE/stride); j++){
				int leftbottom_x = i* stride;
				int leftbottom_y = j* stride;
				float average =  heightMap[leftbottom_x][leftbottom_y] + heightMap[leftbottom_x + stride][leftbottom_y] + heightMap[leftbottom_x][leftbottom_y+stride] + heightMap[leftbottom_x + stride][leftbottom_y +stride];
				average = average /4 ;
				heightMap[leftbottom_x + stride/2][leftbottom_y + stride/2]= average + rand() %10 - 5; 


				heightMap[leftbottom_x + stride/2 ][leftbottom_y] = (average + heightMap[leftbottom_x][leftbottom_y]  + heightMap[leftbottom_x + stride][leftbottom_y] ) /3 + rand() %10 -5; 
				heightMap[leftbottom_x][leftbottom_y + stride/2] = (average + heightMap[leftbottom_x][leftbottom_y]  + heightMap[leftbottom_x][leftbottom_y + stride] ) /3 + rand() %10 -5 ; 
				heightMap[leftbottom_x + stride][leftbottom_y+ stride/2] = (average + heightMap[leftbottom_x + stride ][leftbottom_y]  + heightMap[leftbottom_x + stride][leftbottom_y + stride] ) /3 +rand() %10-5; 
				heightMap[leftbottom_x+ stride/2][leftbottom_y+ stride] = (average + heightMap[leftbottom_x][leftbottom_y + stride]  + heightMap[leftbottom_x + stride][leftbottom_y + stride] ) /3 +rand() %10-5; 
			}


		}
		printf("%d \n", stride);
		stride = stride/2;
	}

 	for (int i=0; i<=SIZE; i++){
 		for(int j=0; j<=SIZE; j++){
	 		printf("%d: x = %d, y = %d; hm = %f\n", i*j, i, j, heightMap[i][j]);
		}
	}

	end = clock();
 	runTime = (double)(end - start)/CLOCKS_PER_SEC;

	printf("Run time for Version_0: %f\n", runTime);
	printf("Version 0\n");
	return 0;
}



///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 1.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 1.0: 
*			1.0 Parallel version: 1 * square kernel + 4 * diamond kernel;  
*			This parallel function parallelize the serial code directly. it change the one square loop to
*			one square kernel and change four diamond loop to four different diamond kernel.	1
*/

/* square kernel to calculate the middle point */
__global__ void Square_1(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();
  	}
}

/* diamond kernel 1_1 to calcualte middle bottom point */
__global__ void Diamond_1_1(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, mi, j;
		int pmi_b, pmj_b;
		float hm_b;
		int num_b;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		mi = i + half;

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand1 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
  }

/* diamond kernel 1_2 to calcualte left point */
__global__ void Diamond_1_2(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, mj;
		int pmi_l, pmj_l;
		float hm_l;
		int num_l;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		mj = j + half;

		/* find 4 diamond vertex */
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;

		/* set the value */
		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand2 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;

		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* diamond kernel 1_3 to calcualte right point */
__global__ void Diamond_1_3(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, mj;
		int pmi_r, pmj_r;
		float hm_r;
		int num_r;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		mj = j + half;

		/* find 4 diamond vertex */
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;

		/* set the value */
		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand3 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* diamond kernel 1_4 to calcualte middle top point */
__global__ void Diamond_1_4(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, mi, nj;
		int pmi_t, pmj_t;
		float hm_t;
		int num_t;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		nj = j + rect;
		mi = i + half;

		/* find 4 diamond vertex */
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		// check1[idx] = hm_l;
		// check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand4 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}

/* host code for version 1.0 */
int version_1 (void) {
	printf("Version 1: square kernel + 4 diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_1_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_1_2<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_1_3<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_1_4<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_1: %f\n", runTime);
	return EXIT_SUCCESS;
}




///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 2.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 2.0:
*			2.0 Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex); 
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/

/* combined diamond kernel to calculate the four point in each thread */
__global__ void Diamond_2(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int pmi_b, pmj_b, pmi_l, pmj_l, pmi_r, pmj_r, pmi_t, pmj_t;
		float hm_b, hm_l, hm_r, hm_t;
		int num_b, num_l, num_r, num_t;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		check1[idx] = hm_l;
		check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand1 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand2 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand3 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand4 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}


/* the host code for version 2: 1 square kernel + 1 stupid diamond kernel */
int version_2 (void) {
	printf("Version 2: square kernel + stupid diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_2<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_2: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}




///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 3.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 3.0:
*			3.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex.
*/

/* smart diamond kernel calculate the diamond vertex and each thread only calculate one vertex */
__global__ void Diamond_3(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p + rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 3: 1 square kernel + 1 smart diamond kernel */
int version_3 (bool print, int block_size) {
	printf("Version 3: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	int size = block_size * block_size;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_1<<<ceil((float)N/size),size>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_3<<<ceil((float)N/size),size>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
	// for (int i=0; i<N; i++){
	//   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
	// }

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_3: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 4.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 4.0:
*			4.0 Less Kernel Version: 1 * square kernal + 1 * simple diamond kernel (1 thread => 4 vertex); 
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/
/* combined diamond kernel to calculate the four point in each thread */
__global__ void Square_Diamond_4(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
  	if (idx < N){
  		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int pmi_b, pmj_b, pmi_l, pmj_l, pmi_r, pmj_r, pmi_t, pmj_t;
		float hm_b, hm_l, hm_r, hm_t;
		int num_b, num_l, num_r, num_t;
		int squareInRow = SIZE/rect;

  		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();

		/* find 4 diamond vertex */
		/* bottom vertex */
		pmi_b = mi;
		pmj_b = j;
		/* left vertex */
		pmi_l = i;
		pmj_l = mj;
		/* right vertex */
		pmi_r = ni;
		pmj_r = mj;
		/* top vertex */
		pmi_t = mi;
		pmj_t = nj;

		/* set the value */
		/* bottom height */
		hm_b = 0;
		num_b = 3;
		if (pmj_b - half >= 0){
			hm_b += hm[pmi_b + (pmj_b-half)*(SIZE+1)];
			num_b = 4;
		}
		hm_b += hm[pmi_b + (pmj_b+half)*(SIZE+1)];
		hm_b += hm[(pmi_b-half) + pmj_b*(SIZE+1)];
		hm_b += hm[(pmi_b+half) + pmj_b*(SIZE+1)];

		/* left height */
		hm_l = 0;
		num_l = 3;
		if (pmi_l - half >= 0){
			hm_l += hm[(pmi_l-half) + pmj_l*(SIZE+1)];
			num_l = 4;
		}
		hm_l += hm[(pmi_l+half) + pmj_l*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l-half)*(SIZE+1)];
		hm_l += hm[pmi_l + (pmj_l+half)*(SIZE+1)];

		/* right height */
		hm_r = 0;
		num_r = 3;
		if (pmi_r + half <= SIZE){
			hm_r += hm[(pmi_r+half) + pmj_r*(SIZE+1)];
			num_r = 4;
		}
		hm_r += hm[(pmi_r-half) + pmj_r*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r-half)*(SIZE+1)];
		hm_r += hm[pmi_r + (pmj_r+half)*(SIZE+1)];

		/* top height */
		hm_t = 0;
		num_t = 3;
		if (pmj_t + half <= SIZE){
			hm_t += hm[pmi_t + (pmj_t+half)*(SIZE+1)];
			num_t = 4;
		}
		hm_t += hm[pmi_t + (pmj_t-half)*(SIZE+1)];
		hm_t += hm[(pmi_t-half) + pmj_t*(SIZE+1)];
		hm_t += hm[(pmi_t+half) + pmj_t*(SIZE+1)];

		/* set check value */
		check1[idx] = hm_l;
		check2[idx] = hm_l;

		/* get height for  */

		/* set random generator */
	    float rand1 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand2 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand3 = v1 + (v2 - v1) * hiprand_uniform(&localState);
	    float rand4 = v1 + (v2 - v1) * hiprand_uniform(&localState);

	    /* set height map */
		hm[pmi_b + pmj_b*(SIZE+1)] = hm_b/num_b + rand1;
      	hm[pmi_l + pmj_l*(SIZE+1)] = hm_l/num_l + rand2;
      	hm[pmi_r + pmj_r*(SIZE+1)] = hm_r/num_r + rand3;
      	hm[pmi_t + pmj_t*(SIZE+1)] = hm_t/num_t + rand4;  
		// hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		rng[idx] = localState;
		__syncthreads();     
  	}
}


/* the host code for version 2: 1 square kernel + 1 stupid diamond kernel */
int version_4 (bool print) {
	printf("Version 2: square kernel + stupid diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_Diamond_4<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_4: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}

int version_5 (void) {
	printf("5\n");
	return 0;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 6.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 6.0:
*			6. Less Threads Version: 1 * kernel + 1 * square device + 1 * diamond device (only active threads we need);
*			This kernel combine the four diamond kernel to one single kernel. However, each thread in diamond
*			kernel needs to calculate four vertex.
*/

/* square kernel to calculate the middle point */
__global__ void Square_6(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int squareInRow = SIZE/rect;
  	if (idx < squareInRow * squareInRow){
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 + rand;
		__syncthreads();
  	}
}

/* smart diamond kernel calculate the diamond vertex and each thread only calculate one vertex */
__global__ void Diamond_6(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int squareInRow = SIZE/rect;
  	if (idx < 4 * squareInRow * squareInRow){
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p + rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 3: 1 square kernel + 1 smart diamond kernel */
int version_6 (void) {
	printf("Version 6: square kernel + smart diamond kernel (active less threads) \n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = CORNER;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = CORNER;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
 	for (int i=SIZE; i>1; i=i/2){
		Square_6<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_6<<<ceil((float)N/256),256>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	for (int i=0; i<N; i++){
	  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
	}
	// printf("\n");	
	// for (int i=0; i<N; i++){
	//   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
	// }

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_6: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


int version_7 (void) {
	printf("7\n");
	return 0;
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 8.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 8.0:
*			8.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex. (A simple revised 2D version of version 3)
*/
__global__ void Square_8(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 +rand;
		__syncthreads();
  	}
}

__global__ void Diamond_8(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p +rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 8: 2D + 1 square kernel + 1 smart diamond kernel. */
int version_8 (bool print, int block_size) {
	printf("Version 8: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = 1;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = 2;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = 3;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = 4;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
	dim3 DimGrid(ceil(((float)SIZE)/block_size),ceil(((float)SIZE)/block_size), 1); 
	dim3 DimBlock(block_size,block_size,1);
 	for (int i=SIZE; i>1; i=i/2){
		Square_8<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_8<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
//	for (int i=0; i<SIZE+1; i++){
//	   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
//	}

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_8: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}


///////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// VERSION 9.0 ////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////
/*	VERSION 9.0:
*			9.0 Smarter Kernel Version: 1 * sqaure kernel + 1 * smart diamond kernel (1 thread => 1 vertex);
*			This version reconstruct the diamond kernel to use different threads for different vertx. Each 
*			thread in diamond kernel only need to calculate one vertex. (A simple revised 2D version of version 3)
*/
__global__ void Square_9(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j, ni, nj, mi, mj;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;
		ni = i + rect;
		nj = j + rect;
		mi = i + half;
		mj = j + half;

		/* set check value */
		check1[idx] = mi;
		check2[idx] = mj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);
		rng[idx] = localState;

	    /* set height map */
		hm[mi + mj*(SIZE+1)] = (hm[i + j*(SIZE+1)] + hm[ni + j*(SIZE+1)] + hm[i + nj*(SIZE+1)] + hm[ni + nj*(SIZE+1)])/4 +rand;
		__syncthreads();
  	}
}

__global__ void Diamond_9(hiprandState* rng, float* hm, int rect, float* check1, float* check2){
	/* set idx */
	int idx_temp = blockIdx.x * blockDim.x + threadIdx.x;
	int idy = blockIdx.y * blockDim.y + threadIdx.y;
  	if (idx_temp < SIZE+1 && idy < SIZE+1){
  		int idx = idy*(SIZE+1) + idx_temp;
		/* initialize vairable */
		int half = rect/2;
		int i, j;
		int pmi, pmj;
		float hm_p;
		int num_p;
		int squareInRow = SIZE/rect;
	  
		/* calculate vertex */
		i = (idx%squareInRow*rect)%SIZE;
		j = (idx/squareInRow*rect)%SIZE;

		/* Calculate the diamond vertex use idx */
		int tid = idx/(squareInRow*squareInRow)%4;
		pmi = i + (1 - tid%2)*half + tid/2*half;
		pmj = j + tid%2*half + tid/2*half;

		/* Set the value */
		hm_p = 0;
		num_p = 0;
		if (pmi - half >= 0){
			hm_p += hm[(pmi-half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmi + half <= SIZE){
			hm_p += hm[(pmi+half) + pmj*(SIZE+1)];
			num_p++;
		}
		if (pmj - half >= 0){
			hm_p += hm[pmi + (pmj-half)*(SIZE+1)];
			num_p++;
		}
		if (pmj + half <= SIZE){
			hm_p += hm[pmi + (pmj+half)*(SIZE+1)];
			num_p++;
		}

		/* set check value */
		check1[idx] = pmi;
		check2[idx] = pmj;

		/* set random generator */
		float v1 = (0.0f - (float)ROUGHNESS)/2;
		float v2 = ((float)ROUGHNESS)/2;
		hiprandState localState = rng[idx];
	    float rand = v1 + (v2 - v1) * hiprand_uniform(&localState);

		/* get height for  */
		hm[pmi + pmj*(SIZE+1)] = hm_p/num_p +rand;
		rng[idx] = localState;
		__syncthreads();    
  	}
}

/* the host code for version 8: 2D + 1 square kernel + 1 smart diamond kernel. */
int version_9 (bool print, int block_size) {
	printf("Version 8: square kernel + smart diamond kernel\n");
	/* initialize variables */
	float check1[N];
	float check2[N];
	float heightMap[N];
	/* initialize device */
	float *dev_heightMap;
	float *dev_check1;
	float *dev_check2;
	/* initialize time*/
	clock_t start, end;
	double runTime;
	/* initial height map */
	for (int i=0; i<N; i++){
	  heightMap[i] = 0;
	}

	/* set height for corner */
	heightMap[0 + 0 * (SIZE+1)] = 1;
	printf("heightMap_corner0: %f\n", heightMap[0 + 0 * (SIZE+1)]);
	heightMap[SIZE + 0 * (SIZE+1)] = 2;
	printf("heightMap_corner1: %f\n", heightMap[SIZE + 0 * (SIZE+1)]);
	heightMap[0 + SIZE * (SIZE+1)] = 3;
	printf("heightMap_corner3: %f\n", heightMap[0 + SIZE * (SIZE+1)]);
	heightMap[SIZE + SIZE * (SIZE+1)] = 4;
	printf("heightMap_corner2: %f\n", heightMap[SIZE + SIZE * (SIZE+1)]);

	hiprandState* rng;
	/* allocate memory for device */
	hipMalloc(&rng, N * sizeof(hiprandState));
	hipMalloc((void**)&dev_heightMap, N * sizeof(float));
	hipMalloc((void**)&dev_check1, N * sizeof(float));
	hipMalloc((void**)&dev_check2, N * sizeof(float));

	/* memory copy from host to device */
	hipMemcpy(dev_heightMap, heightMap, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check1, check1, N * sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(dev_check2, check2, N * sizeof(float), hipMemcpyHostToDevice);

	start = clock();
	/* run kernel */
	dim3 DimGrid(ceil(((float)SIZE)/block_size),ceil(((float)SIZE)/block_size), 1); 
	dim3 DimBlock(block_size,block_size,1);
 	for (int i=SIZE; i>1; i=i/2){
		Square_9<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
		Diamond_9<<<DimGrid,DimBlock>>>(rng, (float*)dev_heightMap, i, dev_check1, dev_check2);
		hipDeviceSynchronize();
 	}
 	end = clock();

	/* memory copy from device to host*/
	hipMemcpy(heightMap, dev_heightMap, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check1, dev_check1, N * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy(check2, dev_check2, N * sizeof(float), hipMemcpyDeviceToHost);

	/* print the output */
	if(print){
		for (int i=0; i<N; i++){
		  printf("%d: x = %d, y = %d; hm = %f\n", i, i%(SIZE+1), i/(SIZE+1), heightMap[i]);
		}
	}
	// printf("\n");	
//	for (int i=0; i<SIZE+1; i++){
//	   printf("%d: pmi = %f, pmj = %f\n", i, check1[i], check2[i]);
//	}

	// printf("%f\n", cpu_time_used);
	hipFree(dev_heightMap);
	hipFree(dev_check1);
	hipFree(dev_check2);

 	runTime = (double)(end - start)/CLOCKS_PER_SEC;
	printf("Run time for Version_8: %0.20f\n", runTime);
	return EXIT_SUCCESS;
}

	.text
	.file	"tg.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	12(%rsp), %rbx
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	8(%rsp), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	4(%rsp), %rsi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %ecx
	cmpq	$9, %rcx
	ja	.LBB0_2
# %bb.1:
	movl	8(%rsp), %eax
	jmpq	*.LJTI0_0(,%rcx,8)
.LBB0_2:
	callq	_Z9version_0v
	jmp	.LBB0_13
.LBB0_3:
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	callq	_Z9version_4b
	jmp	.LBB0_13
.LBB0_4:
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	movl	4(%rsp), %esi
	callq	_Z9version_9bi
	jmp	.LBB0_13
.LBB0_5:
	callq	_Z9version_2v
	jmp	.LBB0_13
.LBB0_6:
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	movl	4(%rsp), %esi
	callq	_Z9version_3bi
	jmp	.LBB0_13
.LBB0_7:
	movl	$.Lstr.7, %edi
	jmp	.LBB0_10
.LBB0_8:
	callq	_Z9version_1v
	jmp	.LBB0_13
.LBB0_9:
	movl	$.Lstr.5, %edi
.LBB0_10:
	callq	puts@PLT
	jmp	.LBB0_13
.LBB0_11:
	callq	_Z9version_6v
	jmp	.LBB0_13
.LBB0_12:
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	movl	4(%rsp), %esi
	callq	_Z9version_8bi
.LBB0_13:
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI0_0:
	.quad	.LBB0_2
	.quad	.LBB0_8
	.quad	.LBB0_5
	.quad	.LBB0_6
	.quad	.LBB0_3
	.quad	.LBB0_9
	.quad	.LBB0_11
	.quad	.LBB0_7
	.quad	.LBB0_12
	.quad	.LBB0_4
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9version_0v
.LCPI1_0:
	.long	0x3e800000                      # float 0.25
.LCPI1_1:
	.long	0xc0a00000                      # float -5
.LCPI1_2:
	.long	0x40400000                      # float 3
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_3:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_0v
	.type	_Z9version_0v,@function
_Z9version_0v:                          # @_Z9version_0v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1052872, %rsp                  # imm = 0x1010C8
	.cfi_def_cfa_offset 1052928
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
.LBB1_1:                                # %.preheader101
                                        # =>This Inner Loop Header: Depth=1
	leaq	(%rsp,%rbx), %rdi
	addq	$192, %rdi
	movl	$2048, %edx                     # imm = 0x800
	xorl	%esi, %esi
	callq	memset@PLT
	addq	$2052, %rbx                     # imm = 0x804
	cmpq	$1050624, %rbx                  # imm = 0x100800
	jne	.LBB1_1
# %bb.2:
	xorl	%eax, %eax
	movl	%eax, 192(%rsp)
	movl	%eax, 1050816(%rsp)
	movl	%eax, 2240(%rsp)
	movl	%eax, 1052864(%rsp)
	movl	$512, %ebx                      # imm = 0x200
	callq	clock
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movl	$512, %esi                      # imm = 0x200
.LBB1_3:                                # %.preheader99.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_5 Depth 3
	movl	$512, %eax                      # imm = 0x200
	xorl	%edx, %edx
	divl	%ebx
                                        # kill: def $eax killed $eax def $rax
	shrl	%esi
	movl	%ebx, 20(%rsp)                  # 4-byte Spill
	movl	%ebx, %edi
	movq	%rdi, %rcx
	shlq	$11, %rcx
	leaq	(%rcx,%rdi,4), %rbp
	leaq	(,%rdi,4), %r9
	movq	%rsi, %rdx
	shlq	$11, %rdx
	leaq	(%rdx,%rsi,4), %r14
	leaq	(%rcx,%rdi,8), %r15
	leaq	(%r14,%rdi,4), %r12
	leaq	(%rdx,%rsi,8), %rcx
	leaq	(%rbp,%rsi,4), %rdx
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	leaq	(,%rsi,4), %rsi
	movq	%r9, %rbx
	movq	%rbp, 72(%rsp)                  # 8-byte Spill
	xorl	%r13d, %r13d
	xorl	%edi, %edi
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movq	%r9, 168(%rsp)                  # 8-byte Spill
.LBB1_4:                                # %.preheader99
                                        #   Parent Loop BB1_3 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_5 Depth 3
	movq	%rdi, 88(%rsp)                  # 8-byte Spill
	movq	%rdx, 128(%rsp)                 # 8-byte Spill
	movq	%rdx, 48(%rsp)                  # 8-byte Spill
	movq	%rsi, 120(%rsp)                 # 8-byte Spill
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rcx, 136(%rsp)                 # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	%r12, 144(%rsp)                 # 8-byte Spill
	movq	%r12, %rcx
	movq	%r15, 152(%rsp)                 # 8-byte Spill
	movq	%r15, %rdx
	movq	%rbx, 112(%rsp)                 # 8-byte Spill
	movq	%r14, 160(%rsp)                 # 8-byte Spill
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movq	%rbp, 104(%rsp)                 # 8-byte Spill
	movq	%r13, 96(%rsp)                  # 8-byte Spill
.LBB1_5:                                #   Parent Loop BB1_3 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%rdx, 8(%rsp)                   # 8-byte Spill
	movq	%rcx, 176(%rsp)                 # 8-byte Spill
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	movss	192(%rsp,%r13), %xmm0           # xmm0 = mem[0],zero,zero,zero
	addss	192(%rsp,%rbp), %xmm0
	addss	192(%rsp,%rbx), %xmm0
	addss	192(%rsp,%rdx), %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	(%rsp), %xmm2                   # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	addss	%xmm2, %xmm0
	movss	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	addss	%xmm1, %xmm0
	movq	32(%rsp), %rax                  # 8-byte Reload
	movss	%xmm0, 192(%rsp,%rax)
	movss	192(%rsp,%r13), %xmm1           # xmm1 = mem[0],zero,zero,zero
	addss	%xmm2, %xmm1
	addss	192(%rsp,%rbp), %xmm1
	movss	.LCPI1_2(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	addss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	addss	.LCPI1_1(%rip), %xmm0
	movq	24(%rsp), %r15                  # 8-byte Reload
	movss	%xmm0, 192(%rsp,%r15)
	movss	192(%rsp,%r13), %xmm0           # xmm0 = mem[0],zero,zero,zero
	addss	(%rsp), %xmm0                   # 4-byte Folded Reload
	addss	192(%rsp,%rbx), %xmm0
	divss	.LCPI1_2(%rip), %xmm0
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	addss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	addss	.LCPI1_1(%rip), %xmm0
	movq	40(%rsp), %r14                  # 8-byte Reload
	movss	%xmm0, 192(%rsp,%r14)
	movss	192(%rsp,%rbp), %xmm0           # xmm0 = mem[0],zero,zero,zero
	addss	(%rsp), %xmm0                   # 4-byte Folded Reload
	movq	8(%rsp), %rax                   # 8-byte Reload
	addss	192(%rsp,%rax), %xmm0
	divss	.LCPI1_2(%rip), %xmm0
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	addss	4(%rsp), %xmm0                  # 4-byte Folded Reload
	addss	.LCPI1_1(%rip), %xmm0
	movq	48(%rsp), %r12                  # 8-byte Reload
	movss	%xmm0, 192(%rsp,%r12)
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	192(%rsp,%rbx), %xmm0
	movq	8(%rsp), %rax                   # 8-byte Reload
	addss	192(%rsp,%rax), %xmm0
	divss	.LCPI1_2(%rip), %xmm0
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	callq	rand
	movq	168(%rsp), %r9                  # 8-byte Reload
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	movq	8(%rsp), %rdx                   # 8-byte Reload
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	subl	%ecx, %eax
	movq	176(%rsp), %rcx                 # 8-byte Reload
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movq	184(%rsp), %rax                 # 8-byte Reload
	addss	(%rsp), %xmm0                   # 4-byte Folded Reload
	addss	.LCPI1_1(%rip), %xmm0
	movss	%xmm0, 192(%rsp,%rcx)
	addq	%r9, %r13
	addq	%r9, %rbp
	addq	%r9, %r15
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	addq	%r9, %rbx
	addq	%r9, %rdx
	addq	%r9, %rcx
	addq	%r9, 32(%rsp)                   # 8-byte Folded Spill
	addq	%r9, %r14
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	addq	%r9, %r12
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	decq	%rax
	jne	.LBB1_5
# %bb.6:                                #   in Loop: Header=BB1_4 Depth=2
	movq	88(%rsp), %rdi                  # 8-byte Reload
	incq	%rdi
	movq	72(%rsp), %rax                  # 8-byte Reload
	movq	96(%rsp), %r13                  # 8-byte Reload
	addq	%rax, %r13
	movq	104(%rsp), %rbp                 # 8-byte Reload
	addq	%rax, %rbp
	movq	160(%rsp), %r14                 # 8-byte Reload
	addq	%rax, %r14
	movq	112(%rsp), %rbx                 # 8-byte Reload
	addq	%rax, %rbx
	movq	152(%rsp), %r15                 # 8-byte Reload
	addq	%rax, %r15
	movq	144(%rsp), %r12                 # 8-byte Reload
	addq	%rax, %r12
	movq	136(%rsp), %rcx                 # 8-byte Reload
	addq	%rax, %rcx
	movq	120(%rsp), %rsi                 # 8-byte Reload
	addq	%rax, %rsi
	movq	128(%rsp), %rdx                 # 8-byte Reload
	addq	%rax, %rdx
	movq	80(%rsp), %rax                  # 8-byte Reload
	cmpq	%rax, %rdi
	jne	.LBB1_4
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB1_3 Depth=1
	movl	$.L.str.4, %edi
	movl	20(%rsp), %ebx                  # 4-byte Reload
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	cmpl	$3, %ebx
	movq	64(%rsp), %rsi                  # 8-byte Reload
	movl	%esi, %ebx
	ja	.LBB1_3
# %bb.8:                                # %.preheader.preheader
	leaq	192(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB1_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_10 Depth 2
	xorl	%ebp, %ebp
	xorl	%r15d, %r15d
.LBB1_10:                               #   Parent Loop BB1_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%ebp, %esi
	movl	%r14d, %edx
	movl	%r15d, %ecx
	movb	$1, %al
	callq	printf
	incq	%r15
	addl	%r14d, %ebp
	cmpq	$513, %r15                      # imm = 0x201
	jne	.LBB1_10
# %bb.11:                               #   in Loop: Header=BB1_9 Depth=1
	incq	%r14
	addq	$2052, %rbx                     # imm = 0x804
	cmpq	$513, %r14                      # imm = 0x201
	jne	.LBB1_9
# %bb.12:
	callq	clock
	subq	56(%rsp), %rax                  # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI1_3(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$1052872, %rsp                  # imm = 0x1010C8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z9version_0v, .Lfunc_end1-_Z9version_0v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_1v
.LCPI2_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_1v
	.type	_Z9version_1v,@function
_Z9version_1v:                          # @_Z9version_1v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r14
	xorl	%r15d, %r15d
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$.L.str.9, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 2048(%r14)
	movl	$.L.str.10, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1050624(%r14)
	movl	$.L.str.11, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1052672(%r14)
	movl	$.L.str.12, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$512, %ebp                      # imm = 0x200
	callq	clock
	movq	%rax, %r14
	leaq	773(%rbx), %r15
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_3
# %bb.2:                                #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
.LBB2_3:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
.LBB2_5:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:                                #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
.LBB2_7:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
.LBB2_9:                                #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
.LBB2_11:                               #   in Loop: Header=BB2_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB2_1
# %bb.12:
	callq	clock
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB2_13:                               # =>This Inner Loop Header: Depth=1
	movl	%r15d, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%r15d, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%r15,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%r15d, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$263169, %r15                   # imm = 0x40401
	jne	.LBB2_13
# %bb.14:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r14, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rbx, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movl	$.L.str.13, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9version_1v, .Lfunc_end2-_Z9version_1v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_2v
.LCPI3_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_2v
	.type	_Z9version_2v,@function
_Z9version_2v:                          # @_Z9version_2v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r14
	xorl	%r15d, %r15d
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$.L.str.9, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 2048(%r14)
	movl	$.L.str.10, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1050624(%r14)
	movl	$.L.str.11, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1052672(%r14)
	movl	$.L.str.12, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$512, %ebp                      # imm = 0x200
	callq	clock
	movq	%rax, %r14
	leaq	773(%rbx), %r15
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_3
# %bb.2:                                #   in Loop: Header=BB3_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
.LBB3_3:                                #   in Loop: Header=BB3_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_5
# %bb.4:                                #   in Loop: Header=BB3_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
.LBB3_5:                                #   in Loop: Header=BB3_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB3_1
# %bb.6:
	callq	clock
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB3_7:                                # =>This Inner Loop Header: Depth=1
	movl	%r15d, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%r15d, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%r15,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%r15d, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$263169, %r15                   # imm = 0x40401
	jne	.LBB3_7
# %bb.8:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r14, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rbx, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movl	$.L.str.15, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z9version_2v, .Lfunc_end3-_Z9version_2v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z9version_3bi
.LCPI4_0:
	.long	0x48808020                      # float 263169
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI4_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_3bi
	.type	_Z9version_3bi,@function
_Z9version_3bi:                         # @_Z9version_3bi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %r14d
	movl	%edi, %ebx
	movl	$.Lstr.3, %edi
	callq	puts@PLT
	imull	%r14d, %r14d
	leaq	32(%rsp), %r15
	xorl	%r12d, %r12d
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$.L.str.9, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 2048(%r15)
	movl	$.L.str.10, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 1050624(%r15)
	movl	$.L.str.11, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 1052672(%r15)
	movl	$.L.str.12, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rbp
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	cvtsi2ss	%r14d, %xmm1
	movq	%rax, %r15
	movss	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rax
	movl	%eax, %r12d
	btsq	$32, %r12
	btsq	$32, %r14
	movl	$512, %ebp                      # imm = 0x200
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_3
# %bb.2:                                #   in Loop: Header=BB4_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
.LBB4_3:                                #   in Loop: Header=BB4_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:                                #   in Loop: Header=BB4_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
.LBB4_5:                                #   in Loop: Header=BB4_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB4_1
# %bb.6:
	callq	clock
	movq	%rax, %r14
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	testb	%bl, %bl
	je	.LBB4_9
# %bb.7:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB4_8:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%ebx, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%rbx,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%ebx, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$263169, %rbx                   # imm = 0x40401
	jne	.LBB4_8
.LBB4_9:                                # %.loopexit
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r15, %r14
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r14, %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movl	$.L.str.17, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z9version_3bi, .Lfunc_end4-_Z9version_3bi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_4b
.LCPI5_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_4b
	.type	_Z9version_4b,@function
_Z9version_4b:                          # @_Z9version_4b
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	movabsq	$4294967552, %r14               # imm = 0x100000100
	movl	$.Lstr.4, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r15
	xorl	%r12d, %r12d
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$.L.str.9, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 2048(%r15)
	movl	$.L.str.10, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 1050624(%r15)
	movl	$.L.str.11, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r12d, 1052672(%r15)
	movl	$.L.str.12, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rbp
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$512, %ebp                      # imm = 0x200
	callq	clock
	movq	%rax, %r15
	leaq	773(%r14), %r12
.LBB5_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_3
# %bb.2:                                #   in Loop: Header=BB5_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
.LBB5_3:                                #   in Loop: Header=BB5_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB5_1
# %bb.4:
	callq	clock
	movq	%rax, %r14
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	testb	%bl, %bl
	je	.LBB5_7
# %bb.5:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB5_6:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%ebx, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%rbx,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%ebx, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$263169, %rbx                   # imm = 0x40401
	jne	.LBB5_6
.LBB5_7:                                # %.loopexit
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r15, %r14
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r14, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	movl	$.L.str.18, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z9version_4b, .Lfunc_end5-_Z9version_4b
	.cfi_endproc
                                        # -- End function
	.globl	_Z9version_5v                   # -- Begin function _Z9version_5v
	.type	_Z9version_5v,@function
_Z9version_5v:                          # @_Z9version_5v
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.Lstr.5, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z9version_5v, .Lfunc_end6-_Z9version_5v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_6v
.LCPI7_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	_Z9version_6v
	.type	_Z9version_6v,@function
_Z9version_6v:                          # @_Z9version_6v
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	movl	$.Lstr.6, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r14
	xorl	%r15d, %r15d
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$.L.str.9, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 2048(%r14)
	movl	$.L.str.10, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1050624(%r14)
	movl	$.L.str.11, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	movl	%r15d, 1052672(%r14)
	movl	$.L.str.12, %edi
	xorps	%xmm0, %xmm0
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$512, %ebp                      # imm = 0x200
	callq	clock
	movq	%rax, %r14
	leaq	773(%rbx), %r15
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_3
# %bb.2:                                #   in Loop: Header=BB7_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
.LBB7_3:                                #   in Loop: Header=BB7_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_5
# %bb.4:                                #   in Loop: Header=BB7_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
.LBB7_5:                                #   in Loop: Header=BB7_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB7_1
# %bb.6:
	callq	clock
	movq	%rax, %rbx
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB7_7:                                # =>This Inner Loop Header: Depth=1
	movl	%r15d, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%r15d, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%r15,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%r15d, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	$263169, %r15                   # imm = 0x40401
	jne	.LBB7_7
# %bb.8:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r14, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rbx, %xmm0
	divsd	.LCPI7_0(%rip), %xmm0
	movl	$.L.str.21, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z9version_6v, .Lfunc_end7-_Z9version_6v
	.cfi_endproc
                                        # -- End function
	.globl	_Z9version_7v                   # -- Begin function _Z9version_7v
	.type	_Z9version_7v,@function
_Z9version_7v:                          # @_Z9version_7v
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z9version_7v, .Lfunc_end8-_Z9version_7v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_8bi
.LCPI9_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI9_1:
	.quad	0x4000000000000000              # double 2
.LCPI9_2:
	.quad	0x4008000000000000              # double 3
.LCPI9_3:
	.quad	0x4010000000000000              # double 4
.LCPI9_5:
	.quad	0x412e848000000000              # double 1.0E+6
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI9_4:
	.long	0x44000000                      # float 512
	.text
	.globl	_Z9version_8bi
	.type	_Z9version_8bi,@function
_Z9version_8bi:                         # @_Z9version_8bi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movl	%edi, %ebx
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r14
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$1065353216, (%r14)             # imm = 0x3F800000
	movsd	.LCPI9_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movl	$1073741824, 2048(%r14)         # imm = 0x40000000
	movsd	.LCPI9_1(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	movl	$1077936128, 1050624(%r14)      # imm = 0x40400000
	movsd	.LCPI9_2(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.11, %edi
	movb	$1, %al
	callq	printf
	movl	$1082130432, 1052672(%r14)      # imm = 0x40800000
	movsd	.LCPI9_3(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	$.L.str.12, %edi
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	cvtsi2ss	%ebp, %xmm1
	movq	%rax, %r14
	movss	.LCPI9_4(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15
	movl	%r15d, %eax
	shlq	$32, %r15
	orq	%rax, %r15
	movl	%ebp, %eax
	movq	%rax, %r12
	shlq	$32, %r12
	orq	%rax, %r12
	movl	$512, %ebp                      # imm = 0x200
.LBB9_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_3
# %bb.2:                                #   in Loop: Header=BB9_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
.LBB9_3:                                #   in Loop: Header=BB9_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB9_5
# %bb.4:                                #   in Loop: Header=BB9_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
.LBB9_5:                                #   in Loop: Header=BB9_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB9_1
# %bb.6:
	callq	clock
	movq	%rax, %r15
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	testb	%bl, %bl
	je	.LBB9_9
# %bb.7:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB9_8:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%ebx, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%rbx,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%ebx, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$263169, %rbx                   # imm = 0x40401
	jne	.LBB9_8
.LBB9_9:                                # %.loopexit
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r14, %r15
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15, %xmm0
	divsd	.LCPI9_5(%rip), %xmm0
	movl	$.L.str.24, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z9version_8bi, .Lfunc_end9-_Z9version_8bi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9version_9bi
.LCPI10_0:
	.quad	0x3ff0000000000000              # double 1
.LCPI10_1:
	.quad	0x4000000000000000              # double 2
.LCPI10_2:
	.quad	0x4008000000000000              # double 3
.LCPI10_3:
	.quad	0x4010000000000000              # double 4
.LCPI10_5:
	.quad	0x412e848000000000              # double 1.0E+6
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI10_4:
	.long	0x44000000                      # float 512
	.text
	.globl	_Z9version_9bi
	.type	_Z9version_9bi,@function
_Z9version_9bi:                         # @_Z9version_9bi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 3158144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movl	%edi, %ebx
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r14
	movl	$1052672, %edx                  # imm = 0x101000
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$1065353216, (%r14)             # imm = 0x3F800000
	movsd	.LCPI10_0(%rip), %xmm0          # xmm0 = mem[0],zero
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movl	$1073741824, 2048(%r14)         # imm = 0x40000000
	movsd	.LCPI10_1(%rip), %xmm0          # xmm0 = mem[0],zero
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	movl	$1077936128, 1050624(%r14)      # imm = 0x40400000
	movsd	.LCPI10_2(%rip), %xmm0          # xmm0 = mem[0],zero
	movl	$.L.str.11, %edi
	movb	$1, %al
	callq	printf
	movl	$1082130432, 1052672(%r14)      # imm = 0x40800000
	movsd	.LCPI10_3(%rip), %xmm0          # xmm0 = mem[0],zero
	movl	$.L.str.12, %edi
	movb	$1, %al
	callq	printf
	leaq	24(%rsp), %rdi
	movl	$12632112, %esi                 # imm = 0xC0C030
	callq	hipMalloc
	leaq	16(%rsp), %r15
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %r13
	movl	$1052676, %esi                  # imm = 0x101004
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	2105408(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	leaq	1052720(%rsp), %rsi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$1, %ecx
	callq	hipMemcpy
	callq	clock
	cvtsi2ss	%ebp, %xmm1
	movq	%rax, %r14
	movss	.LCPI10_4(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	divss	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15
	movl	%r15d, %eax
	shlq	$32, %r15
	orq	%rax, %r15
	movl	%ebp, %eax
	movq	%rax, %r12
	shlq	$32, %r12
	orq	%rax, %r12
	movl	$512, %ebp                      # imm = 0x200
.LBB10_1:                               # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_3
# %bb.2:                                #   in Loop: Header=BB10_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
.LBB10_3:                               #   in Loop: Header=BB10_1 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB10_5
# %bb.4:                                #   in Loop: Header=BB10_1 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rcx
	movq	(%rsp), %r8
	movl	%ebp, %edx
	callq	_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
.LBB10_5:                               #   in Loop: Header=BB10_1 Depth=1
	callq	hipDeviceSynchronize
	movl	%ebp, %eax
	shrl	%eax
	cmpl	$3, %ebp
	movl	%eax, %ebp
	ja	.LBB10_1
# %bb.6:
	callq	clock
	movq	%rax, %r15
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	leaq	2105408(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	leaq	1052720(%rsp), %rdi
	movl	$1052676, %edx                  # imm = 0x101004
	movl	$2, %ecx
	callq	hipMemcpy
	testb	%bl, %bl
	je	.LBB10_9
# %bb.7:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	movl	$4286595041, %r12d              # imm = 0xFF803FE1
.LBB10_8:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebx, %ecx
	imulq	%r12, %rcx
	shrq	$41, %rcx
	movl	%ecx, %eax
	shll	$9, %eax
	addl	%ecx, %eax
	movl	%ebx, %edx
	subl	%eax, %edx
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%rbx,4), %xmm0
	movl	$.L.str.5, %edi
	movl	%ebx, %esi
                                        # kill: def $ecx killed $ecx killed $rcx
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$263169, %rbx                   # imm = 0x40401
	jne	.LBB10_8
.LBB10_9:                               # %.loopexit
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	subq	%r14, %r15
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r15, %xmm0
	divsd	.LCPI10_5(%rip), %xmm0
	movl	$.L.str.24, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$3158088, %rsp                  # imm = 0x303048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z9version_9bi, .Lfunc_end10-_Z9version_9bi
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_ # -- Begin function _Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
	.type	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_,@function
_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_: # @_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Square_1P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_, .Lfunc_end11-_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_ # -- Begin function _Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
	.type	_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_,@function
_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_: # @_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11Diamond_1_1P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_, .Lfunc_end12-_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_ # -- Begin function _Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
	.type	_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_,@function
_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_: # @_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11Diamond_1_2P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_, .Lfunc_end13-_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_ # -- Begin function _Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
	.type	_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_,@function
_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_: # @_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11Diamond_1_3P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_, .Lfunc_end14-_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_ # -- Begin function _Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
	.type	_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_,@function
_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_: # @_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11Diamond_1_4P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_, .Lfunc_end15-_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_ # -- Begin function _Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
	.type	_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_,@function
_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_: # @_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9Diamond_2P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_, .Lfunc_end16-_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_ # -- Begin function _Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
	.type	_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_,@function
_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_: # @_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9Diamond_3P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_, .Lfunc_end17-_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_ # -- Begin function _Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
	.type	_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_,@function
_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_: # @_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_, .Lfunc_end18-_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_ # -- Begin function _Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
	.type	_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_,@function
_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_: # @_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Square_6P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_, .Lfunc_end19-_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_ # -- Begin function _Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
	.type	_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_,@function
_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_: # @_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9Diamond_6P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_, .Lfunc_end20-_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_ # -- Begin function _Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
	.type	_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_,@function
_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_: # @_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Square_8P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_, .Lfunc_end21-_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_ # -- Begin function _Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
	.type	_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_,@function
_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_: # @_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9Diamond_8P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_, .Lfunc_end22-_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_ # -- Begin function _Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
	.type	_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_,@function
_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_: # @_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8Square_9P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_, .Lfunc_end23-_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_ # -- Begin function _Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
	.type	_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_,@function
_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_: # @_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9Diamond_9P12hiprandStatePfiS1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_, .Lfunc_end24-_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB25_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB25_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Square_1P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11Diamond_1_1P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11Diamond_1_2P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11Diamond_1_3P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11Diamond_1_4P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9Diamond_2P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9Diamond_3P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Square_6P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9Diamond_6P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Square_8P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9Diamond_8P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8Square_9P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9Diamond_9P12hiprandStatePfiS1_S1_, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end25:
	.size	__hip_module_ctor, .Lfunc_end25-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB26_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB26_2:
	retq
.Lfunc_end26:
	.size	__hip_module_dtor, .Lfunc_end26-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"what version do you want: "
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"print? (0/1): "
	.size	.L.str.2, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"please define block_size(max = 32): "
	.size	.L.str.3, 37

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d \n"
	.size	.L.str.4, 5

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d: x = %d, y = %d; hm = %f\n"
	.size	.L.str.5, 29

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Run time for Version_0: %f\n"
	.size	.L.str.6, 28

	.type	_Z8Square_1P12hiprandStatePfiS1_S1_,@object # @_Z8Square_1P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z8Square_1P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z8Square_1P12hiprandStatePfiS1_S1_:
	.quad	_Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
	.size	_Z8Square_1P12hiprandStatePfiS1_S1_, 8

	.type	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_,@object # @_Z11Diamond_1_1P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z11Diamond_1_1P12hiprandStatePfiS1_S1_:
	.quad	_Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
	.size	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_, 8

	.type	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_,@object # @_Z11Diamond_1_2P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z11Diamond_1_2P12hiprandStatePfiS1_S1_:
	.quad	_Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
	.size	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_, 8

	.type	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_,@object # @_Z11Diamond_1_3P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z11Diamond_1_3P12hiprandStatePfiS1_S1_:
	.quad	_Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
	.size	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_, 8

	.type	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_,@object # @_Z11Diamond_1_4P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z11Diamond_1_4P12hiprandStatePfiS1_S1_:
	.quad	_Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
	.size	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.9,@object                # @.str.9
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.9:
	.asciz	"heightMap_corner0: %f\n"
	.size	.L.str.9, 23

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"heightMap_corner1: %f\n"
	.size	.L.str.10, 23

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"heightMap_corner3: %f\n"
	.size	.L.str.11, 23

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"heightMap_corner2: %f\n"
	.size	.L.str.12, 23

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Run time for Version_1: %f\n"
	.size	.L.str.13, 28

	.type	_Z9Diamond_2P12hiprandStatePfiS1_S1_,@object # @_Z9Diamond_2P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z9Diamond_2P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z9Diamond_2P12hiprandStatePfiS1_S1_:
	.quad	_Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
	.size	_Z9Diamond_2P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.15,@object               # @.str.15
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.15:
	.asciz	"Run time for Version_2: %0.20f\n"
	.size	.L.str.15, 32

	.type	_Z9Diamond_3P12hiprandStatePfiS1_S1_,@object # @_Z9Diamond_3P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z9Diamond_3P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z9Diamond_3P12hiprandStatePfiS1_S1_:
	.quad	_Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
	.size	_Z9Diamond_3P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.17,@object               # @.str.17
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.17:
	.asciz	"Run time for Version_3: %0.20f\n"
	.size	.L.str.17, 32

	.type	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_,@object # @_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_:
	.quad	_Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
	.size	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.18,@object               # @.str.18
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.18:
	.asciz	"Run time for Version_4: %0.20f\n"
	.size	.L.str.18, 32

	.type	_Z8Square_6P12hiprandStatePfiS1_S1_,@object # @_Z8Square_6P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z8Square_6P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z8Square_6P12hiprandStatePfiS1_S1_:
	.quad	_Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
	.size	_Z8Square_6P12hiprandStatePfiS1_S1_, 8

	.type	_Z9Diamond_6P12hiprandStatePfiS1_S1_,@object # @_Z9Diamond_6P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_6P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z9Diamond_6P12hiprandStatePfiS1_S1_:
	.quad	_Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
	.size	_Z9Diamond_6P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.21,@object               # @.str.21
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.21:
	.asciz	"Run time for Version_6: %0.20f\n"
	.size	.L.str.21, 32

	.type	_Z8Square_8P12hiprandStatePfiS1_S1_,@object # @_Z8Square_8P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z8Square_8P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z8Square_8P12hiprandStatePfiS1_S1_:
	.quad	_Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
	.size	_Z8Square_8P12hiprandStatePfiS1_S1_, 8

	.type	_Z9Diamond_8P12hiprandStatePfiS1_S1_,@object # @_Z9Diamond_8P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_8P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z9Diamond_8P12hiprandStatePfiS1_S1_:
	.quad	_Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
	.size	_Z9Diamond_8P12hiprandStatePfiS1_S1_, 8

	.type	.L.str.24,@object               # @.str.24
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.24:
	.asciz	"Run time for Version_8: %0.20f\n"
	.size	.L.str.24, 32

	.type	_Z8Square_9P12hiprandStatePfiS1_S1_,@object # @_Z8Square_9P12hiprandStatePfiS1_S1_
	.section	.rodata,"a",@progbits
	.globl	_Z8Square_9P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z8Square_9P12hiprandStatePfiS1_S1_:
	.quad	_Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
	.size	_Z8Square_9P12hiprandStatePfiS1_S1_, 8

	.type	_Z9Diamond_9P12hiprandStatePfiS1_S1_,@object # @_Z9Diamond_9P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_9P12hiprandStatePfiS1_S1_
	.p2align	3, 0x0
_Z9Diamond_9P12hiprandStatePfiS1_S1_:
	.quad	_Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
	.size	_Z9Diamond_9P12hiprandStatePfiS1_S1_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8Square_1P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z11Diamond_1_1P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_2, 40

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z11Diamond_1_2P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_3, 40

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z11Diamond_1_3P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_4, 40

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z11Diamond_1_4P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_5, 40

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9Diamond_2P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_6, 37

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z9Diamond_3P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_7, 37

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_8, 45

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z8Square_6P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_9, 36

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z9Diamond_6P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_10, 37

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z8Square_8P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_11, 36

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z9Diamond_8P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_12, 37

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z8Square_9P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_13, 36

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z9Diamond_9P12hiprandStatePfiS1_S1_"
	.size	.L__unnamed_14, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Version 0"
	.size	.Lstr, 10

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Version 1: square kernel + 4 diamond kernel"
	.size	.Lstr.1, 44

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"Version 3: square kernel + smart diamond kernel"
	.size	.Lstr.3, 48

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"Version 2: square kernel + stupid diamond kernel"
	.size	.Lstr.4, 49

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"5"
	.size	.Lstr.5, 2

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"Version 6: square kernel + smart diamond kernel (active less threads) "
	.size	.Lstr.6, 71

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"7"
	.size	.Lstr.7, 2

	.type	.Lstr.9,@object                 # @str.9
.Lstr.9:
	.asciz	"Version 8: square kernel + smart diamond kernel"
	.size	.Lstr.9, 48

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__Square_1P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z26__device_stub__Diamond_1_1P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z26__device_stub__Diamond_1_2P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z26__device_stub__Diamond_1_3P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z26__device_stub__Diamond_1_4P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z24__device_stub__Diamond_2P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z24__device_stub__Diamond_3P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z31__device_stub__Square_Diamond_4P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z23__device_stub__Square_6P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z24__device_stub__Diamond_6P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z23__device_stub__Square_8P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z24__device_stub__Diamond_8P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z23__device_stub__Square_9P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z24__device_stub__Diamond_9P12hiprandStatePfiS1_S1_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8Square_1P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z11Diamond_1_1P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z11Diamond_1_2P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z11Diamond_1_3P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z11Diamond_1_4P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z9Diamond_2P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z9Diamond_3P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z8Square_6P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z9Diamond_6P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z8Square_8P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z9Diamond_8P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z8Square_9P12hiprandStatePfiS1_S1_
	.addrsig_sym _Z9Diamond_9P12hiprandStatePfiS1_S1_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8Square_1P12hiprandStatePfiS1_S1_ ; -- Begin function _Z8Square_1P12hiprandStatePfiS1_S1_
	.globl	_Z8Square_1P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z8Square_1P12hiprandStatePfiS1_S1_,@function
_Z8Square_1P12hiprandStatePfiS1_S1_:    ; @_Z8Square_1P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x40401, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b32 s8, s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s8, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s5, 0, s3
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s4
	s_mul_hi_u32 s5, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_lshr_b32 s5, s8, 31
	s_lshr_b32 s4, s4, 23
	s_add_i32 s5, s8, s5
	s_mul_i32 s6, s4, s3
	s_ashr_i32 s9, s5, 1
	s_sub_i32 s5, 0x200, s6
	s_add_i32 s6, s4, 1
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_add_i32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s3
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s5, v0
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s4
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v3, v3, v5
	v_xor_b32_e32 v5, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_load_b128 s[4:7], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v5
	v_mul_lo_u32 v3, v0, s2
	v_mul_lo_u32 v0, v0, s8
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v1, v3
	v_mul_lo_u32 v4, v3, s8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v0
	v_lshrrev_b32_e32 v3, 23, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[7:8], null, v1, 48, s[0:1]
	v_add_nc_u32_e32 v3, v0, v3
	s_mov_b32 s0, 0x41200000
	v_lshrrev_b32_e32 v5, 23, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0xfffffe00, v3
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v5, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v0, v6
	v_and_b32_e32 v5, 0xfffffe00, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, s9, v10
	v_add_nc_u32_e32 v9, s8, v10
	v_sub_nc_u32_e32 v11, v4, v5
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, s9, v11
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_cvt_f32_i32_e32 v0, v6
	v_cvt_f32_i32_e32 v1, v17
	v_lshl_add_u32 v12, v9, 9, v9
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[2:3], v1, off
	s_clause 0x2
	global_load_b128 v[0:3], v[7:8], off offset:24
	global_load_b32 v4, v[7:8], off offset:40
	global_load_b32 v5, v[7:8], off
	v_add_nc_u32_e32 v14, s8, v11
	v_mad_i32_i24 v9, 0x201, v10, v11
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_i32_i24 v13, 0x201, v10, v14
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_nc_u32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v12, 31, v11
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_co_u32 v11, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s2, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v18, 2, v0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 0x587c5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v18, v0
	v_lshlrev_b32_e32 v18, 4, v4
	v_lshlrev_b32_e32 v19, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v18, v19, v18
	v_xor3_b32 v18, v18, v0, v4
	v_add_co_u32 v0, vcc_lo, s2, v15
	s_clause 0x2
	global_store_b32 v[7:8], v5, off
	global_store_b128 v[7:8], v[1:4], off offset:24
	global_store_b32 v[7:8], v18, off offset:40
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v16, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[9:10], off
	global_load_b32 v3, v[13:14], off
	global_load_b32 v4, v[11:12], off
	global_load_b32 v7, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, 0x201, v17, v[6:7]
	v_add_nc_u32_e32 v1, v18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v4
	v_cvt_f32_u32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v7
	v_ashrrev_i32_e32 v1, 31, v0
	v_fmaak_f32 v3, 0x2f800000, v5, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fmaak_f32 v3, s0, v3, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmamk_f32 v2, v2, 0x3e800000, v3
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Square_1P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8Square_1P12hiprandStatePfiS1_S1_, .Lfunc_end0-_Z8Square_1P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1036
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_ ; -- Begin function _Z11Diamond_1_1P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_,@function
_Z11Diamond_1_1P12hiprandStatePfiS1_S1_: ; @_Z11Diamond_1_1P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v2
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b32 s4, s[2:3], 0x10
	v_ashrrev_i32_e32 v5, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v2, v5
	v_xor_b32_e32 v6, v6, v5
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_lshr_b32 s8, s4, 31
	s_lshr_b32 s7, s7, 23
	s_add_i32 s8, s4, s8
	s_mul_i32 s9, s7, s6
	s_ashr_i32 s8, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_add_i32 s10, s7, 1
	s_sub_i32 s11, s9, s6
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s7, s10, s7
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s7, 1
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s6, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	s_sub_i32 s5, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s6, s5, 31
	s_add_i32 s7, s5, s6
	v_xor_b32_e32 v5, s6, v5
	s_xor_b32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s7
	s_sub_i32 s9, 0, s7
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v6, v3
	v_mul_lo_u32 v4, v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v7, s7, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v3
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s5
	v_mul_lo_u32 v3, v3, s4
	v_sub_nc_u32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v3
	v_mul_lo_u32 v4, v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v5, 23, v5
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v4
	v_and_b32_e32 v5, 0xfffffe00, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 23, v6
	v_sub_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v4, v6
	v_subrev_nc_u32_e32 v8, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v3, 0xfffffe00, v6
	v_sub_nc_u32_e32 v7, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v4, 0x40400000 :: v_dual_add_nc_u32 v3, s8, v7
	v_cmpx_lt_i32_e32 -1, v8
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0x201, v8, v[3:4]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b32 v4, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, 0, v4
	v_mov_b32_e32 v4, 4.0
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v10, s8, v5
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[15:16], null, v2, 48, s[4:5]
	s_load_b64 s[0:1], s[0:1], 0x4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0x201, v10, v[3:4]
	v_mul_i32_i24_e32 v9, 0x201, v5
	v_mad_i32_i24 v10, 0x201, v5, v7
	v_add3_u32 v12, v3, s8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[7:8], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[10:11]
	v_lshlrev_b64 v[11:12], 2, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v19, v[7:8], off
	v_add_co_u32 v7, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v12, vcc_lo
	s_clause 0x1
	global_load_b32 v20, v[9:10], off
	global_load_b32 v21, v[7:8], off
	s_clause 0x4
	global_load_b128 v[7:10], v[15:16], off offset:24
	global_load_b64 v[17:18], v[15:16], off offset:40
	global_load_b32 v2, v[15:16], off
	global_load_b128 v[11:14], v[15:16], off offset:4
	global_load_b32 v22, v[15:16], off offset:20
	s_mul_i32 s0, s0, s1
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v6, v6, v19 :: v_dual_add_nc_u32 v27, 0x587c5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v6, v20
	v_mul_lo_u32 v2, s0, v1
	s_mov_b32 s0, 0x41200000
	v_add_f32_e32 v21, v6, v21
	v_lshrrev_b32_e32 v6, 2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v19, null, v4, v4, v21
	v_xor_b32_e32 v6, v6, v7
	v_bfe_u32 v7, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v20, v19
	v_lshlrev_b32_e32 v25, 1, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v23, v20
	v_lshlrev_b32_e32 v24, 4, v17
	v_div_scale_f32 v26, vcc_lo, v21, v4, v21
	v_xor_b32_e32 v23, v25, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f32_e32 v25, v26, v20
	v_bfe_u32 v24, v0, 20, 10
	v_mad_i32_i24 v0, 0x201, v5, v3
	v_mul_u32_u24_e32 v5, s1, v7
	v_xor3_b32 v6, v23, v6, v17
	v_fma_f32 v3, -v19, v25, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add3_u32 v2, v2, v5, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v6, v27
	v_fmac_f32_e32 v25, v3, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mul_lo_u32 v2, v2, 20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v3, v7
	v_fma_f32 v5, -v19, v25, v26
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v11, v12 offset1:1
	ds_store_2addr_b32 v2, v13, v14 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v22 offset:16
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_div_fmas_f32 v5, v5, v20, v25
	v_add_co_u32 v19, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmaak_f32 v1, s0, v3, 0xc0a00000 :: v_dual_mov_b32 v2, v10
	v_div_fixup_f32 v3, v5, v4, v21
	v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v7, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v4, v3, v1 :: v_dual_mov_b32 v1, v9
	v_mov_b32_e32 v3, v17
	global_store_b32 v[19:20], v4, off
	s_clause 0x4
	global_store_b32 v[15:16], v27, off
	global_store_b128 v[15:16], v[11:14], off offset:4
	global_store_b32 v[15:16], v22, off offset:20
	global_store_b128 v[15:16], v[0:3], off offset:24
	global_store_b64 v[15:16], v[6:7], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB1_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11Diamond_1_1P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z11Diamond_1_1P12hiprandStatePfiS1_S1_, .Lfunc_end1-_Z11Diamond_1_1P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1276
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_ ; -- Begin function _Z11Diamond_1_2P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_,@function
_Z11Diamond_1_2P12hiprandStatePfiS1_S1_: ; @_Z11Diamond_1_2P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v2
	s_cbranch_execz .LBB2_4
; %bb.1:
	s_load_b32 s4, s[2:3], 0x10
	v_ashrrev_i32_e32 v5, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v2, v5
	v_xor_b32_e32 v6, v6, v5
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_lshr_b32 s8, s4, 31
	s_lshr_b32 s7, s7, 23
	s_add_i32 s8, s4, s8
	s_mul_i32 s9, s7, s6
	s_ashr_i32 s8, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_add_i32 s10, s7, 1
	s_sub_i32 s11, s9, s6
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s7, s10, s7
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s7, 1
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s6, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	s_sub_i32 s5, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s6, s5, 31
	s_add_i32 s7, s5, s6
	v_xor_b32_e32 v5, s6, v5
	s_xor_b32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s7
	s_sub_i32 s9, 0, s7
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s9, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v6, v3
	v_mul_lo_u32 v4, v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v7, s7, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v3
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s5
	v_mul_lo_u32 v3, v3, s4
	v_sub_nc_u32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v3
	v_mul_lo_u32 v4, v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v5, 23, v5
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v4
	v_and_b32_e32 v5, 0xfffffe00, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 23, v6
	v_sub_nc_u32_e32 v7, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v4, v6
	v_add_nc_u32_e32 v8, s8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, 0xfffffe00, v6
	v_lshl_add_u32 v5, v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v4, v6
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, 0x40400000
	v_subrev_nc_u32_e32 v9, s8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v9
	s_cbranch_execz .LBB2_3
; %bb.2:
	v_add_nc_u32_e32 v9, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v4, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, 0, v4
	v_mov_b32_e32 v4, 4.0
.LBB2_3:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v8, s8, v8
	v_add3_u32 v9, v3, s8, v5
	v_mad_i32_i24 v7, 0x201, v7, v3
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[15:16], null, v2, 48, s[4:5]
	v_mad_u64_u32 v[11:12], null, 0x201, v8, v[3:4]
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v8, 31, v7
	s_load_b64 s[0:1], s[0:1], 0x4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v19, v[9:10], off
	v_add_co_u32 v9, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo
	s_clause 0x1
	global_load_b32 v20, v[7:8], off
	global_load_b32 v21, v[9:10], off
	s_clause 0x4
	global_load_b128 v[7:10], v[15:16], off offset:24
	global_load_b64 v[17:18], v[15:16], off offset:40
	global_load_b32 v2, v[15:16], off
	global_load_b128 v[11:14], v[15:16], off offset:4
	global_load_b32 v22, v[15:16], off offset:20
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s0, s0, s1
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v6, v6, v19 :: v_dual_add_nc_u32 v27, 0x587c5, v2
	v_add_f32_e32 v6, v6, v20
	v_mul_lo_u32 v2, s0, v1
	s_mov_b32 s0, 0x41200000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v6, v21
	v_lshrrev_b32_e32 v6, 2, v7
	v_div_scale_f32 v19, null, v4, v4, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v7
	v_div_scale_f32 v26, vcc_lo, v21, v4, v21
	v_rcp_f32_e32 v20, v19
	v_bfe_u32 v7, v0, 10, 10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v23, v20 :: v_dual_lshlrev_b32 v25, 1, v6
	v_lshlrev_b32_e32 v24, 4, v17
	v_xor_b32_e32 v23, v25, v24
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v25, v26, v20
	v_bfe_u32 v24, v0, 20, 10
	v_add_nc_u32_e32 v0, v5, v3
	v_mul_u32_u24_e32 v5, s1, v7
	v_xor3_b32 v6, v23, v6, v17
	v_fma_f32 v3, -v19, v25, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v2, v5, v24
	v_add_nc_u32_e32 v7, v6, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v25, v3, v20
	v_ashrrev_i32_e32 v1, 31, v0
	v_mul_lo_u32 v2, v2, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v11, v12 offset1:1
	ds_store_2addr_b32 v2, v13, v14 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v22 offset:16
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fma_f32 v5, -v19, v25, v26
	v_mov_b32_e32 v2, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v5, v5, v20, v25
	v_add_co_u32 v19, vcc_lo, s6, v0
	v_mov_b32_e32 v0, v8
	v_cvt_f32_u32_e32 v3, v7
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v1, vcc_lo
	v_mov_b32_e32 v7, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_fmaak_f32 v1, s0, v3, 0xc0a00000
	v_div_fixup_f32 v3, v5, v4, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v4, v3, v1 :: v_dual_mov_b32 v1, v9
	v_mov_b32_e32 v3, v17
	global_store_b32 v[19:20], v4, off
	s_clause 0x4
	global_store_b32 v[15:16], v27, off
	global_store_b128 v[15:16], v[11:14], off offset:4
	global_store_b32 v[15:16], v22, off offset:20
	global_store_b128 v[15:16], v[0:3], off offset:24
	global_store_b64 v[15:16], v[6:7], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB2_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11Diamond_1_2P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z11Diamond_1_2P12hiprandStatePfiS1_S1_, .Lfunc_end2-_Z11Diamond_1_2P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1248
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_ ; -- Begin function _Z11Diamond_1_3P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_,@function
_Z11Diamond_1_3P12hiprandStatePfiS1_S1_: ; @_Z11Diamond_1_3P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v2
	s_cbranch_execz .LBB3_4
; %bb.1:
	s_load_b32 s9, s[2:3], 0x10
	v_ashrrev_i32_e32 v5, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v2, v5
	v_xor_b32_e32 v6, v6, v5
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s9, s4
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s5
	s_sub_i32 s7, 0, s5
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s6
	s_mul_hi_u32 s7, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s6, s7
	s_lshr_b32 s7, s9, 31
	s_lshr_b32 s6, s6, 23
	s_add_i32 s7, s9, s7
	s_mul_i32 s10, s6, s5
	s_ashr_i32 s8, s7, 1
	s_sub_i32 s7, 0x200, s10
	s_add_i32 s10, s6, 1
	s_sub_i32 s11, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s10, s6
	s_cselect_b32 s7, s11, s7
	s_add_i32 s10, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s5, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s4
	s_sub_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s5, s4, 31
	s_add_i32 s6, s4, s5
	v_xor_b32_e32 v5, s5, v5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s7, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v6, v3
	v_mul_lo_u32 v4, v3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v7, s6, v4
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, 1, v3
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s4
	v_mul_lo_u32 v3, v3, s9
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s2, exec_lo
	v_sub_nc_u32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v3
	v_mul_lo_u32 v4, v4, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 23, v6
	v_add_nc_u32_e32 v6, v3, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_and_b32_e32 v6, 0xfffffe00, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v5, 23, v5
	v_sub_nc_u32_e32 v7, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, v4, v5
	v_add_nc_u32_e32 v8, s8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 0xfffffe00, v5
	v_sub_nc_u32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, v8, 9, v8
	v_dual_mov_b32 v4, 0x40400000 :: v_dual_add_nc_u32 v3, s9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, s8, v3
	v_cmpx_gt_i32_e32 0x201, v9
	s_cbranch_execz .LBB3_3
; %bb.2:
	v_add_nc_u32_e32 v9, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v4, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, 0, v4
	v_mov_b32_e32 v4, 4.0
.LBB3_3:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s2
	v_subrev_nc_u32_e32 v9, s8, v3
	v_add_nc_u32_e32 v12, s8, v8
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[15:16], null, v2, 48, s[4:5]
	s_load_b64 s[0:1], s[0:1], 0x4
	v_add_nc_u32_e32 v8, v9, v5
	v_mad_u64_u32 v[10:11], null, 0x201, v12, v[3:4]
	v_mad_i32_i24 v12, 0x201, v7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[7:8], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[9:10], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v13, vcc_lo
	global_load_b32 v19, v[7:8], off
	v_add_co_u32 v7, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v20, v[11:12], off
	global_load_b32 v21, v[7:8], off
	s_clause 0x4
	global_load_b128 v[7:10], v[15:16], off offset:24
	global_load_b64 v[17:18], v[15:16], off offset:40
	global_load_b32 v2, v[15:16], off
	global_load_b128 v[11:14], v[15:16], off offset:4
	global_load_b32 v22, v[15:16], off offset:20
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s0, s0, s1
	s_waitcnt vmcnt(2)
	v_dual_add_f32 v6, v6, v19 :: v_dual_add_nc_u32 v27, 0x587c5, v2
	v_add_f32_e32 v6, v6, v20
	v_mul_lo_u32 v2, s0, v1
	s_mov_b32 s0, 0x41200000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v6, v21
	v_lshrrev_b32_e32 v6, 2, v7
	v_div_scale_f32 v19, null, v4, v4, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v6, v7
	v_div_scale_f32 v26, vcc_lo, v21, v4, v21
	v_rcp_f32_e32 v20, v19
	v_bfe_u32 v7, v0, 10, 10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v19, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v23, v20 :: v_dual_lshlrev_b32 v25, 1, v6
	v_lshlrev_b32_e32 v24, 4, v17
	v_xor_b32_e32 v23, v25, v24
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v25, v26, v20
	v_bfe_u32 v24, v0, 20, 10
	v_add_nc_u32_e32 v0, v5, v3
	v_mul_u32_u24_e32 v5, s1, v7
	v_xor3_b32 v6, v23, v6, v17
	v_fma_f32 v3, -v19, v25, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v2, v2, v5, v24
	v_add_nc_u32_e32 v7, v6, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, v3, v20
	v_mul_lo_u32 v2, v2, 20
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_u32_e32 v3, v7
	v_mov_b32_e32 v7, v18
	v_ashrrev_i32_e32 v1, 31, v0
	v_fma_f32 v5, -v19, v25, v26
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v11, v12 offset1:1
	ds_store_2addr_b32 v2, v13, v14 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v22 offset:16
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_div_fmas_f32 v5, v5, v20, v25
	v_mov_b32_e32 v2, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_u32 v19, vcc_lo, s6, v0
	v_mov_b32_e32 v0, v8
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v1, vcc_lo
	v_fmaak_f32 v1, s0, v3, 0xc0a00000
	v_div_fixup_f32 v3, v5, v4, v21
	v_dual_add_f32 v4, v3, v1 :: v_dual_mov_b32 v1, v9
	v_mov_b32_e32 v3, v17
	global_store_b32 v[19:20], v4, off
	s_clause 0x4
	global_store_b32 v[15:16], v27, off
	global_store_b128 v[15:16], v[11:14], off offset:4
	global_store_b32 v[15:16], v22, off offset:20
	global_store_b128 v[15:16], v[0:3], off offset:24
	global_store_b64 v[15:16], v[6:7], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB3_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11Diamond_1_3P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z11Diamond_1_3P12hiprandStatePfiS1_S1_, .Lfunc_end3-_Z11Diamond_1_3P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_ ; -- Begin function _Z11Diamond_1_4P12hiprandStatePfiS1_S1_
	.globl	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_,@function
_Z11Diamond_1_4P12hiprandStatePfiS1_S1_: ; @_Z11Diamond_1_4P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v2
	s_cbranch_execz .LBB4_4
; %bb.1:
	s_load_b32 s9, s[2:3], 0x10
	v_ashrrev_i32_e32 v5, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v2, v5
	v_xor_b32_e32 v6, v6, v5
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s9, s4
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s5
	s_sub_i32 s7, 0, s5
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s6
	s_mul_hi_u32 s7, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s6, s7
	s_lshr_b32 s7, s9, 31
	s_lshr_b32 s6, s6, 23
	s_add_i32 s7, s9, s7
	s_mul_i32 s10, s6, s5
	s_ashr_i32 s8, s7, 1
	s_sub_i32 s7, 0x200, s10
	s_add_i32 s10, s6, 1
	s_sub_i32 s11, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s10, s6
	s_cselect_b32 s7, s11, s7
	s_add_i32 s10, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s5, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s4
	s_sub_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s5, s4, 31
	s_add_i32 s6, s4, s5
	v_xor_b32_e32 v5, s5, v5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s7, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v4, s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v4
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v6, v3
	v_mul_lo_u32 v4, v3, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v4
	v_add_nc_u32_e32 v6, 1, v3
	v_subrev_nc_u32_e32 v7, s6, v4
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v7
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	v_cndmask_b32_e32 v3, v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v5
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v3, s4
	v_mul_lo_u32 v3, v3, s9
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s2, exec_lo
	v_sub_nc_u32_e32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v3
	v_mul_lo_u32 v4, v4, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v5, 23, v5
	v_add_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v4
	v_and_b32_e32 v5, 0xfffffe00, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v6, 23, v6
	v_sub_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v4, v6
	v_add_nc_u32_e32 v6, s9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, 0xfffffe00, v5
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v4, v3
	v_dual_mov_b32 v4, 0x40400000 :: v_dual_add_nc_u32 v3, s8, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_gt_i32_e32 0x201, v8
	s_cbranch_execz .LBB4_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, 0x201, v8, v[3:4]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v5, 0, v4 :: v_dual_mov_b32 v4, 4.0
.LBB4_3:
	s_or_b32 exec_lo, exec_lo, s2
	v_subrev_nc_u32_e32 v10, s8, v6
	v_lshl_add_u32 v18, v6, 9, v6
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[14:15], null, v2, 48, s[4:5]
	s_load_b64 s[0:1], s[0:1], 0x4
	v_mad_u64_u32 v[8:9], null, 0x201, v10, v[3:4]
	v_add3_u32 v10, v3, s8, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mul_i32 s0, s0, s1
	global_load_b32 v19, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v19
	v_add_nc_u32_e32 v6, v18, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v11, vcc_lo
	s_clause 0x1
	global_load_b32 v20, v[6:7], off
	global_load_b32 v21, v[8:9], off
	s_clause 0x4
	global_load_b128 v[6:9], v[14:15], off offset:24
	global_load_b64 v[16:17], v[14:15], off offset:40
	global_load_b32 v2, v[14:15], off
	global_load_b128 v[10:13], v[14:15], off offset:4
	global_load_b32 v22, v[14:15], off offset:20
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v24, 4, v16
	v_add_f32_e32 v5, v5, v20
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v27, 0x587c5, v2
	v_mul_lo_u32 v2, s0, v1
	s_mov_b32 s0, 0x41200000
	v_add_f32_e32 v20, v5, v21
	v_lshrrev_b32_e32 v5, 2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v19, null, v4, v4, v20
	v_xor_b32_e32 v5, v5, v6
	v_bfe_u32 v6, v0, 10, 10
	v_div_scale_f32 v26, vcc_lo, v20, v4, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v21, v19
	v_lshlrev_b32_e32 v25, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v6, s1, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v19, v21, 1.0
	v_fmac_f32_e32 v21, v23, v21
	v_xor_b32_e32 v23, v25, v24
	v_bfe_u32 v24, v0, 20, 10
	v_add_nc_u32_e32 v0, v18, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor3_b32 v5, v23, v5, v16
	v_mul_f32_e32 v25, v26, v21
	v_add3_u32 v2, v2, v6, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v18, v5, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v3, -v19, v25, v26
	v_mul_lo_u32 v2, v2, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v10, v11 offset1:1
	ds_store_2addr_b32 v2, v12, v13 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v22 offset:16
	v_dual_fmac_f32 v25, v3, v21 :: v_dual_mov_b32 v2, v9
	v_cvt_f32_u32_e32 v3, v18
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, -v19, v25, v26
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v6, v6, v21, v25
	v_add_co_u32 v18, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v1, s0, v3, 0xc0a00000
	v_div_fixup_f32 v3, v6, v4, v20
	v_mov_b32_e32 v6, v17
	v_mov_b32_e32 v0, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_add_f32 v4, v3, v1 :: v_dual_mov_b32 v1, v8
	v_mov_b32_e32 v3, v16
	global_store_b32 v[18:19], v4, off
	s_clause 0x4
	global_store_b32 v[14:15], v27, off
	global_store_b128 v[14:15], v[10:13], off offset:4
	global_store_b32 v[14:15], v22, off offset:20
	global_store_b128 v[14:15], v[0:3], off offset:24
	global_store_b64 v[14:15], v[5:6], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB4_4:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11Diamond_1_4P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z11Diamond_1_4P12hiprandStatePfiS1_S1_, .Lfunc_end4-_Z11Diamond_1_4P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1276
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9Diamond_2P12hiprandStatePfiS1_S1_ ; -- Begin function _Z9Diamond_2P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_2P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z9Diamond_2P12hiprandStatePfiS1_S1_,@function
_Z9Diamond_2P12hiprandStatePfiS1_S1_:   ; @_Z9Diamond_2P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v3
	s_cbranch_execz .LBB5_10
; %bb.1:
	s_load_b32 s9, s[2:3], 0x10
	v_ashrrev_i32_e32 v4, 31, v3
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v3, v4
	v_xor_b32_e32 v6, v6, v4
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s9, s4
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s5
	s_sub_i32 s7, 0, s5
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s6
	s_mul_hi_u32 s7, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s6, s7
	s_lshr_b32 s7, s9, 31
	s_lshr_b32 s6, s6, 23
	s_add_i32 s7, s9, s7
	s_mul_i32 s10, s6, s5
	s_ashr_i32 s8, s7, 1
	s_sub_i32 s7, 0x200, s10
	s_add_i32 s10, s6, 1
	s_sub_i32 s11, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s10, s6
	s_cselect_b32 s7, s11, s7
	s_add_i32 s10, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s5, s10, s6
	s_mov_b32 s10, exec_lo
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s4, s5, s4
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s6
	s_sub_i32 s7, 0, s6
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v5, s7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v2, v5
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v6, v2
	v_mul_lo_u32 v5, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v6, v5
	v_add_nc_u32_e32 v6, 1, v2
	v_subrev_nc_u32_e32 v7, s6, v5
	v_cmp_le_u32_e32 vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v5, v5, v7
	v_xor_b32_e32 v7, s5, v4
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s6, v5
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v7
	v_sub_nc_u32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v2, s4
	v_mul_lo_u32 v2, v2, s9
	s_load_b128 s[4:7], s[2:3], 0x0
	v_sub_nc_u32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v2
	v_mul_lo_u32 v5, v5, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 23, v6
	v_add_nc_u32_e32 v6, v2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v5
	v_and_b32_e32 v6, 0xfffffe00, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 23, v7
	v_sub_nc_u32_e32 v22, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, 0x40400000 :: v_dual_add_nc_u32 v7, v5, v7
	v_and_b32_e32 v2, 0xfffffe00, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s8, v22
	v_sub_nc_u32_e32 v8, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v5, 0x40400000 :: v_dual_add_nc_u32 v2, s8, v8
	v_cmpx_lt_i32_e32 -1, v7
	s_cbranch_execz .LBB5_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0x201, v7, v[2:3]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v15, 0, v6 :: v_dual_mov_b32 v6, 4.0
.LBB5_3:
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v7, s8, v22
	v_mad_i32_i24 v9, 0x201, v22, v8
	v_add_nc_u32_e32 v21, s8, v2
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v11, v7, 9, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_i32_i24 v12, 0x201, v22, v21
	v_add_nc_u32_e32 v16, v11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v23, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v24, vcc_lo, s7, v13, vcc_lo
	s_clause 0x2
	global_load_b32 v18, v[16:17], off
	global_load_b32 v13, v[9:10], off
	global_load_b32 v10, v[23:24], off
	v_subrev_nc_u32_e32 v9, s8, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v9
	s_cbranch_execz .LBB5_5
; %bb.4:
	v_add_nc_u32_e32 v16, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s6, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
	global_load_b32 v5, v[16:17], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v20, 0, v5 :: v_dual_mov_b32 v5, 4.0
.LBB5_5:
	s_or_b32 exec_lo, exec_lo, s10
	v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v7, s8, v7
	v_add_nc_u32_e32 v14, s9, v8
	v_mul_i32_i24_e32 v17, 0x201, v22
	v_mov_b32_e32 v9, 0x40400000
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v16, v7, 9, v7
	v_mov_b32_e32 v7, 0x40400000
	v_add_nc_u32_e32 v19, s8, v14
	s_mov_b32 s10, exec_lo
	v_add_nc_u32_e32 v23, v16, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s6, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s7, v24, vcc_lo
	global_load_b32 v24, v[23:24], off
	v_mov_b32_e32 v23, 0
	v_cmpx_gt_i32_e32 0x201, v19
	s_cbranch_execz .LBB5_7
; %bb.6:
	v_add_nc_u32_e32 v25, v11, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, s6, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v26, vcc_lo
	global_load_b32 v9, v[25:26], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v23, 0, v9
	v_mov_b32_e32 v9, 4.0
.LBB5_7:
	s_or_b32 exec_lo, exec_lo, s10
	v_subrev_nc_u32_e32 v19, s8, v14
	v_add_nc_u32_e32 v25, v17, v14
	v_add_nc_u32_e32 v27, v16, v14
	v_add_nc_u32_e32 v22, s9, v22
	s_mov_b32 s9, exec_lo
	v_add_nc_u32_e32 v29, v19, v11
	v_ashrrev_i32_e32 v26, 31, v25
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v31, vcc_lo, s6, v25
	v_add_co_ci_u32_e32 v32, vcc_lo, s7, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, s6, v29
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v30, vcc_lo
	v_add_co_u32 v27, vcc_lo, s6, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v28, vcc_lo
	s_clause 0x2
	global_load_b32 v25, v[25:26], off
	global_load_b32 v19, v[31:32], off
	global_load_b32 v16, v[27:28], off
	v_add_nc_u32_e32 v26, s8, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v26
	s_cbranch_execz .LBB5_9
; %bb.8:
	v_mad_u64_u32 v[27:28], null, 0x201, v26, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[26:27], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, s6, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
	global_load_b32 v7, v[26:27], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v12, 0, v7 :: v_dual_mov_b32 v7, 4.0
.LBB5_9:
	s_or_b32 exec_lo, exec_lo, s9
	v_lshl_add_u32 v36, v22, 9, v22
	v_subrev_nc_u32_e32 v22, s8, v22
	s_load_b128 s[8:11], s[2:3], 0x18
	v_lshlrev_b64 v[30:31], 2, v[3:4]
	v_mad_i64_i32 v[34:35], null, v3, 48, s[4:5]
	s_waitcnt vmcnt(6)
	v_dual_add_f32 v15, v15, v18 :: v_dual_add_nc_u32 v26, v36, v8
	v_mad_u64_u32 v[28:29], null, 0x201, v22, v[2:3]
	v_add_f32_e32 v22, v18, v20
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v27, 31, v26
	v_add_nc_u32_e32 v20, v36, v21
	v_add_nc_u32_e32 v14, v11, v14
	s_load_b64 s[4:5], s[0:1], 0x4
	s_waitcnt vmcnt(5)
	v_add_f32_e32 v22, v13, v22
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_ashrrev_i32_e32 v21, 31, v20
	s_mov_b32 s3, 0x41200000
	s_waitcnt vmcnt(3)
	v_add_f32_e32 v22, v24, v22
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v26, vcc_lo, s6, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s7, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v28, vcc_lo, s6, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s7, v29, vcc_lo
	v_add_co_u32 v20, vcc_lo, s6, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v21, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v32, vcc_lo, s8, v30
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v31, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v30
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v31, vcc_lo
	s_clause 0x2
	global_load_b32 v24, v[28:29], off
	global_load_b32 v37, v[26:27], off
	global_load_b32 v38, v[20:21], off
	global_store_b32 v[32:33], v22, off
	global_store_b32 v[3:4], v22, off
	s_clause 0x4
	global_load_b128 v[26:29], v[34:35], off offset:24
	global_load_b64 v[20:21], v[34:35], off offset:40
	global_load_b128 v[30:33], v[34:35], off offset:4
	global_load_b32 v39, v[34:35], off offset:20
	global_load_b32 v40, v[34:35], off
	s_waitcnt vmcnt(10)
	v_dual_add_f32 v4, v23, v25 :: v_dual_add_nc_u32 v3, v17, v2
	v_add_nc_u32_e32 v17, v11, v8
	v_dual_add_f32 v11, v15, v13 :: v_dual_add_nc_u32 v2, v36, v2
	v_div_scale_f32 v36, null, v5, v5, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v18, 31, v17
	v_ashrrev_i32_e32 v15, 31, v14
	v_bfe_u32 v23, v0, 10, 10
	v_rcp_f32_e32 v45, v36
	s_waitcnt vmcnt(9)
	v_add_f32_e32 v8, v4, v19
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_f32_e32 v19, v11, v10
	v_lshlrev_b64 v[13:14], 2, v[14:15]
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt vmcnt(8)
	v_add_f32_e32 v8, v8, v16
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_lshlrev_b64 v[16:17], 2, v[17:18]
	v_div_scale_f32 v4, null, v6, v6, v19
	v_ashrrev_i32_e32 v3, 31, v2
	v_div_scale_f32 v42, null, v9, v9, v8
	v_add_co_u32 v10, s2, s6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s2, s7, v11, s2
	v_add_co_u32 v15, s2, s6, v16
	v_add_co_ci_u32_e64 v16, s2, s7, v17, s2
	v_add_co_u32 v13, s2, s6, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
	s_lshr_b32 s2, s4, 16
	v_rcp_f32_e32 v44, v4
	s_mul_i32 s2, s2, s5
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_mul_lo_u32 v1, s2, v1
	v_rcp_f32_e32 v46, v42
	v_mul_u32_u24_e32 v23, s5, v23
	v_div_scale_f32 v25, vcc_lo, v19, v6, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_add_co_u32 v17, s2, s6, v2
	v_fma_f32 v2, -v4, v44, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_add3_u32 v0, v1, v23, v0
	v_add_co_ci_u32_e64 v18, s2, s7, v3, s2
	v_fma_f32 v47, -v42, v46, 1.0
	v_fma_f32 v3, -v36, v45, 1.0
	v_div_scale_f32 v41, s0, v22, v5, v22
	v_div_scale_f32 v43, s1, v8, v9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v45, v3, v45
	v_mul_lo_u32 v0, v0, 20
	v_mul_f32_e32 v3, v41, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v49, -v36, v3, v41
	s_waitcnt vmcnt(7)
	v_dual_fmac_f32 v3, v49, v45 :: v_dual_add_f32 v12, v12, v24
	s_waitcnt vmcnt(4)
	v_lshrrev_b32_e32 v1, 2, v26
	v_lshrrev_b32_e32 v51, 2, v27
	s_waitcnt vmcnt(2)
	ds_store_2addr_b32 v0, v30, v31 offset1:1
	ds_store_2addr_b32 v0, v32, v33 offset0:2 offset1:3
	s_waitcnt vmcnt(1)
	ds_store_b32 v0, v39 offset:16
	v_xor_b32_e32 v1, v1, v26
	v_fmac_f32_e32 v44, v2, v44
	v_lshlrev_b32_e32 v26, 4, v20
	v_xor_b32_e32 v24, v51, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v46, v47, v46 :: v_dual_lshlrev_b32 v47, 1, v1
	v_mul_f32_e32 v2, v25, v44
	v_fma_f32 v27, -v36, v3, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v26, v47, v26
	v_fma_f32 v48, -v4, v2, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v1, v26, v1, v20
	v_fmac_f32_e32 v2, v48, v44
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v26, 4, v1
	v_fma_f32 v4, -v4, v2, v25
	v_lshlrev_b32_e32 v25, 1, v24
	v_mul_f32_e32 v23, v43, v46
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v4, v4, v44, v2
	v_xor_b32_e32 v25, v25, v26
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v50, -v42, v23, v43
	v_div_fmas_f32 v3, v27, v45, v3
	s_mov_b32 vcc_lo, s1
	v_xor3_b32 v2, v25, v24, v1
	v_div_fixup_f32 v6, v4, v6, v19
	v_fmac_f32_e32 v23, v50, v46
	v_div_fixup_f32 v5, v3, v5, v22
	v_lshrrev_b32_e32 v3, 2, v29
	v_dual_add_f32 v12, v12, v37 :: v_dual_lshlrev_b32 v27, 4, v2
	v_lshrrev_b32_e32 v37, 2, v28
	v_fma_f32 v36, -v42, v23, v43
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v19, v3, v29
	ds_load_b32 v29, v0 offset:16
	v_add_f32_e32 v12, v12, v38
	v_xor_b32_e32 v26, v37, v28
	v_div_fmas_f32 v23, v36, v46, v23
	v_div_scale_f32 v28, null, v7, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v24, 1, v26
	v_div_fixup_f32 v8, v23, v9, v8
	v_div_scale_f32 v22, vcc_lo, v12, v7, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v25, v28
	v_xor_b32_e32 v4, v24, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_xor3_b32 v3, v4, v26, v2
	v_lshlrev_b32_e32 v4, 1, v19
	s_waitcnt vmcnt(0)
	v_add3_u32 v26, v40, v2, 0xb0f8a
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v28, v25, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v25, v9, v25
	v_lshlrev_b32_e32 v9, 4, v3
	v_mul_f32_e32 v23, v22, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v4, v4, v9
	v_add3_u32 v9, v40, v1, 0x587c5
	v_fma_f32 v27, -v28, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor3_b32 v4, v4, v19, v3
	v_add3_u32 v19, v40, v3, 0x10974f
	v_cvt_f32_u32_e32 v0, v9
	v_cvt_f32_u32_e32 v9, v26
	v_fmac_f32_e32 v23, v27, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_u32_e32 v19, v19
	v_fmaak_f32 v9, 0x2f800000, v9, 0x2f800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v22, -v28, v23, v22
	v_fmaak_f32 v19, 0x2f800000, v19, 0x2f800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v9, s3, v9, 0xc0a00000
	v_div_fmas_f32 v22, v22, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v7, v22, v7, v12
	v_fmaak_f32 v12, s3, v19, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v9, v5, v9 :: v_dual_add_nc_u32 v24, 0x161f14, v40
	v_dual_mov_b32 v5, v21 :: v_dual_add_f32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v26, v4, v24
	v_cvt_f32_u32_e32 v26, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v23, 0x2f800000, v26, 0x2f800000
	v_fmaak_f32 v19, s3, v23, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000 :: v_dual_add_f32 v7, v7, v19
	v_dual_fmaak_f32 v25, s3, v0, 0xc0a00000 :: v_dual_mov_b32 v0, v20
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v25
	s_clause 0x3
	global_store_b32 v[10:11], v6, off
	global_store_b32 v[15:16], v9, off
	global_store_b32 v[13:14], v8, off
	global_store_b32 v[17:18], v7, off
	s_clause 0x1
	global_store_b32 v[34:35], v24, off
	global_store_b128 v[34:35], v[30:33], off offset:4
	s_waitcnt lgkmcnt(0)
	s_clause 0x2
	global_store_b32 v[34:35], v29, off offset:20
	global_store_b128 v[34:35], v[0:3], off offset:24
	global_store_b64 v[34:35], v[4:5], off offset:40
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB5_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9Diamond_2P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 52
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z9Diamond_2P12hiprandStatePfiS1_S1_, .Lfunc_end5-_Z9Diamond_2P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2648
; NumSgprs: 18
; NumVgprs: 52
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 52
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z9Diamond_3P12hiprandStatePfiS1_S1_ ; -- Begin function _Z9Diamond_3P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_3P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z9Diamond_3P12hiprandStatePfiS1_S1_,@function
_Z9Diamond_3P12hiprandStatePfiS1_S1_:   ; @_Z9Diamond_3P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v2
	s_cbranch_execz .LBB6_10
; %bb.1:
	s_load_b32 s4, s[2:3], 0x10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_lshr_b32 s8, s4, 31
	s_lshr_b32 s7, s7, 23
	s_add_i32 s8, s4, s8
	s_mul_i32 s9, s7, s6
	s_ashr_i32 s8, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_add_i32 s10, s7, 1
	s_sub_i32 s11, s9, s6
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s7, s10, s7
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s7, 1
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s6, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	s_sub_i32 s5, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s7, s5, 31
	s_mul_i32 s6, s5, s5
	s_add_i32 s9, s5, s7
	v_cvt_f32_u32_e32 v3, s6
	s_xor_b32 s9, s9, s7
	s_sub_i32 s10, 0, s6
	v_cvt_f32_u32_e32 v4, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v5, v3
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s10, v5
	v_add_nc_u32_e32 v7, v2, v3
	s_sub_i32 s10, 0, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v3
	v_mul_hi_u32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, s10, v4
	v_mul_hi_u32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v4, v6
	v_mul_lo_u32 v8, v5, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v6, v7, v8
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v4, v7, v4
	v_subrev_nc_u32_e32 v9, s6, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v6, v6, v9 :: v_dual_cndmask_b32 v5, v5, v8
	v_mul_lo_u32 v9, v4, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v7, v9
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_add_nc_u32_e32 v7, 1, v4
	v_xor_b32_e32 v9, s7, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v8, s9, v6
	v_xor_b32_e32 v5, v5, v3
	v_cmp_le_u32_e32 vcc_lo, s9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v5, v3
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_ashrrev_i32_e32 v7, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, 1, v4
	v_cmp_le_u32_e32 vcc_lo, s9, v6
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v7, 30, v7
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v5, v7
	v_xor_b32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, -4, v6
	v_sub_nc_u32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, v4, s5
	v_mul_lo_u32 v9, v4, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b16 v7, 7, v5
	v_and_b32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v2, v6
	v_add_nc_u16 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s4
	s_load_b128 s[4:7], s[2:3], 0x0
	v_and_b32_e32 v8, 0xfe, v7
	v_bfe_i32 v7, v7, 0, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v6
	v_sub_nc_u16 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i16 v7, 1, v7
	v_ashrrev_i32_e32 v8, 31, v9
	v_lshrrev_b32_e32 v4, 23, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v5, v5, 0, 8
	v_bfe_i32 v7, v7, 0, 16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v8, 23, v8
	v_add_nc_u32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, 1, v5
	v_mul_lo_u32 v7, s8, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v8, v9, v8
	v_and_b32_e32 v4, 0xfffffe00, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, s8
	v_sub_nc_u32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0xfffffe00, v8
	v_mov_b32_e32 v8, 0
	v_add3_u32 v4, v7, v4, v10
	v_mul_lo_u32 v10, s8, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v9, v6
	v_subrev_nc_u32_e32 v5, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v10, v6, v7
	v_mov_b32_e32 v6, 0
	v_cmpx_lt_i32_e32 -1, v5
	s_cbranch_execz .LBB6_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x201, v7, v[5:6]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[8:9]
	v_mov_b32_e32 v8, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, 0, v5
.LBB6_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v5, s8, v4
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v5
	s_cbranch_execz .LBB6_5
; %bb.4:
	v_mad_u64_u32 v[9:10], null, 0x201, v7, v[5:6]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB6_5:
	s_or_b32 exec_lo, exec_lo, s9
	v_subrev_nc_u32_e32 v5, s8, v7
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v5
	s_cbranch_execz .LBB6_7
; %bb.6:
	v_mad_u64_u32 v[9:10], null, 0x201, v5, v[4:5]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB6_7:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v5, s8, v7
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v5
	s_cbranch_execz .LBB6_9
; %bb.8:
	v_mad_u64_u32 v[9:10], null, 0x201, v5, v[4:5]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB6_9:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b128 s[8:11], s[2:3], 0x18
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[17:18], null, v2, 48, s[4:5]
	v_cvt_f32_i32_e32 v5, v4
	v_cvt_f32_i32_e32 v11, v7
	v_cvt_f32_ubyte0_e32 v22, v8
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v24, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, v22, v22, v6
	v_rcp_f32_e32 v23, v8
	v_add_co_u32 v2, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[9:10], v11, off
	s_clause 0x4
	global_load_b128 v[9:12], v[17:18], off offset:24
	global_load_b64 v[19:20], v[17:18], off offset:40
	global_load_b32 v5, v[17:18], off
	global_load_b128 v[13:16], v[17:18], off offset:4
	global_load_b32 v21, v[17:18], off offset:20
	v_fma_f32 v3, -v8, v23, 1.0
	s_mul_i32 s0, s0, s1
	v_div_scale_f32 v25, vcc_lo, v6, v22, v6
	v_mul_lo_u32 v1, s0, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v23, v3, v23
	s_mov_b32 s0, 0x41200000
	s_waitcnt vmcnt(4)
	v_lshrrev_b32_e32 v2, 2, v9
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v26, 4, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v2, v9
	s_waitcnt vmcnt(2)
	v_mad_u64_u32 v[2:3], null, 0x201, v7, v[4:5]
	v_mul_f32_e32 v7, v25, v23
	v_lshlrev_b32_e32 v27, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v27, v26
	v_fma_f32 v26, -v8, v7, v25
	v_add_nc_u32_e32 v27, 0x587c5, v5
	v_mul_u32_u24_e32 v5, s1, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor3_b32 v4, v3, v9, v19
	v_ashrrev_i32_e32 v3, 31, v2
	v_fmac_f32_e32 v7, v26, v23
	v_add3_u32 v5, v1, v5, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v9, v4, v27
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v2, -v8, v7, v25
	v_mul_lo_u32 v5, v5, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v5, v13, v14 offset1:1
	ds_store_2addr_b32 v5, v15, v16 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v21 offset:16
	v_cvt_f32_u32_e32 v3, v9
	v_div_fmas_f32 v2, v2, v23, v7
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_div_fixup_f32 v1, v2, v22, v6
	v_dual_mov_b32 v0, v10 :: v_dual_mov_b32 v5, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v2, s0, v3, 0xc0a00000 :: v_dual_mov_b32 v3, v19
	v_dual_add_f32 v6, v1, v2 :: v_dual_mov_b32 v1, v11
	v_mov_b32_e32 v2, v12
	global_store_b32 v[7:8], v6, off
	s_clause 0x4
	global_store_b32 v[17:18], v27, off
	global_store_b128 v[17:18], v[13:16], off offset:4
	global_store_b32 v[17:18], v21, off offset:20
	global_store_b128 v[17:18], v[0:3], off offset:24
	global_store_b64 v[17:18], v[4:5], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB6_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9Diamond_3P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z9Diamond_3P12hiprandStatePfiS1_S1_, .Lfunc_end6-_Z9Diamond_3P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1736
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_ ; -- Begin function _Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
	.globl	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_,@function
_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_: ; @_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v14, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[14:15]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x40401, v1
	s_cbranch_execz .LBB7_10
; %bb.1:
	s_load_b32 s9, s[2:3], 0x10
	s_load_b64 s[0:1], s[0:1], 0x4
	s_load_b128 s[12:15], s[2:3], 0x18
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s9, 31
	s_lshr_b32 s8, s0, 16
	s_add_i32 s5, s9, s4
	s_lshr_b32 s0, s9, 31
	s_xor_b32 s5, s5, s4
	s_add_i32 s0, s9, s0
	v_cvt_f32_u32_e32 v2, s5
	s_sub_i32 s7, 0, s5
	s_ashr_i32 s0, s0, 1
	s_mul_i32 s8, s8, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s6, s7
	s_add_i32 s6, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s6, s6, 23
	s_mul_i32 s7, s6, s5
	s_add_i32 s10, s6, 1
	s_sub_i32 s7, 0x200, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s11, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s10, s6
	s_cselect_b32 s7, s11, s7
	s_add_i32 s10, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s5, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s4
	s_sub_i32 s4, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s5, s4, 31
	s_add_i32 s6, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	v_cvt_f32_u32_e32 v2, s6
	s_sub_i32 s7, 0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v3, v2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s7, v3
	v_add_nc_u32_e32 v5, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v2
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_hi_u32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v3, s6
	v_sub_nc_u32_e32 v4, v5, v4
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s6, v4
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v4, v4, v6
	v_xor_b32_e32 v6, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_xor_b32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v6
	v_mul_lo_u32 v4, v3, s4
	v_mul_lo_u32 v5, v3, s9
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s2, 0x41200000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v1, v4
	v_ashrrev_i32_e32 v3, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, s9
	v_lshrrev_b32_e32 v3, 23, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v5, v3
	v_ashrrev_i32_e32 v6, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v7, 0xfffffe00, v3
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_lshrrev_b32_e32 v6, 23, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v42, v5, v7
	v_add_nc_u32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s12, v2
	v_add_nc_u32_e32 v32, s0, v42
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0xfffffe00, v6
	v_add_co_u32 v9, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v3, vcc_lo
	v_sub_nc_u32_e32 v24, v4, v6
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[5:6], null, v1, 48, s[4:5]
	v_cvt_f32_i32_e32 v2, v32
	v_add_nc_u32_e32 v31, s9, v42
	v_add_nc_u32_e32 v13, s0, v24
	v_mad_i32_i24 v15, 0x201, v42, v24
	v_add_nc_u32_e32 v26, s9, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshl_add_u32 v25, v31, 9, v31
	v_cvt_f32_i32_e32 v1, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v16, 31, v15
	global_store_b32 v[7:8], v1, off
	global_store_b32 v[9:10], v2, off
	s_clause 0x2
	global_load_b128 v[1:4], v[5:6], off offset:24
	global_load_b64 v[11:12], v[5:6], off offset:40
	global_load_b32 v22, v[5:6], off
	v_add_nc_u32_e32 v17, v25, v24
	v_mad_i32_i24 v19, 0x201, v42, v26
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_nc_u32_e32 v27, v25, v26
	s_clause 0x1
	global_load_b128 v[38:41], v[5:6], off offset:4
	global_load_b32 v43, v[5:6], off offset:20
	v_ashrrev_i32_e32 v18, 31, v17
	v_ashrrev_i32_e32 v20, 31, v19
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_lshlrev_b64 v[33:34], 2, v[19:20]
	v_add_co_u32 v20, vcc_lo, s6, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[35:36], 2, v[27:28]
	s_waitcnt vmcnt(4)
	v_lshrrev_b32_e32 v21, 2, v1
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v15, 4, v11
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v23, 0x587c5, v22
	v_dual_mov_b32 v27, v2 :: v_dual_mov_b32 v28, v3
	v_xor_b32_e32 v1, v21, v1
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v16, vcc_lo
	v_add_co_u32 v16, vcc_lo, s6, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v19, 1, v1
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v18, vcc_lo
	v_add_co_u32 v18, vcc_lo, s6, v33
	v_xor_b32_e32 v15, v19, v15
	v_dual_mov_b32 v29, v4 :: v_dual_mov_b32 v30, v11
	v_add_co_ci_u32_e32 v19, vcc_lo, s7, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_xor3_b32 v1, v15, v1, v11
	s_clause 0x2
	global_store_b32 v[5:6], v23, off
	global_store_b128 v[5:6], v[27:30], off offset:24
	global_store_b32 v[5:6], v1, off offset:40
	s_clause 0x1
	global_load_b32 v15, v[20:21], off
	global_load_b32 v29, v[18:19], off
	v_add_co_u32 v27, vcc_lo, s6, v35
	v_add_co_ci_u32_e32 v28, vcc_lo, s7, v36, vcc_lo
	s_clause 0x1
	global_load_b32 v30, v[16:17], off
	global_load_b32 v33, v[27:28], off
	v_bfe_u32 v27, v0, 10, 10
	v_mul_lo_u32 v35, s8, v14
	v_lshl_add_u32 v28, v32, 9, v32
	v_bfe_u32 v34, v0, 20, 10
	v_add_nc_u32_e32 v37, v1, v23
	v_mul_u32_u24_e32 v27, s1, v27
	v_mov_b32_e32 v0, 0x40400000
	v_dual_mov_b32 v36, 0 :: v_dual_mov_b32 v23, 0x40400000
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add3_u32 v27, v35, v27, v34
	v_cvt_f32_u32_e32 v34, v37
	v_mov_b32_e32 v37, 0
	v_mul_lo_u32 v27, v27, 20
	s_delay_alu instid0(VALU_DEP_3)
	v_fmaak_f32 v35, 0x2f800000, v34, 0x2f800000
	v_mul_i32_i24_e32 v34, 0x201, v42
	s_waitcnt vmcnt(5)
	ds_store_2addr_b32 v27, v38, v39 offset1:1
	ds_store_2addr_b32 v27, v40, v41 offset0:2 offset1:3
	s_waitcnt vmcnt(4)
	ds_store_b32 v27, v43 offset:16
	v_fmaak_f32 v35, s2, v35, 0xc0a00000
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v29, v15, v29
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f32_e32 v30, v29, v30
	v_add_nc_u32_e32 v14, v28, v13
	v_subrev_nc_u32_e32 v29, s0, v42
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v30, v30, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_fmamk_f32 v30, v30, 0x3e800000, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_store_b32 v[14:15], v30, off
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_lt_i32_e32 -1, v29
	s_cbranch_execz .LBB7_3
; %bb.2:
	v_mad_u64_u32 v[37:38], null, 0x201, v29, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v38, 31, v37
	v_lshlrev_b64 v[29:30], 2, v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s6, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s7, v30, vcc_lo
	global_load_b32 v23, v[29:30], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v37, 0, v23
	v_mov_b32_e32 v23, 4.0
.LBB7_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v39, s0, v13
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v29, v39, v34
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_add_co_u32 v29, vcc_lo, s6, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v30, vcc_lo, s7, v30, vcc_lo
	s_clause 0x2
	global_load_b32 v29, v[29:30], off
	global_load_b32 v38, v[14:15], off
	global_load_b32 v30, v[20:21], off
	v_subrev_nc_u32_e32 v14, s0, v24
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v14
	s_cbranch_execz .LBB7_5
; %bb.4:
	v_add_nc_u32_e32 v14, v28, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v0, v[14:15], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v36, 0, v0
	v_mov_b32_e32 v0, 4.0
.LBB7_5:
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v21, 0x40400000 :: v_dual_add_nc_u32 v14, s0, v32
	v_dual_mov_b32 v20, 0x40400000 :: v_dual_add_nc_u32 v41, s0, v26
	v_mov_b32_e32 v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v35, v14, 9, v14
	v_mov_b32_e32 v40, 0
	s_mov_b32 s1, exec_lo
	v_add_nc_u32_e32 v14, v35, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s6, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
	global_load_b32 v33, v[14:15], off
	v_add_co_u32 v14, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v6, vcc_lo
	v_cmpx_gt_i32_e32 0x201, v41
	s_cbranch_execz .LBB7_7
; %bb.6:
	v_add_nc_u32_e32 v40, v28, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v41, 31, v40
	v_lshlrev_b64 v[40:41], 2, v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v40, vcc_lo, s6, v40
	v_add_co_ci_u32_e32 v41, vcc_lo, s7, v41, vcc_lo
	global_load_b32 v21, v[40:41], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v40, 0, v21 :: v_dual_mov_b32 v21, 4.0
.LBB7_7:
	s_or_b32 exec_lo, exec_lo, s1
	v_subrev_nc_u32_e32 v42, s0, v26
	v_add_nc_u32_e32 v41, v35, v26
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v43, v42, v28
	v_ashrrev_i32_e32 v42, 31, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v44, 31, v43
	v_lshlrev_b64 v[41:42], 2, v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[43:44], 2, v[43:44]
	v_add_co_u32 v41, vcc_lo, s6, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v42, vcc_lo, s7, v42, vcc_lo
	v_add_co_u32 v43, vcc_lo, s6, v43
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v44, vcc_lo, s7, v44, vcc_lo
	s_clause 0x2
	global_load_b32 v35, v[41:42], off
	global_load_b32 v41, v[43:44], off
	global_load_b32 v18, v[18:19], off
	v_add_nc_u32_e32 v19, s0, v31
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v19
	s_cbranch_execz .LBB7_9
; %bb.8:
	v_mad_u64_u32 v[42:43], null, 0x201, v19, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v43, 31, v42
	v_lshlrev_b64 v[19:20], 2, v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, s6, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
	global_load_b32 v19, v[19:20], off
	v_mov_b32_e32 v20, 4.0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v32, 0, v19
.LBB7_9:
	s_or_b32 exec_lo, exec_lo, s1
	v_subrev_nc_u32_e32 v19, s0, v31
	v_add_nc_u32_e32 v44, v25, v39
	v_lshrrev_b32_e32 v48, 2, v11
	v_lshrrev_b32_e32 v47, 2, v4
	v_lshrrev_b32_e32 v46, 2, v3
	v_mad_u64_u32 v[42:43], null, 0x201, v19, v[13:14]
	v_ashrrev_i32_e32 v45, 31, v44
	s_waitcnt vmcnt(5)
	v_dual_add_f32 v19, v38, v36 :: v_dual_add_nc_u32 v26, v28, v26
	v_add_nc_u32_e32 v24, v28, v24
	v_xor_b32_e32 v11, v48, v11
	v_lshlrev_b64 v[44:45], 2, v[44:45]
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v19, v30, v19
	v_ashrrev_i32_e32 v43, 31, v42
	v_xor_b32_e32 v4, v47, v4
	s_mov_b32 s3, 0x41200000
	v_lshlrev_b32_e32 v47, 1, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[42:43], 2, v[42:43]
	v_add_co_u32 v42, vcc_lo, s6, v42
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, s7, v43, vcc_lo
	v_add_co_u32 v44, vcc_lo, s6, v44
	v_add_co_ci_u32_e32 v45, vcc_lo, s7, v45, vcc_lo
	s_clause 0x2
	global_load_b32 v31, v[42:43], off
	global_load_b32 v42, v[44:45], off
	global_load_b32 v43, v[16:17], off
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v17, v40, v41
	v_dual_add_f32 v41, v37, v38 :: v_dual_add_nc_u32 v16, v34, v13
	v_lshrrev_b32_e32 v44, 2, v2
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_add_f32 v18, v17, v18 :: v_dual_lshlrev_b32 v45, 4, v1
	v_add_nc_u32_e32 v40, v25, v13
	v_add_f32_e32 v28, v41, v30
	v_xor_b32_e32 v30, v44, v2
	v_ashrrev_i32_e32 v17, 31, v16
	v_add_f32_e32 v35, v18, v35
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_add_f32 v28, v28, v29 :: v_dual_add_nc_u32 v49, 0x1ba6d9, v22
	v_ashrrev_i32_e32 v25, 31, v24
	v_ashrrev_i32_e32 v41, 31, v40
	v_lshlrev_b32_e32 v29, 1, v30
	v_div_scale_f32 v50, null, v21, v21, v35
	v_xor_b32_e32 v34, v46, v3
	v_lshlrev_b64 v[2:3], 2, v[16:17]
	ds_load_b32 v13, v27 offset:16
	ds_load_2addr_b32 v[38:39], v27 offset0:2 offset1:3
	ds_load_2addr_b32 v[36:37], v27 offset1:1
	v_ashrrev_i32_e32 v27, 31, v26
	v_dual_add_f32 v33, v33, v19 :: v_dual_lshlrev_b32 v44, 1, v34
	v_lshlrev_b64 v[16:17], 2, v[24:25]
	v_lshlrev_b64 v[24:25], 2, v[40:41]
	v_xor_b32_e32 v29, v29, v45
	v_div_scale_f32 v40, null, v23, v23, v28
	v_rcp_f32_e32 v52, v50
	v_lshlrev_b64 v[18:19], 2, v[26:27]
	v_div_scale_f32 v45, null, v0, v0, v33
	v_add_co_u32 v26, s2, s6, v2
	v_xor3_b32 v2, v29, v30, v1
	v_rcp_f32_e32 v29, v40
	v_add_co_ci_u32_e64 v27, s2, s7, v3, s2
	v_rcp_f32_e32 v30, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_add3_u32 v3, v22, v2, 0xb0f8a
	v_fma_f32 v55, -v50, v52, 1.0
	v_lshlrev_b32_e32 v53, 4, v2
	v_lshlrev_b32_e32 v46, 1, v4
	v_div_scale_f32 v41, vcc_lo, v28, v23, v28
	v_cvt_f32_u32_e32 v3, v3
	v_fmac_f32_e32 v52, v55, v52
	v_xor_b32_e32 v44, v44, v53
	v_fma_f32 v53, -v40, v29, 1.0
	v_fma_f32 v54, -v45, v30, 1.0
	v_div_scale_f32 v48, s0, v33, v0, v33
	v_div_scale_f32 v51, s1, v35, v21, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v29, v53, v29 :: v_dual_fmac_f32 v30, v54, v30
	v_add_co_u32 v16, s2, s6, v16
	v_add_co_ci_u32_e64 v17, s2, s7, v17, s2
	v_add_co_u32 v18, s2, s6, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v19, s2, s7, v19, s2
	v_add_co_u32 v24, s2, s6, v24
	v_add_co_ci_u32_e64 v25, s2, s7, v25, s2
	global_store_b32 v[7:8], v33, off
	v_mul_f32_e32 v53, v51, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v57, -v50, v53, v51
	v_fmac_f32_e32 v53, v57, v52
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v31, v32, v31
	v_fmaak_f32 v32, 0x2f800000, v3, 0x2f800000
	v_xor3_b32 v3, v44, v34, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v44, v48, v30 :: v_dual_add_f32 v31, v31, v43
	v_dual_fmaak_f32 v32, s3, v32, 0xc0a00000 :: v_dual_lshlrev_b32 v43, 4, v3
	v_add3_u32 v34, v22, v3, 0x10974f
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v55, -v45, v44, v48
	v_dual_add_f32 v31, v31, v42 :: v_dual_mul_f32 v42, v41, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v43, v46, v43
	v_cvt_f32_u32_e32 v34, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v46, -v40, v42, v41
	v_xor3_b32 v4, v43, v4, v3
	v_fmac_f32_e32 v44, v55, v30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v34, 0x2f800000, v34, 0x2f800000
	v_fmac_f32_e32 v42, v46, v29
	v_div_scale_f32 v54, null, v20, v20, v31
	v_lshlrev_b32_e32 v43, 4, v4
	v_add3_u32 v22, v22, v4, 0x161f14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v40, -v40, v42, v41
	v_rcp_f32_e32 v56, v54
	v_fma_f32 v45, -v45, v44, v48
	v_xor_b32_e32 v41, v47, v43
	v_div_scale_f32 v43, s2, v31, v20, v31
	v_div_fmas_f32 v29, v40, v29, v42
	v_cvt_f32_u32_e32 v22, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
	v_xor3_b32 v11, v41, v11, v4
	s_mov_b32 vcc_lo, s0
	v_fma_f32 v46, -v54, v56, 1.0
	v_div_fixup_f32 v23, v29, v23, v28
	v_div_fmas_f32 v30, v45, v30, v44
	s_mov_b32 vcc_lo, s1
	v_fmaak_f32 v22, 0x2f800000, v22, 0x2f800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v56, v46, v56 :: v_dual_add_f32 v7, v32, v23
	v_fmaak_f32 v34, s3, v34, 0xc0a00000
	v_fma_f32 v46, -v50, v53, v51
	v_div_fixup_f32 v0, v30, v0, v33
	v_dual_mul_f32 v41, v43, v56 :: v_dual_fmaak_f32 v22, s3, v22, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v0, v34, v0
	v_fma_f32 v42, -v54, v41, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v41, v42, v56 :: v_dual_add_nc_u32 v40, v11, v49
	v_cvt_f32_u32_e32 v40, v40
	v_div_fmas_f32 v42, v46, v52, v53
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v43, -v54, v41, v43
	v_fmaak_f32 v28, 0x2f800000, v40, 0x2f800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v21, v42, v21, v35
	v_div_fmas_f32 v29, v43, v56, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v28, s3, v28, 0xc0a00000
	v_add_f32_e32 v8, v22, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v20, v29, v20, v31
	v_add_f32_e32 v20, v28, v20
	global_store_b32 v[9:10], v33, off
	s_clause 0x3
	global_store_b32 v[26:27], v7, off
	global_store_b32 v[16:17], v0, off
	global_store_b32 v[18:19], v8, off
	global_store_b32 v[24:25], v20, off
	s_waitcnt lgkmcnt(2)
	s_clause 0x2
	global_store_b32 v[14:15], v13, off offset:16
	global_store_b32 v[5:6], v49, off
	global_store_b128 v[5:6], v[1:4], off offset:24
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b128 v[14:15], v[36:39], off
	global_store_b64 v[5:6], v[11:12], off offset:40
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB7_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 58
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_, .Lfunc_end7-_Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2932
; NumSgprs: 18
; NumVgprs: 58
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 58
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z8Square_6P12hiprandStatePfiS1_S1_ ; -- Begin function _Z8Square_6P12hiprandStatePfiS1_S1_
	.globl	_Z8Square_6P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z8Square_6P12hiprandStatePfiS1_S1_,@function
_Z8Square_6P12hiprandStatePfiS1_S1_:    ; @_Z8Square_6P12hiprandStatePfiS1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s3, s4, 31
	s_and_b32 s2, s2, 0xffff
	s_add_i32 s5, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s3
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s7, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s6, s7
	s_add_i32 s6, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s6, s6, 23
	s_mul_i32 s7, s6, s5
	s_add_i32 s8, s6, 1
	s_sub_i32 s7, 0x200, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s9, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s8, s6
	s_cselect_b32 s7, s9, s7
	s_add_i32 s8, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s2, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s3
	s_sub_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s2, s2
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_ashr_i32 s3, s2, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s5, s2, s3
	s_load_b128 s[8:11], s[0:1], 0x18
	s_xor_b32 s5, s5, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	v_xor_b32_e32 v4, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s6, v0
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v0, s5
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s5, v3
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v3, v3, v5
	v_xor_b32_e32 v5, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s5, v3
	s_lshr_b32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s4, s5
	s_ashr_i32 s5, s5, 1
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v0, s2
	v_mul_lo_u32 v0, v0, s4
	s_load_b128 s[0:3], s[0:1], 0x0
	v_sub_nc_u32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, v3, s4
	v_ashrrev_i32_e32 v3, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 23, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[7:8], null, v1, 48, s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v0, v3
	s_mov_b32 s0, 0x41200000
	v_lshrrev_b32_e32 v5, 23, v5
	v_and_b32_e32 v6, 0xfffffe00, v3
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, v4, v5
	v_sub_nc_u32_e32 v10, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, 0xfffffe00, v5
	v_add_nc_u32_e32 v17, s5, v10
	v_add_nc_u32_e32 v9, s4, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, v4, v5
	v_add_co_u32 v4, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
	v_add_nc_u32_e32 v6, s5, v11
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f32_i32_e32 v0, v6
	v_cvt_f32_i32_e32 v1, v17
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[2:3], v1, off
	s_clause 0x2
	global_load_b128 v[0:3], v[7:8], off offset:24
	global_load_b32 v4, v[7:8], off offset:40
	global_load_b32 v5, v[7:8], off
	v_lshl_add_u32 v12, v9, 9, v9
	v_add_nc_u32_e32 v14, s4, v11
	v_mad_i32_i24 v9, 0x201, v10, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v11, v12, v11
	v_mad_i32_i24 v13, 0x201, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_nc_u32_e32 v15, v12, v14
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	v_add_co_u32 v11, vcc_lo, s2, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s2, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v18, 2, v0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 0x587c5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v18, v0
	v_lshlrev_b32_e32 v18, 4, v4
	v_lshlrev_b32_e32 v19, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v18, v19, v18
	v_xor3_b32 v18, v18, v0, v4
	v_add_co_u32 v0, vcc_lo, s2, v15
	s_clause 0x2
	global_store_b32 v[7:8], v5, off
	global_store_b128 v[7:8], v[1:4], off offset:24
	global_store_b32 v[7:8], v18, off offset:40
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v16, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[9:10], off
	global_load_b32 v3, v[13:14], off
	global_load_b32 v4, v[11:12], off
	global_load_b32 v7, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, 0x201, v17, v[6:7]
	v_add_nc_u32_e32 v1, v18, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v4
	v_cvt_f32_u32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_dual_add_f32 v2, v2, v7 :: v_dual_fmaak_f32 v3, 0x2f800000, v5, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fmaak_f32 v3, s0, v3, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmamk_f32 v2, v2, 0x3e800000, v3
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB8_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Square_6P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z8Square_6P12hiprandStatePfiS1_S1_, .Lfunc_end8-_Z8Square_6P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1036
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9Diamond_6P12hiprandStatePfiS1_S1_ ; -- Begin function _Z9Diamond_6P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_6P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z9Diamond_6P12hiprandStatePfiS1_S1_,@function
_Z9Diamond_6P12hiprandStatePfiS1_S1_:   ; @_Z9Diamond_6P12hiprandStatePfiS1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[2:3], 0x10
	s_load_b32 s5, s[2:3], 0x34
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s6, s4, 31
	s_and_b32 s5, s5, 0xffff
	s_add_i32 s7, s4, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s6
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s9, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v1
	v_and_b32_e32 v1, 0x3ff, v0
	s_mul_i32 s9, s9, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
	s_mul_hi_u32 s9, s8, s9
	s_add_i32 s8, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s8, s8, 23
	s_mul_i32 s9, s8, s7
	s_add_i32 s10, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s11, s9, s7
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s8, s10, s8
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s8, 1
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s7, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s7, s6
	s_sub_i32 s5, s5, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s6, s5, s5
	s_lshl_b32 s7, s6, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s7, v2
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB9_10
; %bb.1:
	s_ashr_i32 s7, s5, 31
	v_cvt_f32_u32_e32 v3, s6
	s_add_i32 s8, s5, s7
	s_sub_i32 s9, 0, s6
	s_xor_b32 s8, s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	v_cvt_f32_u32_e32 v4, s8
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_mul_f32 v4, 0x4f7ffffe, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_u32_f32_e32 v5, v3
	v_ashrrev_i32_e32 v3, 31, v2
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, s9, v5
	v_add_nc_u32_e32 v7, v2, v3
	s_sub_i32 s9, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v3
	v_mul_hi_u32 v6, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, s9, v4
	s_mov_b32 s9, exec_lo
	v_mul_hi_u32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v4, v6
	v_mul_lo_u32 v8, v5, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_sub_nc_u32_e32 v6, v7, v8
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	v_subrev_nc_u32_e32 v9, s6, v6
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_mul_hi_u32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_add_nc_u32_e32 v8, 1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s6, v6
	v_mul_lo_u32 v9, v4, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v6, v7, v9
	v_add_nc_u32_e32 v7, 1, v4
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_xor_b32_e32 v9, s7, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v6
	v_subrev_nc_u32_e32 v8, s8, v6
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_xor_b32_e32 v5, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_add_nc_u32_e32 v8, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v5, v5, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v5
	v_cndmask_b32_e32 v4, v4, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 30, v7
	v_xor_b32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v5, v7
	v_sub_nc_u32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, -4, v6
	v_mul_lo_u32 v9, v4, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, v4, s5
	s_lshr_b32 s5, s4, 31
	v_lshrrev_b16 v7, 7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v2, v6
	v_and_b32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, s4
	v_add_nc_u16 v7, v5, v7
	s_add_i32 s4, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_ashr_i32 s8, s4, 1
	s_load_b128 s[4:7], s[2:3], 0x0
	v_and_b32_e32 v8, 0xfe, v7
	v_bfe_i32 v7, v7, 0, 8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v6
	v_sub_nc_u16 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i16 v7, 1, v7
	v_lshrrev_b32_e32 v4, 23, v4
	v_ashrrev_i32_e32 v8, 31, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v5, v5, 0, 8
	v_bfe_i32 v7, v7, 0, 16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, v6, v4
	v_lshrrev_b32_e32 v8, 23, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, 1, v5
	v_mul_lo_u32 v7, s8, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v4, 0xfffffe00, v4
	v_add_nc_u32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v10, s8
	v_sub_nc_u32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0xfffffe00, v8
	v_mov_b32_e32 v8, 0
	v_add3_u32 v4, v7, v4, v10
	v_mul_lo_u32 v10, s8, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v9, v6
	v_subrev_nc_u32_e32 v5, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v10, v6, v7
	v_mov_b32_e32 v6, 0
	v_cmpx_lt_i32_e32 -1, v5
	s_cbranch_execz .LBB9_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x201, v7, v[5:6]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[8:9]
	v_mov_b32_e32 v8, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, 0, v5
.LBB9_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v5, s8, v4
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v5
	s_cbranch_execz .LBB9_5
; %bb.4:
	v_mad_u64_u32 v[9:10], null, 0x201, v7, v[5:6]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB9_5:
	s_or_b32 exec_lo, exec_lo, s9
	v_subrev_nc_u32_e32 v5, s8, v7
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v5
	s_cbranch_execz .LBB9_7
; %bb.6:
	v_mad_u64_u32 v[9:10], null, 0x201, v5, v[4:5]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB9_7:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v5, s8, v7
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v5
	s_cbranch_execz .LBB9_9
; %bb.8:
	v_mad_u64_u32 v[9:10], null, 0x201, v5, v[4:5]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	global_load_b32 v5, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v5
.LBB9_9:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b128 s[8:11], s[2:3], 0x18
	v_lshlrev_b64 v[9:10], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[17:18], null, v2, 48, s[4:5]
	v_cvt_f32_i32_e32 v5, v4
	v_cvt_f32_i32_e32 v11, v7
	v_cvt_f32_ubyte0_e32 v22, v8
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v24, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, v22, v22, v6
	v_rcp_f32_e32 v23, v8
	v_add_co_u32 v2, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[9:10], v11, off
	s_clause 0x4
	global_load_b128 v[9:12], v[17:18], off offset:24
	global_load_b64 v[19:20], v[17:18], off offset:40
	global_load_b32 v5, v[17:18], off
	global_load_b128 v[13:16], v[17:18], off offset:4
	global_load_b32 v21, v[17:18], off offset:20
	v_fma_f32 v3, -v8, v23, 1.0
	s_mul_i32 s0, s0, s1
	v_div_scale_f32 v25, vcc_lo, v6, v22, v6
	v_mul_lo_u32 v1, s0, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v23, v3, v23
	s_mov_b32 s0, 0x41200000
	s_waitcnt vmcnt(4)
	v_lshrrev_b32_e32 v2, 2, v9
	s_waitcnt vmcnt(3)
	v_lshlrev_b32_e32 v26, 4, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v2, v9
	s_waitcnt vmcnt(2)
	v_mad_u64_u32 v[2:3], null, 0x201, v7, v[4:5]
	v_mul_f32_e32 v7, v25, v23
	v_lshlrev_b32_e32 v27, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v27, v26
	v_fma_f32 v26, -v8, v7, v25
	v_add_nc_u32_e32 v27, 0x587c5, v5
	v_mul_u32_u24_e32 v5, s1, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_xor3_b32 v4, v3, v9, v19
	v_ashrrev_i32_e32 v3, 31, v2
	v_fmac_f32_e32 v7, v26, v23
	v_add3_u32 v5, v1, v5, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v9, v4, v27
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v2, -v8, v7, v25
	v_mul_lo_u32 v5, v5, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v5, v13, v14 offset1:1
	ds_store_2addr_b32 v5, v15, v16 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v21 offset:16
	v_cvt_f32_u32_e32 v3, v9
	v_div_fmas_f32 v2, v2, v23, v7
	v_add_co_u32 v7, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000
	v_div_fixup_f32 v1, v2, v22, v6
	v_dual_mov_b32 v0, v10 :: v_dual_mov_b32 v5, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v2, s0, v3, 0xc0a00000 :: v_dual_mov_b32 v3, v19
	v_dual_add_f32 v6, v1, v2 :: v_dual_mov_b32 v1, v11
	v_mov_b32_e32 v2, v12
	global_store_b32 v[7:8], v6, off
	s_clause 0x4
	global_store_b32 v[17:18], v27, off
	global_store_b128 v[17:18], v[13:16], off offset:4
	global_store_b32 v[17:18], v21, off offset:20
	global_store_b128 v[17:18], v[0:3], off offset:24
	global_store_b64 v[17:18], v[4:5], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB9_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9Diamond_6P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z9Diamond_6P12hiprandStatePfiS1_S1_, .Lfunc_end9-_Z9Diamond_6P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1732
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z8Square_8P12hiprandStatePfiS1_S1_ ; -- Begin function _Z8Square_8P12hiprandStatePfiS1_S1_
	.globl	_Z8Square_8P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z8Square_8P12hiprandStatePfiS1_S1_,@function
_Z8Square_8P12hiprandStatePfiS1_S1_:    ; @_Z8Square_8P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 0x201, v2
	s_cbranch_execz .LBB10_2
; %bb.1:
	s_load_b32 s8, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s8, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s5, 0, s3
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s4
	s_mul_hi_u32 s5, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_lshr_b32 s5, s8, 31
	s_lshr_b32 s4, s4, 23
	s_add_i32 s5, s8, s5
	s_mul_i32 s6, s4, s3
	s_ashr_i32 s9, s5, 1
	s_sub_i32 s5, 0x200, s6
	s_add_i32 s6, s4, 1
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_add_i32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s3
	v_cvt_f32_u32_e32 v2, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v4, v2
	v_mad_u64_u32 v[2:3], null, 0x201, v1, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s5, v4
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v4, v0
	v_add_nc_u32_e32 v1, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v1, v1, v3
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v4, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v4
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v1
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
	v_xor_b32_e32 v5, s3, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	s_load_b128 s[4:7], s[0:1], 0x18
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s2
	v_mul_lo_u32 v4, v0, s8
	s_load_b128 s[0:3], s[0:1], 0x0
	v_sub_nc_u32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v4
	v_mul_lo_u32 v5, v1, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 23, v0
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v5
	v_and_b32_e32 v6, 0xfffffe00, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v1, 23, v1
	v_sub_nc_u32_e32 v9, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v5, v1
	v_add_nc_u32_e32 v16, s9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v7, 0xfffffe00, v1
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_cvt_f32_i32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, v5, v7
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[6:7], null, v2, 48, s[0:1]
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, s9, v10
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_cvt_f32_i32_e32 v2, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[3:4], v2, off
	global_store_b32 v[0:1], v8, off
	s_clause 0x2
	global_load_b128 v[0:3], v[6:7], off offset:24
	global_load_b32 v4, v[6:7], off offset:40
	global_load_b32 v17, v[6:7], off
	v_add_nc_u32_e32 v8, s8, v9
	v_add_nc_u32_e32 v13, s8, v10
	s_mov_b32 s0, 0x41200000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v11, v8, 9, v8
	v_mad_i32_i24 v8, 0x201, v9, v10
	v_mad_i32_i24 v12, 0x201, v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v11, v10
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v18, 2, v0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, 0x587c5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v18, v0
	v_lshlrev_b32_e32 v18, 4, v4
	v_lshlrev_b32_e32 v19, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v18, v19, v18
	v_xor3_b32 v18, v18, v0, v4
	v_add_co_u32 v0, vcc_lo, s2, v14
	s_clause 0x2
	global_store_b32 v[6:7], v17, off
	global_store_b128 v[6:7], v[1:4], off offset:24
	global_store_b32 v[6:7], v18, off offset:40
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v15, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[8:9], off
	global_load_b32 v3, v[12:13], off
	global_load_b32 v4, v[10:11], off
	global_load_b32 v6, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, 0x201, v16, v[5:6]
	v_add_nc_u32_e32 v1, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v4
	v_cvt_f32_u32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v6
	v_ashrrev_i32_e32 v1, 31, v0
	v_fmaak_f32 v3, 0x2f800000, v5, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fmaak_f32 v3, s0, v3, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmamk_f32 v2, v2, 0x3e800000, v3
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB10_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Square_8P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z8Square_8P12hiprandStatePfiS1_S1_, .Lfunc_end10-_Z8Square_8P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1096
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9Diamond_8P12hiprandStatePfiS1_S1_ ; -- Begin function _Z9Diamond_8P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_8P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z9Diamond_8P12hiprandStatePfiS1_S1_,@function
_Z9Diamond_8P12hiprandStatePfiS1_S1_:   ; @_Z9Diamond_8P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[6:7], null, s15, s5, v[1:2]
	s_mov_b32 s4, exec_lo
	v_max_i32_e32 v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v3
	s_cbranch_execz .LBB11_10
; %bb.1:
	s_load_b32 s4, s[2:3], 0x10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_lshr_b32 s8, s4, 31
	s_lshr_b32 s7, s7, 23
	s_add_i32 s8, s4, s8
	s_mul_i32 s9, s7, s6
	s_ashr_i32 s8, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_add_i32 s10, s7, 1
	s_sub_i32 s11, s9, s6
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s7, s10, s7
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s7, 1
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s6, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	s_sub_i32 s5, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s6, s5, s5
	s_ashr_i32 s7, s5, 31
	v_cvt_f32_u32_e32 v3, s6
	s_add_i32 s9, s5, s7
	s_sub_i32 s10, 0, s6
	s_xor_b32 s9, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v7, s9
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v8, v3
	v_mad_u64_u32 v[3:4], null, 0x201, v6, v[5:6]
	v_rcp_iflag_f32_e32 v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s10, v8
	s_sub_i32 s10, 0, s9
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_hi_u32 v6, v8, v6
	v_add_nc_u32_e32 v7, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v5
	v_xor_b32_e32 v7, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v8, v6
	v_mul_lo_u32 v8, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v7, v6
	v_mul_hi_u32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v6, s6
	v_add_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v7, v9
	v_add_nc_u32_e32 v9, 1, v6
	v_subrev_nc_u32_e32 v10, s6, v8
	v_cmp_le_u32_e32 vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_mul_hi_u32 v5, v7, v5
	v_xor_b32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v5, s9
	v_add_nc_u32_e32 v8, 1, v5
	v_sub_nc_u32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v10
	v_xor_b32_e32 v10, s7, v4
	v_subrev_nc_u32_e32 v9, s9, v7
	v_cmp_le_u32_e32 vcc_lo, s9, v7
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_ashrrev_i32_e32 v8, 31, v6
	v_add_nc_u32_e32 v9, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s9, v7
	v_lshrrev_b32_e32 v8, 30, v8
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	v_add_nc_u32_e32 v7, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v10
	v_and_b32_e32 v7, -4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v10
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v5, s5
	v_lshrrev_b16 v8, 7, v6
	v_mul_lo_u32 v10, v5, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v8, 1, v8
	v_sub_nc_u32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v8, v6, v8
	v_mul_lo_u32 v7, v7, s4
	s_load_b128 s[4:7], s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v9, 0xfe, v8
	v_bfe_i32 v8, v8, 0, 8
	v_ashrrev_i32_e32 v5, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v6, v6, v9
	v_ashrrev_i16 v8, 1, v8
	v_ashrrev_i32_e32 v9, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 23, v5
	v_bfe_i32 v6, v6, 0, 8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v8, v8, 0, 16
	v_lshrrev_b32_e32 v9, 23, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v7, v5
	v_sub_nc_u32_e32 v11, 1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, s8, v8
	v_add_nc_u32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v5, 0xfffffe00, v5
	v_mul_lo_u32 v11, v11, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v5, v7, v5
	v_and_b32_e32 v7, 0xfffffe00, v9
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v5, v8, v5, v11
	v_mul_lo_u32 v11, s8, v6
	v_sub_nc_u32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s8, v5
	v_add3_u32 v8, v11, v7, v8
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB11_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0x201, v8, v[6:7]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[9:10]
	v_mov_b32_e32 v9, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, 0, v6
.LBB11_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v6, s8, v5
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v6
	s_cbranch_execz .LBB11_5
; %bb.4:
	v_mad_u64_u32 v[10:11], null, 0x201, v8, v[6:7]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB11_5:
	s_or_b32 exec_lo, exec_lo, s9
	v_subrev_nc_u32_e32 v6, s8, v8
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB11_7
; %bb.6:
	v_mad_u64_u32 v[10:11], null, 0x201, v6, v[5:6]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB11_7:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v6, s8, v8
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v6
	s_cbranch_execz .LBB11_9
; %bb.8:
	v_mad_u64_u32 v[10:11], null, 0x201, v6, v[5:6]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB11_9:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b128 s[8:11], s[2:3], 0x18
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[18:19], null, v3, 48, s[4:5]
	v_cvt_f32_i32_e32 v6, v5
	v_cvt_f32_i32_e32 v12, v8
	v_cvt_f32_ubyte0_e32 v21, v9
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v22, null, v21, v21, v7
	v_rcp_f32_e32 v23, v22
	v_add_co_u32 v3, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	global_store_b32 v[3:4], v6, off
	global_store_b32 v[10:11], v12, off
	s_clause 0x4
	global_load_b128 v[10:13], v[18:19], off offset:24
	global_load_b64 v[3:4], v[18:19], off offset:40
	global_load_b32 v6, v[18:19], off
	global_load_b128 v[14:17], v[18:19], off offset:4
	global_load_b32 v20, v[18:19], off offset:20
	v_div_scale_f32 v26, vcc_lo, v7, v21, v7
	v_fmac_f32_e32 v23, v24, v23
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v1, s1, v1
	s_mul_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s0, v2
	s_mov_b32 s0, 0x41200000
	v_add3_u32 v2, v2, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v14, v15 offset1:1
	ds_store_2addr_b32 v2, v16, v17 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v20 offset:16
	v_lshrrev_b32_e32 v9, 2, v10
	v_lshlrev_b32_e32 v24, 4, v3
	v_mov_b32_e32 v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v25, v9, v10
	v_mad_u64_u32 v[9:10], null, 0x201, v8, v[5:6]
	v_lshlrev_b32_e32 v27, 1, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_xor_b32_e32 v5, v27, v24
	v_add_nc_u32_e32 v27, 0x587c5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[9:10]
	v_xor3_b32 v5, v5, v25, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v27
	v_cvt_f32_u32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v6, 0x2f800000, v6, 0x2f800000
	v_mul_f32_e32 v8, v26, v23
	v_fmaak_f32 v6, s0, v6, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v22, v8, v26
	v_fmac_f32_e32 v8, v24, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v22, v8, v26
	v_div_fmas_f32 v10, v9, v23, v8
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v10, v21, v7
	v_dual_mov_b32 v0, v11 :: v_dual_add_f32 v7, v1, v6
	v_mov_b32_e32 v1, v12
	v_mov_b32_e32 v6, v4
	global_store_b32 v[8:9], v7, off
	s_clause 0x4
	global_store_b32 v[18:19], v27, off
	global_store_b128 v[18:19], v[14:17], off offset:4
	global_store_b32 v[18:19], v20, off offset:20
	global_store_b128 v[18:19], v[0:3], off offset:24
	global_store_b64 v[18:19], v[5:6], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB11_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9Diamond_8P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z9Diamond_8P12hiprandStatePfiS1_S1_, .Lfunc_end11-_Z9Diamond_8P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1764
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z8Square_9P12hiprandStatePfiS1_S1_ ; -- Begin function _Z8Square_9P12hiprandStatePfiS1_S1_
	.globl	_Z8Square_9P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z8Square_9P12hiprandStatePfiS1_S1_,@function
_Z8Square_9P12hiprandStatePfiS1_S1_:    ; @_Z8Square_9P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v0, v1
	v_cmpx_gt_i32_e32 0x201, v2
	s_cbranch_execz .LBB12_2
; %bb.1:
	s_load_b32 s8, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s8, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, s3
	s_sub_i32 s5, 0, s3
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_readfirstlane_b32 s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s5, s5, s4
	s_mul_hi_u32 s5, s4, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s4, s4, s5
	s_lshr_b32 s5, s8, 31
	s_lshr_b32 s4, s4, 23
	s_add_i32 s5, s8, s5
	s_mul_i32 s6, s4, s3
	s_ashr_i32 s9, s5, 1
	s_sub_i32 s5, 0x200, s6
	s_add_i32 s6, s4, 1
	s_sub_i32 s7, s5, s3
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s4, s6, s4
	s_cselect_b32 s5, s7, s5
	s_add_i32 s6, s4, 1
	s_cmp_ge_u32 s5, s3
	s_cselect_b32 s3, s6, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	s_sub_i32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_add_i32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s4, s4, s3
	v_cvt_f32_u32_e32 v2, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v4, v2
	v_mad_u64_u32 v[2:3], null, 0x201, v1, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, s5, v4
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v0, v4, v0
	v_add_nc_u32_e32 v1, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v1, v1, v3
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v1, v0
	v_mul_lo_u32 v4, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v4
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v1
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
	v_xor_b32_e32 v5, s3, v3
	v_add_nc_u32_e32 v4, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s4, v1
	s_load_b128 s[4:7], s[0:1], 0x18
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s2
	v_mul_lo_u32 v4, v0, s8
	s_load_b128 s[0:3], s[0:1], 0x0
	v_sub_nc_u32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v0, 31, v4
	v_mul_lo_u32 v5, v1, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 23, v0
	v_add_nc_u32_e32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v5
	v_and_b32_e32 v6, 0xfffffe00, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v1, 23, v1
	v_sub_nc_u32_e32 v9, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v5, v1
	v_add_nc_u32_e32 v16, s9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v7, 0xfffffe00, v1
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_cvt_f32_i32_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v10, v5, v7
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[6:7], null, v2, 48, s[0:1]
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, s9, v10
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_cvt_f32_i32_e32 v2, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[3:4], v2, off
	global_store_b32 v[0:1], v8, off
	s_clause 0x2
	global_load_b128 v[0:3], v[6:7], off offset:24
	global_load_b32 v4, v[6:7], off offset:40
	global_load_b32 v17, v[6:7], off
	v_add_nc_u32_e32 v8, s8, v9
	v_add_nc_u32_e32 v13, s8, v10
	s_mov_b32 s0, 0x41200000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v11, v8, 9, v8
	v_mad_i32_i24 v8, 0x201, v9, v10
	v_mad_i32_i24 v12, 0x201, v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v11, v10
	v_ashrrev_i32_e32 v9, 31, v8
	v_add_nc_u32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt vmcnt(2)
	v_lshrrev_b32_e32 v18, 2, v0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v17, 0x587c5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v18, v0
	v_lshlrev_b32_e32 v18, 4, v4
	v_lshlrev_b32_e32 v19, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v18, v19, v18
	v_xor3_b32 v18, v18, v0, v4
	v_add_co_u32 v0, vcc_lo, s2, v14
	s_clause 0x2
	global_store_b32 v[6:7], v17, off
	global_store_b128 v[6:7], v[1:4], off offset:24
	global_store_b32 v[6:7], v18, off offset:40
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v15, vcc_lo
	s_clause 0x3
	global_load_b32 v2, v[8:9], off
	global_load_b32 v3, v[12:13], off
	global_load_b32 v4, v[10:11], off
	global_load_b32 v6, v[0:1], off
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v2, v2, v3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, 0x201, v16, v[5:6]
	v_add_nc_u32_e32 v1, v18, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v2, v4
	v_cvt_f32_u32_e32 v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v6
	v_ashrrev_i32_e32 v1, 31, v0
	v_fmaak_f32 v3, 0x2f800000, v5, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_fmaak_f32 v3, s0, v3, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_fmamk_f32 v2, v2, 0x3e800000, v3
	global_store_b32 v[0:1], v2, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB12_2:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8Square_9P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z8Square_9P12hiprandStatePfiS1_S1_, .Lfunc_end12-_Z8Square_9P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1096
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9Diamond_9P12hiprandStatePfiS1_S1_ ; -- Begin function _Z9Diamond_9P12hiprandStatePfiS1_S1_
	.globl	_Z9Diamond_9P12hiprandStatePfiS1_S1_
	.p2align	8
	.type	_Z9Diamond_9P12hiprandStatePfiS1_S1_,@function
_Z9Diamond_9P12hiprandStatePfiS1_S1_:   ; @_Z9Diamond_9P12hiprandStatePfiS1_S1_
; %bb.0:
	s_load_b32 s4, s[2:3], 0x34
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[6:7], null, s15, s5, v[1:2]
	s_mov_b32 s4, exec_lo
	v_max_i32_e32 v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v3
	s_cbranch_execz .LBB13_10
; %bb.1:
	s_load_b32 s4, s[2:3], 0x10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s4, s5
	s_xor_b32 s6, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s6
	s_sub_i32 s8, 0, s6
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_lshr_b32 s8, s4, 31
	s_lshr_b32 s7, s7, 23
	s_add_i32 s8, s4, s8
	s_mul_i32 s9, s7, s6
	s_ashr_i32 s8, s8, 1
	s_sub_i32 s9, 0x200, s9
	s_add_i32 s10, s7, 1
	s_sub_i32 s11, s9, s6
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s7, s10, s7
	s_cselect_b32 s9, s11, s9
	s_add_i32 s10, s7, 1
	s_cmp_ge_u32 s9, s6
	s_cselect_b32 s6, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s5
	s_sub_i32 s5, s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s6, s5, s5
	s_ashr_i32 s7, s5, 31
	v_cvt_f32_u32_e32 v3, s6
	s_add_i32 s9, s5, s7
	s_sub_i32 s10, 0, s6
	s_xor_b32 s9, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v7, s9
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v8, v3
	v_mad_u64_u32 v[3:4], null, 0x201, v6, v[5:6]
	v_rcp_iflag_f32_e32 v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, s10, v8
	s_sub_i32 s10, 0, s9
	v_ashrrev_i32_e32 v4, 31, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_mul_hi_u32 v6, v8, v6
	v_add_nc_u32_e32 v7, v3, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v5, v5
	v_xor_b32_e32 v7, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v8, v6
	v_mul_lo_u32 v8, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v7, v6
	v_mul_hi_u32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v6, s6
	v_add_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v7, v9
	v_add_nc_u32_e32 v9, 1, v6
	v_subrev_nc_u32_e32 v10, s6, v8
	v_cmp_le_u32_e32 vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 1, v6
	v_cmp_le_u32_e32 vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	v_mul_hi_u32 v5, v7, v5
	v_xor_b32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v5, s9
	v_add_nc_u32_e32 v8, 1, v5
	v_sub_nc_u32_e32 v6, v6, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v10
	v_xor_b32_e32 v10, s7, v4
	v_subrev_nc_u32_e32 v9, s9, v7
	v_cmp_le_u32_e32 vcc_lo, s9, v7
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v7, v9, vcc_lo
	v_ashrrev_i32_e32 v8, 31, v6
	v_add_nc_u32_e32 v9, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s9, v7
	v_lshrrev_b32_e32 v8, 30, v8
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	v_add_nc_u32_e32 v7, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v10
	v_and_b32_e32 v7, -4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v10
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v5, s5
	v_lshrrev_b16 v8, 7, v6
	v_mul_lo_u32 v10, v5, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v8, 1, v8
	v_sub_nc_u32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v8, v6, v8
	v_mul_lo_u32 v7, v7, s4
	s_load_b128 s[4:7], s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v9, 0xfe, v8
	v_bfe_i32 v8, v8, 0, 8
	v_ashrrev_i32_e32 v5, 31, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u16 v6, v6, v9
	v_ashrrev_i16 v8, 1, v8
	v_ashrrev_i32_e32 v9, 31, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshrrev_b32_e32 v5, 23, v5
	v_bfe_i32 v6, v6, 0, 8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfe_i32 v8, v8, 0, 16
	v_lshrrev_b32_e32 v9, 23, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v7, v5
	v_sub_nc_u32_e32 v11, 1, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, s8, v8
	v_add_nc_u32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v5, 0xfffffe00, v5
	v_mul_lo_u32 v11, v11, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v5, v7, v5
	v_and_b32_e32 v7, 0xfffffe00, v9
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v5, v8, v5, v11
	v_mul_lo_u32 v11, s8, v6
	v_sub_nc_u32_e32 v7, v10, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s8, v5
	v_add3_u32 v8, v11, v7, v8
	v_mov_b32_e32 v7, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB13_3
; %bb.2:
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0x201, v8, v[6:7]
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[9:10]
	v_mov_b32_e32 v9, 1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s6, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, 0, v6
.LBB13_3:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v6, s8, v5
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v6
	s_cbranch_execz .LBB13_5
; %bb.4:
	v_mad_u64_u32 v[10:11], null, 0x201, v8, v[6:7]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB13_5:
	s_or_b32 exec_lo, exec_lo, s9
	v_subrev_nc_u32_e32 v6, s8, v8
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 -1, v6
	s_cbranch_execz .LBB13_7
; %bb.6:
	v_mad_u64_u32 v[10:11], null, 0x201, v6, v[5:6]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB13_7:
	s_or_b32 exec_lo, exec_lo, s9
	v_add_nc_u32_e32 v6, s8, v8
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x201, v6
	s_cbranch_execz .LBB13_9
; %bb.8:
	v_mad_u64_u32 v[10:11], null, 0x201, v6, v[5:6]
	v_add_nc_u32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	global_load_b32 v6, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v6
.LBB13_9:
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b128 s[8:11], s[2:3], 0x18
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[18:19], null, v3, 48, s[4:5]
	v_cvt_f32_i32_e32 v6, v5
	v_cvt_f32_i32_e32 v12, v8
	v_cvt_f32_ubyte0_e32 v21, v9
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v0, v0, 20, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v22, null, v21, v21, v7
	v_rcp_f32_e32 v23, v22
	v_add_co_u32 v3, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	global_store_b32 v[3:4], v6, off
	global_store_b32 v[10:11], v12, off
	s_clause 0x4
	global_load_b128 v[10:13], v[18:19], off offset:24
	global_load_b64 v[3:4], v[18:19], off offset:40
	global_load_b32 v6, v[18:19], off
	global_load_b128 v[14:17], v[18:19], off offset:4
	global_load_b32 v20, v[18:19], off offset:20
	v_div_scale_f32 v26, vcc_lo, v7, v21, v7
	v_fmac_f32_e32 v23, v24, v23
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v1, s1, v1
	s_mul_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, s0, v2
	s_mov_b32 s0, 0x41200000
	v_add3_u32 v2, v2, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, 20
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v2, v14, v15 offset1:1
	ds_store_2addr_b32 v2, v16, v17 offset0:2 offset1:3
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v20 offset:16
	v_lshrrev_b32_e32 v9, 2, v10
	v_lshlrev_b32_e32 v24, 4, v3
	v_mov_b32_e32 v2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v25, v9, v10
	v_mad_u64_u32 v[9:10], null, 0x201, v8, v[5:6]
	v_lshlrev_b32_e32 v27, 1, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_xor_b32_e32 v5, v27, v24
	v_add_nc_u32_e32 v27, 0x587c5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[9:10]
	v_xor3_b32 v5, v5, v25, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v27
	v_cvt_f32_u32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v6, 0x2f800000, v6, 0x2f800000
	v_mul_f32_e32 v8, v26, v23
	v_fmaak_f32 v6, s0, v6, 0xc0a00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v22, v8, v26
	v_fmac_f32_e32 v8, v24, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v22, v8, v26
	v_div_fmas_f32 v10, v9, v23, v8
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v10, v21, v7
	v_dual_mov_b32 v0, v11 :: v_dual_add_f32 v7, v1, v6
	v_mov_b32_e32 v1, v12
	v_mov_b32_e32 v6, v4
	global_store_b32 v[8:9], v7, off
	s_clause 0x4
	global_store_b32 v[18:19], v27, off
	global_store_b128 v[18:19], v[14:17], off offset:4
	global_store_b32 v[18:19], v20, off offset:20
	global_store_b128 v[18:19], v[0:3], off offset:24
	global_store_b64 v[18:19], v[5:6], off offset:40
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB13_10:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9Diamond_9P12hiprandStatePfiS1_S1_
		.amdhsa_group_segment_fixed_size 20480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	_Z9Diamond_9P12hiprandStatePfiS1_S1_, .Lfunc_end13-_Z9Diamond_9P12hiprandStatePfiS1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1764
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 20480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8Square_1P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8Square_1P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11Diamond_1_1P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11Diamond_1_1P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11Diamond_1_2P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11Diamond_1_2P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11Diamond_1_3P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11Diamond_1_3P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11Diamond_1_4P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11Diamond_1_4P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9Diamond_2P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9Diamond_2P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     52
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9Diamond_3P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9Diamond_3P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16Square_Diamond_4P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16Square_Diamond_4P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     58
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8Square_6P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8Square_6P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9Diamond_6P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9Diamond_6P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8Square_8P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8Square_8P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9Diamond_8P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9Diamond_8P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8Square_9P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8Square_9P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 20480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9Diamond_9P12hiprandStatePfiS1_S1_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9Diamond_9P12hiprandStatePfiS1_S1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
