// fermi

// Avoid mangling of function names
extern "C" {
    __global__ void matmulKernel (int n, int m, int p, float* c, const float* a, const float* b);
}

__global__ void matmulKernel (int n, int m, int p, float* c, const float* a, const float* b) {


    const int ttj = threadIdx.x;
    const int wtj = threadIdx.y;
    const int bj = blockIdx.x;
    const int bi = blockIdx.y;
    
    __shared__ float l_a[2048];
    float sums[16];
    for (int ei = 0; ei < 16; ei++) {
    
        sums[ei] = 0.0;
    }
    for (int l = 0; l < p / 128; l++) {
    
        for (int ei = 0; ei < 16; ei++) {
        
            l_a[32 * wtj + ttj + 128 * ei] = a[32 * wtj + ttj + 128 * l + (ei 
                    + 16 * bi) * (128 * (p / 128))];
        }
        __syncthreads();
        for (int k2 = 0; k2 < p / (p / 128); k2++) {
        
            const float bkj = b[128 * bj + (32 * wtj + ttj) + (l * p / (p / 
                    128) + k2) * m];
            for (int ei = 0; ei < 16; ei++) {
            
                sums[ei] += l_a[k2 + 128 * ei] * bkj;
            }
        }
        __syncthreads();
    }
    for (int ei = 0; ei < 16; ei++) {
    
        c[32 * wtj + ttj + 128 * bj + (ei + 16 * bi) * (128 * (m / 128))] += 
                sums[ei];
    }
}






	.file	"tmpxft_002d0bc6_00000000-6_matmulKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_
	.type	_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_, @function
_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	matmulKernel(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_, .-_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_
	.globl	matmulKernel
	.type	matmulKernel, @function
matmulKernel:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z12matmulKerneliiiPfPKfS1_iiiPfPKfS1_
	.cfi_endproc
.LFE2033:
	.size	matmulKernel, .-matmulKernel
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"matmulKernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	matmulKernel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// fermi

// Avoid mangling of function names
extern "C" {
    __global__ void matmulKernel (int n, int m, int p, float* c, const float* a, const float* b);
}

__global__ void matmulKernel (int n, int m, int p, float* c, const float* a, const float* b) {


    const int ttj = threadIdx.x;
    const int wtj = threadIdx.y;
    const int bj = blockIdx.x;
    const int bi = blockIdx.y;
    
    __shared__ float l_a[2048];
    float sums[16];
    for (int ei = 0; ei < 16; ei++) {
    
        sums[ei] = 0.0;
    }
    for (int l = 0; l < p / 128; l++) {
    
        for (int ei = 0; ei < 16; ei++) {
        
            l_a[32 * wtj + ttj + 128 * ei] = a[32 * wtj + ttj + 128 * l + (ei 
                    + 16 * bi) * (128 * (p / 128))];
        }
        __syncthreads();
        for (int k2 = 0; k2 < p / (p / 128); k2++) {
        
            const float bkj = b[128 * bj + (32 * wtj + ttj) + (l * p / (p / 
                    128) + k2) * m];
            for (int ei = 0; ei < 16; ei++) {
            
                sums[ei] += l_a[k2 + 128 * ei] * bkj;
            }
        }
        __syncthreads();
    }
    for (int ei = 0; ei < 16; ei++) {
    
        c[32 * wtj + ttj + 128 * bj + (ei + 16 * bi) * (128 * (m / 128))] += 
                sums[ei];
    }
}






	.text
	.file	"matmulKernel.hip"
	.globl	__device_stub__matmulKernel     # -- Begin function __device_stub__matmulKernel
	.type	__device_stub__matmulKernel,@function
__device_stub__matmulKernel:            # @__device_stub__matmulKernel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$matmulKernel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__matmulKernel, .Lfunc_end0-__device_stub__matmulKernel
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$matmulKernel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	matmulKernel,@object            # @matmulKernel
	.section	.rodata,"a",@progbits
	.globl	matmulKernel
	.p2align	3, 0x0
matmulKernel:
	.quad	__device_stub__matmulKernel
	.size	matmulKernel, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"matmulKernel"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__matmulKernel
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym matmulKernel
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	matmulKernel            ; -- Begin function matmulKernel
	.globl	matmulKernel
	.p2align	8
	.type	matmulKernel,@function
matmulKernel:                           ; @matmulKernel
; %bb.0:
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr1
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s2
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 16
	v_movreld_b32_e32 v1, 0
	s_cbranch_scc0 .LBB0_1
; %bb.2:                                ; %.preheader62
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x4
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[8:9], s[0:1], 0x20
	v_bfe_u32 v17, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v18, 5, v17
	v_add_nc_u32_e32 v19, v18, v0
	s_waitcnt lgkmcnt(0)
	s_cmpk_gt_i32 s3, 0x7f
	s_cbranch_scc1 .LBB0_4
; %bb.3:                                ; %.preheader62..preheader_crit_edge
	v_add_nc_u32_e32 v20, v18, v0
	s_lshl_b32 s1, s15, 4
	s_mov_b32 s0, 0
	s_branch .LBB0_5
.LBB0_4:
	s_mov_b32 s0, -1
                                        ; implicit-def: $sgpr1
                                        ; implicit-def: $vgpr20
.LBB0_5:                                ; %Flow122
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_16
; %bb.6:                                ; %.preheader61.lr.ph
	s_ashr_i32 s0, s3, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s0, s0, 25
	s_add_i32 s10, s3, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s12, s10, 7
	v_cvt_f32_u32_e32 v20, s12
	s_sub_i32 s1, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v20, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v20, 0x4f7ffffe, v20
	v_cvt_u32_f32_e32 v20, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v20
	v_lshlrev_b32_e32 v20, 2, v0
	s_mul_i32 s1, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v20, v17, 7, v20
	s_mul_hi_u32 s1, s0, s1
	s_add_i32 s13, s0, s1
	s_lshl_b32 s1, s15, 4
	s_mul_hi_u32 s0, s3, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s11, s0, s12
	s_add_i32 s16, s0, 1
	s_sub_i32 s11, s3, s11
	s_sub_i32 s17, s11, s12
	s_cmp_ge_u32 s11, s12
	s_cselect_b32 s0, s16, s0
	s_cselect_b32 s11, s17, s11
	s_add_i32 s16, s0, 1
	s_cmp_ge_u32 s11, s12
	s_mul_i32 s11, s15, s12
	s_cselect_b32 s15, s16, s0
	s_cmp_le_u32 s12, s3
	v_lshl_or_b32 v21, s11, 11, v0
	s_cselect_b32 s0, -1, 0
	v_lshl_add_u32 v0, s14, 7, v19
	v_cndmask_b32_e64 v22, 0, 1, s0
	s_mov_b32 s16, 0
	v_add_nc_u32_e32 v21, v21, v18
	s_and_b32 s17, s10, 0xffffff80
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ne_u32_e64 s0, 1, v22
.LBB0_7:                                ; %.preheader61
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;     Child Loop BB0_11 Depth 2
                                        ;       Child Loop BB0_12 Depth 3
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v17, v21
	s_mov_b32 s10, 0
.LBB0_8:                                ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	v_lshlrev_b64 v[22:23], 2, v[17:18]
	v_add_nc_u32_e32 v17, s17, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v22, vcc_lo, s6, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s7, v23, vcc_lo
	global_load_b32 v18, v[22:23], off
	v_add_nc_u32_e32 v22, s10, v20
	s_addk_i32 s10, 0x200
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s10, 0x2000
	s_waitcnt vmcnt(0)
	ds_store_b32 v22, v18
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_14
; %bb.10:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_7 Depth=1
	s_mul_i32 s10, s16, s3
	s_mov_b32 s20, 0
	s_mul_hi_u32 s11, s10, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s18, s11, s12
	s_sub_i32 s10, s10, s18
	s_add_i32 s18, s11, 1
	s_sub_i32 s19, s10, s12
	s_cmp_ge_u32 s10, s12
	s_cselect_b32 s11, s18, s11
	s_cselect_b32 s10, s19, s10
	s_add_i32 s19, s11, 1
	s_cmp_ge_u32 s10, s12
	s_mov_b32 s18, 0
	s_cselect_b32 s19, s19, s11
.LBB0_11:                               ;   Parent Loop BB0_7 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_12 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_add_i32 s10, s19, s20
	s_mov_b32 s21, s18
	v_mad_u64_u32 v[17:18], null, s10, s2, v[0:1]
	s_mov_b64 s[10:11], 0
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_add_co_u32 v17, vcc_lo, s8, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
	global_load_b32 v17, v[17:18], off
.LBB0_12:                               ;   Parent Loop BB0_7 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v18, s21
	s_mov_b32 m0, s10
	s_addk_i32 s21, 0x200
	v_movrels_b32_e32 v22, v1
	s_add_u32 s10, s10, 1
	ds_load_b32 v18, v18
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, 16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v22, v17, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_movreld_b32_e32 v1, v22
	s_cbranch_scc0 .LBB0_12
; %bb.13:                               ;   in Loop: Header=BB0_11 Depth=2
	s_add_i32 s20, s20, 1
	s_add_i32 s18, s18, 4
	s_cmp_ge_i32 s20, s15
	s_cbranch_scc0 .LBB0_11
.LBB0_14:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_7 Depth=1
	v_add_nc_u32_e32 v21, 0x80, v21
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s12
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_7
; %bb.15:                               ; %Flow121
	v_mov_b32_e32 v20, v19
.LBB0_16:                               ; %.preheader
	s_ashr_i32 s0, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s0, s0, 25
	s_add_i32 s0, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s2, s0, 7
	s_mul_i32 s1, s1, s2
	s_and_b32 s2, s0, 0xffffff80
	s_add_i32 s14, s14, s1
	s_mov_b64 s[0:1], 0
	v_lshl_add_u32 v17, s14, 7, v20
.LBB0_17:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v20, v1
	s_addc_u32 s1, s1, 0
	v_lshlrev_b64 v[18:19], 2, v[17:18]
	s_cmp_eq_u32 s0, 16
	v_add_nc_u32_e32 v17, s2, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s4, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
	global_load_b32 v0, v[18:19], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v20, v0
	global_store_b32 v[18:19], v0, off
	s_cbranch_scc0 .LBB0_17
; %bb.18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel matmulKernel
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	matmulKernel, .Lfunc_end0-matmulKernel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 836
; NumSgprs: 24
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           matmulKernel
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         matmulKernel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
