// inspired by https://devblogs.nvidia.com/efficient-matrix-transpose-cuda-cc/
// TILE_DIM=32, BLOCK_ROWS=8
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
// can be used to transpose non-square 2D arrays
__global__
void transposeNoBankConflicts32x8(float *odata, const float *idata, int xdim, int ydim) {
    __shared__ float tile[32][32 + 1];
    int tilex = blockIdx.x * 32;
    int tiley = blockIdx.y * 32;
    int x = tilex + threadIdx.x;
    int y = tiley + threadIdx.y;

    for (int j = 0; j < 32; j += 8) {
        int index = (y + j) * xdim + x;
        if (index < (xdim*ydim)) {
            tile[threadIdx.y + j][threadIdx.x] = idata[index];
        }
    }

    __syncthreads();
    x = tiley + threadIdx.x; // transpose tiles
    y = tilex + threadIdx.y; // transpose tiles
    if (x >= ydim) return; // output matrix has y columns
    int maxJ = min(32, xdim - y); // output matrix has x rows
    for (int j = 0; j < maxJ; j += 8) {
        int index = (y+j) * ydim + x;
        odata[index] = tile[threadIdx.x][threadIdx.y + j];
    }
}

__global__
void iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNew(float* input,
        float* output, int xDim, int yDim) {
    // assign column to thread
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    // we will process data line by line, but data are stored in
    // columns!
    if (idx >= yDim) return; // only threads with data should continue
    float* line = output + idx; // FIXME rename to sth reasonable

    // adjust gain
    float z = sqrtf(3.f) - 2.f;
    float z1 = 1.0 - z;
    float gain = -(z1 * z1) / z;
    // copy original data
    for (int i = 0; i < xDim; i++) {
        line[i * yDim] = input[(i * yDim) + idx] * gain;
    }
    // prepare some values
    float sum = (line[0] + powf(z, xDim) * line[(xDim - 1) * yDim]) * (1.f + z) / z;
    z1 = z;
    float z2 = powf(z, 2 * xDim - 2);
    float iz = 1.f / z;
    for (int j = 1; j < (xDim - 1); ++j) {
        sum += (z2 + z1) * line[j * yDim];
        z1 *= z;
        z2 *= iz;
    }
    line[0] = sum * z / (1.f - powf(z, 2 * xDim));
    for (int j = 1; j < xDim; ++j) {
        line[j * yDim] += z * line[(j - 1) * yDim];
    }
    line[(xDim - 1) * yDim] *= z / (z - 1.f);
    for (int j = xDim - 2; 0 <= j; --j) {
        line[j * yDim] = z * (line[(j + 1) * yDim] - line[j * yDim]);
    }
}


__global__
void iirConvolve2D_Cardinal_Bspline_3_MirrorOffBound(float* input,
        float* output, size_t xDim, size_t yDim) {
    // assign line to thread
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    if (idy >= yDim) return; // only threads with data should continue
    float* line = output + (idy * xDim);

    // adjust gain
    float z = sqrtf(3.f) - 2.f;
    float z1 = 1.0 - z;
    float gain = -(z1 * z1) / z;

    // copy original data
    for (int i = 0; i < xDim; i++) {
        line[i] = input[i + (idy * xDim)] * gain;
    }
    // prepare some values
    float sum = (line[0] + powf(z, xDim) * line[xDim - 1]) * (1.f + z) / z;
    z1 = z;
    float z2 = powf(z, 2 * xDim - 2);
    float iz = 1.f / z;
    for (int j = 1; j < (xDim - 1); ++j) {
        sum += (z2 + z1) * line[j];
        z1 *= z;
        z2 *= iz;
    }
    line[0] = sum * z / (1.f - powf(z, 2 * xDim));
    for (int j = 1; j < xDim; ++j) {
        line[j] += z * line[j - 1];
    }
    line[xDim - 1] *= z / (z - 1.f);
    for (int j = xDim - 2; 0 <= j; --j) {
        line[j] = z * (line[j + 1] - line[j]);
    }
}

	.file	"tmpxft_003624af_00000000-6_cuda_gpu_iirconvolve.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii
	.type	_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii, @function
_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z28transposeNoBankConflicts32x8PfPKfii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii, .-_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii
	.globl	_Z28transposeNoBankConflicts32x8PfPKfii
	.type	_Z28transposeNoBankConflicts32x8PfPKfii, @function
_Z28transposeNoBankConflicts32x8PfPKfii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z28transposeNoBankConflicts32x8PfPKfiiPfPKfii
	.cfi_endproc
.LFE2033:
	.size	_Z28transposeNoBankConflicts32x8PfPKfii, .-_Z28transposeNoBankConflicts32x8PfPKfii
	.globl	_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii
	.type	_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii, @function
_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii, .-_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii
	.globl	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.type	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, @function
_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z74__device_stub__Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_iiPfS_ii
	.cfi_endproc
.LFE2035:
	.size	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, .-_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.globl	_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm
	.type	_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm, @function
_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm, .-_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm
	.globl	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.type	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, @function
_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z71__device_stub__Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mmPfS_mm
	.cfi_endproc
.LFE2037:
	.size	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, .-_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm"
.LC1:
	.string	"_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii"
.LC2:
	.string	"_Z28transposeNoBankConflicts32x8PfPKfii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28transposeNoBankConflicts32x8PfPKfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// inspired by https://devblogs.nvidia.com/efficient-matrix-transpose-cuda-cc/
// TILE_DIM=32, BLOCK_ROWS=8
// No bank-conflict transpose
// Same as transposeCoalesced except the first tile dimension is padded
// to avoid shared memory bank conflicts.
// can be used to transpose non-square 2D arrays
__global__
void transposeNoBankConflicts32x8(float *odata, const float *idata, int xdim, int ydim) {
    __shared__ float tile[32][32 + 1];
    int tilex = blockIdx.x * 32;
    int tiley = blockIdx.y * 32;
    int x = tilex + threadIdx.x;
    int y = tiley + threadIdx.y;

    for (int j = 0; j < 32; j += 8) {
        int index = (y + j) * xdim + x;
        if (index < (xdim*ydim)) {
            tile[threadIdx.y + j][threadIdx.x] = idata[index];
        }
    }

    __syncthreads();
    x = tiley + threadIdx.x; // transpose tiles
    y = tilex + threadIdx.y; // transpose tiles
    if (x >= ydim) return; // output matrix has y columns
    int maxJ = min(32, xdim - y); // output matrix has x rows
    for (int j = 0; j < maxJ; j += 8) {
        int index = (y+j) * ydim + x;
        odata[index] = tile[threadIdx.x][threadIdx.y + j];
    }
}

__global__
void iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNew(float* input,
        float* output, int xDim, int yDim) {
    // assign column to thread
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    // we will process data line by line, but data are stored in
    // columns!
    if (idx >= yDim) return; // only threads with data should continue
    float* line = output + idx; // FIXME rename to sth reasonable

    // adjust gain
    float z = sqrtf(3.f) - 2.f;
    float z1 = 1.0 - z;
    float gain = -(z1 * z1) / z;
    // copy original data
    for (int i = 0; i < xDim; i++) {
        line[i * yDim] = input[(i * yDim) + idx] * gain;
    }
    // prepare some values
    float sum = (line[0] + powf(z, xDim) * line[(xDim - 1) * yDim]) * (1.f + z) / z;
    z1 = z;
    float z2 = powf(z, 2 * xDim - 2);
    float iz = 1.f / z;
    for (int j = 1; j < (xDim - 1); ++j) {
        sum += (z2 + z1) * line[j * yDim];
        z1 *= z;
        z2 *= iz;
    }
    line[0] = sum * z / (1.f - powf(z, 2 * xDim));
    for (int j = 1; j < xDim; ++j) {
        line[j * yDim] += z * line[(j - 1) * yDim];
    }
    line[(xDim - 1) * yDim] *= z / (z - 1.f);
    for (int j = xDim - 2; 0 <= j; --j) {
        line[j * yDim] = z * (line[(j + 1) * yDim] - line[j * yDim]);
    }
}


__global__
void iirConvolve2D_Cardinal_Bspline_3_MirrorOffBound(float* input,
        float* output, size_t xDim, size_t yDim) {
    // assign line to thread
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    if (idy >= yDim) return; // only threads with data should continue
    float* line = output + (idy * xDim);

    // adjust gain
    float z = sqrtf(3.f) - 2.f;
    float z1 = 1.0 - z;
    float gain = -(z1 * z1) / z;

    // copy original data
    for (int i = 0; i < xDim; i++) {
        line[i] = input[i + (idy * xDim)] * gain;
    }
    // prepare some values
    float sum = (line[0] + powf(z, xDim) * line[xDim - 1]) * (1.f + z) / z;
    z1 = z;
    float z2 = powf(z, 2 * xDim - 2);
    float iz = 1.f / z;
    for (int j = 1; j < (xDim - 1); ++j) {
        sum += (z2 + z1) * line[j];
        z1 *= z;
        z2 *= iz;
    }
    line[0] = sum * z / (1.f - powf(z, 2 * xDim));
    for (int j = 1; j < xDim; ++j) {
        line[j] += z * line[j - 1];
    }
    line[xDim - 1] *= z / (z - 1.f);
    for (int j = xDim - 2; 0 <= j; --j) {
        line[j] = z * (line[j + 1] - line[j]);
    }
}

	.text
	.file	"cuda_gpu_iirconvolve.hip"
	.globl	_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii # -- Begin function _Z43__device_stub__transposeNoBankConflicts32x8PfPKfii
	.type	_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii,@function
_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii: # @_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28transposeNoBankConflicts32x8PfPKfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii, .Lfunc_end0-_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii # -- Begin function _Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.type	_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii,@function
_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii: # @_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, .Lfunc_end1-_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm # -- Begin function _Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.type	_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm,@function
_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm: # @_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, .Lfunc_end2-_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28transposeNoBankConflicts32x8PfPKfii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z28transposeNoBankConflicts32x8PfPKfii,@object # @_Z28transposeNoBankConflicts32x8PfPKfii
	.section	.rodata,"a",@progbits
	.globl	_Z28transposeNoBankConflicts32x8PfPKfii
	.p2align	3, 0x0
_Z28transposeNoBankConflicts32x8PfPKfii:
	.quad	_Z43__device_stub__transposeNoBankConflicts32x8PfPKfii
	.size	_Z28transposeNoBankConflicts32x8PfPKfii, 8

	.type	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii,@object # @_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.globl	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.p2align	3, 0x0
_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii:
	.quad	_Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.size	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, 8

	.type	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm,@object # @_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.globl	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.p2align	3, 0x0
_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm:
	.quad	_Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.size	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z28transposeNoBankConflicts32x8PfPKfii"
	.size	.L__unnamed_1, 40

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii"
	.size	.L__unnamed_2, 61

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm"
	.size	.L__unnamed_3, 58

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z43__device_stub__transposeNoBankConflicts32x8PfPKfii
	.addrsig_sym _Z65__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.addrsig_sym _Z62__device_stub__iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z28transposeNoBankConflicts32x8PfPKfii
	.addrsig_sym _Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.addrsig_sym _Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z28transposeNoBankConflicts32x8PfPKfii ; -- Begin function _Z28transposeNoBankConflicts32x8PfPKfii
	.globl	_Z28transposeNoBankConflicts32x8PfPKfii
	.p2align	8
	.type	_Z28transposeNoBankConflicts32x8PfPKfii,@function
_Z28transposeNoBankConflicts32x8PfPKfii: ; @_Z28transposeNoBankConflicts32x8PfPKfii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s0, s15, 5
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s1, s14, 5
	s_mov_b32 s10, -8
	v_add_nc_u32_e32 v1, s0, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s2, v1
	v_lshlrev_b32_e32 v1, 2, v3
	s_mul_i32 s8, s3, s2
	s_lshl_b32 s9, s2, 3
	v_mad_u32_u24 v4, 0x84, v2, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v0, v3, v0, s1
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v0
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v1, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
.LBB0_3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v4, 0x420, v4
	v_add_nc_u32_e32 v0, s9, v0
	s_add_i32 s10, s10, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s10, 23
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	v_add_nc_u32_e32 v0, s0, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s6, exec_lo
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB0_8
; %bb.5:
	v_add_nc_u32_e32 v1, s1, v2
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, s2, v1
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.6:                                ; %.lr.ph.preheader
	v_mul_lo_u32 v1, s3, v1
	v_lshlrev_b32_e32 v4, 2, v2
	v_min_i32_e32 v2, 32, v0
	s_lshl_b32 s2, s3, 3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u32_u24 v4, 0x84, v3, v4
	v_add3_u32 v0, v3, v1, s0
.LBB0_7:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v3, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s3, s3, 8
	v_add_nc_u32_e32 v4, 32, v4
	v_cmp_ge_i32_e32 vcc_lo, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	s_or_b32 s1, vcc_lo, s1
	v_add_co_u32 v5, s0, s4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s0, s5, v6, s0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[5:6], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_7
.LBB0_8:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28transposeNoBankConflicts32x8PfPKfii
		.amdhsa_group_segment_fixed_size 4224
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z28transposeNoBankConflicts32x8PfPKfii, .Lfunc_end0-_Z28transposeNoBankConflicts32x8PfPKfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 416
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4224 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii ; -- Begin function _Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.globl	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
	.p2align	8
	.type	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii,@function
_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii: ; @_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v4
	s_cbranch_execz .LBB1_14
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v5, 31, v4
	s_cmp_lt_i32 s4, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	s_ashr_i32 s7, s5, 31
	s_mov_b32 s6, s5
	s_mov_b32 s8, s4
	s_lshl_b64 s[6:7], s[6:7], 2
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s8, s8, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s8, 0
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v5, v[8:9], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v5, 0x40bfffff, v5 :: v_dual_add_nc_u32 v4, s5, v4
	global_store_b32 v[6:7], v5, off
	v_add_co_u32 v6, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_cbranch_scc0 .LBB1_3
.LBB1_4:                                ; %._crit_edge
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s1, -1, 0
	s_add_i32 s8, s4, -1
	v_cndmask_b32_e64 v6, 0x3e8930a4, 1.0, s1
	s_mul_i32 s6, s8, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s7, s6, 31
	s_lshl_b64 s[10:11], s[6:7], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v4, v6
	v_frexp_exp_i32_f32_e32 v6, v6
	s_lshl_b32 s7, s4, 1
	s_cmp_lt_i32 s4, 3
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v4, v4, v5
	v_cvt_f32_i32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, 1.0, v4
	v_add_f32_e32 v8, -1.0, v4
	v_add_f32_e32 v10, -1.0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v10
	v_rcp_f32_e32 v7, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v8, v7
	v_mul_f32_e32 v11, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v9, v5, -v11
	v_fmac_f32_e32 v10, v9, v4
	v_add_co_u32 v4, s0, v0, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v5, s0, s11, v1, s0
	v_add_f32_e32 v12, v11, v10
	s_clause 0x1
	global_load_b32 v14, v[0:1], off
	global_load_b32 v15, v[4:5], off
	s_mov_b32 s0, 0x3e76c4e1
	v_sub_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v8, v12 :: v_dual_sub_f32 v10, v11, v10
	v_sub_f32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v12
	v_add_f32_e32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v13, v8
	v_mul_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v9, v7
	v_sub_f32_e32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v8, v8 :: v_dual_sub_f32 v7, v7, v9
	v_fma_f32 v9, v8, v8, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v7, v7
	v_fmac_f32_e32 v9, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v10, v9
	v_fmaak_f32 v12, s0, v11, 0x3e91f4c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v12, v11, v12, 0x3ecccdef
	v_mul_f32_e32 v13, v11, v12
	v_dual_sub_f32 v10, v11, v10 :: v_dual_mul_f32 v17, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v9, v10
	v_fma_f32 v10, v11, v12, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v11, v8, -v17
	v_fmac_f32_e32 v10, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v11, v7
	v_ldexp_f32 v7, v7, 1
	v_add_f32_e32 v12, v13, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v9, v8
	v_ldexp_f32 v8, v8, 1
	v_sub_f32_e32 v13, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v17, v18 :: v_dual_add_f32 v16, 0x3f2aaaaa, v12
	v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, 0xbf2aaaaa, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, 0x31739010, v10
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v12
	v_add_f32_e32 v9, v16, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v11, v9
	v_sub_f32_e32 v12, v16, v9
	v_sub_f32_e32 v16, v11, v17
	v_add_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v12, v11, v9, -v13
	v_sub_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v11, v10
	v_fmac_f32_e32 v12, v16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v13, v12
	v_add_f32_e32 v10, v8, v9
	v_sub_f32_e32 v11, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v13, 0x3f317218, v6 :: v_dual_sub_f32 v8, v10, v8
	v_sub_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, 0x3f317218, v6, -v13
	v_dual_sub_f32 v8, v9, v8 :: v_dual_add_f32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, 0xb102e308, v6
	v_add_f32_e32 v6, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v13, v12 :: v_dual_add_f32 v8, v10, v6
	v_sub_f32_e32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v7, v8 :: v_dual_sub_f32 v10, v8, v10
	v_dual_sub_f32 v12, v12, v13 :: v_dual_sub_f32 v11, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v10
	v_sub_f32_e32 v16, v9, v11
	v_sub_f32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v12, v6 :: v_dual_sub_f32 v7, v7, v16
	v_dual_add_f32 v7, v8, v7 :: v_dual_sub_f32 v8, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v10, v7
	v_sub_f32_e32 v10, v10, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v6, v6, v8 :: v_dual_add_f32 v11, v9, v7
	v_dual_sub_f32 v8, v12, v10 :: v_dual_sub_f32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v6, v6, v8 :: v_dual_sub_f32 v7, v7, v9
	v_cvt_f32_i32_e32 v9, s4
	v_add_f32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v6
	v_sub_f32_e32 v8, v7, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, v7, v9
	v_sub_f32_e32 v8, v6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v9, v7, -v10
	v_cmp_class_f32_e64 vcc_lo, v10, 0x204
	v_dual_fmac_f32 v6, v9, v8 :: v_dual_mul_f32 v9, 0.5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v10, v6
	v_cndmask_b32_e32 v12, v11, v10, vcc_lo
	v_sub_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_sub_f32_e32 v6, v6, v10
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v16, v12, v13
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_trunc_f32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	v_fma_f32 v18, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v19, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v18, 0x32a5705f, v16 :: v_dual_sub_f32 v17, v17, v19
	v_cvt_i32_f32_e32 v11, v19
	v_add_f32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v17, v17
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v17, v11
	v_add_f32_e32 v11, v13, v6
	v_cndmask_b32_e64 v6, 0xbe8930a4, 1.0, s1
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, v12, v9
	v_fma_f32 v11, v10, v11, v10
	v_cndmask_b32_e32 v9, 1.0, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v11, v10, vcc_lo
	v_bfi_b32 v9, 0x7fffffff, v10, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v9, v15
	v_mul_f32_e32 v9, 0x3f3b67ae, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v10, null, 0xbe8930a4, 0xbe8930a4, v9
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_div_scale_f32 v12, vcc_lo, v9, 0xbe8930a4, v9
	v_mul_f32_e32 v13, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v10, v13, v12
	v_fmac_f32_e32 v13, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v10, v13, v12
	v_div_fmas_f32 v10, v10, v11, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v9, v10, 0xbe8930a4, v9
	s_cbranch_scc1 .LBB1_7
; %bb.5:                                ; %.lr.ph93.preheader
	s_add_i32 s1, s7, -2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s1, 0
	s_cselect_b32 s10, -1, 0
	s_add_i32 s9, s4, -2
	v_cndmask_b32_e64 v10, 0x3e8930a4, 1.0, s10
	v_frexp_mant_f32_e32 v11, v10
	v_frexp_exp_i32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v11
	v_cndmask_b32_e64 v12, 0, 1, vcc_lo
	v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f32 v11, v11, v12
	v_cvt_f32_i32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, -1.0, v11
	v_add_f32_e32 v12, 1.0, v11
	v_rcp_f32_e32 v13, v12
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v15, v14, v13 :: v_dual_add_f32 v16, -1.0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v12, v15
	v_sub_f32_e32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, v15, v12, -v17
	v_fmac_f32_e32 v12, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v17, v12
	v_dual_sub_f32 v16, v14, v11 :: v_dual_sub_f32 v17, v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v17, v12
	v_sub_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v14, v11
	v_add_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v16, v11
	v_mul_f32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v15, v11
	v_mul_f32_e32 v14, v12, v12
	v_sub_f32_e32 v13, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v13
	v_fma_f32 v13, v12, v12, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v11, v11
	v_fmac_f32_e32 v13, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v14, v13
	v_fmaak_f32 v16, s0, v15, 0x3e91f4c4
	v_sub_f32_e32 v14, v15, v14
	s_mov_b32 s0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v16, v15, v16, 0x3ecccdef :: v_dual_sub_f32 v13, v13, v14
	v_mul_f32_e32 v17, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v15, v16, -v17
	v_dual_fmac_f32 v14, v13, v16 :: v_dual_mul_f32 v19, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v16, v17, v14
	v_fma_f32 v20, v15, v12, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v17, v16, v17 :: v_dual_fmac_f32 v20, v15, v11
	v_add_f32_e32 v18, 0x3f2aaaaa, v16
	v_ldexp_f32 v11, v11, 1
	v_sub_f32_e32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v13, v12
	v_ldexp_f32 v12, v12, 1
	v_add_f32_e32 v14, 0x31739010, v14
	v_add_f32_e32 v17, 0xbf2aaaaa, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v16, v17
	v_add_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v18, v14
	v_dual_add_f32 v15, v19, v20 :: v_dual_sub_f32 v16, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v17, v15, v13
	v_sub_f32_e32 v18, v15, v19
	v_add_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, v15, v13, -v17
	v_sub_f32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v15, v14
	v_fmac_f32_e32 v16, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v17, v16
	v_sub_f32_e32 v14, v13, v17
	v_add_f32_e32 v15, v12, v13
	v_mul_f32_e32 v17, 0x3f317218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v16, v14
	v_sub_f32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, 0x3f317218, v10, -v17
	v_dual_add_f32 v11, v11, v14 :: v_dual_sub_f32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, 0xb102e308, v10
	v_add_f32_e32 v10, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v17, v16 :: v_dual_add_f32 v12, v15, v10
	v_sub_f32_e32 v17, v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v13, v11, v12
	v_sub_f32_e32 v15, v12, v15
	v_sub_f32_e32 v14, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v10, v15
	v_sub_f32_e32 v18, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v11, v18
	v_sub_f32_e32 v12, v12, v14
	v_add_f32_e32 v11, v12, v11
	v_sub_f32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v16, v10
	v_add_f32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v14, v16 :: v_dual_add_f32 v15, v13, v11
	v_dual_sub_f32 v14, v14, v12 :: v_dual_sub_f32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v13 :: v_dual_sub_f32 v10, v10, v12
	v_sub_f32_e32 v12, v16, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v10, v10, v12
	v_cvt_f32_i32_e32 v12, s1
	s_ashr_i32 s1, s5, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v11
	s_add_u32 s2, s2, s0
	s_addc_u32 s3, s3, s1
	v_add_f32_e32 v11, v15, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v11, v15
	v_mul_f32_e32 v14, v11, v12
	v_sub_f32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v12, v11, -v14
	v_cmp_class_f32_e64 vcc_lo, v14, 0x204
	v_dual_fmac_f32 v11, v12, v10 :: v_dual_mul_f32 v12, 0.5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v14, v11
	v_cndmask_b32_e32 v13, v10, v14, vcc_lo
	v_sub_f32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
	v_sub_f32_e32 v10, v11, v10
	v_cndmask_b32_e64 v15, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v13, v15
	v_mul_f32_e32 v17, 0x3fb8aa3b, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v18, 0x3fb8aa3b, v16, -v17
	v_rndne_f32_e32 v19, v17
	v_dual_fmac_f32 v18, 0x32a5705f, v16 :: v_dual_sub_f32 v17, v17, v19
	v_cvt_i32_f32_e32 v14, v19
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v13|
	v_trunc_f32_e32 v13, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v17, v17, v18
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	v_exp_f32_e32 v17, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v15, v10
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v11, v17, v14
	v_cndmask_b32_e64 v14, 0xbe8930a4, 1.0, s10
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, v13, v12
	v_fma_f32 v10, v11, v10, v11
	v_cndmask_b32_e32 v12, 1.0, v14, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_bfi_b32 v10, 0x7fffffff, v10, v12
	v_mov_b32_e32 v11, 0xbe8930a4
.LBB1_6:                                ; %.lr.ph93
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v12, v[2:3], off
	v_add_f32_e32 v13, v11, v10
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_mul_f32_e32 v11, 0xbe8930a4, v11
	v_mul_f32_e32 v10, 0xc06ed9ea, v10
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_add_i32 s9, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s9, 0
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v13, v12
	s_cbranch_scc0 .LBB1_6
.LBB1_7:                                ; %._crit_edge94
	v_cvt_f32_i32_e32 v2, s7
	s_cmp_lt_i32 s4, 2
	s_mov_b32 s0, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v7, v2
	v_fma_f32 v7, v2, v7, -v3
	v_cmp_class_f32_e64 vcc_lo, v3, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, v2, v8 :: v_dual_mul_f32 v2, 0.5, v2
	v_add_f32_e32 v8, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v8, v3, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v10, v11
	v_mul_f32_e32 v13, 0x3fb8aa3b, v12
	v_sub_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0x3fb8aa3b, v12, -v13
	v_rndne_f32_e32 v15, v13
	v_dual_sub_f32 v3, v7, v3 :: v_dual_fmamk_f32 v14, v12, 0x32a5705f, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v13, v15
	v_cvt_i32_f32_e32 v8, v15
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v13, v14
	v_add_f32_e32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v13, v8
	v_trunc_f32_e32 v8, v2
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, v8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v3, v7, v3, v7
	v_cndmask_b32_e32 v2, 1.0, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v2, 0x7fffffff, v3, v2
	v_dual_mul_f32 v3, 0xbe8930a4, v9 :: v_dual_sub_f32 v2, 1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v6, null, v2, v2, v3
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v7
	v_div_scale_f32 v8, vcc_lo, v3, v2, v3
	v_mul_f32_e32 v9, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v6, v9, v8
	v_fmac_f32_e32 v9, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v6, v9, v8
	v_div_fmas_f32 v6, v6, v7, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v2, v6, v2, v3
	global_store_b32 v[0:1], v2, off
	s_cbranch_scc0 .LBB1_9
; %bb.8:                                ; %.loopexit.critedge
	global_load_b32 v2, v[4:5], off
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, 0x3e58658d, v2
	global_store_b32 v[4:5], v2, off
.LBB1_9:                                ; %Flow133
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_14
; %bb.10:                               ; %.lr.ph97.preheader
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_ashr_i32 s1, s5, 31
	s_mov_b32 s0, s5
	s_mov_b32 s2, s8
	s_lshl_b64 s[0:1], s[0:1], 2
.LBB1_11:                               ; %.lr.ph97
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 0
	global_load_b32 v7, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v7, 0xbe8930a4, v6
	global_store_b32 v[2:3], v7, off
	s_cbranch_scc0 .LBB1_11
; %bb.12:                               ; %._crit_edge98
	global_load_b32 v2, v[4:5], off
	s_add_i32 s0, s4, -2
	s_mov_b32 s1, 0
	s_mul_i32 s0, s5, s0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, 0x3e58658d, v2
	global_store_b32 v[4:5], v2, off
.LBB1_13:                               ; %.lr.ph101
                                        ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s6, s1
	s_add_i32 s10, s0, s1
	s_ashr_i32 s3, s2, 31
	s_ashr_i32 s11, s10, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_lshl_b64 s[10:11], s[10:11], 2
	v_add_co_u32 v2, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
	s_add_i32 s8, s8, -1
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	s_sub_i32 s1, s1, s5
	s_cmp_eq_u32 s8, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, 0xbe8930a4, v2
	global_store_b32 v[4:5], v2, off
	s_cbranch_scc0 .LBB1_13
.LBB1_14:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii, .Lfunc_end1-_Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3096
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm ; -- Begin function _Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.globl	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
	.p2align	8
	.type	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm,@function
_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm: ; @_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s8, s8, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s15, s8, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB2_15
; %bb.1:
	v_mul_lo_u32 v1, v1, s4
	v_mul_lo_u32 v4, v0, s5
	v_mad_u64_u32 v[2:3], null, v0, s4, 0
	s_cmp_eq_u64 s[4:5], 0
	s_mov_b64 s[6:7], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v3, v4, v1
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	s_cbranch_scc1 .LBB2_5
; %bb.2:                                ; %.lr.ph
	v_add_co_u32 v6, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v8, v4
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v10, v[6:7], off
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	v_add_co_u32 v6, vcc_lo, v6, 4
	v_cmp_ge_u64_e64 s0, s[6:7], s[4:5]
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v10, 0x40bfffff, v10
	global_store_b32 v[8:9], v10, off
	v_add_co_u32 v8, s0, v8, 4
	v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
	s_cbranch_vccz .LBB2_3
; %bb.4:                                ; %Flow130
	s_mov_b32 s10, 0xbe8930a4
	s_mov_b32 s8, 0x3e8930a4
	s_branch .LBB2_6
.LBB2_5:
	s_mov_b32 s8, 1.0
	s_mov_b32 s10, 1.0
.LBB2_6:                                ; %._crit_edge
	v_frexp_mant_f32_e32 v6, s8
	s_clz_i32_u32 s0, s5
	s_mov_b32 s11, 0x3e76c4e1
	s_min_u32 s0, s0, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[4:5], s0
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6
	s_sub_i32 s1, 32, s0
	s_min_u32 s0, s6, 1
	s_or_b32 s9, s7, s0
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_add_u32 s6, s4, -1
	s_addc_u32 s7, s5, -1
	s_lshl_b64 s[12:13], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v6, v6, v7
	v_add_f32_e32 v9, -1.0, v6
	v_add_f32_e32 v7, 1.0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v10, v9, v8 :: v_dual_add_f32 v11, -1.0, v7
	v_mul_f32_e32 v12, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v6, v11
	v_fma_f32 v11, v10, v7, -v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v10, v6
	v_add_co_u32 v6, s0, v4, s12
	v_add_co_ci_u32_e64 v7, s0, s13, v5, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f32_e32 v13, v12, v11
	s_clause 0x1
	global_load_b32 v15, v[4:5], off
	global_load_b32 v16, v[6:7], off offset:-4
	v_cmp_lt_u64_e64 s0, s[6:7], 2
	v_sub_f32_e32 v14, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v9, v14
	v_sub_f32_e32 v9, v9, v13
	v_sub_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v12, v11
	v_add_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v14, v9
	v_mul_f32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v10, v8
	v_sub_f32_e32 v10, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v11, v9, v9 :: v_dual_sub_f32 v8, v8, v10
	v_fma_f32 v10, v9, v9, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v8, v8
	v_fmac_f32_e32 v10, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v11, v10
	v_fmaak_f32 v13, s11, v12, 0x3e91f4c4
	v_sub_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v13, v12, v13, 0x3ecccdef :: v_dual_sub_f32 v10, v10, v11
	v_mul_f32_e32 v14, v12, v13
	v_mul_f32_e32 v18, v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v12, v13, -v14
	v_fma_f32 v19, v12, v9, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v10, v13
	v_fmac_f32_e32 v19, v12, v8
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v14, v11
	v_fmac_f32_e32 v19, v10, v9
	v_ldexp_f32 v9, v9, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v13, v14
	v_dual_add_f32 v12, v18, v19 :: v_dual_add_f32 v17, 0x3f2aaaaa, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v11, v14 :: v_dual_add_f32 v14, 0xbf2aaaaa, v17
	v_add_f32_e32 v11, 0x31739010, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v14
	v_add_f32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v17, v11
	v_mul_f32_e32 v14, v12, v10
	v_sub_f32_e32 v13, v17, v10
	v_sub_f32_e32 v17, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, v11, v13
	v_fma_f32 v13, v12, v10, -v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v19, v17
	v_fmac_f32_e32 v13, v12, v11
	v_frexp_exp_i32_f32_e32 v11, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v17, v10
	v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v14, v13
	v_cvt_f32_i32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v9, v11
	v_sub_f32_e32 v14, v11, v14
	v_mul_f32_e32 v17, 0x3f317218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v12, v9
	v_sub_f32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, 0x3f317218, v10, -v17
	v_sub_f32_e32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v8, v13
	v_fmac_f32_e32 v14, 0xb102e308, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v8, v9 :: v_dual_add_f32 v9, v17, v14
	v_add_f32_e32 v10, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v9, v10 :: v_dual_sub_f32 v12, v10, v12
	v_dual_sub_f32 v8, v8, v12 :: v_dual_sub_f32 v13, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v11, v13
	v_sub_f32_e32 v10, v10, v13
	v_sub_f32_e32 v17, v9, v17
	v_dual_sub_f32 v9, v9, v18 :: v_dual_sub_f32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v10, v9
	v_add_f32_e32 v12, v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v12, v14
	v_add_f32_e32 v9, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v12, v12, v10 :: v_dual_add_f32 v13, v11, v9
	v_sub_f32_e32 v8, v8, v10
	v_dual_sub_f32 v10, v14, v12 :: v_dual_sub_f32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v8, v10 :: v_dual_sub_f32 v9, v9, v11
	v_add_f32_e32 v8, v8, v9
	v_cvt_f32_u32_e32 v9, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v13, v8
	v_ldexp_f32 v9, v9, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, v10, v9
	v_sub_f32_e32 v11, v10, v13
	v_cmp_class_f32_e64 vcc_lo, v12, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v8, v11
	v_fma_f32 v8, v9, v10, -v12
	v_fmac_f32_e32 v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v12, v8
	v_cndmask_b32_e32 v14, v13, v12, vcc_lo
	v_sub_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v14
	v_sub_f32_e32 v8, v8, v12
	v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v14|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v18, v14, v17
	v_dual_cndmask_b32 v8, 0, v8 :: v_dual_mul_f32 v19, 0x3fb8aa3b, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v17, v8
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v18
	v_fma_f32 v20, 0x3fb8aa3b, v18, -v19
	v_rndne_f32_e32 v21, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v20, 0x32a5705f, v18 :: v_dual_sub_f32 v19, v19, v21
	v_cvt_i32_f32_e32 v13, v21
	v_add_f32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v19, v19
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v12, v19, v13
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v12, 0x7f800000, v12, vcc_lo
	v_fma_f32 v8, v12, v8, v12
	v_mul_f32_e32 v9, 0.5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v13, v9
	v_cmp_neq_f32_e32 vcc_lo, v13, v9
	v_cndmask_b32_e64 v9, 1.0, s10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v12
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_bfi_b32 v8, 0x7fffffff, v8, v9
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v15, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x3f3b67ae, v15
	v_div_scale_f32 v9, null, 0xbe8930a4, 0xbe8930a4, v8
	v_div_scale_f32 v14, vcc_lo, v8, 0xbe8930a4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v12, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v9, v12, 1.0
	v_fmac_f32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v14, v12
	v_fma_f32 v15, -v9, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v12
	v_fma_f32 v9, -v9, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v12, v13
	s_and_b32 vcc_lo, exec_lo, s0
	s_lshl_b64 s[0:1], s[4:5], 1
	v_div_fixup_f32 v12, v9, 0xbe8930a4, v8
	s_cbranch_vccnz .LBB2_9
; %bb.7:                                ; %.lr.ph87.preheader
	s_add_u32 s8, s0, -2
	s_addc_u32 s9, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u64 s[8:9], 0
	s_cselect_b32 s12, -1, 0
	v_cndmask_b32_e64 v8, 0x3e8930a4, 1.0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v9, v8
	v_frexp_exp_i32_f32_e32 v8, v8
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v9
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_ldexp_f32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v8, v8
	v_add_f32_e32 v15, -1.0, v9
	v_add_f32_e32 v13, 1.0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v16, v15, v14
	v_dual_mul_f32 v18, v13, v16 :: v_dual_add_f32 v17, -1.0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v16, v13, -v18
	v_sub_f32_e32 v9, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v16, v9
	v_add_f32_e32 v9, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v15, v9 :: v_dual_sub_f32 v18, v9, v18
	v_sub_f32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v18, v13
	v_sub_f32_e32 v9, v15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v13, v9
	v_add_f32_e32 v9, v17, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v14, v9
	v_add_f32_e32 v13, v16, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v13, v16
	v_mul_f32_e32 v15, v13, v13
	v_sub_f32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, v13, v13, -v15
	v_add_f32_e32 v16, v9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, v13, v16
	v_add_f32_e32 v16, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, v13, v16
	v_fmaak_f32 v17, s11, v16, 0x3e91f4c4
	v_sub_f32_e32 v15, v16, v15
	s_clz_i32_u32 s11, s9
	v_fma_f32 v21, v16, v13, -v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_fmaak_f32 v17, v16, v17, 0x3ecccdef :: v_dual_sub_f32 v14, v14, v15
	s_min_u32 s11, s11, 32
	s_lshl_b64 s[8:9], s[8:9], s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, v16, v17
	v_fmac_f32_e32 v21, v16, v9
	v_ldexp_f32 v9, v9, 1
	s_min_u32 s8, s8, 1
	v_fma_f32 v15, v16, v17, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, v14, v13
	s_or_b32 s8, s9, s8
	v_fmac_f32_e32 v15, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v16, v20, v21 :: v_dual_add_f32 v17, v18, v15
	v_dual_sub_f32 v18, v17, v18 :: v_dual_add_f32 v19, 0x3f2aaaaa, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v15, v15, v18 :: v_dual_add_f32 v18, 0xbf2aaaaa, v19
	v_add_f32_e32 v15, 0x31739010, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v17, v18
	v_add_f32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v19, v15
	v_sub_f32_e32 v17, v19, v14
	v_mul_f32_e32 v18, v16, v14
	v_sub_f32_e32 v19, v16, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v15, v15, v17
	v_fma_f32 v17, v16, v14, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v21, v19
	v_fmac_f32_e32 v17, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v14
	v_add_f32_e32 v14, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v14, v18 :: v_dual_mul_f32 v18, 0x3f317218, v8
	v_ldexp_f32 v13, v13, 1
	v_sub_f32_e32 v15, v17, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, 0x3f317218, v8, -v18
	v_add_f32_e32 v16, v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v9, v9, v15
	v_fmac_f32_e32 v17, 0xb102e308, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v16, v13
	v_sub_f32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v8, v9, v13
	v_add_f32_e32 v9, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v13, v16, v8 :: v_dual_sub_f32 v18, v9, v18
	v_add_f32_e32 v14, v9, v13
	v_sub_f32_e32 v16, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v17, v17, v18
	v_dual_sub_f32 v15, v14, v9 :: v_dual_sub_f32 v8, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v14, v15
	v_sub_f32_e32 v13, v13, v15
	v_add_f32_e32 v15, v17, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v9, v19
	v_add_f32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v15, v17
	v_add_f32_e32 v9, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v13
	v_sub_f32_e32 v8, v8, v13
	v_dual_add_f32 v16, v14, v9 :: v_dual_sub_f32 v13, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v16, v14
	v_dual_add_f32 v8, v8, v13 :: v_dual_sub_f32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v8, v9
	v_cvt_f32_u32_e32 v9, s8
	s_sub_i32 s8, 32, s11
	v_add_f32_e32 v13, v16, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f32 v9, v9, s8
	s_mov_b64 s[8:9], 1
	v_sub_f32_e32 v14, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, v13, v9 :: v_dual_sub_f32 v8, v8, v14
	v_fma_f32 v13, v9, v13, -v15
	v_cmp_class_f32_e64 vcc_lo, v15, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v9, v8
	v_mul_f32_e32 v9, 0.5, v9
	v_add_f32_e32 v8, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v8, v15, vcc_lo
	v_sub_f32_e32 v8, v8, v15
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v13, v8
	v_cndmask_b32_e64 v16, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v14|
	v_sub_f32_e32 v17, v14, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cndmask_b32_e64 v14, 0xbe8930a4, 1.0, s12
	v_mul_f32_e32 v18, 0x3fb8aa3b, v17
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v16, v8
	v_fma_f32 v19, 0x3fb8aa3b, v17, -v18
	v_rndne_f32_e32 v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v19, 0x32a5705f, v17 :: v_dual_sub_f32 v18, v18, v20
	v_cvt_i32_f32_e32 v15, v20
	v_add_f32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v18, v18
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v13, v18, v15
	v_trunc_f32_e32 v15, v9
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v13, 0x7f800000, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v17, vcc_lo, s3, v1, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, v15, v9
	v_fma_f32 v8, v13, v8, v13
	v_cndmask_b32_e32 v14, 1.0, v14, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v8, v13, vcc_lo
	v_add_co_u32 v8, vcc_lo, v16, 4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v17, vcc_lo
	v_bfi_b32 v13, 0x7fffffff, v13, v14
	v_mov_b32_e32 v14, 0xbe8930a4
.LBB2_8:                                ; %.lr.ph87
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v15, v[8:9], off
	s_add_u32 s8, s8, 1
	v_add_f32_e32 v16, v14, v13
	s_addc_u32 s9, s9, 0
	v_add_co_u32 v8, vcc_lo, v8, 4
	v_cmp_le_u64_e64 s11, s[6:7], s[8:9]
	v_mul_f32_e32 v14, 0xbe8930a4, v14
	v_mul_f32_e32 v13, 0xc06ed9ea, v13
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	s_and_b32 vcc_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v12, v16, v15
	s_cbranch_vccz .LBB2_8
.LBB2_9:                                ; %._crit_edge88
	s_clz_i32_u32 s6, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s6, s6, 32
	s_lshl_b64 s[0:1], s[0:1], s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s0, s0, 1
	s_or_b32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v8, s0
	s_sub_i32 s0, 32, s6
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v8, v8, s0
	v_cmp_lt_u64_e64 s0, s[4:5], 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v10, v8, v10, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, v8, v11
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_dual_mul_f32 v8, 0.5, v8 :: v_dual_add_f32 v11, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v11, v9, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_sub_f32_e32 v15, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, 0x3fb8aa3b, v15 :: v_dual_sub_f32 v9, v11, v9
	v_fma_f32 v17, 0x3fb8aa3b, v15, -v16
	v_rndne_f32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v10, v9
	v_dual_fmamk_f32 v17, v15, 0x32a5705f, v17 :: v_dual_sub_f32 v16, v16, v18
	v_cvt_i32_f32_e32 v11, v18
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v13|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v16, v17
	v_cndmask_b32_e32 v9, 0, v9, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_exp_f32_e32 v16, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v9, v14, v9
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v10, v16, v11
	v_trunc_f32_e32 v11, v8
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v9, v10, v9, v10
	v_cndmask_b32_e64 v8, 1.0, s10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v10
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_bfi_b32 v8, 0x7fffffff, v9, v8
	v_mul_f32_e32 v9, 0xbe8930a4, v12
	v_sub_f32_e32 v8, 1.0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v10, null, v8, v8, v9
	v_div_scale_f32 v13, vcc_lo, v9, v8, v9
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v10, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v10, v12, v13
	v_div_fmas_f32 v10, v10, v11, v12
	s_and_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v8, v10, v8, v9
	global_store_b32 v[4:5], v8, off
	s_cbranch_vccnz .LBB2_12
; %bb.10:                               ; %.lr.ph91.preheader
	v_add_co_u32 v4, vcc_lo, v0, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	s_mov_b64 s[0:1], 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB2_11:                               ; %.lr.ph91
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[8:9], v[4:5], off offset:-4
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_ge_u64_e64 s6, s[0:1], s[4:5]
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, 0xbe8930a4, v8
	global_store_b32 v[4:5], v9, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB2_11
.LBB2_12:                               ; %._crit_edge92
	global_load_b32 v4, v[6:7], off offset:-4
	s_add_i32 s0, s4, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s0, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, 0x3e58658d, v4
	global_store_b32 v[6:7], v4, off offset:-4
	s_cbranch_scc1 .LBB2_15
; %bb.13:                               ; %.lr.ph95.preheader
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_mov_b32 s1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[6:7], s[0:1], 2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_add_i32 s0, s4, -1
	s_add_u32 s1, s2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_addc_u32 s2, s3, s7
	v_add_co_u32 v0, vcc_lo, s1, v0
	global_load_b32 v2, v[2:3], off offset:4
	v_add_co_ci_u32_e32 v1, vcc_lo, s2, v1, vcc_lo
.LBB2_14:                               ; %.lr.ph95
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
	v_mul_f32_e32 v2, 0xbe8930a4, v2
	global_store_b32 v[0:1], v2, off
	v_add_co_u32 v0, vcc_lo, v0, -4
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	s_cbranch_scc1 .LBB2_14
.LBB2_15:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm, .Lfunc_end2-_Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3260
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4224
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28transposeNoBankConflicts32x8PfPKfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z28transposeNoBankConflicts32x8PfPKfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z50iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundNewPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z47iirConvolve2D_Cardinal_Bspline_3_MirrorOffBoundPfS_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
