#include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <stdlib.h>
#include "device_launch_parameters.h"
#include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <thrust/count.h>
const int BASE1 = 10000 + 7;
const int BASE2 = 100000 + 3;
const int MOD1 = 1000000 + 3;
const int MOD2 = 1000000 + 37;
__global__ void findhash(int *d_qvert,int *d_qverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_qtree,int *d_hash1,int *d_hash2)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	int l=d_qvert[ver+1];
	int hash1=1,hash2=1;
	int flag=0;
	for(i=d_qvert[ver];i<l;i++)
	{
		int m=d_qelist[i];
		bool treeedge=d_qtree[i];
		if(treeedge){
			int tt=d_qvid[m];
			if(tt==0)
				return;
			flag=1;
			hash1=(hash1*1L*BASE1)*tt % MOD1;
			hash2=(hash2*1L*BASE2)*tt % MOD2;
		}
	}
	if(flag==0)
		return;
	if(flag==1){
		*d_over=false;
		d_hash1[hash1]=1;
		d_hash2[hash2]=1;
	}
	
}
__global__ void setdeg1(int *d_qvert,int *d_qverc,int *d_qvid,bool *d_qtree)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	
	int l=d_qvert[ver+1];
	bool treeedge;
	
	for(i=d_qvert[ver];i<l;i++)
	{
		treeedge=d_qtree[i];
		
		if(treeedge)
			return;
	}
//printf("%d %d\n",ver,i);
	d_qvid[ver]=1;	
}
/*__global__ void alignhash(bool *d_hash1,bool *d_hash2)
{
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=1000038)
		return ;
	if(d_hash1[ver] || d_hash2[ver]){
		d_hash1=true;
	}
}*/
__global__ void puttoid(int *d_qvert,int *d_qverc,int *d_qvid,int *d_qelist,bool *d_qtree,int *d_loc,int * d_qidtov)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	int l=d_qvert[ver+1];
	int hash1=1,hash2=1;
	int flag=0;
	for(i=d_qvert[ver];i<l;i++)
	{
		int m=d_qelist[i];
		bool treeedge=d_qtree[i];
		if(treeedge){
			int tt=d_qvid[m];
			if(tt==0)
				return;
			flag=1;
			hash1=(hash1*1L*BASE1)*tt % MOD1;
			hash2=(hash2*1L*BASE2)*tt % MOD2;
		}
	}
	//printf("%d %d %d \n",ver,flag,d_loc[hash1]);
	if(flag==0)
		return;
	int id=d_loc[hash1];
	d_qvid[ver]=id;
	d_qidtov[id]=ver;
}
__device__ bool chechall(int ver,bool *check,int i,int dfrom,int dto,int *d_delist,int *d_qelist,int *d_qvid,int qfrom,int qto,int ** d_dcvslist){
	//int ql=qfrom-qto;
	int ql=qto-qfrom;
	int j,k,l;
	//d_dcvslist[2][ql]=true;
	if(i==ql){
		
		k=d_qelist[i+qfrom-1];
		k=d_qvid[k];
		if(k>=d_qvid[ver])
			return true;
		for(j=dfrom;j<dto;j++){
			l=d_delist[j];
			if(check[l])
				continue;
			if(!d_dcvslist[k][l])
				continue;
			return true;
		}
	}
	else{
		int res=false;
		k=d_qelist[i+qfrom-1];
		k=d_qvid[k];
		if(k>=d_qvid[ver])
			return chechall(ver,check,i+1,dfrom,dto,d_delist,d_qelist,d_qvid,qfrom,qto,d_dcvslist);
		
		for(j=dfrom;j<dto;j++){
			l=d_delist[j];
			if(check[l])
				continue;
			if(!d_dcvslist[k][l])
				continue;
			check[l]=true;
			res|=chechall(ver,check,i+1,dfrom,dto,d_delist,d_qelist,d_qvid,qfrom,qto,d_dcvslist);
			if(res==true)
				return true;
			check[l]=false;
		}
	}
	return false;
}
__global__ void findcvs(int ver,int *d_dvert,int *d_dverc,int *d_delist,int *d_qvert,int *d_qelist,int *d_qvid,int ** d_dcvslist )
{
	//int i;
	int dver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(dver>=d_dverc[0])
		return ;
	int ql=d_qvert[ver+1]-d_qvert[ver];
	int dl=d_dvert[dver+1]-d_dvert[dver];
	if(ql>dl)
		return;
	bool *checked=(bool*)malloc(sizeof(bool)*d_dverc[0]);
	//bool *checked=new bool[d_dverc[0]];
	memset(checked,false,sizeof(bool)*d_dverc[0]);
	//chechall(bool *check,int i,int dfrom,int dto,int *d_delist,int *d_qelist,int *d_qvid,int qfrom,int qto,bool ** d_dcvslist)
	if(chechall(ver,checked,1,d_dvert[dver],d_dvert[dver+1],d_delist,d_qelist,d_qvid,d_qvert[ver],d_qvert[ver+1],d_dcvslist))
		d_dcvslist[d_qvid[ver]][dver]=true;
	free(checked);
}
__global__ void puttolist(int *d_dverc,int *d_loc,int * d_dcvslist )
{
	int dver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(dver>=d_dverc[0])
		return ;
	if(d_loc[dver]!=d_loc[dver+1])
		d_dcvslist[d_loc[dver]]=dver;
}
__global__ void checkperm(bool *found,int * qdmap,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist){
	int i;
	//found[0]=false;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	int n,p,j,k,flag=0;
	//for(ver=0;ver<d_qverc[0];ver++){
		int l=d_qvert[ver+1];
		int dver=qdmap[ver];
		
		n=d_dvert[dver+1];
		for(i=d_qvert[ver];i<l;i++)
		{
			flag=0;
			j=d_qelist[i];
			p=d_dvert[dver];
			k=qdmap[j];
			for(;p<n;p++){
				if(k==d_delist[p]){
					flag=1;
					break;
				}
			}
			if(!flag){
				*found=false;
				return;
			}
		}
	//}
}

__global__ void findall(int *d_mapans,int *d_cans,int *d_qvid,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist,int ** d_cvsverlist,int * d_size_cvs)
{
	bool found[1]={true};
	long long int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 
	long long int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
			  + (threadIdx.z * (blockDim.x * blockDim.y))
			  + (threadIdx.y * blockDim.x)
			  + threadIdx.x;
	int i=0;
	long long int indexperm=threadId;
	for(i=0;i<d_qverc[0];i++){
		int j=d_qvid[i];
		indexperm/=d_size_cvs[j];
	}
	if(indexperm)
		return;
	indexperm=threadId;	
	int *d_qdmap=&d_mapans[d_qverc[0]*threadId];//new int[d_qverc[0]];
	for(i=0;i<d_qverc[0];i++){
		int j=d_qvid[i];
		d_qdmap[i]=d_cvsverlist[j][indexperm%d_size_cvs[j]];
		indexperm/=d_size_cvs[j];
	}
	
	//dim3 blocks((max/16 )+ 1,(max/16)+1);
	//dim3 threads(16,16);
	//found[0]=true;
	//checkperm<<<blocks,threads>>> (found,d_qdmap,d_qverc,d_qelist,d_qvert,d_dvert,d_delist);
	int n,p,j,k,flag=0,ver;
	for(ver=0;ver<d_qverc[0];ver++){
		int l=d_qvert[ver+1];
		int dver=d_qdmap[ver];
		
		n=d_dvert[dver+1];
		for(i=d_qvert[ver];i<l;i++)
		{
			flag=0;
			j=d_qelist[i];
			p=d_dvert[dver];
			k=d_qdmap[j];
			for(;p<n;p++){
				if(k==d_delist[p]){
					flag=1;
					break;
				}
			}
			if(!flag){
				*found=false;
				return;
			}
		}
	}
	if(found[0]){
		d_cans[threadId]=1;	//printf("%d ", threadId);
	}
	//delete d_qdmap;
}
int * qdmap;
int *d_qverc,*d_dverc;
int *d_qvid,*d_qidtov,*h_qidtov,*h_qvid;
int *d_qvert,*d_qelist,*d_dvert,*d_delist;//,*d_dvelist,*d_qvelist;
bool *d_qtree,*d_over;	
int *d_qdmap;
bool h_over;
/*void callforallperm(bool * check,int ** cvslist,int i,int max,int dmax){
	int j,k,l;
	l=h_qvid[i-1];
	//printf("i%d %di",i,l);
	if(i==max){
		for(j=0;j<dmax;j++)
			if(cvslist[l][j] && !check[j]){
				qdmap[i-1]=j;
				dim3 blocks((max/16 )+ 1,(max/16)+1);
				dim3 threads(16,16);
				h_over=true;
				//for(k=0;k<max;k++)
				//		printf("%d ",qdmap[k]);
				
				cudaMemcpy(d_over, &h_over, sizeof(bool), cudaMemcpyHostToDevice) ;
				cudaMemcpy(d_qdmap, qdmap, sizeof(int)*(max+1), cudaMemcpyHostToDevice);
				checkperm<<<blocks,threads>>> (d_over,d_qdmap,d_qverc,d_qelist,d_qvert,d_dvert,d_delist);
				//checkperm(bool *found,int * qdmap,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist)
				cudaError_t err = cudaGetLastError();
					if(err!=cudaSuccess)
					{
						printf("Error: %s\n", cudaGetErrorString(err));
						printf("Not Ok");
					}
				cudaMemcpy(&h_over, d_over, sizeof(bool), cudaMemcpyDeviceToHost) ;
				if(h_over){
					for(k=0;k<max;k++)
						printf("%d ",qdmap[k]);
					//printf("\n");
						printf("OK\n");
				}
				//printf("\n");
			}
	}
	else{
		for(j=0;j<dmax;j++){
				//printf("%d %d %d\n",j,check[j],cvslist[l][j]);
				if(cvslist[l][j] && !check[j]){
				check[j]=true;
				qdmap[i-1]=j;
				callforallperm(check,cvslist,i+1,max,dmax);
				check[j]=false;
			}
		}
	}
}*/

int main(int argc, char **argv)
{
	int deviceId = 4;
	cudaSetDevice(deviceId);
	int h_qverc,h_dverc;
	
	
	int *h_qvert,*h_qelist,*h_dvert,*h_delist;//,*h_dvelist,*h_qvelist;
	
	bool *h_qtree;
	int *d_hash1,*d_hash2;
	
	int i,j;
	int **h_cvslist,**d_cvslist,**h_tem;
	scanf("%d",&h_qverc);
	h_qvert=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_qvid=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_qidtov=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_tem=(int **)malloc(sizeof(int*)*(h_qverc+1));
	h_cvslist=(int **)malloc(sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		scanf("%d",&h_qvert[i]);
	}
	h_qelist=(int *)malloc(sizeof(int)*h_qvert[h_qverc]);
	for(i=0;i<h_qvert[h_qverc];i++)
		scanf("%d",&h_qelist[i]);
	h_qtree=(bool *)malloc(sizeof(bool)*h_qvert[h_qverc]);
	for(i=0;i<h_qvert[h_qverc];i++){
		scanf("%d",&j);
		if(j==1)
			h_qtree[i]=true;
		else
			h_qtree[i]=false;
	}
	
	scanf("%d",&h_dverc);
	h_dvert=(int *)malloc(sizeof(int)*(h_dverc+1));
	for(i=0;i<=h_dverc;i++){
		scanf("%d",&h_dvert[i]);
	}
	for(i=0;i<=h_qverc;i++)
		h_cvslist[i]=(int *)malloc(sizeof(int)*(h_dverc+1));
	
	h_delist=(int *)malloc(sizeof(int)*h_dvert[h_dverc]);
	for(i=0;i<h_dvert[h_dverc];i++)
		scanf("%d",&h_delist[i]);
	cudaMalloc(&d_qverc,sizeof(int));
	cudaMalloc(&d_over,sizeof(bool));
	cudaMalloc(&d_qvert,sizeof(int)*(h_qverc+1));
	cudaMalloc(&d_qidtov,sizeof(int)*(h_qverc+1));
	//cudaMalloc(&d_loc,sizeof(int)*(h_qverc+1));
	cudaMalloc(&d_qelist,sizeof(int)*h_qvert[h_qverc]);
	cudaMalloc(&d_qtree,sizeof(bool)*h_qvert[h_qverc]);
	cudaMalloc(&d_hash1,sizeof(int)*1000038);
	cudaMalloc(&d_hash2,sizeof(int)*1000038);
	
	cudaMalloc(&d_qvid,sizeof(int)*(h_qverc+1));
	cudaMemcpy(d_qverc,&h_qverc,sizeof(int),cudaMemcpyHostToDevice);
	cudaMemcpy(d_qvert,h_qvert,sizeof(int)*(h_qverc+1),cudaMemcpyHostToDevice);
	cudaMemcpy(d_qelist,h_qelist,sizeof(int)*h_qvert[h_qverc],cudaMemcpyHostToDevice);
	cudaMemcpy(d_qtree,h_qtree,sizeof(bool)*h_qvert[h_qverc],cudaMemcpyHostToDevice);
	cudaMemset(d_hash1,0,sizeof(int)*1000038);
	cudaMemset(d_hash2,0,sizeof(int)*1000038);
	//cudaMemset(d_loc,0,sizeof(int)*(h_qverc+1));
	cudaMemset(d_qidtov,-1,sizeof(int)*(h_qverc+1));
	cudaMemset(d_qvid,0,sizeof(int)*(h_qverc+1));
	int *h_hash1=(int *)malloc(sizeof(int)*1000038);
	int *h_hash2=(int *)malloc(sizeof(int)*1000038);
	dim3 blocks((sqrt(h_qverc)/16 )+ 1,(sqrt(h_qverc)/16)+1);
	dim3 threads(16,16);
	
	//int *d_qvert,int *d_dverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_hash1,bool *d_hash2)
	h_over=true;
	//h_qvid[1]=1;
	//h_qvid[3]=1;
	//cudaMemcpy(d_qvid,h_qvid,sizeof(int)*(h_qverc+1),cudaMemcpyHostToDevice);
//printf("qt%d %dqt\n",h_qtree[0],h_qtree[1]);
	setdeg1<<<blocks,threads>>>(d_qvert,d_qverc,d_qvid,d_qtree);

	h_over=false;
	int maxval=2;
	while(!h_over)
	{
		h_over=true;
		cudaMemcpy(d_over, &h_over, sizeof(bool), cudaMemcpyHostToDevice) ;
		cudaMemset(d_hash1,0,sizeof(int)*1000038);
		findhash <<<blocks,threads>>> (d_qvert,d_qverc,d_qvid,d_qelist,d_over,d_qtree,d_hash1,d_hash2);
		//(int *d_qvert,int *d_dverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_hash1,bool *d_qtree,bool *d_hash2)
		cudaError_t err = cudaGetLastError();
		if(err!=cudaSuccess)
		{
			printf("Error: %s\n", cudaGetErrorString(err));
			printf("Not Ok");
		}
		cudaMemcpy(h_hash1,d_hash1,sizeof(int)*1000038,cudaMemcpyDeviceToHost);
		h_hash1[0]+=maxval;
		thrust::exclusive_scan(h_hash1,h_hash1+1000038,h_hash1);
		maxval=h_hash1[1000037];
		cudaMemcpy(d_hash1,h_hash1,sizeof(int)*1000038,cudaMemcpyHostToDevice);
		puttoid<<<blocks,threads>>>(d_qvert,d_qverc,d_qvid,d_qelist,d_qtree,d_hash1,d_qidtov);
///		cudaMemcpy(h_hash2,d_hash2,sizeof(bool)*1000038,cudaMemcpyDeviceToHost);
		cudaMemcpy(&h_over, d_over, sizeof(bool), cudaMemcpyDeviceToHost) ;
		
		//printf("over flag:%d ",h_over);
		/*for(i=0;i<h_qverc;i++){
			//if()
				printf("%d ",h_qvid[i]);
//			if(h_hash2[i])
//				printf("h2 %d ",i);
//			if(h_hash1[i] || h_hash2[i])
//				printf("\n");
		}
		printf("\n");*/

	}	
	cudaMemcpy(h_qvid,d_qvid,sizeof(int)*h_qverc,cudaMemcpyDeviceToHost);
	cudaMemcpy(h_qidtov,d_qidtov,sizeof(int)*(h_qverc+1),cudaMemcpyDeviceToHost);
	for(i=0;i<=h_qverc;i++){
		printf("%d ",h_qidtov[i]);
	}
	printf("\n");
	for(i=0;i<=h_qverc;i++){
		printf("%d ",h_qvid[i]);
	}
	printf("\n");
	cudaFree(d_qtree);
	cudaFree(d_hash1);
	cudaFree(d_hash2);
	free(h_hash1);
	free(h_hash2);
	free(h_qtree);
	
	cudaMalloc(&d_cvslist,sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		cudaMalloc(&h_tem[i],sizeof(int)*(h_dverc+1));
		cudaMemset(h_tem[i],0,sizeof(int)*(h_dverc+1));
	}
	cudaMemset(h_tem[1],1,sizeof(int)*(h_dverc+1));
	cudaMemcpy(d_cvslist,h_tem,sizeof(int*)*(h_qverc+1),cudaMemcpyHostToDevice);
	cudaMalloc(&d_dvert,sizeof(int)*(h_dverc+1));
	cudaMalloc(&d_dverc,sizeof(int));
	cudaMalloc(&d_delist,sizeof(int)*h_dvert[h_dverc]);	
	cudaMemcpy(d_dverc,&h_dverc,sizeof(int),cudaMemcpyHostToDevice);
	cudaMemcpy(d_dvert,h_dvert,sizeof(int)*(h_dverc+1),cudaMemcpyHostToDevice);
	cudaMemcpy(d_delist,h_delist,sizeof(int)*h_dvert[h_dverc],cudaMemcpyHostToDevice);
	dim3 dblocks((sqrt(h_dverc)/16 )+ 1,(sqrt(h_dverc)/16)+1);
	dim3 dthreads(16,16);
	int **d_cvsverlist,**d_temverlist;
	int *d_size_cvs,*h_size_cvs;
	memset(h_cvslist[1],1,sizeof(int)*(h_dverc+1));
	h_size_cvs=(int *)malloc(sizeof(int)*(h_qverc+1));
	memset(h_size_cvs,0,sizeof(int)*(h_qverc+1));
	cudaMalloc(&d_size_cvs,sizeof(int)*(h_qverc+1));
	cudaMemset(d_size_cvs,0,sizeof(int)*(h_qverc+1));
	cudaMalloc(&d_cvsverlist,sizeof(int*)*(h_qverc+1));
	d_temverlist=(int **)malloc(sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		cudaMalloc(&d_temverlist[i],sizeof(int)*(h_dverc+1));
		cudaMemset(d_temverlist[i],0,sizeof(int)*(h_dverc+1));
	}
	cudaMemcpy(d_cvsverlist,d_temverlist,sizeof(int*)*(h_qverc+1),cudaMemcpyHostToDevice);
	long long int totalthreads=1;
	for(i=0;i<h_dverc;i++)
		h_cvslist[1][i]=i;
	cudaMemcpy(d_temverlist[1],h_cvslist[1],sizeof(int)*(h_dverc+1),cudaMemcpyHostToDevice);
	h_size_cvs[1]=h_dverc;
	for(i=0;i<=h_qverc;i++)
	{
		if(h_qidtov[i]!=-1)
		{

		//findcvs(int ver,int *d_dvert,int *d_dverc,int *d_delist,int *d_qvert,int *d_qelist,int *d_qvid,bool ** d_dcvslist )
		findcvs<<<dblocks,dthreads>>>(h_qidtov[i],d_dvert,d_dverc,d_delist,d_qvert,d_qelist,d_qvid,d_cvslist);
		cudaError_t err = cudaGetLastError();
	
		cudaMemcpy(h_cvslist[i],h_tem[i],sizeof(int)*(h_dverc+1),cudaMemcpyDeviceToHost);
		for(j=0;j<=h_dverc;j++)
			if(h_cvslist[i][j])
				printf("%d ",j);
		printf("\n");
		//printf("%d ",h_qidtov[i]);
		thrust::exclusive_scan(h_cvslist[i],h_cvslist[i]+h_dverc+1,h_cvslist[i]);
		h_size_cvs[i]=h_cvslist[i][h_dverc];
		cudaMemcpy(h_tem[i],h_cvslist[i],sizeof(int)*(h_dverc+1),cudaMemcpyHostToDevice);
		puttolist<<<dblocks,dthreads>>>(d_dverc,h_tem[i],d_temverlist[i]);
	//	cudaMemcpy(h_cvslist[i],d_temverlist[i],sizeof(int)*(h_dverc+1),cudaMemcpyDeviceToHost);
	//	for(j=0;j<=h_dverc;j++)
	//		printf("%d ",h_cvslist[i][j]);	
		}	
		
	}
	//	cudaMemcpy(h_delist,d_delist,sizeof(int)*(h_dvert[h_dverc]),cudaMemcpyDeviceToHost);
	//	for(j=0;j<h_dvert[h_dverc];j++)
	//		printf("%d ",h_delist[j]);	
			
	for(i=0;i<h_qverc;i++)
		if(h_size_cvs[h_qvid[i]])
		totalthreads*=h_size_cvs[h_qvid[i]];
	printf("Start %lld\n",totalthreads);
	cudaMemcpy(d_size_cvs,h_size_cvs,sizeof(int)*(h_qverc+1),cudaMemcpyHostToDevice);
	//totalthreads=1000;
	dim3 dpblocks(((int)(sqrt(totalthreads)/16 )+ 1),((int)(sqrt(totalthreads)/16)+1));
	dim3 dpthreads(16,16);
	 int *d_mapans,*d_countans,*h_countans;
	cudaMalloc(&d_mapans,sizeof( int)*totalthreads*(h_qverc+1));
	cudaMalloc(&d_countans,sizeof( int)*(totalthreads+1));
	cudaMemset(d_countans,0,sizeof( int)*(totalthreads+1));
	//h_countans=(int *)malloc(sizeof(int)*(totalthreads+1));
	//h_countans=0;
	//cudaMemcpy(d_countans, &h_countans, sizeof( int), cudaMemcpyHostToDevice) ;
	//cudaMemcpy(&h_countans, d_qverc, sizeof(int), cudaMemcpyDeviceToHost) ;
	//printf("%d\n",h_countans);
	findall<<<dpblocks,dpthreads>>> (d_mapans,d_countans,d_qvid,d_qverc,d_qelist,d_qvert,d_dvert,d_delist,d_cvsverlist,d_size_cvs);
	thrust::device_ptr<int> cptr=thrust::device_pointer_cast(d_countans);
	//int sum=thrust::count(cptr,cptr+totalthreads,1);
	//cudaMemcpy(h_countans, d_countans, sizeof(int)*totalthreads, cudaMemcpyDeviceToHost) ;
	//thrust::exclusive_scan(h_countans,h_countans+totalthreads+1,h_countans);
	//printf("%d\n",h_countans[totalthreads-1] );
	//printf("%d\n",h_countans);
	//printf("%d\n",sum);
	/*j=0;
	for(i=0;i<totalthreads;i++)
		if(h_countans[i])
			j++;
	printf("%d\n",j);
	*///bool * check=(bool *)malloc(sizeof(bool)*(h_dverc+1));
	//memset(check,false,sizeof(bool)*(h_dverc+1));
	//qdmap=(int *)malloc(sizeof(int)*(h_qverc+1));
	//cudaMalloc(&d_qdmap,sizeof(int)*(h_qverc+1));
	//callforallperm(check,h_cvslist,1,h_qverc,h_dverc);

	cudaFree(d_over);
	cudaFree(d_qverc);
	cudaFree(d_qvert);
	cudaFree(d_qelist);
	cudaFree(d_qvid);
	cudaFree(d_qidtov);
	cudaFree(d_dvert);
	cudaFree(d_delist);
	cudaFree(d_dverc);
	cudaFree(d_cvslist);
	cudaFree(d_cvsverlist);
	cudaFree(d_size_cvs);
	/*free(h_qvid);
	free(h_qvert);
	//free(h_qelist);
	free(h_qidtov);
	free(h_cvslist);
	free(h_dvert);
	free(h_delist);*/
}
	

	.file	"tmpxft_0025a6ec_00000000-6_isokernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.weak	nvtxEtiGetModuleFunctionTable_v3
	.hidden	nvtxEtiGetModuleFunctionTable_v3
	.type	nvtxEtiGetModuleFunctionTable_v3, @function
nvtxEtiGetModuleFunctionTable_v3:
.LFB6203:
	.cfi_startproc
	endbr64
	decl	%edi
	xorl	%eax, %eax
	cmpl	$5, %edi
	ja	.L1
	leaq	.L4(%rip), %rcx
	movslq	(%rcx,%rdi,4), %rax
	addq	%rcx, %rax
	notrack jmp	*%rax
	.section	.rodata.nvtxEtiGetModuleFunctionTable_v3,"aG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.align 4
	.align 4
.L4:
	.long	.L9-.L4
	.long	.L14-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
.L9:
	leaq	560+nvtxGlobals_v3(%rip), %rcx
	jmp	.L18
.L7:
	leaq	776+nvtxGlobals_v3(%rip), %rcx
	movl	$128, %eax
	jmp	.L8
.L6:
	leaq	904+nvtxGlobals_v3(%rip), %rcx
	jmp	.L19
.L5:
	leaq	968+nvtxGlobals_v3(%rip), %rcx
.L18:
	movl	$136, %eax
	jmp	.L8
.L3:
	leaq	1104+nvtxGlobals_v3(%rip), %rcx
.L19:
	movl	$64, %eax
	jmp	.L8
.L14:
	leaq	696+nvtxGlobals_v3(%rip), %rcx
	movl	$80, %eax
.L8:
	testq	%rdx, %rdx
	je	.L10
	shrl	$3, %eax
	decl	%eax
	movl	%eax, (%rdx)
.L10:
	testq	%rsi, %rsi
	jne	.L11
.L12:
	movl	$1, %eax
	ret
.L11:
	movq	%rcx, (%rsi)
	jmp	.L12
.L1:
	ret
	.cfi_endproc
.LFE6203:
	.size	nvtxEtiGetModuleFunctionTable_v3, .-nvtxEtiGetModuleFunctionTable_v3
	.section	.text.nvtxGetExportTable_v3,"axG",@progbits,nvtxGetExportTable_v3,comdat
	.weak	nvtxGetExportTable_v3
	.hidden	nvtxGetExportTable_v3
	.type	nvtxGetExportTable_v3, @function
nvtxGetExportTable_v3:
.LFB6204:
	.cfi_startproc
	endbr64
	leaq	8+nvtxGlobals_v3(%rip), %rax
	cmpl	$1, %edi
	je	.L21
	cmpl	$3, %edi
	leaq	16(%rax), %rax
	movl	$0, %edx
	cmovne	%rdx, %rax
.L21:
	ret
	.cfi_endproc
.LFE6204:
	.size	nvtxGetExportTable_v3, .-nvtxGetExportTable_v3
	.section	.text.nvtxEtiSetInjectionNvtxVersion_v3,"axG",@progbits,nvtxEtiSetInjectionNvtxVersion_v3,comdat
	.weak	nvtxEtiSetInjectionNvtxVersion_v3
	.hidden	nvtxEtiSetInjectionNvtxVersion_v3
	.type	nvtxEtiSetInjectionNvtxVersion_v3, @function
nvtxEtiSetInjectionNvtxVersion_v3:
.LFB6205:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE6205:
	.size	nvtxEtiSetInjectionNvtxVersion_v3, .-nvtxEtiSetInjectionNvtxVersion_v3
	.text
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB11189:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE11189:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0, @function
_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0:
.LFB12112:
	.cfi_startproc
	cmpq	%rsi, %rdi
	je	.L28
	xorl	%eax, %eax
	movl	(%rdi), %ecx
	subq	%rdi, %rsi
	movl	%eax, (%rdx)
	xorl	%eax, %eax
.L30:
	addq	$4, %rax
	cmpq	%rsi, %rax
	je	.L28
	movl	(%rdi,%rax), %r8d
	movl	%ecx, (%rdx,%rax)
	addl	%r8d, %ecx
	jmp	.L30
.L28:
	ret
	.cfi_endproc
.LFE12112:
	.size	_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0, .-_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0
	.type	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0:
.LFB12116:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE12116:
	.size	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	.section	.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,"axG",@progbits,_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,comdat
	.weak	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.hidden	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.type	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, @function
_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:
.LFB11614:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L34:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11614:
	.size	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, .-_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.section	.text.nvtxSetInitFunctionsToNoops_v3,"axG",@progbits,nvtxSetInitFunctionsToNoops_v3,comdat
	.weak	nvtxSetInitFunctionsToNoops_v3
	.hidden	nvtxSetInitFunctionsToNoops_v3
	.type	nvtxSetInitFunctionsToNoops_v3, @function
nvtxSetInitFunctionsToNoops_v3:
.LFB6270:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	leaq	nvtxMarkEx_impl_init_v3(%rip), %rdx
	setne	%al
	cmpq	%rdx, 48+nvtxGlobals_v3(%rip)
	je	.L167
	testb	%al, %al
	je	.L39
.L167:
	xorl	%r10d, %r10d
	movq	%r10, 48+nvtxGlobals_v3(%rip)
.L39:
	leaq	nvtxMarkA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 56+nvtxGlobals_v3(%rip)
	je	.L168
	testb	%al, %al
	je	.L41
.L168:
	xorl	%r9d, %r9d
	movq	%r9, 56+nvtxGlobals_v3(%rip)
.L41:
	leaq	nvtxMarkW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 64+nvtxGlobals_v3(%rip)
	je	.L169
	testb	%al, %al
	je	.L43
.L169:
	xorl	%r8d, %r8d
	movq	%r8, 64+nvtxGlobals_v3(%rip)
.L43:
	leaq	nvtxRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 72+nvtxGlobals_v3(%rip)
	je	.L170
	testb	%al, %al
	je	.L45
.L170:
	xorl	%edi, %edi
	movq	%rdi, 72+nvtxGlobals_v3(%rip)
.L45:
	leaq	nvtxRangeStartA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 80+nvtxGlobals_v3(%rip)
	je	.L171
	testb	%al, %al
	je	.L47
.L171:
	xorl	%esi, %esi
	movq	%rsi, 80+nvtxGlobals_v3(%rip)
.L47:
	leaq	nvtxRangeStartW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 88+nvtxGlobals_v3(%rip)
	je	.L172
	testb	%al, %al
	je	.L49
.L172:
	xorl	%ecx, %ecx
	movq	%rcx, 88+nvtxGlobals_v3(%rip)
.L49:
	leaq	nvtxRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 96+nvtxGlobals_v3(%rip)
	je	.L173
	testb	%al, %al
	je	.L51
.L173:
	xorl	%edx, %edx
	movq	%rdx, 96+nvtxGlobals_v3(%rip)
.L51:
	leaq	nvtxRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 104+nvtxGlobals_v3(%rip)
	je	.L174
	testb	%al, %al
	je	.L53
.L174:
	xorl	%r11d, %r11d
	movq	%r11, 104+nvtxGlobals_v3(%rip)
.L53:
	leaq	nvtxRangePushA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 112+nvtxGlobals_v3(%rip)
	je	.L175
	testb	%al, %al
	je	.L55
.L175:
	xorl	%r10d, %r10d
	movq	%r10, 112+nvtxGlobals_v3(%rip)
.L55:
	leaq	nvtxRangePushW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 120+nvtxGlobals_v3(%rip)
	je	.L176
	testb	%al, %al
	je	.L57
.L176:
	xorl	%r9d, %r9d
	movq	%r9, 120+nvtxGlobals_v3(%rip)
.L57:
	leaq	nvtxRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 128+nvtxGlobals_v3(%rip)
	je	.L177
	testb	%al, %al
	je	.L59
.L177:
	xorl	%r8d, %r8d
	movq	%r8, 128+nvtxGlobals_v3(%rip)
.L59:
	leaq	nvtxNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 136+nvtxGlobals_v3(%rip)
	je	.L178
	testb	%al, %al
	je	.L61
.L178:
	xorl	%edi, %edi
	movq	%rdi, 136+nvtxGlobals_v3(%rip)
.L61:
	leaq	nvtxNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 144+nvtxGlobals_v3(%rip)
	je	.L179
	testb	%al, %al
	je	.L63
.L179:
	xorl	%esi, %esi
	movq	%rsi, 144+nvtxGlobals_v3(%rip)
.L63:
	leaq	nvtxNameOsThreadA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 152+nvtxGlobals_v3(%rip)
	je	.L180
	testb	%al, %al
	je	.L65
.L180:
	xorl	%ecx, %ecx
	movq	%rcx, 152+nvtxGlobals_v3(%rip)
.L65:
	leaq	nvtxNameOsThreadW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 160+nvtxGlobals_v3(%rip)
	je	.L181
	testb	%al, %al
	je	.L67
.L181:
	xorl	%edx, %edx
	movq	%rdx, 160+nvtxGlobals_v3(%rip)
.L67:
	leaq	nvtxNameCuDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 168+nvtxGlobals_v3(%rip)
	je	.L182
	testb	%al, %al
	je	.L69
.L182:
	xorl	%r11d, %r11d
	movq	%r11, 168+nvtxGlobals_v3(%rip)
.L69:
	leaq	nvtxNameCuDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 176+nvtxGlobals_v3(%rip)
	je	.L183
	testb	%al, %al
	je	.L71
.L183:
	xorl	%r10d, %r10d
	movq	%r10, 176+nvtxGlobals_v3(%rip)
.L71:
	leaq	nvtxNameCuContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 184+nvtxGlobals_v3(%rip)
	je	.L184
	testb	%al, %al
	je	.L73
.L184:
	xorl	%r9d, %r9d
	movq	%r9, 184+nvtxGlobals_v3(%rip)
.L73:
	leaq	nvtxNameCuContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 192+nvtxGlobals_v3(%rip)
	je	.L185
	testb	%al, %al
	je	.L75
.L185:
	xorl	%r8d, %r8d
	movq	%r8, 192+nvtxGlobals_v3(%rip)
.L75:
	leaq	nvtxNameCuStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 200+nvtxGlobals_v3(%rip)
	je	.L186
	testb	%al, %al
	je	.L77
.L186:
	xorl	%edi, %edi
	movq	%rdi, 200+nvtxGlobals_v3(%rip)
.L77:
	leaq	nvtxNameCuStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 208+nvtxGlobals_v3(%rip)
	je	.L187
	testb	%al, %al
	je	.L79
.L187:
	xorl	%esi, %esi
	movq	%rsi, 208+nvtxGlobals_v3(%rip)
.L79:
	leaq	nvtxNameCuEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 216+nvtxGlobals_v3(%rip)
	je	.L188
	testb	%al, %al
	je	.L81
.L188:
	xorl	%ecx, %ecx
	movq	%rcx, 216+nvtxGlobals_v3(%rip)
.L81:
	leaq	nvtxNameCuEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 224+nvtxGlobals_v3(%rip)
	je	.L189
	testb	%al, %al
	je	.L83
.L189:
	xorl	%edx, %edx
	movq	%rdx, 224+nvtxGlobals_v3(%rip)
.L83:
	leaq	nvtxNameClDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 232+nvtxGlobals_v3(%rip)
	je	.L190
	testb	%al, %al
	je	.L85
.L190:
	xorl	%r11d, %r11d
	movq	%r11, 232+nvtxGlobals_v3(%rip)
.L85:
	leaq	nvtxNameClDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 240+nvtxGlobals_v3(%rip)
	je	.L191
	testb	%al, %al
	je	.L87
.L191:
	xorl	%r10d, %r10d
	movq	%r10, 240+nvtxGlobals_v3(%rip)
.L87:
	leaq	nvtxNameClContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 248+nvtxGlobals_v3(%rip)
	je	.L192
	testb	%al, %al
	je	.L89
.L192:
	xorl	%r9d, %r9d
	movq	%r9, 248+nvtxGlobals_v3(%rip)
.L89:
	leaq	nvtxNameClContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 256+nvtxGlobals_v3(%rip)
	je	.L193
	testb	%al, %al
	je	.L91
.L193:
	xorl	%r8d, %r8d
	movq	%r8, 256+nvtxGlobals_v3(%rip)
.L91:
	leaq	nvtxNameClCommandQueueA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 264+nvtxGlobals_v3(%rip)
	je	.L194
	testb	%al, %al
	je	.L93
.L194:
	xorl	%edi, %edi
	movq	%rdi, 264+nvtxGlobals_v3(%rip)
.L93:
	leaq	nvtxNameClCommandQueueW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 272+nvtxGlobals_v3(%rip)
	je	.L195
	testb	%al, %al
	je	.L95
.L195:
	xorl	%esi, %esi
	movq	%rsi, 272+nvtxGlobals_v3(%rip)
.L95:
	leaq	nvtxNameClMemObjectA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 280+nvtxGlobals_v3(%rip)
	je	.L196
	testb	%al, %al
	je	.L97
.L196:
	xorl	%ecx, %ecx
	movq	%rcx, 280+nvtxGlobals_v3(%rip)
.L97:
	leaq	nvtxNameClMemObjectW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 288+nvtxGlobals_v3(%rip)
	je	.L197
	testb	%al, %al
	je	.L99
.L197:
	xorl	%edx, %edx
	movq	%rdx, 288+nvtxGlobals_v3(%rip)
.L99:
	leaq	nvtxNameClSamplerA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 296+nvtxGlobals_v3(%rip)
	je	.L198
	testb	%al, %al
	je	.L101
.L198:
	xorl	%r11d, %r11d
	movq	%r11, 296+nvtxGlobals_v3(%rip)
.L101:
	leaq	nvtxNameClSamplerW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 304+nvtxGlobals_v3(%rip)
	je	.L199
	testb	%al, %al
	je	.L103
.L199:
	xorl	%r10d, %r10d
	movq	%r10, 304+nvtxGlobals_v3(%rip)
.L103:
	leaq	nvtxNameClProgramA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 312+nvtxGlobals_v3(%rip)
	je	.L200
	testb	%al, %al
	je	.L105
.L200:
	xorl	%r9d, %r9d
	movq	%r9, 312+nvtxGlobals_v3(%rip)
.L105:
	leaq	nvtxNameClProgramW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 320+nvtxGlobals_v3(%rip)
	je	.L201
	testb	%al, %al
	je	.L107
.L201:
	xorl	%r8d, %r8d
	movq	%r8, 320+nvtxGlobals_v3(%rip)
.L107:
	leaq	nvtxNameClEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 328+nvtxGlobals_v3(%rip)
	je	.L202
	testb	%al, %al
	je	.L109
.L202:
	xorl	%edi, %edi
	movq	%rdi, 328+nvtxGlobals_v3(%rip)
.L109:
	leaq	nvtxNameClEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 336+nvtxGlobals_v3(%rip)
	je	.L203
	testb	%al, %al
	je	.L111
.L203:
	xorl	%esi, %esi
	movq	%rsi, 336+nvtxGlobals_v3(%rip)
.L111:
	leaq	nvtxNameCudaDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 344+nvtxGlobals_v3(%rip)
	je	.L204
	testb	%al, %al
	je	.L113
.L204:
	xorl	%ecx, %ecx
	movq	%rcx, 344+nvtxGlobals_v3(%rip)
.L113:
	leaq	nvtxNameCudaDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 352+nvtxGlobals_v3(%rip)
	je	.L205
	testb	%al, %al
	je	.L115
.L205:
	xorl	%edx, %edx
	movq	%rdx, 352+nvtxGlobals_v3(%rip)
.L115:
	leaq	nvtxNameCudaStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 360+nvtxGlobals_v3(%rip)
	je	.L206
	testb	%al, %al
	je	.L117
.L206:
	xorl	%r11d, %r11d
	movq	%r11, 360+nvtxGlobals_v3(%rip)
.L117:
	leaq	nvtxNameCudaStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 368+nvtxGlobals_v3(%rip)
	je	.L207
	testb	%al, %al
	je	.L119
.L207:
	xorl	%r10d, %r10d
	movq	%r10, 368+nvtxGlobals_v3(%rip)
.L119:
	leaq	nvtxNameCudaEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 376+nvtxGlobals_v3(%rip)
	je	.L208
	testb	%al, %al
	je	.L121
.L208:
	xorl	%r9d, %r9d
	movq	%r9, 376+nvtxGlobals_v3(%rip)
.L121:
	leaq	nvtxNameCudaEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 384+nvtxGlobals_v3(%rip)
	je	.L209
	testb	%al, %al
	je	.L123
.L209:
	xorl	%r8d, %r8d
	movq	%r8, 384+nvtxGlobals_v3(%rip)
.L123:
	leaq	nvtxDomainMarkEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 392+nvtxGlobals_v3(%rip)
	je	.L210
	testb	%al, %al
	je	.L125
.L210:
	xorl	%edi, %edi
	movq	%rdi, 392+nvtxGlobals_v3(%rip)
.L125:
	leaq	nvtxDomainRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 400+nvtxGlobals_v3(%rip)
	je	.L211
	testb	%al, %al
	je	.L127
.L211:
	xorl	%esi, %esi
	movq	%rsi, 400+nvtxGlobals_v3(%rip)
.L127:
	leaq	nvtxDomainRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 408+nvtxGlobals_v3(%rip)
	je	.L212
	testb	%al, %al
	je	.L129
.L212:
	xorl	%ecx, %ecx
	movq	%rcx, 408+nvtxGlobals_v3(%rip)
.L129:
	leaq	nvtxDomainRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 416+nvtxGlobals_v3(%rip)
	je	.L213
	testb	%al, %al
	je	.L131
.L213:
	xorl	%edx, %edx
	movq	%rdx, 416+nvtxGlobals_v3(%rip)
.L131:
	leaq	nvtxDomainRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 424+nvtxGlobals_v3(%rip)
	je	.L214
	testb	%al, %al
	je	.L133
.L214:
	xorl	%r11d, %r11d
	movq	%r11, 424+nvtxGlobals_v3(%rip)
.L133:
	leaq	nvtxDomainResourceCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 432+nvtxGlobals_v3(%rip)
	je	.L215
	testb	%al, %al
	je	.L135
.L215:
	xorl	%r10d, %r10d
	movq	%r10, 432+nvtxGlobals_v3(%rip)
.L135:
	leaq	nvtxDomainResourceDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 440+nvtxGlobals_v3(%rip)
	je	.L216
	testb	%al, %al
	je	.L137
.L216:
	xorl	%r9d, %r9d
	movq	%r9, 440+nvtxGlobals_v3(%rip)
.L137:
	leaq	nvtxDomainNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 448+nvtxGlobals_v3(%rip)
	je	.L217
	testb	%al, %al
	je	.L139
.L217:
	xorl	%r8d, %r8d
	movq	%r8, 448+nvtxGlobals_v3(%rip)
.L139:
	leaq	nvtxDomainNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 456+nvtxGlobals_v3(%rip)
	je	.L218
	testb	%al, %al
	je	.L141
.L218:
	xorl	%edi, %edi
	movq	%rdi, 456+nvtxGlobals_v3(%rip)
.L141:
	leaq	nvtxDomainRegisterStringA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 464+nvtxGlobals_v3(%rip)
	je	.L219
	testb	%al, %al
	je	.L143
.L219:
	xorl	%esi, %esi
	movq	%rsi, 464+nvtxGlobals_v3(%rip)
.L143:
	leaq	nvtxDomainRegisterStringW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 472+nvtxGlobals_v3(%rip)
	je	.L220
	testb	%al, %al
	je	.L145
.L220:
	xorl	%ecx, %ecx
	movq	%rcx, 472+nvtxGlobals_v3(%rip)
.L145:
	leaq	nvtxDomainCreateA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 480+nvtxGlobals_v3(%rip)
	je	.L221
	testb	%al, %al
	je	.L147
.L221:
	xorl	%edx, %edx
	movq	%rdx, 480+nvtxGlobals_v3(%rip)
.L147:
	leaq	nvtxDomainCreateW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 488+nvtxGlobals_v3(%rip)
	je	.L222
	testb	%al, %al
	je	.L149
.L222:
	xorl	%r11d, %r11d
	movq	%r11, 488+nvtxGlobals_v3(%rip)
.L149:
	leaq	nvtxDomainDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 496+nvtxGlobals_v3(%rip)
	je	.L223
	testb	%al, %al
	je	.L151
.L223:
	xorl	%r10d, %r10d
	movq	%r10, 496+nvtxGlobals_v3(%rip)
.L151:
	leaq	nvtxInitialize_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 504+nvtxGlobals_v3(%rip)
	je	.L224
	testb	%al, %al
	je	.L153
.L224:
	xorl	%r9d, %r9d
	movq	%r9, 504+nvtxGlobals_v3(%rip)
.L153:
	leaq	nvtxDomainSyncUserCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 512+nvtxGlobals_v3(%rip)
	je	.L225
	testb	%al, %al
	je	.L155
.L225:
	xorl	%r8d, %r8d
	movq	%r8, 512+nvtxGlobals_v3(%rip)
.L155:
	leaq	nvtxDomainSyncUserDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 520+nvtxGlobals_v3(%rip)
	je	.L226
	testb	%al, %al
	je	.L157
.L226:
	xorl	%edi, %edi
	movq	%rdi, 520+nvtxGlobals_v3(%rip)
.L157:
	leaq	nvtxDomainSyncUserAcquireStart_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 528+nvtxGlobals_v3(%rip)
	je	.L227
	testb	%al, %al
	je	.L159
.L227:
	xorl	%esi, %esi
	movq	%rsi, 528+nvtxGlobals_v3(%rip)
.L159:
	leaq	nvtxDomainSyncUserAcquireFailed_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 536+nvtxGlobals_v3(%rip)
	je	.L228
	testb	%al, %al
	je	.L161
.L228:
	xorl	%ecx, %ecx
	movq	%rcx, 536+nvtxGlobals_v3(%rip)
.L161:
	leaq	nvtxDomainSyncUserAcquireSuccess_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 544+nvtxGlobals_v3(%rip)
	je	.L229
	testb	%al, %al
	je	.L163
.L229:
	xorl	%edx, %edx
	movq	%rdx, 544+nvtxGlobals_v3(%rip)
.L163:
	leaq	nvtxDomainSyncUserReleasing_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 552+nvtxGlobals_v3(%rip)
	je	.L230
	testb	%al, %al
	je	.L38
.L230:
	xorl	%eax, %eax
	movq	%rax, 552+nvtxGlobals_v3(%rip)
.L38:
	ret
	.cfi_endproc
.LFE6270:
	.size	nvtxSetInitFunctionsToNoops_v3, .-nvtxSetInitFunctionsToNoops_v3
	.section	.rodata.nvtxInitializeInjectionLibrary_v3.str1.1,"aMS",@progbits,1
.LC0:
	.string	"NVTX_INJECTION64_PATH"
.LC1:
	.string	"InitializeInjectionNvtx2"
	.section	.text.nvtxInitializeInjectionLibrary_v3,"axG",@progbits,nvtxInitializeInjectionLibrary_v3,comdat
	.weak	nvtxInitializeInjectionLibrary_v3
	.hidden	nvtxInitializeInjectionLibrary_v3
	.type	nvtxInitializeInjectionLibrary_v3, @function
nvtxInitializeInjectionLibrary_v3:
.LFB6271:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC0(%rip), %rdi
	call	getenv@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L424
	movl	$1, %esi
	movq	%rax, %rdi
	call	dlopen@PLT
	movl	$4, %edx
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L423
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	dlsym@PLT
	testq	%rax, %rax
	jne	.L426
	movq	%rbx, %rdi
	call	dlclose@PLT
	movl	$5, %edx
	jmp	.L423
.L424:
	movq	InitializeInjectionNvtx2_fnptr(%rip), %rax
	movl	$7, %edx
	testq	%rax, %rax
	je	.L423
.L426:
	leaq	nvtxGetExportTable_v3(%rip), %rdi
	call	*%rax
	xorl	%edx, %edx
	testl	%eax, %eax
	jne	.L423
	testq	%rbx, %rbx
	je	.L427
	movq	%rbx, %rdi
	call	dlclose@PLT
.L427:
	movl	$6, %edx
.L423:
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6271:
	.size	nvtxInitializeInjectionLibrary_v3, .-nvtxInitializeInjectionLibrary_v3
	.section	.text.nvtxInitOnce_v3,"axG",@progbits,nvtxInitOnce_v3,comdat
	.weak	nvtxInitOnce_v3
	.hidden	nvtxInitOnce_v3
	.type	nvtxInitOnce_v3, @function
nvtxInitOnce_v3:
.LFB6272:
	.cfi_startproc
	endbr64
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L443
	pushq	%rdx
	.cfi_def_cfa_offset 16
	movl	$1, %eax
	xorl	%edx, %edx
	mfence
	lock cmpxchgl	%edx, nvtxGlobals_v3(%rip)
	testl	%eax, %eax
	jne	.L446
	call	nvtxInitializeInjectionLibrary_v3
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	call	nvtxSetInitFunctionsToNoops_v3
	movl	$2, %eax
	mfence
	xchgl	nvtxGlobals_v3(%rip), %eax
	jmp	.L435
.L446:
	mfence
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L435
	call	sched_yield@PLT
	jmp	.L446
.L435:
	popq	%rax
	.cfi_def_cfa_offset 8
	ret
.L443:
	ret
	.cfi_endproc
.LFE6272:
	.size	nvtxInitOnce_v3, .-nvtxInitOnce_v3
	.section	.text.nvtxDomainSyncUserReleasing_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserReleasing_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserReleasing_impl_init_v3
	.hidden	nvtxDomainSyncUserReleasing_impl_init_v3
	.type	nvtxDomainSyncUserReleasing_impl_init_v3, @function
nvtxDomainSyncUserReleasing_impl_init_v3:
.LFB6269:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	552+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L447
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L447:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6269:
	.size	nvtxDomainSyncUserReleasing_impl_init_v3, .-nvtxDomainSyncUserReleasing_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireSuccess_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireSuccess_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.type	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, @function
nvtxDomainSyncUserAcquireSuccess_impl_init_v3:
.LFB6268:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	544+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L450
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L450:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6268:
	.size	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, .-nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireFailed_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireFailed_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.type	nvtxDomainSyncUserAcquireFailed_impl_init_v3, @function
nvtxDomainSyncUserAcquireFailed_impl_init_v3:
.LFB6267:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	536+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L453
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L453:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6267:
	.size	nvtxDomainSyncUserAcquireFailed_impl_init_v3, .-nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireStart_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireStart_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.type	nvtxDomainSyncUserAcquireStart_impl_init_v3, @function
nvtxDomainSyncUserAcquireStart_impl_init_v3:
.LFB6266:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	528+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L456
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L456:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6266:
	.size	nvtxDomainSyncUserAcquireStart_impl_init_v3, .-nvtxDomainSyncUserAcquireStart_impl_init_v3
	.section	.text.nvtxDomainSyncUserDestroy_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserDestroy_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserDestroy_impl_init_v3
	.hidden	nvtxDomainSyncUserDestroy_impl_init_v3
	.type	nvtxDomainSyncUserDestroy_impl_init_v3, @function
nvtxDomainSyncUserDestroy_impl_init_v3:
.LFB6265:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	520+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L459
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L459:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6265:
	.size	nvtxDomainSyncUserDestroy_impl_init_v3, .-nvtxDomainSyncUserDestroy_impl_init_v3
	.section	.text.nvtxDomainSyncUserCreate_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserCreate_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserCreate_impl_init_v3
	.hidden	nvtxDomainSyncUserCreate_impl_init_v3
	.type	nvtxDomainSyncUserCreate_impl_init_v3, @function
nvtxDomainSyncUserCreate_impl_init_v3:
.LFB6264:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	512+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L463
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L463:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6264:
	.size	nvtxDomainSyncUserCreate_impl_init_v3, .-nvtxDomainSyncUserCreate_impl_init_v3
	.section	.text.nvtxInitialize_impl_init_v3,"axG",@progbits,nvtxInitialize_impl_init_v3,comdat
	.weak	nvtxInitialize_impl_init_v3
	.hidden	nvtxInitialize_impl_init_v3
	.type	nvtxInitialize_impl_init_v3, @function
nvtxInitialize_impl_init_v3:
.LFB6235:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	504+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L465
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L465:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6235:
	.size	nvtxInitialize_impl_init_v3, .-nvtxInitialize_impl_init_v3
	.section	.text.nvtxDomainDestroy_impl_init_v3,"axG",@progbits,nvtxDomainDestroy_impl_init_v3,comdat
	.weak	nvtxDomainDestroy_impl_init_v3
	.hidden	nvtxDomainDestroy_impl_init_v3
	.type	nvtxDomainDestroy_impl_init_v3, @function
nvtxDomainDestroy_impl_init_v3:
.LFB6234:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	496+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L468
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L468:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6234:
	.size	nvtxDomainDestroy_impl_init_v3, .-nvtxDomainDestroy_impl_init_v3
	.section	.text.nvtxDomainCreateW_impl_init_v3,"axG",@progbits,nvtxDomainCreateW_impl_init_v3,comdat
	.weak	nvtxDomainCreateW_impl_init_v3
	.hidden	nvtxDomainCreateW_impl_init_v3
	.type	nvtxDomainCreateW_impl_init_v3, @function
nvtxDomainCreateW_impl_init_v3:
.LFB6233:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	488+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L472
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L472:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6233:
	.size	nvtxDomainCreateW_impl_init_v3, .-nvtxDomainCreateW_impl_init_v3
	.section	.text.nvtxDomainCreateA_impl_init_v3,"axG",@progbits,nvtxDomainCreateA_impl_init_v3,comdat
	.weak	nvtxDomainCreateA_impl_init_v3
	.hidden	nvtxDomainCreateA_impl_init_v3
	.type	nvtxDomainCreateA_impl_init_v3, @function
nvtxDomainCreateA_impl_init_v3:
.LFB6232:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	480+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L475
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L475:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6232:
	.size	nvtxDomainCreateA_impl_init_v3, .-nvtxDomainCreateA_impl_init_v3
	.section	.text.nvtxDomainRegisterStringW_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringW_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringW_impl_init_v3
	.hidden	nvtxDomainRegisterStringW_impl_init_v3
	.type	nvtxDomainRegisterStringW_impl_init_v3, @function
nvtxDomainRegisterStringW_impl_init_v3:
.LFB6231:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	472+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L478
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L478:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6231:
	.size	nvtxDomainRegisterStringW_impl_init_v3, .-nvtxDomainRegisterStringW_impl_init_v3
	.section	.text.nvtxDomainRegisterStringA_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringA_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringA_impl_init_v3
	.hidden	nvtxDomainRegisterStringA_impl_init_v3
	.type	nvtxDomainRegisterStringA_impl_init_v3, @function
nvtxDomainRegisterStringA_impl_init_v3:
.LFB6230:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	464+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L481
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L481:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6230:
	.size	nvtxDomainRegisterStringA_impl_init_v3, .-nvtxDomainRegisterStringA_impl_init_v3
	.section	.text.nvtxDomainNameCategoryW_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryW_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryW_impl_init_v3
	.hidden	nvtxDomainNameCategoryW_impl_init_v3
	.type	nvtxDomainNameCategoryW_impl_init_v3, @function
nvtxDomainNameCategoryW_impl_init_v3:
.LFB6229:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	456+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L483
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L483:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6229:
	.size	nvtxDomainNameCategoryW_impl_init_v3, .-nvtxDomainNameCategoryW_impl_init_v3
	.section	.text.nvtxDomainNameCategoryA_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryA_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryA_impl_init_v3
	.hidden	nvtxDomainNameCategoryA_impl_init_v3
	.type	nvtxDomainNameCategoryA_impl_init_v3, @function
nvtxDomainNameCategoryA_impl_init_v3:
.LFB6228:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	448+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L486
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L486:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6228:
	.size	nvtxDomainNameCategoryA_impl_init_v3, .-nvtxDomainNameCategoryA_impl_init_v3
	.section	.text.nvtxDomainResourceDestroy_impl_init_v3,"axG",@progbits,nvtxDomainResourceDestroy_impl_init_v3,comdat
	.weak	nvtxDomainResourceDestroy_impl_init_v3
	.hidden	nvtxDomainResourceDestroy_impl_init_v3
	.type	nvtxDomainResourceDestroy_impl_init_v3, @function
nvtxDomainResourceDestroy_impl_init_v3:
.LFB6227:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	440+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L489
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L489:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6227:
	.size	nvtxDomainResourceDestroy_impl_init_v3, .-nvtxDomainResourceDestroy_impl_init_v3
	.section	.text.nvtxDomainResourceCreate_impl_init_v3,"axG",@progbits,nvtxDomainResourceCreate_impl_init_v3,comdat
	.weak	nvtxDomainResourceCreate_impl_init_v3
	.hidden	nvtxDomainResourceCreate_impl_init_v3
	.type	nvtxDomainResourceCreate_impl_init_v3, @function
nvtxDomainResourceCreate_impl_init_v3:
.LFB6226:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	432+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L493
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L493:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6226:
	.size	nvtxDomainResourceCreate_impl_init_v3, .-nvtxDomainResourceCreate_impl_init_v3
	.section	.text.nvtxDomainRangePop_impl_init_v3,"axG",@progbits,nvtxDomainRangePop_impl_init_v3,comdat
	.weak	nvtxDomainRangePop_impl_init_v3
	.hidden	nvtxDomainRangePop_impl_init_v3
	.type	nvtxDomainRangePop_impl_init_v3, @function
nvtxDomainRangePop_impl_init_v3:
.LFB6225:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	424+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L496
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L496:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6225:
	.size	nvtxDomainRangePop_impl_init_v3, .-nvtxDomainRangePop_impl_init_v3
	.section	.text.nvtxDomainRangePushEx_impl_init_v3,"axG",@progbits,nvtxDomainRangePushEx_impl_init_v3,comdat
	.weak	nvtxDomainRangePushEx_impl_init_v3
	.hidden	nvtxDomainRangePushEx_impl_init_v3
	.type	nvtxDomainRangePushEx_impl_init_v3, @function
nvtxDomainRangePushEx_impl_init_v3:
.LFB6224:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	416+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L499
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L499:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6224:
	.size	nvtxDomainRangePushEx_impl_init_v3, .-nvtxDomainRangePushEx_impl_init_v3
	.section	.text.nvtxDomainRangeEnd_impl_init_v3,"axG",@progbits,nvtxDomainRangeEnd_impl_init_v3,comdat
	.weak	nvtxDomainRangeEnd_impl_init_v3
	.hidden	nvtxDomainRangeEnd_impl_init_v3
	.type	nvtxDomainRangeEnd_impl_init_v3, @function
nvtxDomainRangeEnd_impl_init_v3:
.LFB6223:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	408+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L501
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L501:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6223:
	.size	nvtxDomainRangeEnd_impl_init_v3, .-nvtxDomainRangeEnd_impl_init_v3
	.section	.text.nvtxDomainRangeStartEx_impl_init_v3,"axG",@progbits,nvtxDomainRangeStartEx_impl_init_v3,comdat
	.weak	nvtxDomainRangeStartEx_impl_init_v3
	.hidden	nvtxDomainRangeStartEx_impl_init_v3
	.type	nvtxDomainRangeStartEx_impl_init_v3, @function
nvtxDomainRangeStartEx_impl_init_v3:
.LFB6222:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	400+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L505
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L505:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6222:
	.size	nvtxDomainRangeStartEx_impl_init_v3, .-nvtxDomainRangeStartEx_impl_init_v3
	.section	.text.nvtxDomainMarkEx_impl_init_v3,"axG",@progbits,nvtxDomainMarkEx_impl_init_v3,comdat
	.weak	nvtxDomainMarkEx_impl_init_v3
	.hidden	nvtxDomainMarkEx_impl_init_v3
	.type	nvtxDomainMarkEx_impl_init_v3, @function
nvtxDomainMarkEx_impl_init_v3:
.LFB6221:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	392+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L507
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L507:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6221:
	.size	nvtxDomainMarkEx_impl_init_v3, .-nvtxDomainMarkEx_impl_init_v3
	.section	.text.nvtxNameCudaEventW_impl_init_v3,"axG",@progbits,nvtxNameCudaEventW_impl_init_v3,comdat
	.weak	nvtxNameCudaEventW_impl_init_v3
	.hidden	nvtxNameCudaEventW_impl_init_v3
	.type	nvtxNameCudaEventW_impl_init_v3, @function
nvtxNameCudaEventW_impl_init_v3:
.LFB6249:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	384+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L510
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L510:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6249:
	.size	nvtxNameCudaEventW_impl_init_v3, .-nvtxNameCudaEventW_impl_init_v3
	.section	.text.nvtxNameCudaEventA_impl_init_v3,"axG",@progbits,nvtxNameCudaEventA_impl_init_v3,comdat
	.weak	nvtxNameCudaEventA_impl_init_v3
	.hidden	nvtxNameCudaEventA_impl_init_v3
	.type	nvtxNameCudaEventA_impl_init_v3, @function
nvtxNameCudaEventA_impl_init_v3:
.LFB6248:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	376+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L513
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L513:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6248:
	.size	nvtxNameCudaEventA_impl_init_v3, .-nvtxNameCudaEventA_impl_init_v3
	.section	.text.nvtxNameCudaStreamW_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamW_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamW_impl_init_v3
	.hidden	nvtxNameCudaStreamW_impl_init_v3
	.type	nvtxNameCudaStreamW_impl_init_v3, @function
nvtxNameCudaStreamW_impl_init_v3:
.LFB6247:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	368+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L516
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L516:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6247:
	.size	nvtxNameCudaStreamW_impl_init_v3, .-nvtxNameCudaStreamW_impl_init_v3
	.section	.text.nvtxNameCudaStreamA_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamA_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamA_impl_init_v3
	.hidden	nvtxNameCudaStreamA_impl_init_v3
	.type	nvtxNameCudaStreamA_impl_init_v3, @function
nvtxNameCudaStreamA_impl_init_v3:
.LFB6246:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	360+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L519
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L519:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6246:
	.size	nvtxNameCudaStreamA_impl_init_v3, .-nvtxNameCudaStreamA_impl_init_v3
	.section	.text.nvtxNameCudaDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceW_impl_init_v3
	.hidden	nvtxNameCudaDeviceW_impl_init_v3
	.type	nvtxNameCudaDeviceW_impl_init_v3, @function
nvtxNameCudaDeviceW_impl_init_v3:
.LFB6245:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	352+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L522
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L522:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6245:
	.size	nvtxNameCudaDeviceW_impl_init_v3, .-nvtxNameCudaDeviceW_impl_init_v3
	.section	.text.nvtxNameCudaDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceA_impl_init_v3
	.hidden	nvtxNameCudaDeviceA_impl_init_v3
	.type	nvtxNameCudaDeviceA_impl_init_v3, @function
nvtxNameCudaDeviceA_impl_init_v3:
.LFB6244:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	344+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L525
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L525:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6244:
	.size	nvtxNameCudaDeviceA_impl_init_v3, .-nvtxNameCudaDeviceA_impl_init_v3
	.section	.text.nvtxNameClEventW_impl_init_v3,"axG",@progbits,nvtxNameClEventW_impl_init_v3,comdat
	.weak	nvtxNameClEventW_impl_init_v3
	.hidden	nvtxNameClEventW_impl_init_v3
	.type	nvtxNameClEventW_impl_init_v3, @function
nvtxNameClEventW_impl_init_v3:
.LFB6263:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	336+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L528
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L528:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6263:
	.size	nvtxNameClEventW_impl_init_v3, .-nvtxNameClEventW_impl_init_v3
	.section	.text.nvtxNameClEventA_impl_init_v3,"axG",@progbits,nvtxNameClEventA_impl_init_v3,comdat
	.weak	nvtxNameClEventA_impl_init_v3
	.hidden	nvtxNameClEventA_impl_init_v3
	.type	nvtxNameClEventA_impl_init_v3, @function
nvtxNameClEventA_impl_init_v3:
.LFB6262:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	328+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L531
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L531:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6262:
	.size	nvtxNameClEventA_impl_init_v3, .-nvtxNameClEventA_impl_init_v3
	.section	.text.nvtxNameClProgramW_impl_init_v3,"axG",@progbits,nvtxNameClProgramW_impl_init_v3,comdat
	.weak	nvtxNameClProgramW_impl_init_v3
	.hidden	nvtxNameClProgramW_impl_init_v3
	.type	nvtxNameClProgramW_impl_init_v3, @function
nvtxNameClProgramW_impl_init_v3:
.LFB6261:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	320+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L534
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L534:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6261:
	.size	nvtxNameClProgramW_impl_init_v3, .-nvtxNameClProgramW_impl_init_v3
	.section	.text.nvtxNameClProgramA_impl_init_v3,"axG",@progbits,nvtxNameClProgramA_impl_init_v3,comdat
	.weak	nvtxNameClProgramA_impl_init_v3
	.hidden	nvtxNameClProgramA_impl_init_v3
	.type	nvtxNameClProgramA_impl_init_v3, @function
nvtxNameClProgramA_impl_init_v3:
.LFB6260:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	312+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L537
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L537:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6260:
	.size	nvtxNameClProgramA_impl_init_v3, .-nvtxNameClProgramA_impl_init_v3
	.section	.text.nvtxNameClSamplerW_impl_init_v3,"axG",@progbits,nvtxNameClSamplerW_impl_init_v3,comdat
	.weak	nvtxNameClSamplerW_impl_init_v3
	.hidden	nvtxNameClSamplerW_impl_init_v3
	.type	nvtxNameClSamplerW_impl_init_v3, @function
nvtxNameClSamplerW_impl_init_v3:
.LFB6259:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	304+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L540
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L540:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6259:
	.size	nvtxNameClSamplerW_impl_init_v3, .-nvtxNameClSamplerW_impl_init_v3
	.section	.text.nvtxNameClSamplerA_impl_init_v3,"axG",@progbits,nvtxNameClSamplerA_impl_init_v3,comdat
	.weak	nvtxNameClSamplerA_impl_init_v3
	.hidden	nvtxNameClSamplerA_impl_init_v3
	.type	nvtxNameClSamplerA_impl_init_v3, @function
nvtxNameClSamplerA_impl_init_v3:
.LFB6258:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	296+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L543
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L543:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6258:
	.size	nvtxNameClSamplerA_impl_init_v3, .-nvtxNameClSamplerA_impl_init_v3
	.section	.text.nvtxNameClMemObjectW_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectW_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectW_impl_init_v3
	.hidden	nvtxNameClMemObjectW_impl_init_v3
	.type	nvtxNameClMemObjectW_impl_init_v3, @function
nvtxNameClMemObjectW_impl_init_v3:
.LFB6257:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	288+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L546
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L546:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6257:
	.size	nvtxNameClMemObjectW_impl_init_v3, .-nvtxNameClMemObjectW_impl_init_v3
	.section	.text.nvtxNameClMemObjectA_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectA_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectA_impl_init_v3
	.hidden	nvtxNameClMemObjectA_impl_init_v3
	.type	nvtxNameClMemObjectA_impl_init_v3, @function
nvtxNameClMemObjectA_impl_init_v3:
.LFB6256:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	280+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L549
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L549:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6256:
	.size	nvtxNameClMemObjectA_impl_init_v3, .-nvtxNameClMemObjectA_impl_init_v3
	.section	.text.nvtxNameClCommandQueueW_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueW_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueW_impl_init_v3
	.hidden	nvtxNameClCommandQueueW_impl_init_v3
	.type	nvtxNameClCommandQueueW_impl_init_v3, @function
nvtxNameClCommandQueueW_impl_init_v3:
.LFB6255:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	272+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L552
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L552:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6255:
	.size	nvtxNameClCommandQueueW_impl_init_v3, .-nvtxNameClCommandQueueW_impl_init_v3
	.section	.text.nvtxNameClCommandQueueA_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueA_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueA_impl_init_v3
	.hidden	nvtxNameClCommandQueueA_impl_init_v3
	.type	nvtxNameClCommandQueueA_impl_init_v3, @function
nvtxNameClCommandQueueA_impl_init_v3:
.LFB6254:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	264+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L555
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L555:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6254:
	.size	nvtxNameClCommandQueueA_impl_init_v3, .-nvtxNameClCommandQueueA_impl_init_v3
	.section	.text.nvtxNameClContextW_impl_init_v3,"axG",@progbits,nvtxNameClContextW_impl_init_v3,comdat
	.weak	nvtxNameClContextW_impl_init_v3
	.hidden	nvtxNameClContextW_impl_init_v3
	.type	nvtxNameClContextW_impl_init_v3, @function
nvtxNameClContextW_impl_init_v3:
.LFB6253:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	256+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L558
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L558:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6253:
	.size	nvtxNameClContextW_impl_init_v3, .-nvtxNameClContextW_impl_init_v3
	.section	.text.nvtxNameClContextA_impl_init_v3,"axG",@progbits,nvtxNameClContextA_impl_init_v3,comdat
	.weak	nvtxNameClContextA_impl_init_v3
	.hidden	nvtxNameClContextA_impl_init_v3
	.type	nvtxNameClContextA_impl_init_v3, @function
nvtxNameClContextA_impl_init_v3:
.LFB6252:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	248+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L561
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L561:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6252:
	.size	nvtxNameClContextA_impl_init_v3, .-nvtxNameClContextA_impl_init_v3
	.section	.text.nvtxNameClDeviceW_impl_init_v3,"axG",@progbits,nvtxNameClDeviceW_impl_init_v3,comdat
	.weak	nvtxNameClDeviceW_impl_init_v3
	.hidden	nvtxNameClDeviceW_impl_init_v3
	.type	nvtxNameClDeviceW_impl_init_v3, @function
nvtxNameClDeviceW_impl_init_v3:
.LFB6251:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	240+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L564
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L564:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6251:
	.size	nvtxNameClDeviceW_impl_init_v3, .-nvtxNameClDeviceW_impl_init_v3
	.section	.text.nvtxNameClDeviceA_impl_init_v3,"axG",@progbits,nvtxNameClDeviceA_impl_init_v3,comdat
	.weak	nvtxNameClDeviceA_impl_init_v3
	.hidden	nvtxNameClDeviceA_impl_init_v3
	.type	nvtxNameClDeviceA_impl_init_v3, @function
nvtxNameClDeviceA_impl_init_v3:
.LFB6250:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	232+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L567
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L567:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6250:
	.size	nvtxNameClDeviceA_impl_init_v3, .-nvtxNameClDeviceA_impl_init_v3
	.section	.text.nvtxNameCuEventW_impl_init_v3,"axG",@progbits,nvtxNameCuEventW_impl_init_v3,comdat
	.weak	nvtxNameCuEventW_impl_init_v3
	.hidden	nvtxNameCuEventW_impl_init_v3
	.type	nvtxNameCuEventW_impl_init_v3, @function
nvtxNameCuEventW_impl_init_v3:
.LFB6243:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	224+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L570
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L570:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6243:
	.size	nvtxNameCuEventW_impl_init_v3, .-nvtxNameCuEventW_impl_init_v3
	.section	.text.nvtxNameCuEventA_impl_init_v3,"axG",@progbits,nvtxNameCuEventA_impl_init_v3,comdat
	.weak	nvtxNameCuEventA_impl_init_v3
	.hidden	nvtxNameCuEventA_impl_init_v3
	.type	nvtxNameCuEventA_impl_init_v3, @function
nvtxNameCuEventA_impl_init_v3:
.LFB6242:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	216+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L573
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L573:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6242:
	.size	nvtxNameCuEventA_impl_init_v3, .-nvtxNameCuEventA_impl_init_v3
	.section	.text.nvtxNameCuStreamW_impl_init_v3,"axG",@progbits,nvtxNameCuStreamW_impl_init_v3,comdat
	.weak	nvtxNameCuStreamW_impl_init_v3
	.hidden	nvtxNameCuStreamW_impl_init_v3
	.type	nvtxNameCuStreamW_impl_init_v3, @function
nvtxNameCuStreamW_impl_init_v3:
.LFB6241:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	208+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L576
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L576:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6241:
	.size	nvtxNameCuStreamW_impl_init_v3, .-nvtxNameCuStreamW_impl_init_v3
	.section	.text.nvtxNameCuStreamA_impl_init_v3,"axG",@progbits,nvtxNameCuStreamA_impl_init_v3,comdat
	.weak	nvtxNameCuStreamA_impl_init_v3
	.hidden	nvtxNameCuStreamA_impl_init_v3
	.type	nvtxNameCuStreamA_impl_init_v3, @function
nvtxNameCuStreamA_impl_init_v3:
.LFB6240:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	200+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L579
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L579:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6240:
	.size	nvtxNameCuStreamA_impl_init_v3, .-nvtxNameCuStreamA_impl_init_v3
	.section	.text.nvtxNameCuContextW_impl_init_v3,"axG",@progbits,nvtxNameCuContextW_impl_init_v3,comdat
	.weak	nvtxNameCuContextW_impl_init_v3
	.hidden	nvtxNameCuContextW_impl_init_v3
	.type	nvtxNameCuContextW_impl_init_v3, @function
nvtxNameCuContextW_impl_init_v3:
.LFB6239:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	192+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L582
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L582:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6239:
	.size	nvtxNameCuContextW_impl_init_v3, .-nvtxNameCuContextW_impl_init_v3
	.section	.text.nvtxNameCuContextA_impl_init_v3,"axG",@progbits,nvtxNameCuContextA_impl_init_v3,comdat
	.weak	nvtxNameCuContextA_impl_init_v3
	.hidden	nvtxNameCuContextA_impl_init_v3
	.type	nvtxNameCuContextA_impl_init_v3, @function
nvtxNameCuContextA_impl_init_v3:
.LFB6238:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	184+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L585
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L585:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6238:
	.size	nvtxNameCuContextA_impl_init_v3, .-nvtxNameCuContextA_impl_init_v3
	.section	.text.nvtxNameCuDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceW_impl_init_v3
	.hidden	nvtxNameCuDeviceW_impl_init_v3
	.type	nvtxNameCuDeviceW_impl_init_v3, @function
nvtxNameCuDeviceW_impl_init_v3:
.LFB6237:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	176+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L588
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L588:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6237:
	.size	nvtxNameCuDeviceW_impl_init_v3, .-nvtxNameCuDeviceW_impl_init_v3
	.section	.text.nvtxNameCuDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceA_impl_init_v3
	.hidden	nvtxNameCuDeviceA_impl_init_v3
	.type	nvtxNameCuDeviceA_impl_init_v3, @function
nvtxNameCuDeviceA_impl_init_v3:
.LFB6236:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	168+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L591
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L591:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6236:
	.size	nvtxNameCuDeviceA_impl_init_v3, .-nvtxNameCuDeviceA_impl_init_v3
	.section	.text.nvtxNameOsThreadW_impl_init_v3,"axG",@progbits,nvtxNameOsThreadW_impl_init_v3,comdat
	.weak	nvtxNameOsThreadW_impl_init_v3
	.hidden	nvtxNameOsThreadW_impl_init_v3
	.type	nvtxNameOsThreadW_impl_init_v3, @function
nvtxNameOsThreadW_impl_init_v3:
.LFB6220:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	160+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L594
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L594:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6220:
	.size	nvtxNameOsThreadW_impl_init_v3, .-nvtxNameOsThreadW_impl_init_v3
	.section	.text.nvtxNameOsThreadA_impl_init_v3,"axG",@progbits,nvtxNameOsThreadA_impl_init_v3,comdat
	.weak	nvtxNameOsThreadA_impl_init_v3
	.hidden	nvtxNameOsThreadA_impl_init_v3
	.type	nvtxNameOsThreadA_impl_init_v3, @function
nvtxNameOsThreadA_impl_init_v3:
.LFB6219:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	152+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L597
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L597:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6219:
	.size	nvtxNameOsThreadA_impl_init_v3, .-nvtxNameOsThreadA_impl_init_v3
	.section	.text.nvtxNameCategoryW_impl_init_v3,"axG",@progbits,nvtxNameCategoryW_impl_init_v3,comdat
	.weak	nvtxNameCategoryW_impl_init_v3
	.hidden	nvtxNameCategoryW_impl_init_v3
	.type	nvtxNameCategoryW_impl_init_v3, @function
nvtxNameCategoryW_impl_init_v3:
.LFB6218:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	144+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L600
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L600:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6218:
	.size	nvtxNameCategoryW_impl_init_v3, .-nvtxNameCategoryW_impl_init_v3
	.section	.text.nvtxNameCategoryA_impl_init_v3,"axG",@progbits,nvtxNameCategoryA_impl_init_v3,comdat
	.weak	nvtxNameCategoryA_impl_init_v3
	.hidden	nvtxNameCategoryA_impl_init_v3
	.type	nvtxNameCategoryA_impl_init_v3, @function
nvtxNameCategoryA_impl_init_v3:
.LFB6217:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	136+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L603
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L603:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6217:
	.size	nvtxNameCategoryA_impl_init_v3, .-nvtxNameCategoryA_impl_init_v3
	.section	.text.nvtxRangePop_impl_init_v3,"axG",@progbits,nvtxRangePop_impl_init_v3,comdat
	.weak	nvtxRangePop_impl_init_v3
	.hidden	nvtxRangePop_impl_init_v3
	.type	nvtxRangePop_impl_init_v3, @function
nvtxRangePop_impl_init_v3:
.LFB6216:
	.cfi_startproc
	endbr64
	pushq	%rsi
	.cfi_def_cfa_offset 16
	call	nvtxInitOnce_v3
	movq	128+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L607
	popq	%rcx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L607:
	.cfi_restore_state
	movl	$-2, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6216:
	.size	nvtxRangePop_impl_init_v3, .-nvtxRangePop_impl_init_v3
	.section	.text.nvtxRangePushW_impl_init_v3,"axG",@progbits,nvtxRangePushW_impl_init_v3,comdat
	.weak	nvtxRangePushW_impl_init_v3
	.hidden	nvtxRangePushW_impl_init_v3
	.type	nvtxRangePushW_impl_init_v3, @function
nvtxRangePushW_impl_init_v3:
.LFB6215:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	120+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L610
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L610:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6215:
	.size	nvtxRangePushW_impl_init_v3, .-nvtxRangePushW_impl_init_v3
	.section	.text.nvtxRangePushA_impl_init_v3,"axG",@progbits,nvtxRangePushA_impl_init_v3,comdat
	.weak	nvtxRangePushA_impl_init_v3
	.hidden	nvtxRangePushA_impl_init_v3
	.type	nvtxRangePushA_impl_init_v3, @function
nvtxRangePushA_impl_init_v3:
.LFB6214:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	112+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L613
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L613:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6214:
	.size	nvtxRangePushA_impl_init_v3, .-nvtxRangePushA_impl_init_v3
	.section	.text.nvtxRangePushEx_impl_init_v3,"axG",@progbits,nvtxRangePushEx_impl_init_v3,comdat
	.weak	nvtxRangePushEx_impl_init_v3
	.hidden	nvtxRangePushEx_impl_init_v3
	.type	nvtxRangePushEx_impl_init_v3, @function
nvtxRangePushEx_impl_init_v3:
.LFB6213:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	104+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L616
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L616:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6213:
	.size	nvtxRangePushEx_impl_init_v3, .-nvtxRangePushEx_impl_init_v3
	.section	.text.nvtxRangeEnd_impl_init_v3,"axG",@progbits,nvtxRangeEnd_impl_init_v3,comdat
	.weak	nvtxRangeEnd_impl_init_v3
	.hidden	nvtxRangeEnd_impl_init_v3
	.type	nvtxRangeEnd_impl_init_v3, @function
nvtxRangeEnd_impl_init_v3:
.LFB6212:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	96+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L618
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L618:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6212:
	.size	nvtxRangeEnd_impl_init_v3, .-nvtxRangeEnd_impl_init_v3
	.section	.text.nvtxRangeStartW_impl_init_v3,"axG",@progbits,nvtxRangeStartW_impl_init_v3,comdat
	.weak	nvtxRangeStartW_impl_init_v3
	.hidden	nvtxRangeStartW_impl_init_v3
	.type	nvtxRangeStartW_impl_init_v3, @function
nvtxRangeStartW_impl_init_v3:
.LFB6211:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	88+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L622
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L622:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6211:
	.size	nvtxRangeStartW_impl_init_v3, .-nvtxRangeStartW_impl_init_v3
	.section	.text.nvtxRangeStartA_impl_init_v3,"axG",@progbits,nvtxRangeStartA_impl_init_v3,comdat
	.weak	nvtxRangeStartA_impl_init_v3
	.hidden	nvtxRangeStartA_impl_init_v3
	.type	nvtxRangeStartA_impl_init_v3, @function
nvtxRangeStartA_impl_init_v3:
.LFB6210:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	80+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L625
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L625:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6210:
	.size	nvtxRangeStartA_impl_init_v3, .-nvtxRangeStartA_impl_init_v3
	.section	.text.nvtxRangeStartEx_impl_init_v3,"axG",@progbits,nvtxRangeStartEx_impl_init_v3,comdat
	.weak	nvtxRangeStartEx_impl_init_v3
	.hidden	nvtxRangeStartEx_impl_init_v3
	.type	nvtxRangeStartEx_impl_init_v3, @function
nvtxRangeStartEx_impl_init_v3:
.LFB6209:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	72+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L628
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L628:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6209:
	.size	nvtxRangeStartEx_impl_init_v3, .-nvtxRangeStartEx_impl_init_v3
	.section	.text.nvtxMarkW_impl_init_v3,"axG",@progbits,nvtxMarkW_impl_init_v3,comdat
	.weak	nvtxMarkW_impl_init_v3
	.hidden	nvtxMarkW_impl_init_v3
	.type	nvtxMarkW_impl_init_v3, @function
nvtxMarkW_impl_init_v3:
.LFB6208:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	64+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L630
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L630:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6208:
	.size	nvtxMarkW_impl_init_v3, .-nvtxMarkW_impl_init_v3
	.section	.text.nvtxMarkA_impl_init_v3,"axG",@progbits,nvtxMarkA_impl_init_v3,comdat
	.weak	nvtxMarkA_impl_init_v3
	.hidden	nvtxMarkA_impl_init_v3
	.type	nvtxMarkA_impl_init_v3, @function
nvtxMarkA_impl_init_v3:
.LFB6207:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	56+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L633
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L633:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6207:
	.size	nvtxMarkA_impl_init_v3, .-nvtxMarkA_impl_init_v3
	.section	.text.nvtxMarkEx_impl_init_v3,"axG",@progbits,nvtxMarkEx_impl_init_v3,comdat
	.weak	nvtxMarkEx_impl_init_v3
	.hidden	nvtxMarkEx_impl_init_v3
	.type	nvtxMarkEx_impl_init_v3, @function
nvtxMarkEx_impl_init_v3:
.LFB6206:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	48+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L636
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L636:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6206:
	.size	nvtxMarkEx_impl_init_v3, .-nvtxMarkEx_impl_init_v3
	.text
	.globl	_Z8chechalliPbiiiPiS0_S0_iiPS0_
	.type	_Z8chechalliPbiiiPiS0_S0_iiPS0_, @function
_Z8chechalliPbiiiPiS0_S0_iiPS0_:
.LFB11185:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE11185:
	.size	_Z8chechalliPbiiiPiS0_S0_iiPS0_, .-_Z8chechalliPbiiiPiS0_S0_iiPS0_
	.globl	_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_
	.type	_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_, @function
_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_:
.LFB11211:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L641
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z8findhashPiS_S_S_PbS0_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L641:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L643
	call	__stack_chk_fail@PLT
.L643:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11211:
	.size	_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_, .-_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_
	.globl	_Z8findhashPiS_S_S_PbS0_S_S_
	.type	_Z8findhashPiS_S_S_PbS0_S_S_, @function
_Z8findhashPiS_S_S_PbS0_S_S_:
.LFB11212:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_
	.cfi_endproc
.LFE11212:
	.size	_Z8findhashPiS_S_S_PbS0_S_S_, .-_Z8findhashPiS_S_S_PbS0_S_S_
	.globl	_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb
	.type	_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb, @function
_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb:
.LFB11213:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L646
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7setdeg1PiS_S_Pb(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L646:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L648
	call	__stack_chk_fail@PLT
.L648:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11213:
	.size	_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb, .-_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb
	.globl	_Z7setdeg1PiS_S_Pb
	.type	_Z7setdeg1PiS_S_Pb, @function
_Z7setdeg1PiS_S_Pb:
.LFB11214:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb
	.cfi_endproc
.LFE11214:
	.size	_Z7setdeg1PiS_S_Pb, .-_Z7setdeg1PiS_S_Pb
	.globl	_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_
	.type	_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_, @function
_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_:
.LFB11215:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L651
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z7puttoidPiS_S_S_PbS_S_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L651:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L653
	call	__stack_chk_fail@PLT
.L653:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11215:
	.size	_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_, .-_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_
	.globl	_Z7puttoidPiS_S_S_PbS_S_
	.type	_Z7puttoidPiS_S_S_PbS_S_, @function
_Z7puttoidPiS_S_S_PbS_S_:
.LFB11216:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_
	.cfi_endproc
.LFE11216:
	.size	_Z7puttoidPiS_S_S_PbS_S_, .-_Z7puttoidPiS_S_S_PbS_S_
	.globl	_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_
	.type	_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_, @function
_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_:
.LFB11217:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L656
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z7findcvsiPiS_S_S_S_S_PS_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L656:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L658
	call	__stack_chk_fail@PLT
.L658:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11217:
	.size	_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_, .-_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_
	.globl	_Z7findcvsiPiS_S_S_S_S_PS_
	.type	_Z7findcvsiPiS_S_S_S_S_PS_, @function
_Z7findcvsiPiS_S_S_S_S_PS_:
.LFB11218:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_
	.cfi_endproc
.LFE11218:
	.size	_Z7findcvsiPiS_S_S_S_S_PS_, .-_Z7findcvsiPiS_S_S_S_S_PS_
	.globl	_Z32__device_stub__Z9puttolistPiS_S_PiS_S_
	.type	_Z32__device_stub__Z9puttolistPiS_S_PiS_S_, @function
_Z32__device_stub__Z9puttolistPiS_S_PiS_S_:
.LFB11219:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L661
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9puttolistPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L661:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L663
	call	__stack_chk_fail@PLT
.L663:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11219:
	.size	_Z32__device_stub__Z9puttolistPiS_S_PiS_S_, .-_Z32__device_stub__Z9puttolistPiS_S_PiS_S_
	.globl	_Z9puttolistPiS_S_
	.type	_Z9puttolistPiS_S_, @function
_Z9puttolistPiS_S_:
.LFB11220:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9puttolistPiS_S_PiS_S_
	.cfi_endproc
.LFE11220:
	.size	_Z9puttolistPiS_S_, .-_Z9puttolistPiS_S_
	.globl	_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_
	.type	_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_, @function
_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_:
.LFB11221:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L666
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z9checkpermPbPiS0_S0_S0_S0_S0_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L666:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L668
	call	__stack_chk_fail@PLT
.L668:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11221:
	.size	_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_, .-_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_
	.globl	_Z9checkpermPbPiS0_S0_S0_S0_S0_
	.type	_Z9checkpermPbPiS0_S0_S0_S0_S0_, @function
_Z9checkpermPbPiS0_S0_S0_S0_S0_:
.LFB11222:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z9checkpermPbPiS0_S0_S0_S0_S0_PbPiS0_S0_S0_S0_S0_
	.cfi_endproc
.LFE11222:
	.size	_Z9checkpermPbPiS0_S0_S0_S0_S0_, .-_Z9checkpermPbPiS0_S0_S0_S0_S0_
	.globl	_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_
	.type	_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_, @function
_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_:
.LFB11223:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 112(%rsp)
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L671
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z7findallPiS_S_S_S_S_S_S_PS_S_(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L671:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L673
	call	__stack_chk_fail@PLT
.L673:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11223:
	.size	_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_, .-_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_
	.globl	_Z7findallPiS_S_S_S_S_S_S_PS_S_
	.type	_Z7findallPiS_S_S_S_S_S_S_PS_S_, @function
_Z7findallPiS_S_S_S_S_S_S_PS_S_:
.LFB11224:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_
	.cfi_endproc
.LFE11224:
	.size	_Z7findallPiS_S_S_S_S_S_S_PS_S_, .-_Z7findallPiS_S_S_S_S_S_S_PS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"%d"
.LC5:
	.string	"Error: %s\n"
.LC6:
	.string	"Not Ok"
.LC7:
	.string	"%d "
.LC8:
	.string	"\n"
.LC9:
	.string	"Start %lld\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB11186:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$4, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	leaq	60(%rsp), %rax
	leaq	.LC2(%rip), %rdi
	movq	%rax, %rsi
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	60(%rsp), %eax
	leal	1(%rax), %r12d
	movslq	%r12d, %r12
	leaq	0(,%r12,4), %rbp
	salq	$3, %r12
	movq	%rbp, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rbx, %r14
	movq	%rax, h_qvid(%rip)
	call	malloc@PLT
	movq	%r12, %rdi
	movq	%rax, h_qidtov(%rip)
	call	malloc@PLT
	movq	%r12, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %r12
.L677:
	movslq	60(%rsp), %rax
	cmpl	%r13d, %eax
	jl	.L726
	movq	%r14, %rsi
	leaq	.LC2(%rip), %rdi
	xorl	%eax, %eax
	incl	%r13d
	call	__isoc23_scanf@PLT
	addq	$4, %r14
	jmp	.L677
.L726:
	movslq	(%rbx,%rax,4), %rdi
	xorl	%r13d, %r13d
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, 8(%rsp)
	movq	%rax, %r14
.L679:
	movslq	60(%rsp), %rax
	movslq	(%rbx,%rax,4), %rdi
	cmpl	%r13d, %edi
	jle	.L727
	movq	%r14, %rsi
	leaq	.LC2(%rip), %rdi
	xorl	%eax, %eax
	incl	%r13d
	call	__isoc23_scanf@PLT
	addq	$4, %r14
	jmp	.L679
.L727:
	call	malloc@PLT
	xorl	%r15d, %r15d
	leaq	68(%rsp), %r13
	movq	%rax, %r14
.L681:
	movslq	60(%rsp), %rax
	cmpl	%r15d, (%rbx,%rax,4)
	jle	.L728
	xorl	%eax, %eax
	movq	%r13, %rsi
	leaq	.LC2(%rip), %rdi
	call	__isoc23_scanf@PLT
	cmpl	$1, 68(%rsp)
	sete	(%r14,%r15)
	incq	%r15
	jmp	.L681
.L728:
	leaq	64(%rsp), %rax
	leaq	.LC2(%rip), %rdi
	movq	%rax, %rsi
	movq	%rax, 32(%rsp)
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movl	64(%rsp), %eax
	leal	1(%rax), %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	xorl	%ecx, %ecx
	movq	%rax, %r13
	movq	%rax, %rsi
.L683:
	movl	64(%rsp), %r15d
	cmpl	%ecx, %r15d
	jl	.L729
	leaq	.LC2(%rip), %rdi
	xorl	%eax, %eax
	movl	%ecx, 40(%rsp)
	movq	%rsi, 16(%rsp)
	call	__isoc23_scanf@PLT
	movl	40(%rsp), %ecx
	movq	16(%rsp), %rsi
	incl	%ecx
	addq	$4, %rsi
	jmp	.L683
.L729:
	leal	1(%r15), %eax
	xorl	%ecx, %ecx
	cltq
	salq	$2, %rax
	movq	%rax, 16(%rsp)
.L685:
	cmpl	%ecx, 60(%rsp)
	jl	.L730
	movq	16(%rsp), %rdi
	movq	%rcx, 40(%rsp)
	call	malloc@PLT
	movq	40(%rsp), %rcx
	movq	%rax, (%r12,%rcx,8)
	incq	%rcx
	jmp	.L685
.L730:
	movslq	%r15d, %rdx
	xorl	%r15d, %r15d
	movslq	0(%r13,%rdx,4), %rdi
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, 16(%rsp)
	movq	%rax, %rcx
.L687:
	movslq	64(%rsp), %rax
	cmpl	%r15d, 0(%r13,%rax,4)
	jle	.L731
	movq	%rcx, %rsi
	leaq	.LC2(%rip), %rdi
	xorl	%eax, %eax
	incl	%r15d
	movq	%rcx, 40(%rsp)
	call	__isoc23_scanf@PLT
	movq	40(%rsp), %rcx
	addq	$4, %rcx
	jmp	.L687
.L731:
	movl	$4, %esi
	leaq	d_qverc(%rip), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$1, %esi
	leaq	d_over(%rip), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	60(%rsp), %eax
	leaq	d_qvert(%rip), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	60(%rsp), %eax
	leaq	d_qidtov(%rip), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	60(%rsp), %rax
	leaq	d_qelist(%rip), %rdi
	movslq	(%rbx,%rax,4), %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	60(%rsp), %rax
	leaq	d_qtree(%rip), %rdi
	movslq	(%rbx,%rax,4), %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	72(%rsp), %rdi
	movl	$4000152, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	80(%rsp), %rdi
	movl	$4000152, %esi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	60(%rsp), %eax
	leaq	d_qvid(%rip), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	d_qverc(%rip), %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	60(%rsp), %eax
	movq	%rbx, %rsi
	movq	d_qvert(%rip), %rdi
	movl	$1, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	60(%rsp), %rax
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	d_qelist(%rip), %rdi
	movslq	(%rbx,%rax,4), %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	60(%rsp), %rax
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	d_qtree(%rip), %rdi
	movslq	(%rbx,%rax,4), %rdx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4000152, %edx
	call	cudaMemset@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4000152, %edx
	call	cudaMemset@PLT
	movl	60(%rsp), %eax
	movq	d_qidtov(%rip), %rdi
	orl	$-1, %esi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemset@PLT
	movl	60(%rsp), %eax
	movq	d_qvid(%rip), %rdi
	xorl	%esi, %esi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemset@PLT
	movl	$4000152, %edi
	call	malloc@PLT
	cvtsi2sdl	60(%rsp), %xmm2
	movq	%rax, %rbx
	movaps	%xmm2, %xmm0
	movq	%xmm2, %r15
	call	sqrt@PLT
	movsd	%xmm0, 8(%rsp)
	movq	%r15, %xmm0
	call	sqrt@PLT
	mulsd	.LC3(%rip), %xmm0
	movsd	8(%rsp), %xmm1
	xorl	%r9d, %r9d
	addsd	.LC4(%rip), %xmm0
	mulsd	.LC3(%rip), %xmm1
	xorl	%r8d, %r8d
	movabsq	$68719476752, %rdx
	addsd	.LC4(%rip), %xmm1
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 136(%rsp)
	movq	%rdx, 140(%rsp)
	cvttsd2siq	%xmm0, %rax
	movb	$1, h_over(%rip)
	movl	$1, 148(%rsp)
	movl	%eax, 128(%rsp)
	cvttsd2siq	%xmm1, %rax
	movl	%eax, 132(%rsp)
	movq	128(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L689
	movq	d_qtree(%rip), %rcx
	movq	d_qvid(%rip), %rdx
	movq	d_qverc(%rip), %rsi
	movq	d_qvert(%rip), %rdi
	call	_Z32__device_stub__Z7setdeg1PiS_S_PbPiS_S_Pb
.L689:
	movb	$0, h_over(%rip)
	movl	$2, %r15d
.L690:
	cmpb	$0, h_over(%rip)
	jne	.L732
	movq	d_over(%rip), %rdi
	movl	$1, %ecx
	movl	$1, %edx
	leaq	h_over(%rip), %rsi
	movb	$1, h_over(%rip)
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4000152, %edx
	call	cudaMemset@PLT
	movl	148(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	140(%rsp), %rdx
	movq	128(%rsp), %rdi
	movl	136(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L691
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	movq	d_qtree(%rip), %r9
	movq	d_over(%rip), %r8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movq	d_qelist(%rip), %rcx
	movq	d_qvid(%rip), %rdx
	movq	d_qverc(%rip), %rsi
	movq	d_qvert(%rip), %rdi
	call	_Z42__device_stub__Z8findhashPiS_S_S_PbS0_S_S_PiS_S_S_PbS0_S_S_
	popq	%r8
	.cfi_def_cfa_offset 280
	popq	%r9
	.cfi_def_cfa_offset 272
.L691:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L692
	call	cudaGetErrorString@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L692:
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movl	$4000152, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	addl	%r15d, (%rbx)
	movq	%rbx, %rdx
	movq	%rbx, %rdi
	leaq	4000152(%rbx), %rsi
	call	_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4000152, %edx
	movl	4000148(%rbx), %r15d
	call	cudaMemcpy@PLT
	movl	148(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	140(%rsp), %rdx
	movq	128(%rsp), %rdi
	movl	136(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L693
	movq	d_qverc(%rip), %rsi
	movq	d_qvert(%rip), %rdi
	pushq	%rcx
	.cfi_def_cfa_offset 280
	pushq	d_qidtov(%rip)
	.cfi_def_cfa_offset 288
	movq	d_qtree(%rip), %r8
	movq	88(%rsp), %r9
	movq	d_qelist(%rip), %rcx
	movq	d_qvid(%rip), %rdx
	call	_Z38__device_stub__Z7puttoidPiS_S_S_PbS_S_PiS_S_S_PbS_S_
	popq	%rsi
	.cfi_def_cfa_offset 280
	popq	%rdi
	.cfi_def_cfa_offset 272
.L693:
	movq	d_over(%rip), %rsi
	movl	$2, %ecx
	movl	$1, %edx
	leaq	h_over(%rip), %rdi
	call	cudaMemcpy@PLT
	jmp	.L690
.L732:
	movslq	60(%rsp), %rdx
	movq	d_qvid(%rip), %rsi
	movl	$2, %ecx
	xorl	%r15d, %r15d
	movq	h_qvid(%rip), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	60(%rsp), %eax
	movl	$2, %ecx
	movq	d_qidtov(%rip), %rsi
	movq	h_qidtov(%rip), %rdi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
.L695:
	cmpl	%r15d, 60(%rsp)
	jl	.L733
	movq	h_qidtov(%rip), %rax
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movl	(%rax,%r15,4), %edx
	xorl	%eax, %eax
	incq	%r15
	call	__printf_chk@PLT
	jmp	.L695
.L733:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%r15d, %r15d
	call	__printf_chk@PLT
.L697:
	cmpl	%r15d, 60(%rsp)
	jl	.L734
	movq	h_qvid(%rip), %rax
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movl	(%rax,%r15,4), %edx
	xorl	%eax, %eax
	incq	%r15
	call	__printf_chk@PLT
	jmp	.L697
.L734:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	d_qtree(%rip), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	movq	%rbp, %rbx
	call	free@PLT
	movq	%r14, %rdi
	xorl	%r14d, %r14d
	call	free@PLT
	movl	60(%rsp), %eax
	leaq	88(%rsp), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
.L699:
	movl	64(%rsp), %eax
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	cmpl	%r14d, 60(%rsp)
	jl	.L735
	movq	%rdx, %rsi
	movq	%rbx, %rdi
	incl	%r14d
	addq	$8, %rbx
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	movq	-8(%rbx), %rdi
	xorl	%esi, %esi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemset@PLT
	jmp	.L699
.L735:
	movq	8(%rbp), %rdi
	movl	$1, %esi
	xorl	%r15d, %r15d
	call	cudaMemset@PLT
	movl	60(%rsp), %eax
	movq	88(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	leaq	d_dvert(%rip), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	$4, %esi
	leaq	d_dverc(%rip), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movslq	64(%rsp), %rax
	leaq	d_delist(%rip), %rdi
	movslq	0(%r13,%rax,4), %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	d_dverc(%rip), %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movq	%r13, %rsi
	movq	d_dvert(%rip), %rdi
	movl	$1, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movslq	64(%rsp), %rax
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	d_delist(%rip), %rdi
	movslq	0(%r13,%rax,4), %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %ebx
	cvtsi2sdl	%ebx, %xmm3
	movaps	%xmm3, %xmm0
	movq	%xmm3, %r14
	call	sqrt@PLT
	movq	%xmm0, %r13
	movq	%r14, %xmm0
	call	sqrt@PLT
	mulsd	.LC3(%rip), %xmm0
	leal	1(%rbx), %ecx
	movq	8(%r12), %rdi
	addsd	.LC4(%rip), %xmm0
	movslq	%ecx, %rcx
	movl	$1, 160(%rsp)
	movl	$1, 172(%rsp)
	salq	$2, %rcx
	cvttsd2siq	%xmm0, %rax
	movq	%r13, %xmm0
	mulsd	.LC3(%rip), %xmm0
	addsd	.LC4(%rip), %xmm0
	movl	%eax, 152(%rsp)
	cvttsd2siq	%xmm0, %rax
	movl	%eax, 156(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 164(%rsp)
	movb	$1, %al
	rep stosb
	movl	60(%rsp), %eax
	leal	1(%rax), %r13d
	movslq	%r13d, %r13
	salq	$2, %r13
	movq	%r13, %rdi
	call	malloc@PLT
	movq	%r13, %rcx
	movq	%r13, %rdx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	__memset_chk@PLT
	movq	%r13, %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	60(%rsp), %eax
	movq	104(%rsp), %rdi
	xorl	%esi, %esi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemset@PLT
	movl	60(%rsp), %eax
	leaq	96(%rsp), %rdi
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$3, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	60(%rsp), %eax
	leal	1(%rax), %edi
	movslq	%edi, %rdi
	salq	$3, %rdi
	call	malloc@PLT
	movq	%rax, %r13
	movq	%rax, %r14
.L701:
	movl	60(%rsp), %edx
	cmpl	%r15d, %edx
	jl	.L736
	movl	64(%rsp), %eax
	movq	%r14, %rdi
	incl	%r15d
	addq	$8, %r14
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movl	64(%rsp), %eax
	movq	-8(%r14), %rdi
	xorl	%esi, %esi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemset@PLT
	jmp	.L701
.L736:
	incl	%edx
	movq	96(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	movslq	%edx, %rdx
	salq	$3, %rdx
	call	cudaMemcpy@PLT
	movq	8(%r12), %rsi
	xorl	%eax, %eax
.L703:
	movl	64(%rsp), %edx
	cmpl	%eax, %edx
	jle	.L737
	movl	%eax, (%rsi,%rax,4)
	incq	%rax
	jmp	.L703
.L737:
	incl	%edx
	movq	8(%r13), %rdi
	movl	$1, %ecx
	xorl	%r15d, %r15d
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	64(%rsp), %eax
	movl	%eax, 4(%rbx)
.L705:
	movl	60(%rsp), %ecx
	cmpl	%r15d, %ecx
	jl	.L738
	movq	h_qidtov(%rip), %rax
	leaq	0(,%r15,4), %r14
	cmpl	$-1, (%rax,%r15,4)
	je	.L707
	movl	172(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	164(%rsp), %rdx
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L708
	movq	h_qidtov(%rip), %rax
	movq	d_dverc(%rip), %rdx
	movq	d_qelist(%rip), %r9
	movq	d_qvert(%rip), %r8
	movl	(%rax,%r14), %edi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	movq	d_delist(%rip), %rcx
	pushq	d_qvid(%rip)
	.cfi_def_cfa_offset 288
	movq	d_dvert(%rip), %rsi
	call	_Z40__device_stub__Z7findcvsiPiS_S_S_S_S_PS_iPiS_S_S_S_S_PS_
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L708:
	call	cudaGetLastError@PLT
	movl	64(%rsp), %eax
	movq	0(%rbp,%r15,8), %rsi
	movl	$2, %ecx
	movq	(%r12,%r15,8), %rdi
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	xorl	%edx, %edx
.L709:
	movl	%edx, 68(%rsp)
	cmpl	%edx, 64(%rsp)
	jl	.L739
	movq	(%r12,%r15,8), %rcx
	movslq	%edx, %rax
	cmpl	$0, (%rcx,%rax,4)
	je	.L710
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L710:
	movl	68(%rsp), %eax
	leal	1(%rax), %edx
	jmp	.L709
.L739:
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	(%r12,%r15,8), %r9
	movslq	64(%rsp), %rax
	movq	%r9, %rdx
	leaq	4(%r9,%rax,4), %rsi
	movq	%r9, %rdi
	call	_ZN6thrust20THRUST_200700_890_NS14exclusive_scanIPiS2_EET0_T_S4_S3_.isra.0
	movslq	64(%rsp), %rax
	movq	0(%rbp,%r15,8), %rdi
	movq	%r9, %rsi
	movl	$1, %ecx
	movq	%rax, %rdx
	movl	(%r9,%rax,4), %eax
	incl	%edx
	movl	%eax, (%rbx,%r15,4)
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	172(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	164(%rsp), %rdx
	movq	152(%rsp), %rdi
	movl	160(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L707
	movq	0(%r13,%r15,8), %rdx
	movq	0(%rbp,%r15,8), %rsi
	movq	d_dverc(%rip), %rdi
	call	_Z32__device_stub__Z9puttolistPiS_S_PiS_S_
.L707:
	incq	%r15
	jmp	.L705
.L738:
	movq	h_qvid(%rip), %rsi
	xorl	%eax, %eax
	movl	$1, %ebp
.L714:
	cmpl	%eax, %ecx
	jle	.L740
	movslq	(%rsi,%rax,4), %rdx
	movslq	(%rbx,%rdx,4), %rdx
	testl	%edx, %edx
	je	.L715
	imulq	%rdx, %rbp
.L715:
	incq	%rax
	jmp	.L714
.L740:
	movq	%rbp, %rdx
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	60(%rsp), %eax
	movq	104(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	leal	1(%rax), %edx
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	cvtsi2sdq	%rbp, %xmm4
	movaps	%xmm4, %xmm0
	movq	%xmm4, %rbx
	call	sqrt@PLT
	movsd	%xmm0, 8(%rsp)
	movq	%rbx, %xmm0
	leaq	4(,%rbp,4), %rbx
	call	sqrt@PLT
	mulsd	.LC3(%rip), %xmm0
	leaq	112(%rsp), %rdi
	movl	$1, 184(%rsp)
	movl	$1, 196(%rsp)
	cvttsd2sil	%xmm0, %eax
	movsd	.LC3(%rip), %xmm0
	mulsd	8(%rsp), %xmm0
	incl	%eax
	movl	%eax, 176(%rsp)
	cvttsd2sil	%xmm0, %eax
	incl	%eax
	movl	%eax, 180(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 188(%rsp)
	movl	60(%rsp), %eax
	leal	1(%rax), %esi
	movslq	%esi, %rsi
	imulq	%rbp, %rsi
	salq	$2, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	leaq	120(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z10cudaMallocIiE9cudaErrorPPT_m.isra.0
	movq	120(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movl	196(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	188(%rsp), %rdx
	movq	176(%rsp), %rdi
	movl	184(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L717
	pushq	104(%rsp)
	.cfi_def_cfa_offset 280
	movq	d_qvert(%rip), %r9
	movq	d_qelist(%rip), %r8
	pushq	104(%rsp)
	.cfi_def_cfa_offset 288
	movq	d_qverc(%rip), %rcx
	pushq	d_delist(%rip)
	.cfi_def_cfa_offset 296
	movq	d_qvid(%rip), %rdx
	pushq	d_dvert(%rip)
	.cfi_def_cfa_offset 304
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z45__device_stub__Z7findallPiS_S_S_S_S_S_S_PS_S_PiS_S_S_S_S_S_S_PS_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 272
.L717:
	movq	d_over(%rip), %rdi
	call	cudaFree@PLT
	movq	d_qverc(%rip), %rdi
	call	cudaFree@PLT
	movq	d_qvert(%rip), %rdi
	call	cudaFree@PLT
	movq	d_qelist(%rip), %rdi
	call	cudaFree@PLT
	movq	d_qvid(%rip), %rdi
	call	cudaFree@PLT
	movq	d_qidtov(%rip), %rdi
	call	cudaFree@PLT
	movq	d_dvert(%rip), %rdi
	call	cudaFree@PLT
	movq	d_delist(%rip), %rdi
	call	cudaFree@PLT
	movq	d_dverc(%rip), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L718
	call	__stack_chk_fail@PLT
.L718:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE11186:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv"
.LC11:
	.string	"_Z7findallPiS_S_S_S_S_S_S_PS_S_"
.LC12:
	.string	"_Z9checkpermPbPiS0_S0_S0_S0_S0_"
.LC13:
	.string	"_Z9puttolistPiS_S_"
.LC14:
	.string	"_Z7findcvsiPiS_S_S_S_S_PS_"
.LC15:
	.string	"_Z7puttoidPiS_S_S_PbS_S_"
.LC16:
	.string	"_Z7setdeg1PiS_S_Pb"
.LC17:
	.string	"_Z8findhashPiS_S_S_PbS0_S_S_"
.LC18:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo5beginE"
.LC19:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo3endE"
.LC20:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo6cbeginE"
.LC21:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo4cendE"
.LC22:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo6rbeginE"
.LC23:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo4rendE"
.LC24:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo7crbeginE"
.LC25:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__45__cpo5crendE"
.LC26:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__445_GLOBAL__N__34ebdb36_12_isokernel_cu_df4162d16ignoreE"
.LC27:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__419piecewise_constructE"
.LC28:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__48in_placeE"
.LC29:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__420unreachable_sentinelE"
.LC30:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std3__47nulloptE"
.LC31:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4swapE"
.LC32:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo9iter_moveE"
.LC33:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo7advanceE"
.LC34:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo5beginE"
.LC35:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo3endE"
.LC36:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo6cbeginE"
.LC37:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4cendE"
.LC38:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo9iter_swapE"
.LC39:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4nextE"
.LC40:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4prevE"
.LC41:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4dataE"
.LC42:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo5cdataE"
.LC43:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo4sizeE"
.LC44:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo5ssizeE"
.LC45:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d14cuda3std6ranges3__45__cpo8distanceE"
.LC46:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS8cuda_cub3parE"
.LC47:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS8cuda_cub10par_nosyncE"
.LC48:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
.LC49:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_1E"
.LC50:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_2E"
.LC51:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_3E"
.LC52:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_4E"
.LC53:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_5E"
.LC54:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_6E"
.LC55:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_7E"
.LC56:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_8E"
.LC57:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders2_9E"
.LC58:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS12placeholders3_10E"
.LC59:
	.string	"_ZN43_INTERNAL_34ebdb36_12_isokernel_cu_df4162d16thrust20THRUST_200700_890_NS3seqE"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB11228:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7findallPiS_S_S_S_S_S_S_PS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9checkpermPbPiS0_S0_S0_S0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9puttolistPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7findcvsiPiS_S_S_S_S_PS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7puttoidPiS_S_S_PbS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z7setdeg1PiS_S_Pb(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8findhashPiS_S_S_PbS0_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC18(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6rbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4rendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo7crbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5crendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__445_GLOBAL__N__34ebdb36_12_isokernel_cu_df4162d16ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__420unreachable_sentinelE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__47nulloptE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4nextE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4prevE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4dataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5cdataE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4sizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo5ssizeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC45(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo8distanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC46(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC48(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC51(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC54(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC55(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC56(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC57(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC58(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NSL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE11228:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	h_over
	.bss
	.type	h_over, @object
	.size	h_over, 1
h_over:
	.zero	1
	.globl	d_qdmap
	.align 8
	.type	d_qdmap, @object
	.size	d_qdmap, 8
d_qdmap:
	.zero	8
	.globl	d_over
	.align 8
	.type	d_over, @object
	.size	d_over, 8
d_over:
	.zero	8
	.globl	d_qtree
	.align 8
	.type	d_qtree, @object
	.size	d_qtree, 8
d_qtree:
	.zero	8
	.globl	d_delist
	.align 8
	.type	d_delist, @object
	.size	d_delist, 8
d_delist:
	.zero	8
	.globl	d_dvert
	.align 8
	.type	d_dvert, @object
	.size	d_dvert, 8
d_dvert:
	.zero	8
	.globl	d_qelist
	.align 8
	.type	d_qelist, @object
	.size	d_qelist, 8
d_qelist:
	.zero	8
	.globl	d_qvert
	.align 8
	.type	d_qvert, @object
	.size	d_qvert, 8
d_qvert:
	.zero	8
	.globl	h_qvid
	.align 8
	.type	h_qvid, @object
	.size	h_qvid, 8
h_qvid:
	.zero	8
	.globl	h_qidtov
	.align 8
	.type	h_qidtov, @object
	.size	h_qidtov, 8
h_qidtov:
	.zero	8
	.globl	d_qidtov
	.align 8
	.type	d_qidtov, @object
	.size	d_qidtov, 8
d_qidtov:
	.zero	8
	.globl	d_qvid
	.align 8
	.type	d_qvid, @object
	.size	d_qvid, 8
d_qvid:
	.zero	8
	.globl	d_dverc
	.align 8
	.type	d_dverc, @object
	.size	d_dverc, 8
d_dverc:
	.zero	8
	.globl	d_qverc
	.align 8
	.type	d_qverc, @object
	.size	d_qverc, 8
d_qverc:
	.zero	8
	.globl	qdmap
	.align 8
	.type	qdmap, @object
	.size	qdmap, 8
qdmap:
	.zero	8
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NSL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NSL3seqE, 1
_ZN6thrust20THRUST_200700_890_NSL3seqE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E:
	.zero	1
	.weak	_ZN4cuda3std3__47nulloptE
	.section	.rodata._ZN4cuda3std3__47nulloptE,"aG",@progbits,_ZN4cuda3std3__47nulloptE,comdat
	.type	_ZN4cuda3std3__47nulloptE, @gnu_unique_object
	.size	_ZN4cuda3std3__47nulloptE, 1
_ZN4cuda3std3__47nulloptE:
	.zero	1
	.hidden	InitializeInjectionNvtx2_fnptr
	.weak	InitializeInjectionNvtx2_fnptr
	.bss
	.align 8
	.type	InitializeInjectionNvtx2_fnptr, @object
	.size	InitializeInjectionNvtx2_fnptr, 8
InitializeInjectionNvtx2_fnptr:
	.zero	8
	.hidden	nvtxGlobals_v3
	.weak	nvtxGlobals_v3
	.section	.data.rel.local,"aw"
	.align 32
	.type	nvtxGlobals_v3, @object
	.size	nvtxGlobals_v3, 1168
nvtxGlobals_v3:
	.long	0
	.zero	4
	.quad	16
	.quad	nvtxEtiGetModuleFunctionTable_v3
	.quad	24
	.long	3
	.long	0
	.quad	nvtxEtiSetInjectionNvtxVersion_v3
	.quad	nvtxMarkEx_impl_init_v3
	.quad	nvtxMarkA_impl_init_v3
	.quad	nvtxMarkW_impl_init_v3
	.quad	nvtxRangeStartEx_impl_init_v3
	.quad	nvtxRangeStartA_impl_init_v3
	.quad	nvtxRangeStartW_impl_init_v3
	.quad	nvtxRangeEnd_impl_init_v3
	.quad	nvtxRangePushEx_impl_init_v3
	.quad	nvtxRangePushA_impl_init_v3
	.quad	nvtxRangePushW_impl_init_v3
	.quad	nvtxRangePop_impl_init_v3
	.quad	nvtxNameCategoryA_impl_init_v3
	.quad	nvtxNameCategoryW_impl_init_v3
	.quad	nvtxNameOsThreadA_impl_init_v3
	.quad	nvtxNameOsThreadW_impl_init_v3
	.quad	nvtxNameCuDeviceA_impl_init_v3
	.quad	nvtxNameCuDeviceW_impl_init_v3
	.quad	nvtxNameCuContextA_impl_init_v3
	.quad	nvtxNameCuContextW_impl_init_v3
	.quad	nvtxNameCuStreamA_impl_init_v3
	.quad	nvtxNameCuStreamW_impl_init_v3
	.quad	nvtxNameCuEventA_impl_init_v3
	.quad	nvtxNameCuEventW_impl_init_v3
	.quad	nvtxNameClDeviceA_impl_init_v3
	.quad	nvtxNameClDeviceW_impl_init_v3
	.quad	nvtxNameClContextA_impl_init_v3
	.quad	nvtxNameClContextW_impl_init_v3
	.quad	nvtxNameClCommandQueueA_impl_init_v3
	.quad	nvtxNameClCommandQueueW_impl_init_v3
	.quad	nvtxNameClMemObjectA_impl_init_v3
	.quad	nvtxNameClMemObjectW_impl_init_v3
	.quad	nvtxNameClSamplerA_impl_init_v3
	.quad	nvtxNameClSamplerW_impl_init_v3
	.quad	nvtxNameClProgramA_impl_init_v3
	.quad	nvtxNameClProgramW_impl_init_v3
	.quad	nvtxNameClEventA_impl_init_v3
	.quad	nvtxNameClEventW_impl_init_v3
	.quad	nvtxNameCudaDeviceA_impl_init_v3
	.quad	nvtxNameCudaDeviceW_impl_init_v3
	.quad	nvtxNameCudaStreamA_impl_init_v3
	.quad	nvtxNameCudaStreamW_impl_init_v3
	.quad	nvtxNameCudaEventA_impl_init_v3
	.quad	nvtxNameCudaEventW_impl_init_v3
	.quad	nvtxDomainMarkEx_impl_init_v3
	.quad	nvtxDomainRangeStartEx_impl_init_v3
	.quad	nvtxDomainRangeEnd_impl_init_v3
	.quad	nvtxDomainRangePushEx_impl_init_v3
	.quad	nvtxDomainRangePop_impl_init_v3
	.quad	nvtxDomainResourceCreate_impl_init_v3
	.quad	nvtxDomainResourceDestroy_impl_init_v3
	.quad	nvtxDomainNameCategoryA_impl_init_v3
	.quad	nvtxDomainNameCategoryW_impl_init_v3
	.quad	nvtxDomainRegisterStringA_impl_init_v3
	.quad	nvtxDomainRegisterStringW_impl_init_v3
	.quad	nvtxDomainCreateA_impl_init_v3
	.quad	nvtxDomainCreateW_impl_init_v3
	.quad	nvtxDomainDestroy_impl_init_v3
	.quad	nvtxInitialize_impl_init_v3
	.quad	nvtxDomainSyncUserCreate_impl_init_v3
	.quad	nvtxDomainSyncUserDestroy_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.quad	nvtxDomainSyncUserReleasing_impl_init_v3
	.quad	0
	.quad	nvtxGlobals_v3+48
	.quad	nvtxGlobals_v3+56
	.quad	nvtxGlobals_v3+64
	.quad	nvtxGlobals_v3+72
	.quad	nvtxGlobals_v3+80
	.quad	nvtxGlobals_v3+88
	.quad	nvtxGlobals_v3+96
	.quad	nvtxGlobals_v3+104
	.quad	nvtxGlobals_v3+112
	.quad	nvtxGlobals_v3+120
	.quad	nvtxGlobals_v3+128
	.quad	nvtxGlobals_v3+136
	.quad	nvtxGlobals_v3+144
	.quad	nvtxGlobals_v3+152
	.quad	nvtxGlobals_v3+160
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+168
	.quad	nvtxGlobals_v3+176
	.quad	nvtxGlobals_v3+184
	.quad	nvtxGlobals_v3+192
	.quad	nvtxGlobals_v3+200
	.quad	nvtxGlobals_v3+208
	.quad	nvtxGlobals_v3+216
	.quad	nvtxGlobals_v3+224
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+232
	.quad	nvtxGlobals_v3+240
	.quad	nvtxGlobals_v3+248
	.quad	nvtxGlobals_v3+256
	.quad	nvtxGlobals_v3+264
	.quad	nvtxGlobals_v3+272
	.quad	nvtxGlobals_v3+280
	.quad	nvtxGlobals_v3+288
	.quad	nvtxGlobals_v3+296
	.quad	nvtxGlobals_v3+304
	.quad	nvtxGlobals_v3+312
	.quad	nvtxGlobals_v3+320
	.quad	nvtxGlobals_v3+328
	.quad	nvtxGlobals_v3+336
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+344
	.quad	nvtxGlobals_v3+352
	.quad	nvtxGlobals_v3+360
	.quad	nvtxGlobals_v3+368
	.quad	nvtxGlobals_v3+376
	.quad	nvtxGlobals_v3+384
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+392
	.quad	nvtxGlobals_v3+400
	.quad	nvtxGlobals_v3+408
	.quad	nvtxGlobals_v3+416
	.quad	nvtxGlobals_v3+424
	.quad	nvtxGlobals_v3+432
	.quad	nvtxGlobals_v3+440
	.quad	nvtxGlobals_v3+448
	.quad	nvtxGlobals_v3+456
	.quad	nvtxGlobals_v3+464
	.quad	nvtxGlobals_v3+472
	.quad	nvtxGlobals_v3+480
	.quad	nvtxGlobals_v3+488
	.quad	nvtxGlobals_v3+496
	.quad	nvtxGlobals_v3+504
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+512
	.quad	nvtxGlobals_v3+520
	.quad	nvtxGlobals_v3+528
	.quad	nvtxGlobals_v3+536
	.quad	nvtxGlobals_v3+544
	.quad	nvtxGlobals_v3+552
	.quad	0
	.weak	_ZN4cuda3std3__420unreachable_sentinelE
	.section	.rodata._ZN4cuda3std3__420unreachable_sentinelE,"aG",@progbits,_ZN4cuda3std3__420unreachable_sentinelE,comdat
	.type	_ZN4cuda3std3__420unreachable_sentinelE, @gnu_unique_object
	.size	_ZN4cuda3std3__420unreachable_sentinelE, 1
_ZN4cuda3std3__420unreachable_sentinelE:
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	.weak	_ZN4cuda3std3__45__cpo5crendE
	.section	.rodata._ZN4cuda3std3__45__cpo5crendE,"aG",@progbits,_ZN4cuda3std3__45__cpo5crendE,comdat
	.type	_ZN4cuda3std3__45__cpo5crendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5crendE, 1
_ZN4cuda3std3__45__cpo5crendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo7crbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo7crbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo7crbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo7crbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo7crbeginE, 1
_ZN4cuda3std3__45__cpo7crbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4rendE
	.section	.rodata._ZN4cuda3std3__45__cpo4rendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4rendE,comdat
	.type	_ZN4cuda3std3__45__cpo4rendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4rendE, 1
_ZN4cuda3std3__45__cpo4rendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6rbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6rbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6rbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6rbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6rbeginE, 1
_ZN4cuda3std3__45__cpo6rbeginE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo8distanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo8distanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo8distanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo8distanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo8distanceE, 1
_ZN4cuda3std6ranges3__45__cpo8distanceE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo5ssizeE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5ssizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5ssizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5ssizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo5ssizeE, 1
_ZN4cuda3std6ranges3__45__cpo5ssizeE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4sizeE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4sizeE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4sizeE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4sizeE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4sizeE, 1
_ZN4cuda3std6ranges3__45__cpo4sizeE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo5cdataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo5cdataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo5cdataE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo5cdataE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo5cdataE, 1
_ZN4cuda3std6ranges3__45__cpo5cdataE:
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	.weak	_ZN4cuda3std6ranges3__45__cpo4dataE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4dataE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4dataE,comdat
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	.zero	1
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1068498944
	.align 8
.LC4:
	.long	0
	.long	1072693248
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

#include <stdlib.h>

#include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <thrust/count.h>
const int BASE1 = 10000 + 7;
const int BASE2 = 100000 + 3;
const int MOD1 = 1000000 + 3;
const int MOD2 = 1000000 + 37;
__global__ void findhash(int *d_qvert,int *d_qverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_qtree,int *d_hash1,int *d_hash2)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	int l=d_qvert[ver+1];
	int hash1=1,hash2=1;
	int flag=0;
	for(i=d_qvert[ver];i<l;i++)
	{
		int m=d_qelist[i];
		bool treeedge=d_qtree[i];
		if(treeedge){
			int tt=d_qvid[m];
			if(tt==0)
				return;
			flag=1;
			hash1=(hash1*1L*BASE1)*tt % MOD1;
			hash2=(hash2*1L*BASE2)*tt % MOD2;
		}
	}
	if(flag==0)
		return;
	if(flag==1){
		*d_over=false;
		d_hash1[hash1]=1;
		d_hash2[hash2]=1;
	}
	
}
__global__ void setdeg1(int *d_qvert,int *d_qverc,int *d_qvid,bool *d_qtree)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	
	int l=d_qvert[ver+1];
	bool treeedge;
	
	for(i=d_qvert[ver];i<l;i++)
	{
		treeedge=d_qtree[i];
		
		if(treeedge)
			return;
	}
//printf("%d %d\n",ver,i);
	d_qvid[ver]=1;	
}
/*__global__ void alignhash(bool *d_hash1,bool *d_hash2)
{
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=1000038)
		return ;
	if(d_hash1[ver] || d_hash2[ver]){
		d_hash1=true;
	}
}*/
__global__ void puttoid(int *d_qvert,int *d_qverc,int *d_qvid,int *d_qelist,bool *d_qtree,int *d_loc,int * d_qidtov)
{
	int i;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	if(d_qvid[ver]!=0)
		return;
	int l=d_qvert[ver+1];
	int hash1=1,hash2=1;
	int flag=0;
	for(i=d_qvert[ver];i<l;i++)
	{
		int m=d_qelist[i];
		bool treeedge=d_qtree[i];
		if(treeedge){
			int tt=d_qvid[m];
			if(tt==0)
				return;
			flag=1;
			hash1=(hash1*1L*BASE1)*tt % MOD1;
			hash2=(hash2*1L*BASE2)*tt % MOD2;
		}
	}
	//printf("%d %d %d \n",ver,flag,d_loc[hash1]);
	if(flag==0)
		return;
	int id=d_loc[hash1];
	d_qvid[ver]=id;
	d_qidtov[id]=ver;
}
__device__ bool chechall(int ver,bool *check,int i,int dfrom,int dto,int *d_delist,int *d_qelist,int *d_qvid,int qfrom,int qto,int ** d_dcvslist){
	//int ql=qfrom-qto;
	int ql=qto-qfrom;
	int j,k,l;
	//d_dcvslist[2][ql]=true;
	if(i==ql){
		
		k=d_qelist[i+qfrom-1];
		k=d_qvid[k];
		if(k>=d_qvid[ver])
			return true;
		for(j=dfrom;j<dto;j++){
			l=d_delist[j];
			if(check[l])
				continue;
			if(!d_dcvslist[k][l])
				continue;
			return true;
		}
	}
	else{
		int res=false;
		k=d_qelist[i+qfrom-1];
		k=d_qvid[k];
		if(k>=d_qvid[ver])
			return chechall(ver,check,i+1,dfrom,dto,d_delist,d_qelist,d_qvid,qfrom,qto,d_dcvslist);
		
		for(j=dfrom;j<dto;j++){
			l=d_delist[j];
			if(check[l])
				continue;
			if(!d_dcvslist[k][l])
				continue;
			check[l]=true;
			res|=chechall(ver,check,i+1,dfrom,dto,d_delist,d_qelist,d_qvid,qfrom,qto,d_dcvslist);
			if(res==true)
				return true;
			check[l]=false;
		}
	}
	return false;
}
__global__ void findcvs(int ver,int *d_dvert,int *d_dverc,int *d_delist,int *d_qvert,int *d_qelist,int *d_qvid,int ** d_dcvslist )
{
	//int i;
	int dver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(dver>=d_dverc[0])
		return ;
	int ql=d_qvert[ver+1]-d_qvert[ver];
	int dl=d_dvert[dver+1]-d_dvert[dver];
	if(ql>dl)
		return;
	bool *checked=(bool*)malloc(sizeof(bool)*d_dverc[0]);
	//bool *checked=new bool[d_dverc[0]];
	memset(checked,false,sizeof(bool)*d_dverc[0]);
	//chechall(bool *check,int i,int dfrom,int dto,int *d_delist,int *d_qelist,int *d_qvid,int qfrom,int qto,bool ** d_dcvslist)
	if(chechall(ver,checked,1,d_dvert[dver],d_dvert[dver+1],d_delist,d_qelist,d_qvid,d_qvert[ver],d_qvert[ver+1],d_dcvslist))
		d_dcvslist[d_qvid[ver]][dver]=true;
	free(checked);
}
__global__ void puttolist(int *d_dverc,int *d_loc,int * d_dcvslist )
{
	int dver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(dver>=d_dverc[0])
		return ;
	if(d_loc[dver]!=d_loc[dver+1])
		d_dcvslist[d_loc[dver]]=dver;
}
__global__ void checkperm(bool *found,int * qdmap,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist){
	int i;
	//found[0]=false;
	int ver=threadIdx.x*blockDim.y+threadIdx.y+blockDim.x*blockDim.y*(blockIdx.x*gridDim.y+blockIdx.y);
	if(ver>=d_qverc[0])
		return ;
	int n,p,j,k,flag=0;
	//for(ver=0;ver<d_qverc[0];ver++){
		int l=d_qvert[ver+1];
		int dver=qdmap[ver];
		
		n=d_dvert[dver+1];
		for(i=d_qvert[ver];i<l;i++)
		{
			flag=0;
			j=d_qelist[i];
			p=d_dvert[dver];
			k=qdmap[j];
			for(;p<n;p++){
				if(k==d_delist[p]){
					flag=1;
					break;
				}
			}
			if(!flag){
				*found=false;
				return;
			}
		}
	//}
}

__global__ void findall(int *d_mapans,int *d_cans,int *d_qvid,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist,int ** d_cvsverlist,int * d_size_cvs)
{
	bool found[1]={true};
	long long int blockId = blockIdx.x 
			 + blockIdx.y * gridDim.x 
			 + gridDim.x * gridDim.y * blockIdx.z; 
	long long int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
			  + (threadIdx.z * (blockDim.x * blockDim.y))
			  + (threadIdx.y * blockDim.x)
			  + threadIdx.x;
	int i=0;
	long long int indexperm=threadId;
	for(i=0;i<d_qverc[0];i++){
		int j=d_qvid[i];
		indexperm/=d_size_cvs[j];
	}
	if(indexperm)
		return;
	indexperm=threadId;	
	int *d_qdmap=&d_mapans[d_qverc[0]*threadId];//new int[d_qverc[0]];
	for(i=0;i<d_qverc[0];i++){
		int j=d_qvid[i];
		d_qdmap[i]=d_cvsverlist[j][indexperm%d_size_cvs[j]];
		indexperm/=d_size_cvs[j];
	}
	
	//dim3 blocks((max/16 )+ 1,(max/16)+1);
	//dim3 threads(16,16);
	//found[0]=true;
	//checkperm<<<blocks,threads>>> (found,d_qdmap,d_qverc,d_qelist,d_qvert,d_dvert,d_delist);
	int n,p,j,k,flag=0,ver;
	for(ver=0;ver<d_qverc[0];ver++){
		int l=d_qvert[ver+1];
		int dver=d_qdmap[ver];
		
		n=d_dvert[dver+1];
		for(i=d_qvert[ver];i<l;i++)
		{
			flag=0;
			j=d_qelist[i];
			p=d_dvert[dver];
			k=d_qdmap[j];
			for(;p<n;p++){
				if(k==d_delist[p]){
					flag=1;
					break;
				}
			}
			if(!flag){
				*found=false;
				return;
			}
		}
	}
	if(found[0]){
		d_cans[threadId]=1;	//printf("%d ", threadId);
	}
	//delete d_qdmap;
}
int * qdmap;
int *d_qverc,*d_dverc;
int *d_qvid,*d_qidtov,*h_qidtov,*h_qvid;
int *d_qvert,*d_qelist,*d_dvert,*d_delist;//,*d_dvelist,*d_qvelist;
bool *d_qtree,*d_over;	
int *d_qdmap;
bool h_over;
/*void callforallperm(bool * check,int ** cvslist,int i,int max,int dmax){
	int j,k,l;
	l=h_qvid[i-1];
	//printf("i%d %di",i,l);
	if(i==max){
		for(j=0;j<dmax;j++)
			if(cvslist[l][j] && !check[j]){
				qdmap[i-1]=j;
				dim3 blocks((max/16 )+ 1,(max/16)+1);
				dim3 threads(16,16);
				h_over=true;
				//for(k=0;k<max;k++)
				//		printf("%d ",qdmap[k]);
				
				cudaMemcpy(d_over, &h_over, sizeof(bool), cudaMemcpyHostToDevice) ;
				cudaMemcpy(d_qdmap, qdmap, sizeof(int)*(max+1), cudaMemcpyHostToDevice);
				checkperm<<<blocks,threads>>> (d_over,d_qdmap,d_qverc,d_qelist,d_qvert,d_dvert,d_delist);
				//checkperm(bool *found,int * qdmap,int * d_qverc,int * d_qelist,int * d_qvert,int * d_dvert,int *d_delist)
				cudaError_t err = cudaGetLastError();
					if(err!=cudaSuccess)
					{
						printf("Error: %s\n", cudaGetErrorString(err));
						printf("Not Ok");
					}
				cudaMemcpy(&h_over, d_over, sizeof(bool), cudaMemcpyDeviceToHost) ;
				if(h_over){
					for(k=0;k<max;k++)
						printf("%d ",qdmap[k]);
					//printf("\n");
						printf("OK\n");
				}
				//printf("\n");
			}
	}
	else{
		for(j=0;j<dmax;j++){
				//printf("%d %d %d\n",j,check[j],cvslist[l][j]);
				if(cvslist[l][j] && !check[j]){
				check[j]=true;
				qdmap[i-1]=j;
				callforallperm(check,cvslist,i+1,max,dmax);
				check[j]=false;
			}
		}
	}
}*/

int main(int argc, char **argv)
{
	int deviceId = 4;
	hipSetDevice(deviceId);
	int h_qverc,h_dverc;
	
	
	int *h_qvert,*h_qelist,*h_dvert,*h_delist;//,*h_dvelist,*h_qvelist;
	
	bool *h_qtree;
	int *d_hash1,*d_hash2;
	
	int i,j;
	int **h_cvslist,**d_cvslist,**h_tem;
	scanf("%d",&h_qverc);
	h_qvert=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_qvid=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_qidtov=(int *)malloc(sizeof(int)*(h_qverc+1));
	h_tem=(int **)malloc(sizeof(int*)*(h_qverc+1));
	h_cvslist=(int **)malloc(sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		scanf("%d",&h_qvert[i]);
	}
	h_qelist=(int *)malloc(sizeof(int)*h_qvert[h_qverc]);
	for(i=0;i<h_qvert[h_qverc];i++)
		scanf("%d",&h_qelist[i]);
	h_qtree=(bool *)malloc(sizeof(bool)*h_qvert[h_qverc]);
	for(i=0;i<h_qvert[h_qverc];i++){
		scanf("%d",&j);
		if(j==1)
			h_qtree[i]=true;
		else
			h_qtree[i]=false;
	}
	
	scanf("%d",&h_dverc);
	h_dvert=(int *)malloc(sizeof(int)*(h_dverc+1));
	for(i=0;i<=h_dverc;i++){
		scanf("%d",&h_dvert[i]);
	}
	for(i=0;i<=h_qverc;i++)
		h_cvslist[i]=(int *)malloc(sizeof(int)*(h_dverc+1));
	
	h_delist=(int *)malloc(sizeof(int)*h_dvert[h_dverc]);
	for(i=0;i<h_dvert[h_dverc];i++)
		scanf("%d",&h_delist[i]);
	hipMalloc(&d_qverc,sizeof(int));
	hipMalloc(&d_over,sizeof(bool));
	hipMalloc(&d_qvert,sizeof(int)*(h_qverc+1));
	hipMalloc(&d_qidtov,sizeof(int)*(h_qverc+1));
	//cudaMalloc(&d_loc,sizeof(int)*(h_qverc+1));
	hipMalloc(&d_qelist,sizeof(int)*h_qvert[h_qverc]);
	hipMalloc(&d_qtree,sizeof(bool)*h_qvert[h_qverc]);
	hipMalloc(&d_hash1,sizeof(int)*1000038);
	hipMalloc(&d_hash2,sizeof(int)*1000038);
	
	hipMalloc(&d_qvid,sizeof(int)*(h_qverc+1));
	hipMemcpy(d_qverc,&h_qverc,sizeof(int),hipMemcpyHostToDevice);
	hipMemcpy(d_qvert,h_qvert,sizeof(int)*(h_qverc+1),hipMemcpyHostToDevice);
	hipMemcpy(d_qelist,h_qelist,sizeof(int)*h_qvert[h_qverc],hipMemcpyHostToDevice);
	hipMemcpy(d_qtree,h_qtree,sizeof(bool)*h_qvert[h_qverc],hipMemcpyHostToDevice);
	hipMemset(d_hash1,0,sizeof(int)*1000038);
	hipMemset(d_hash2,0,sizeof(int)*1000038);
	//cudaMemset(d_loc,0,sizeof(int)*(h_qverc+1));
	hipMemset(d_qidtov,-1,sizeof(int)*(h_qverc+1));
	hipMemset(d_qvid,0,sizeof(int)*(h_qverc+1));
	int *h_hash1=(int *)malloc(sizeof(int)*1000038);
	int *h_hash2=(int *)malloc(sizeof(int)*1000038);
	dim3 blocks((sqrt(h_qverc)/16 )+ 1,(sqrt(h_qverc)/16)+1);
	dim3 threads(16,16);
	
	//int *d_qvert,int *d_dverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_hash1,bool *d_hash2)
	h_over=true;
	//h_qvid[1]=1;
	//h_qvid[3]=1;
	//cudaMemcpy(d_qvid,h_qvid,sizeof(int)*(h_qverc+1),cudaMemcpyHostToDevice);
//printf("qt%d %dqt\n",h_qtree[0],h_qtree[1]);
	setdeg1<<<blocks,threads>>>(d_qvert,d_qverc,d_qvid,d_qtree);

	h_over=false;
	int maxval=2;
	while(!h_over)
	{
		h_over=true;
		hipMemcpy(d_over, &h_over, sizeof(bool), hipMemcpyHostToDevice) ;
		hipMemset(d_hash1,0,sizeof(int)*1000038);
		findhash <<<blocks,threads>>> (d_qvert,d_qverc,d_qvid,d_qelist,d_over,d_qtree,d_hash1,d_hash2);
		//(int *d_qvert,int *d_dverc,int *d_qvid,int *d_qelist,bool *d_over,bool *d_hash1,bool *d_qtree,bool *d_hash2)
		hipError_t err = hipGetLastError();
		if(err!=hipSuccess)
		{
			printf("Error: %s\n", hipGetErrorString(err));
			printf("Not Ok");
		}
		hipMemcpy(h_hash1,d_hash1,sizeof(int)*1000038,hipMemcpyDeviceToHost);
		h_hash1[0]+=maxval;
		thrust::exclusive_scan(h_hash1,h_hash1+1000038,h_hash1);
		maxval=h_hash1[1000037];
		hipMemcpy(d_hash1,h_hash1,sizeof(int)*1000038,hipMemcpyHostToDevice);
		puttoid<<<blocks,threads>>>(d_qvert,d_qverc,d_qvid,d_qelist,d_qtree,d_hash1,d_qidtov);
///		cudaMemcpy(h_hash2,d_hash2,sizeof(bool)*1000038,cudaMemcpyDeviceToHost);
		hipMemcpy(&h_over, d_over, sizeof(bool), hipMemcpyDeviceToHost) ;
		
		//printf("over flag:%d ",h_over);
		/*for(i=0;i<h_qverc;i++){
			//if()
				printf("%d ",h_qvid[i]);
//			if(h_hash2[i])
//				printf("h2 %d ",i);
//			if(h_hash1[i] || h_hash2[i])
//				printf("\n");
		}
		printf("\n");*/

	}	
	hipMemcpy(h_qvid,d_qvid,sizeof(int)*h_qverc,hipMemcpyDeviceToHost);
	hipMemcpy(h_qidtov,d_qidtov,sizeof(int)*(h_qverc+1),hipMemcpyDeviceToHost);
	for(i=0;i<=h_qverc;i++){
		printf("%d ",h_qidtov[i]);
	}
	printf("\n");
	for(i=0;i<=h_qverc;i++){
		printf("%d ",h_qvid[i]);
	}
	printf("\n");
	hipFree(d_qtree);
	hipFree(d_hash1);
	hipFree(d_hash2);
	free(h_hash1);
	free(h_hash2);
	free(h_qtree);
	
	hipMalloc(&d_cvslist,sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		hipMalloc(&h_tem[i],sizeof(int)*(h_dverc+1));
		hipMemset(h_tem[i],0,sizeof(int)*(h_dverc+1));
	}
	hipMemset(h_tem[1],1,sizeof(int)*(h_dverc+1));
	hipMemcpy(d_cvslist,h_tem,sizeof(int*)*(h_qverc+1),hipMemcpyHostToDevice);
	hipMalloc(&d_dvert,sizeof(int)*(h_dverc+1));
	hipMalloc(&d_dverc,sizeof(int));
	hipMalloc(&d_delist,sizeof(int)*h_dvert[h_dverc]);	
	hipMemcpy(d_dverc,&h_dverc,sizeof(int),hipMemcpyHostToDevice);
	hipMemcpy(d_dvert,h_dvert,sizeof(int)*(h_dverc+1),hipMemcpyHostToDevice);
	hipMemcpy(d_delist,h_delist,sizeof(int)*h_dvert[h_dverc],hipMemcpyHostToDevice);
	dim3 dblocks((sqrt(h_dverc)/16 )+ 1,(sqrt(h_dverc)/16)+1);
	dim3 dthreads(16,16);
	int **d_cvsverlist,**d_temverlist;
	int *d_size_cvs,*h_size_cvs;
	memset(h_cvslist[1],1,sizeof(int)*(h_dverc+1));
	h_size_cvs=(int *)malloc(sizeof(int)*(h_qverc+1));
	memset(h_size_cvs,0,sizeof(int)*(h_qverc+1));
	hipMalloc(&d_size_cvs,sizeof(int)*(h_qverc+1));
	hipMemset(d_size_cvs,0,sizeof(int)*(h_qverc+1));
	hipMalloc(&d_cvsverlist,sizeof(int*)*(h_qverc+1));
	d_temverlist=(int **)malloc(sizeof(int*)*(h_qverc+1));
	for(i=0;i<=h_qverc;i++){
		hipMalloc(&d_temverlist[i],sizeof(int)*(h_dverc+1));
		hipMemset(d_temverlist[i],0,sizeof(int)*(h_dverc+1));
	}
	hipMemcpy(d_cvsverlist,d_temverlist,sizeof(int*)*(h_qverc+1),hipMemcpyHostToDevice);
	long long int totalthreads=1;
	for(i=0;i<h_dverc;i++)
		h_cvslist[1][i]=i;
	hipMemcpy(d_temverlist[1],h_cvslist[1],sizeof(int)*(h_dverc+1),hipMemcpyHostToDevice);
	h_size_cvs[1]=h_dverc;
	for(i=0;i<=h_qverc;i++)
	{
		if(h_qidtov[i]!=-1)
		{

		//findcvs(int ver,int *d_dvert,int *d_dverc,int *d_delist,int *d_qvert,int *d_qelist,int *d_qvid,bool ** d_dcvslist )
		findcvs<<<dblocks,dthreads>>>(h_qidtov[i],d_dvert,d_dverc,d_delist,d_qvert,d_qelist,d_qvid,d_cvslist);
		hipError_t err = hipGetLastError();
	
		hipMemcpy(h_cvslist[i],h_tem[i],sizeof(int)*(h_dverc+1),hipMemcpyDeviceToHost);
		for(j=0;j<=h_dverc;j++)
			if(h_cvslist[i][j])
				printf("%d ",j);
		printf("\n");
		//printf("%d ",h_qidtov[i]);
		thrust::exclusive_scan(h_cvslist[i],h_cvslist[i]+h_dverc+1,h_cvslist[i]);
		h_size_cvs[i]=h_cvslist[i][h_dverc];
		hipMemcpy(h_tem[i],h_cvslist[i],sizeof(int)*(h_dverc+1),hipMemcpyHostToDevice);
		puttolist<<<dblocks,dthreads>>>(d_dverc,h_tem[i],d_temverlist[i]);
	//	cudaMemcpy(h_cvslist[i],d_temverlist[i],sizeof(int)*(h_dverc+1),cudaMemcpyDeviceToHost);
	//	for(j=0;j<=h_dverc;j++)
	//		printf("%d ",h_cvslist[i][j]);	
		}	
		
	}
	//	cudaMemcpy(h_delist,d_delist,sizeof(int)*(h_dvert[h_dverc]),cudaMemcpyDeviceToHost);
	//	for(j=0;j<h_dvert[h_dverc];j++)
	//		printf("%d ",h_delist[j]);	
			
	for(i=0;i<h_qverc;i++)
		if(h_size_cvs[h_qvid[i]])
		totalthreads*=h_size_cvs[h_qvid[i]];
	printf("Start %lld\n",totalthreads);
	hipMemcpy(d_size_cvs,h_size_cvs,sizeof(int)*(h_qverc+1),hipMemcpyHostToDevice);
	//totalthreads=1000;
	dim3 dpblocks(((int)(sqrt(totalthreads)/16 )+ 1),((int)(sqrt(totalthreads)/16)+1));
	dim3 dpthreads(16,16);
	 int *d_mapans,*d_countans,*h_countans;
	hipMalloc(&d_mapans,sizeof( int)*totalthreads*(h_qverc+1));
	hipMalloc(&d_countans,sizeof( int)*(totalthreads+1));
	hipMemset(d_countans,0,sizeof( int)*(totalthreads+1));
	//h_countans=(int *)malloc(sizeof(int)*(totalthreads+1));
	//h_countans=0;
	//cudaMemcpy(d_countans, &h_countans, sizeof( int), cudaMemcpyHostToDevice) ;
	//cudaMemcpy(&h_countans, d_qverc, sizeof(int), cudaMemcpyDeviceToHost) ;
	//printf("%d\n",h_countans);
	findall<<<dpblocks,dpthreads>>> (d_mapans,d_countans,d_qvid,d_qverc,d_qelist,d_qvert,d_dvert,d_delist,d_cvsverlist,d_size_cvs);
	thrust::device_ptr<int> cptr=thrust::device_pointer_cast(d_countans);
	//int sum=thrust::count(cptr,cptr+totalthreads,1);
	//cudaMemcpy(h_countans, d_countans, sizeof(int)*totalthreads, cudaMemcpyDeviceToHost) ;
	//thrust::exclusive_scan(h_countans,h_countans+totalthreads+1,h_countans);
	//printf("%d\n",h_countans[totalthreads-1] );
	//printf("%d\n",h_countans);
	//printf("%d\n",sum);
	/*j=0;
	for(i=0;i<totalthreads;i++)
		if(h_countans[i])
			j++;
	printf("%d\n",j);
	*///bool * check=(bool *)malloc(sizeof(bool)*(h_dverc+1));
	//memset(check,false,sizeof(bool)*(h_dverc+1));
	//qdmap=(int *)malloc(sizeof(int)*(h_qverc+1));
	//cudaMalloc(&d_qdmap,sizeof(int)*(h_qverc+1));
	//callforallperm(check,h_cvslist,1,h_qverc,h_dverc);

	hipFree(d_over);
	hipFree(d_qverc);
	hipFree(d_qvert);
	hipFree(d_qelist);
	hipFree(d_qvid);
	hipFree(d_qidtov);
	hipFree(d_dvert);
	hipFree(d_delist);
	hipFree(d_dverc);
	hipFree(d_cvslist);
	hipFree(d_cvsverlist);
	hipFree(d_size_cvs);
	/*free(h_qvid);
	free(h_qvert);
	//free(h_qelist);
	free(h_qidtov);
	free(h_cvslist);
	free(h_dvert);
	free(h_delist);*/
}
	

	.text
	.file	"isokernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_ # -- Begin function _Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	.type	_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_,@function
_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_: # @_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8findhashPiS_S_S_PbS0_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_, .Lfunc_end0-_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__setdeg1PiS_S_Pb # -- Begin function _Z22__device_stub__setdeg1PiS_S_Pb
	.type	_Z22__device_stub__setdeg1PiS_S_Pb,@function
_Z22__device_stub__setdeg1PiS_S_Pb:     # @_Z22__device_stub__setdeg1PiS_S_Pb
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7setdeg1PiS_S_Pb, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__setdeg1PiS_S_Pb, .Lfunc_end1-_Z22__device_stub__setdeg1PiS_S_Pb
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__puttoidPiS_S_S_PbS_S_ # -- Begin function _Z22__device_stub__puttoidPiS_S_S_PbS_S_
	.type	_Z22__device_stub__puttoidPiS_S_S_PbS_S_,@function
_Z22__device_stub__puttoidPiS_S_S_PbS_S_: # @_Z22__device_stub__puttoidPiS_S_S_PbS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7puttoidPiS_S_S_PbS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z22__device_stub__puttoidPiS_S_S_PbS_S_, .Lfunc_end2-_Z22__device_stub__puttoidPiS_S_S_PbS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_ # -- Begin function _Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	.type	_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_,@function
_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_: # @_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7findcvsiPiS_S_S_S_S_PS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_, .Lfunc_end3-_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__puttolistPiS_S_ # -- Begin function _Z24__device_stub__puttolistPiS_S_
	.type	_Z24__device_stub__puttolistPiS_S_,@function
_Z24__device_stub__puttolistPiS_S_:     # @_Z24__device_stub__puttolistPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9puttolistPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z24__device_stub__puttolistPiS_S_, .Lfunc_end4-_Z24__device_stub__puttolistPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_ # -- Begin function _Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_
	.type	_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_,@function
_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_: # @_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9checkpermPbPiS0_S0_S0_S0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_, .Lfunc_end5-_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_ # -- Begin function _Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	.type	_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_,@function
_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_: # @_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7findallPiS_S_S_S_S_S_S_PS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_, .Lfunc_end6-_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI7_0:
	.quad	0x3fb0000000000000              # double 0.0625
.LCPI7_1:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4, %edi
	callq	hipSetDevice
	leaq	4(%rsp), %rbx
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%rbx), %r14
	leaq	4(,%r14,4), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, h_qvid(%rip)
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, h_qidtov(%rip)
	leaq	8(,%r14,8), %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	testq	%r14, %r14
	js	.LBB7_3
# %bb.1:                                # %.lr.ph.preheader
	movq	$-1, %r12
	movq	%r15, %rbx
.LBB7_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	4(%rsp), %r14
	incq	%r12
	addq	$4, %rbx
	cmpq	%r14, %r12
	jl	.LBB7_2
.LBB7_3:                                # %._crit_edge
	movslq	(%r15,%r14,4), %rbx
	leaq	(,%rbx,4), %rdi
	callq	malloc
	testq	%rbx, %rbx
	movq	%rax, 96(%rsp)                  # 8-byte Spill
	jle	.LBB7_85
# %bb.4:                                # %.lr.ph248.preheader
	movq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB7_5:                                # %.lr.ph248
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r14
	movslq	4(%rsp), %rax
	movslq	(%r15,%rax,4), %r12
	addq	$4, %rbx
	cmpq	%r12, %r14
	jl	.LBB7_5
# %bb.6:                                # %._crit_edge249
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r13
	testl	%r12d, %r12d
	jle	.LBB7_9
# %bb.7:                                # %.lr.ph253.preheader
	leaq	12(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB7_8:                                # %.lr.ph253
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	cmpl	$1, 12(%rsp)
	sete	(%r13,%r14)
	incq	%r14
	movslq	4(%rsp), %rax
	movslq	(%r15,%rax,4), %rax
	cmpq	%rax, %r14
	jl	.LBB7_8
	jmp	.LBB7_9
.LBB7_85:                               # %._crit_edge249.thread
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r13
.LBB7_9:                                # %._crit_edge254
	movq	%r13, 40(%rsp)                  # 8-byte Spill
	leaq	8(%rsp), %rbx
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%rbx), %r14
	leaq	4(,%r14,4), %rdi
	callq	malloc
	testq	%r14, %r14
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	js	.LBB7_12
# %bb.10:                               # %.lr.ph258.preheader
	movq	%rax, %r12
	movq	$-1, %r13
	movq	%rax, %rbx
.LBB7_11:                               # %.lr.ph258
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	8(%rsp), %r14
	incq	%r13
	addq	$4, %rbx
	cmpq	%r14, %r13
	jl	.LBB7_11
.LBB7_12:                               # %.preheader238
	movl	4(%rsp), %r13d
	movslq	%r14d, %r14
	testl	%r13d, %r13d
	movq	24(%rsp), %r12                  # 8-byte Reload
	js	.LBB7_15
# %bb.13:                               # %.lr.ph262
	leaq	4(,%r14,4), %rbx
	incq	%r13
	xorl	%ebp, %ebp
.LBB7_14:                               # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, (%r12,%rbp,8)
	incq	%rbp
	cmpq	%rbp, %r13
	jne	.LBB7_14
.LBB7_15:                               # %._crit_edge263
	movq	56(%rsp), %r12                  # 8-byte Reload
	movslq	(%r12,%r14,4), %rbx
	leaq	(,%rbx,4), %rdi
	callq	malloc
	movq	%rax, %r13
	testq	%rbx, %rbx
	jle	.LBB7_18
# %bb.16:                               # %.lr.ph266.preheader
	movq	%r13, %rbx
	xorl	%r14d, %r14d
.LBB7_17:                               # %.lr.ph266
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r14
	movslq	8(%rsp), %rax
	movslq	(%r12,%rax,4), %rax
	addq	$4, %rbx
	cmpq	%rax, %r14
	jl	.LBB7_17
.LBB7_18:                               # %._crit_edge267
	movq	%r13, 48(%rsp)                  # 8-byte Spill
	movl	$d_qverc, %edi
	movl	$4, %esi
	callq	hipMalloc
	movl	$d_over, %edi
	movl	$1, %esi
	callq	hipMalloc
	leaq	4(%rsp), %rbx
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rsi
	movl	$d_qvert, %edi
	callq	hipMalloc
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rsi
	movl	$d_qidtov, %edi
	callq	hipMalloc
	movslq	(%rbx), %rax
	movslq	(%r15,%rax,4), %rsi
	shlq	$2, %rsi
	movl	$d_qelist, %edi
	callq	hipMalloc
	movslq	(%rbx), %rax
	movslq	(%r15,%rax,4), %rsi
	movl	$d_qtree, %edi
	callq	hipMalloc
	leaq	32(%rsp), %rbp
	movl	$4000152, %esi                  # imm = 0x3D0998
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	88(%rsp), %r13
	movl	$4000152, %esi                  # imm = 0x3D0998
	movq	%r13, %rdi
	callq	hipMalloc
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rsi
	movl	$d_qvid, %edi
	callq	hipMalloc
	movq	d_qverc(%rip), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_qvert(%rip), %rdi
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_qelist(%rip), %rdi
	movslq	(%rbx), %rax
	movslq	(%r15,%rax,4), %rdx
	shlq	$2, %rdx
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_qtree(%rip), %rdi
	movslq	(%rbx), %rax
	movslq	(%r15,%rax,4), %rdx
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$4000152, %edx                  # imm = 0x3D0998
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%r13), %rdi
	movl	$4000152, %edx                  # imm = 0x3D0998
	xorl	%esi, %esi
	callq	hipMemset
	movq	d_qidtov(%rip), %rdi
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rdx
	movl	$-1, %esi
	callq	hipMemset
	movq	d_qvid(%rip), %rdi
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movl	$4000152, %edi                  # imm = 0x3D0998
	callq	malloc
	cvtsi2sdl	(%rbx), %xmm0
	movq	%rax, %rbp
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB7_20
# %bb.19:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB7_21
.LBB7_20:                               # %call.sqrt
	callq	sqrt
	xorpd	%xmm1, %xmm1
.LBB7_21:                               # %._crit_edge267.split
	movabsq	$68719476752, %r15              # imm = 0x1000000010
	mulsd	.LCPI7_0(%rip), %xmm0
	addsd	.LCPI7_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2sdl	4(%rsp), %xmm0
	ucomisd	%xmm1, %xmm0
	jb	.LBB7_23
# %bb.22:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB7_24
.LBB7_23:                               # %call.sqrt425
	callq	sqrt
.LBB7_24:                               # %._crit_edge267.split.split
	mulsd	.LCPI7_0(%rip), %xmm0
	addsd	.LCPI7_1(%rip), %xmm0
	cvttsd2si	%xmm0, %r13
	movl	%ebx, %eax
	shlq	$32, %r13
	orq	%rax, %r13
	movb	$1, h_over(%rip)
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_26
# %bb.25:
	movq	d_qvert(%rip), %rdi
	movq	d_qverc(%rip), %rsi
	movq	d_qvid(%rip), %rdx
	movq	d_qtree(%rip), %rcx
	callq	_Z22__device_stub__setdeg1PiS_S_Pb
.LBB7_26:
	movl	$2, %ebx
.LBB7_27:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_32 Depth 2
	movb	$1, h_over(%rip)
	movq	d_over(%rip), %rdi
	movl	$h_over, %esi
	movl	$1, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	movl	$4000152, %edx                  # imm = 0x3D0998
	xorl	%esi, %esi
	callq	hipMemset
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_29
# %bb.28:                               #   in Loop: Header=BB7_27 Depth=1
	movq	d_qvert(%rip), %rdi
	movq	d_qverc(%rip), %rsi
	movq	d_qvid(%rip), %rdx
	movq	d_qelist(%rip), %rcx
	movq	d_over(%rip), %r8
	movq	d_qtree(%rip), %r9
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB7_29:                               #   in Loop: Header=BB7_27 Depth=1
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB7_31
# %bb.30:                               #   in Loop: Header=BB7_27 Depth=1
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
.LBB7_31:                               #   in Loop: Header=BB7_27 Depth=1
	movq	32(%rsp), %rsi
	movl	$4000152, %edx                  # imm = 0x3D0998
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	addl	(%rbp), %ebx
	movl	$0, (%rbp)
	movl	$4, %eax
.LBB7_32:                               # %.lr.ph.i.i.i.i.i.i.i
                                        #   Parent Loop BB7_27 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbp,%rax), %ecx
	addl	%ebx, %ecx
	movl	%ebx, (%rbp,%rax)
	addq	$4, %rax
	movl	%ecx, %ebx
	cmpq	$4000152, %rax                  # imm = 0x3D0998
	jne	.LBB7_32
# %bb.33:                               # %_ZN6thrust14exclusive_scanIPiS1_EET0_T_S3_S2_.exit
                                        #   in Loop: Header=BB7_27 Depth=1
	movl	4000148(%rbp), %ebx
	movq	32(%rsp), %rdi
	movl	$4000152, %edx                  # imm = 0x3D0998
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_35
# %bb.34:                               #   in Loop: Header=BB7_27 Depth=1
	movq	d_qvert(%rip), %rdi
	movq	d_qverc(%rip), %rsi
	movq	d_qvid(%rip), %rdx
	movq	d_qelist(%rip), %rcx
	movq	d_qtree(%rip), %r8
	movq	32(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	pushq	d_qidtov(%rip)
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__puttoidPiS_S_S_PbS_S_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB7_35:                               #   in Loop: Header=BB7_27 Depth=1
	movq	d_over(%rip), %rsi
	movl	$h_over, %edi
	movl	$1, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpb	$0, h_over(%rip)
	je	.LBB7_27
# %bb.36:
	movq	h_qvid(%rip), %rdi
	movq	d_qvid(%rip), %rsi
	movslq	4(%rsp), %rdx
	shlq	$2, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	h_qidtov(%rip), %rdi
	movq	d_qidtov(%rip), %rsi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 4(%rsp)
	js	.LBB7_39
# %bb.37:                               # %.lr.ph272.preheader
	movq	$-1, %rbx
.LBB7_38:                               # %.lr.ph272
                                        # =>This Inner Loop Header: Depth=1
	movq	h_qidtov(%rip), %rax
	movl	4(%rax,%rbx,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movslq	4(%rsp), %rax
	incq	%rbx
	cmpq	%rax, %rbx
	jl	.LBB7_38
.LBB7_39:                               # %._crit_edge273
	movl	$10, %edi
	callq	putchar@PLT
	cmpl	$0, 4(%rsp)
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	48(%rsp), %r13                  # 8-byte Reload
	js	.LBB7_42
# %bb.40:                               # %.lr.ph277.preheader
	movq	$-1, %rbx
.LBB7_41:                               # %.lr.ph277
                                        # =>This Inner Loop Header: Depth=1
	movq	h_qvid(%rip), %rax
	movl	4(%rax,%rbx,4), %esi
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
	movslq	4(%rsp), %rax
	incq	%rbx
	cmpq	%rax, %rbx
	jl	.LBB7_41
.LBB7_42:                               # %._crit_edge278
	movl	$10, %edi
	callq	putchar@PLT
	movq	d_qtree(%rip), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	88(%rsp), %rdi
	callq	hipFree
	movq	%rbp, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movslq	4(%rsp), %rax
	leaq	8(,%rax,8), %rsi
	leaq	80(%rsp), %rdi
	callq	hipMalloc
	cmpl	$0, 4(%rsp)
	js	.LBB7_45
# %bb.43:                               # %.lr.ph282.preheader
	movq	$-1, %r14
	movq	16(%rsp), %rbx                  # 8-byte Reload
.LBB7_44:                               # %.lr.ph282
                                        # =>This Inner Loop Header: Depth=1
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rsi
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movslq	4(%rsp), %rax
	incq	%r14
	addq	$8, %rbx
	cmpq	%rax, %r14
	jl	.LBB7_44
.LBB7_45:                               # %._crit_edge283
	movq	16(%rsp), %r14                  # 8-byte Reload
	movq	8(%r14), %rdi
	leaq	8(%rsp), %rbx
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rdx
	movl	$1, %esi
	callq	hipMemset
	movq	80(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	8(,%rax,8), %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rsi
	movl	$d_dvert, %edi
	callq	hipMalloc
	movl	$d_dverc, %edi
	movl	$4, %esi
	callq	hipMalloc
	movslq	(%rbx), %rax
	movslq	(%r12,%rax,4), %rsi
	shlq	$2, %rsi
	movl	$d_delist, %edi
	callq	hipMalloc
	movq	d_dverc(%rip), %rdi
	movl	$4, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_dvert(%rip), %rdi
	movslq	(%rbx), %rax
	leaq	4(,%rax,4), %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	d_delist(%rip), %rdi
	movslq	(%rbx), %rax
	movslq	(%r12,%rax,4), %rdx
	shlq	$2, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2sdl	(%rbx), %xmm0
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB7_47
# %bb.46:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB7_48
.LBB7_47:                               # %call.sqrt426
	callq	sqrt
	xorpd	%xmm1, %xmm1
.LBB7_48:                               # %._crit_edge283.split
	movsd	%xmm0, 56(%rsp)                 # 8-byte Spill
	xorps	%xmm0, %xmm0
	cvtsi2sdl	8(%rsp), %xmm0
	ucomisd	%xmm1, %xmm0
	jb	.LBB7_50
# %bb.49:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB7_51
.LBB7_50:                               # %call.sqrt427
	callq	sqrt
.LBB7_51:                               # %._crit_edge283.split.split
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	8(%rax), %rbx
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	%rbx, %rdi
	movl	$1, %esi
	callq	memset@PLT
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %r13
	movl	$1, %edi
	movq	%r13, %rsi
	callq	calloc@PLT
	movq	%rax, %r12
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movslq	4(%rsp), %rax
	leaq	8(,%rax,8), %rsi
	leaq	72(%rsp), %rdi
	callq	hipMalloc
	movslq	4(%rsp), %r14
	leaq	8(,%r14,8), %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %rbp
	testq	%r14, %r14
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	js	.LBB7_55
# %bb.52:                               # %.lr.ph287.preheader
	movq	$-1, %r14
.LBB7_53:                               # %.lr.ph287
                                        # =>This Inner Loop Header: Depth=1
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rsi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	xorl	%esi, %esi
	callq	hipMemset
	movslq	4(%rsp), %rax
	incq	%r14
	addq	$8, %rbp
	cmpq	%rax, %r14
	jl	.LBB7_53
# %bb.54:                               # %._crit_edge288.loopexit
	leaq	8(,%rax,8), %r13
	movq	40(%rsp), %rbp                  # 8-byte Reload
.LBB7_55:                               # %._crit_edge288
	movq	72(%rsp), %rdi
	movq	%rbp, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	8(%rsp), %eax
	testl	%eax, %eax
	jle	.LBB7_58
# %bb.56:                               # %.lr.ph292.preheader
	xorl	%ecx, %ecx
.LBB7_57:                               # %.lr.ph292
                                        # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rbx,%rcx,4)
	incq	%rcx
	movslq	8(%rsp), %rax
	cmpq	%rax, %rcx
	jl	.LBB7_57
.LBB7_58:                               # %._crit_edge293
	movq	8(%rbp), %rdi
	cltq
	leaq	4(,%rax,4), %rdx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	8(%rsp), %eax
	movl	%eax, 4(%r12)
	movl	$1, %r13d
	cmpl	$0, 4(%rsp)
	js	.LBB7_78
# %bb.59:                               # %.lr.ph303.preheader
	movsd	56(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	mulsd	.LCPI7_0(%rip), %xmm0
	addsd	.LCPI7_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rax
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	mulsd	.LCPI7_0(%rip), %xmm0
	addsd	.LCPI7_1(%rip), %xmm0
	cvttsd2si	%xmm0, %rbx
	movl	%eax, %eax
	shlq	$32, %rbx
	orq	%rax, %rbx
	xorl	%r14d, %r14d
.LBB7_60:                               # %.lr.ph303
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_65 Depth 2
                                        #     Child Loop BB7_71 Depth 2
	movq	h_qidtov(%rip), %rax
	cmpl	$-1, (%rax,%r14,4)
	je	.LBB7_74
# %bb.61:                               #   in Loop: Header=BB7_60 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_63
# %bb.62:                               #   in Loop: Header=BB7_60 Depth=1
	movq	h_qidtov(%rip), %rax
	movl	(%rax,%r14,4), %edi
	movq	d_dvert(%rip), %rsi
	movq	d_dverc(%rip), %rdx
	movq	d_delist(%rip), %rcx
	movq	d_qvert(%rip), %r8
	movq	d_qelist(%rip), %r9
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	d_qvid(%rip)
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB7_63:                               #   in Loop: Header=BB7_60 Depth=1
	callq	hipGetLastError
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%r14,8), %rbp
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%r14,8), %rsi
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	%rbp, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$0, 12(%rsp)
	movl	8(%rsp), %eax
	testl	%eax, %eax
	js	.LBB7_68
# %bb.64:                               # %.lr.ph298.preheader
                                        #   in Loop: Header=BB7_60 Depth=1
	xorl	%esi, %esi
.LBB7_65:                               # %.lr.ph298
                                        #   Parent Loop BB7_60 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	%esi, %rcx
	cmpl	$0, (%rbp,%rcx,4)
	je	.LBB7_67
# %bb.66:                               #   in Loop: Header=BB7_65 Depth=2
	movl	$.L.str.3, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %esi
	movl	8(%rsp), %eax
.LBB7_67:                               #   in Loop: Header=BB7_65 Depth=2
	leal	1(%rsi), %ecx
	movl	%ecx, 12(%rsp)
	cmpl	%eax, %esi
	movl	%ecx, %esi
	jl	.LBB7_65
.LBB7_68:                               # %._crit_edge299
                                        #   in Loop: Header=BB7_60 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	movslq	8(%rsp), %rax
	leaq	4(,%rax,4), %rcx
	addq	%rbp, %rcx
	cmpq	%rcx, %rbp
	je	.LBB7_72
# %bb.69:                               #   in Loop: Header=BB7_60 Depth=1
	movl	(%rbp), %ecx
	movl	$0, (%rbp)
	testl	%eax, %eax
	je	.LBB7_72
# %bb.70:                               # %.lr.ph.i.i.i.i.i.i.i210.preheader
                                        #   in Loop: Header=BB7_60 Depth=1
	shlq	$2, %rax
	xorl	%edx, %edx
.LBB7_71:                               # %.lr.ph.i.i.i.i.i.i.i210
                                        #   Parent Loop BB7_60 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	4(%rbp,%rdx), %esi
	addl	%ecx, %esi
	movl	%ecx, 4(%rbp,%rdx)
	addq	$4, %rdx
	movl	%esi, %ecx
	cmpq	%rdx, %rax
	jne	.LBB7_71
.LBB7_72:                               # %_ZN6thrust14exclusive_scanIPiS1_EET0_T_S3_S2_.exit217
                                        #   in Loop: Header=BB7_60 Depth=1
	movslq	8(%rsp), %rax
	movl	(%rbp,%rax,4), %ecx
	movl	%ecx, (%r12,%r14,4)
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movq	(%rcx,%r14,8), %rdi
	leaq	4(,%rax,4), %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_74
# %bb.73:                               #   in Loop: Header=BB7_60 Depth=1
	movq	d_dverc(%rip), %rdi
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%r14,8), %rsi
	movq	40(%rsp), %rax                  # 8-byte Reload
	movq	(%rax,%r14,8), %rdx
	callq	_Z24__device_stub__puttolistPiS_S_
.LBB7_74:                               #   in Loop: Header=BB7_60 Depth=1
	leaq	1(%r14), %rcx
	movslq	4(%rsp), %rax
	cmpq	%rax, %r14
	movq	%rcx, %r14
	jl	.LBB7_60
# %bb.75:                               # %.preheader
	movl	%eax, %eax
	testl	%eax, %eax
	jle	.LBB7_78
# %bb.76:                               # %.lr.ph307
	movl	$1, %r13d
	movq	h_qvid(%rip), %rcx
	xorl	%edx, %edx
.LBB7_77:                               # =>This Inner Loop Header: Depth=1
	movslq	(%rcx,%rdx,4), %rsi
	movl	(%r12,%rsi,4), %esi
	cmpl	$1, %esi
	adcl	$0, %esi
	movslq	%esi, %rsi
	imulq	%rsi, %r13
	incq	%rdx
	cmpq	%rdx, %rax
	jne	.LBB7_77
.LBB7_78:                               # %._crit_edge308
	movl	$.L.str.5, %edi
	movq	%r13, %rsi
	xorl	%eax, %eax
	callq	printf
	movq	64(%rsp), %rdi
	movslq	4(%rsp), %rax
	leaq	4(,%rax,4), %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2sd	%r13, %xmm2
	sqrtsd	%xmm2, %xmm1
	xorpd	%xmm3, %xmm3
	ucomisd	%xmm3, %xmm2
	movapd	%xmm1, %xmm0
	jae	.LBB7_80
# %bb.79:                               # %call.sqrt428
	movapd	%xmm2, %xmm0
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movsd	%xmm2, 24(%rsp)                 # 8-byte Spill
	callq	sqrt
	xorpd	%xmm3, %xmm3
	movsd	24(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movsd	16(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
.LBB7_80:                               # %._crit_edge308.split
	mulsd	.LCPI7_0(%rip), %xmm0
	cvttsd2si	%xmm0, %ebp
	incl	%ebp
	ucomisd	%xmm3, %xmm2
	jae	.LBB7_82
# %bb.81:                               # %call.sqrt429
	movapd	%xmm2, %xmm0
	callq	sqrt
	movapd	%xmm0, %xmm1
.LBB7_82:                               # %._crit_edge308.split.split
	mulsd	.LCPI7_0(%rip), %xmm1
	cvttsd2si	%xmm1, %ebx
	incl	%ebx
	movl	%ebp, %eax
	shlq	$32, %rbx
	orq	%rax, %rbx
	leaq	(,%r13,4), %rax
	movslq	4(%rsp), %rsi
	incq	%rsi
	imulq	%rax, %rsi
	leaq	112(%rsp), %rdi
	callq	hipMalloc
	leaq	4(,%r13,4), %r14
	leaq	104(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	xorl	%esi, %esi
	movq	%r14, %rdx
	callq	hipMemset
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_84
# %bb.83:
	movq	112(%rsp), %rdi
	movq	104(%rsp), %rsi
	movq	d_qvid(%rip), %rdx
	movq	d_qverc(%rip), %rcx
	movq	d_qelist(%rip), %r8
	movq	d_qvert(%rip), %r9
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	d_delist(%rip)
	.cfi_adjust_cfa_offset 8
	pushq	d_dvert(%rip)
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB7_84:
	movq	d_over(%rip), %rdi
	callq	hipFree
	movq	d_qverc(%rip), %rdi
	callq	hipFree
	movq	d_qvert(%rip), %rdi
	callq	hipFree
	movq	d_qelist(%rip), %rdi
	callq	hipFree
	movq	d_qvid(%rip), %rdi
	callq	hipFree
	movq	d_qidtov(%rip), %rdi
	callq	hipFree
	movq	d_dvert(%rip), %rdi
	callq	hipFree
	movq	d_delist(%rip), %rdi
	callq	hipFree
	movq	d_dverc(%rip), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8findhashPiS_S_S_PbS0_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7setdeg1PiS_S_Pb, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7puttoidPiS_S_S_PbS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7findcvsiPiS_S_S_S_S_PS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9puttolistPiS_S_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9checkpermPbPiS0_S0_S0_S0_S0_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7findallPiS_S_S_S_S_S_S_PS_S_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8findhashPiS_S_S_PbS0_S_S_,@object # @_Z8findhashPiS_S_S_PbS0_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z8findhashPiS_S_S_PbS0_S_S_
	.p2align	3, 0x0
_Z8findhashPiS_S_S_PbS0_S_S_:
	.quad	_Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	.size	_Z8findhashPiS_S_S_PbS0_S_S_, 8

	.type	_Z7setdeg1PiS_S_Pb,@object      # @_Z7setdeg1PiS_S_Pb
	.globl	_Z7setdeg1PiS_S_Pb
	.p2align	3, 0x0
_Z7setdeg1PiS_S_Pb:
	.quad	_Z22__device_stub__setdeg1PiS_S_Pb
	.size	_Z7setdeg1PiS_S_Pb, 8

	.type	_Z7puttoidPiS_S_S_PbS_S_,@object # @_Z7puttoidPiS_S_S_PbS_S_
	.globl	_Z7puttoidPiS_S_S_PbS_S_
	.p2align	3, 0x0
_Z7puttoidPiS_S_S_PbS_S_:
	.quad	_Z22__device_stub__puttoidPiS_S_S_PbS_S_
	.size	_Z7puttoidPiS_S_S_PbS_S_, 8

	.type	_Z7findcvsiPiS_S_S_S_S_PS_,@object # @_Z7findcvsiPiS_S_S_S_S_PS_
	.globl	_Z7findcvsiPiS_S_S_S_S_PS_
	.p2align	3, 0x0
_Z7findcvsiPiS_S_S_S_S_PS_:
	.quad	_Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	.size	_Z7findcvsiPiS_S_S_S_S_PS_, 8

	.type	_Z9puttolistPiS_S_,@object      # @_Z9puttolistPiS_S_
	.globl	_Z9puttolistPiS_S_
	.p2align	3, 0x0
_Z9puttolistPiS_S_:
	.quad	_Z24__device_stub__puttolistPiS_S_
	.size	_Z9puttolistPiS_S_, 8

	.type	_Z9checkpermPbPiS0_S0_S0_S0_S0_,@object # @_Z9checkpermPbPiS0_S0_S0_S0_S0_
	.globl	_Z9checkpermPbPiS0_S0_S0_S0_S0_
	.p2align	3, 0x0
_Z9checkpermPbPiS0_S0_S0_S0_S0_:
	.quad	_Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_
	.size	_Z9checkpermPbPiS0_S0_S0_S0_S0_, 8

	.type	_Z7findallPiS_S_S_S_S_S_S_PS_S_,@object # @_Z7findallPiS_S_S_S_S_S_S_PS_S_
	.globl	_Z7findallPiS_S_S_S_S_S_S_PS_S_
	.p2align	3, 0x0
_Z7findallPiS_S_S_S_S_S_S_PS_S_:
	.quad	_Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	.size	_Z7findallPiS_S_S_S_S_S_S_PS_S_, 8

	.type	qdmap,@object                   # @qdmap
	.bss
	.globl	qdmap
	.p2align	3, 0x0
qdmap:
	.quad	0
	.size	qdmap, 8

	.type	d_qverc,@object                 # @d_qverc
	.globl	d_qverc
	.p2align	3, 0x0
d_qverc:
	.quad	0
	.size	d_qverc, 8

	.type	d_dverc,@object                 # @d_dverc
	.globl	d_dverc
	.p2align	3, 0x0
d_dverc:
	.quad	0
	.size	d_dverc, 8

	.type	d_qvid,@object                  # @d_qvid
	.globl	d_qvid
	.p2align	3, 0x0
d_qvid:
	.quad	0
	.size	d_qvid, 8

	.type	d_qidtov,@object                # @d_qidtov
	.globl	d_qidtov
	.p2align	3, 0x0
d_qidtov:
	.quad	0
	.size	d_qidtov, 8

	.type	h_qidtov,@object                # @h_qidtov
	.globl	h_qidtov
	.p2align	3, 0x0
h_qidtov:
	.quad	0
	.size	h_qidtov, 8

	.type	h_qvid,@object                  # @h_qvid
	.globl	h_qvid
	.p2align	3, 0x0
h_qvid:
	.quad	0
	.size	h_qvid, 8

	.type	d_qvert,@object                 # @d_qvert
	.globl	d_qvert
	.p2align	3, 0x0
d_qvert:
	.quad	0
	.size	d_qvert, 8

	.type	d_qelist,@object                # @d_qelist
	.globl	d_qelist
	.p2align	3, 0x0
d_qelist:
	.quad	0
	.size	d_qelist, 8

	.type	d_dvert,@object                 # @d_dvert
	.globl	d_dvert
	.p2align	3, 0x0
d_dvert:
	.quad	0
	.size	d_dvert, 8

	.type	d_delist,@object                # @d_delist
	.globl	d_delist
	.p2align	3, 0x0
d_delist:
	.quad	0
	.size	d_delist, 8

	.type	d_qtree,@object                 # @d_qtree
	.globl	d_qtree
	.p2align	3, 0x0
d_qtree:
	.quad	0
	.size	d_qtree, 8

	.type	d_over,@object                  # @d_over
	.globl	d_over
	.p2align	3, 0x0
d_over:
	.quad	0
	.size	d_over, 8

	.type	d_qdmap,@object                 # @d_qdmap
	.globl	d_qdmap
	.p2align	3, 0x0
d_qdmap:
	.quad	0
	.size	d_qdmap, 8

	.type	h_over,@object                  # @h_over
	.globl	h_over
h_over:
	.byte	0                               # 0x0
	.size	h_over, 1

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Error: %s\n"
	.size	.L.str.1, 11

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Not Ok"
	.size	.L.str.2, 7

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d "
	.size	.L.str.3, 4

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Start %lld\n"
	.size	.L.str.5, 12

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8findhashPiS_S_S_PbS0_S_S_"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7setdeg1PiS_S_Pb"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z7puttoidPiS_S_S_PbS_S_"
	.size	.L__unnamed_3, 25

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z7findcvsiPiS_S_S_S_S_PS_"
	.size	.L__unnamed_4, 27

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z9puttolistPiS_S_"
	.size	.L__unnamed_5, 19

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9checkpermPbPiS0_S0_S0_S0_S0_"
	.size	.L__unnamed_6, 32

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z7findallPiS_S_S_S_S_S_S_PS_S_"
	.size	.L__unnamed_7, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__findhashPiS_S_S_PbS0_S_S_
	.addrsig_sym _Z22__device_stub__setdeg1PiS_S_Pb
	.addrsig_sym _Z22__device_stub__puttoidPiS_S_S_PbS_S_
	.addrsig_sym _Z22__device_stub__findcvsiPiS_S_S_S_S_PS_
	.addrsig_sym _Z24__device_stub__puttolistPiS_S_
	.addrsig_sym _Z24__device_stub__checkpermPbPiS0_S0_S0_S0_S0_
	.addrsig_sym _Z22__device_stub__findallPiS_S_S_S_S_S_S_PS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8findhashPiS_S_S_PbS0_S_S_
	.addrsig_sym _Z7setdeg1PiS_S_Pb
	.addrsig_sym _Z7puttoidPiS_S_S_PbS_S_
	.addrsig_sym _Z7findcvsiPiS_S_S_S_S_PS_
	.addrsig_sym _Z9puttolistPiS_S_
	.addrsig_sym _Z9checkpermPbPiS0_S0_S0_S0_S0_
	.addrsig_sym _Z7findallPiS_S_S_S_S_S_S_PS_S_
	.addrsig_sym d_qverc
	.addrsig_sym d_dverc
	.addrsig_sym d_qvid
	.addrsig_sym d_qidtov
	.addrsig_sym d_qvert
	.addrsig_sym d_qelist
	.addrsig_sym d_dvert
	.addrsig_sym d_delist
	.addrsig_sym d_qtree
	.addrsig_sym d_over
	.addrsig_sym h_over
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8findhashPiS_S_S_PbS0_S_S_ ; -- Begin function _Z8findhashPiS_S_S_PbS0_S_S_
	.globl	_Z8findhashPiS_S_S_PbS0_S_S_
	.p2align	8
	.type	_Z8findhashPiS_S_S_PbS0_S_S_,@function
_Z8findhashPiS_S_S_PbS0_S_S_:           ; @_Z8findhashPiS_S_S_PbS0_S_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x44
	s_load_b512 s[16:31], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x4c
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s14
	s_load_b32 s2, s[18:19], 0x0
	s_and_b32 s3, s0, 0xffff
	s_add_i32 s1, s1, s15
	s_lshr_b32 s0, s0, 16
	v_mad_u64_u32 v[2:3], null, s1, s3, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_17
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v2, vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_17
; %bb.2:
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_mov_b32_e32 v2, 1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s0, -1
	global_load_b64 v[0:1], v[0:1], off
	s_mov_b32 s2, -1
	s_mov_b32 s1, exec_lo
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB0_14
; %bb.3:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v3, 31, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v6, 1
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v0, 1
	s_mov_b32 s3, 0
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_mov_b32 s4, 0x34386e
	s_mov_b32 s5, 0x32738c
                                        ; implicit-def: $sgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
.LBB0_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v9, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, s27, v3, vcc_lo
	s_mov_b32 s7, -1
	s_mov_b32 s6, exec_lo
	global_load_u8 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v7
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	global_load_b32 v9, v[4:5], off
	s_mov_b32 s7, 0
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v10, vcc_lo
	global_load_b32 v7, v[9:10], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v7
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	v_mad_i64_i32 v[8:9], null, v6, v7, 0
	s_add_u32 s0, 0x115c, s4
	s_addc_u32 s9, 0, 0
	v_add_co_u32 v13, s0, 0xf4200000, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s0, 0
	s_mov_b32 s7, exec_lo
	v_mad_u64_u32 v[10:11], null, 0x2717, v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readfirstlane_b32 s0, v13
	s_addc_u32 s9, s9, 0x10c6
	s_mul_i32 s10, s9, 0xfff0bdbd
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_hi_u32 s11, s0, 0xfff0bdbd
	v_mov_b32_e32 v6, v11
	s_add_i32 s11, s11, s10
	s_mul_i32 s12, s0, 0xfff0bdbd
	s_sub_i32 s11, s11, s0
	s_mul_hi_u32 s10, s9, s12
	v_mad_u64_u32 v[11:12], null, 0x2717, v9, v[6:7]
	s_mul_i32 s13, s9, s12
	s_mul_hi_u32 s12, s0, s12
	s_mul_i32 s15, s0, s11
	s_mul_hi_u32 s0, s0, s11
	s_add_u32 s12, s12, s15
	s_addc_u32 s0, 0, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v11
	s_mul_hi_u32 s14, s9, s11
	s_add_u32 s12, s12, s13
	s_addc_u32 s0, s0, s10
	s_mul_i32 s11, s9, s11
	v_add_co_u32 v8, vcc_lo, v10, v16
	s_addc_u32 s10, s14, 0
	s_add_u32 s0, s0, s11
	v_mov_b32_e32 v6, v11
	v_add_co_u32 v14, s0, v13, s0
	s_addc_u32 s10, 0, s10
	v_xor_b32_e32 v17, v8, v16
	s_cmp_lg_u32 s0, 0
	v_mad_i64_i32 v[8:9], null, v0, v7, 0
	s_addc_u32 s0, s9, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, v6, v16, vcc_lo
	v_mad_u64_u32 v[6:7], null, v17, s0, 0
	v_mul_hi_u32 v0, v17, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v18, v10, v16
	v_mad_u64_u32 v[10:11], null, 0x186a3, v8, 0
	v_mad_u64_u32 v[12:13], null, v18, v14, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v7, vcc_lo
	v_mad_u64_u32 v[6:7], null, v18, s0, 0
	s_add_u32 s0, 0x120a, s5
	v_mov_b32_e32 v0, v11
	v_add_co_u32 v11, s0, 0xcec00000, s0
	s_addc_u32 s9, 0, 0
	s_cmp_lg_u32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0x186a3, v9, v[0:1]
	v_readfirstlane_b32 s0, v11
	s_addc_u32 s9, s9, 0x10c6
	v_add_co_u32 v0, vcc_lo, v8, v12
	s_mul_i32 s10, s9, 0xfff0bd9b
	s_delay_alu instid0(VALU_DEP_2)
	s_mul_hi_u32 s11, s0, 0xfff0bd9b
	v_add_co_ci_u32_e32 v0, vcc_lo, v19, v13, vcc_lo
	s_add_i32 s11, s11, s10
	v_ashrrev_i32_e32 v13, 31, v14
	s_sub_i32 s10, s11, s0
	s_mul_i32 s11, s0, 0xfff0bd9b
	s_mul_i32 s15, s0, s10
	s_mul_hi_u32 s13, s9, s11
	s_mul_i32 s14, s9, s11
	s_mul_hi_u32 s11, s0, s11
	s_mul_hi_u32 s0, s0, s10
	s_add_u32 s11, s11, s15
	s_addc_u32 s0, 0, s0
	s_mul_hi_u32 s12, s9, s10
	s_add_u32 s11, s11, s14
	s_addc_u32 s0, s0, s13
	s_mul_i32 s10, s9, s10
	s_addc_u32 s11, s12, 0
	s_add_u32 s0, s0, s10
	v_mov_b32_e32 v8, v14
	v_add_co_u32 v11, s10, v11, s0
	v_add_co_u32 v9, s0, v10, v13
	s_addc_u32 s11, 0, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v8, s0, v8, v13, s0
	v_xor_b32_e32 v14, v9, v13
	s_cmp_lg_u32 s10, 0
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
	s_addc_u32 s0, s9, s11
	v_xor_b32_e32 v15, v8, v13
	v_mad_u64_u32 v[7:8], null, v14, s0, 0
	v_mul_hi_u32 v12, v14, v11
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v9, vcc_lo
	v_mad_u64_u32 v[9:10], null, v15, v11, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, v12, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_mad_u64_u32 v[6:7], null, v15, s0, 0
	v_mad_u64_u32 v[11:12], null, 0xf4243, v0, 0
	v_add_co_u32 v0, vcc_lo, v20, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v0, vcc_lo, v8, v10, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v0, v6
	v_mov_b32_e32 v0, v12
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[6:7], null, 0xf4265, v8, 0
	v_mad_u64_u32 v[8:9], null, 0xf4243, v19, v[0:1]
	v_sub_co_u32 v9, vcc_lo, v17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v0, v7
	v_sub_co_ci_u32_e32 v11, vcc_lo, v18, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[7:8], null, 0xf4265, v10, v[0:1]
	v_subrev_co_u32 v0, vcc_lo, 0xf4243, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo
	v_sub_co_u32 v6, vcc_lo, v14, v6
	v_cmp_lt_u32_e64 s0, 0xf4242, v0
	v_sub_co_ci_u32_e32 v7, vcc_lo, v15, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_u32 v12, vcc_lo, 0xf4265, v6
	v_cndmask_b32_e64 v10, 0, -1, s0
	v_cmp_eq_u32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0xf4264, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, -1, v10, s0
	v_add_nc_u32_e32 v10, 0xfff0bdbd, v0
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0xf4242, v9
	v_cndmask_b32_e64 v8, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v10, -1, v15, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0xf4264, v6
	v_add_nc_u32_e32 v15, 0xfff0bd9b, v12
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e32 v8, -1, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v7, -1, v14, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e32 v10, v12, v15, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_mov_b32_e32 v8, 1
	v_cndmask_b32_e32 v0, v9, v0, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v16
	v_cndmask_b32_e32 v6, v6, v10, vcc_lo
	v_xor_b32_e32 v7, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v0, v16
	v_sub_nc_u32_e32 v0, v7, v13
.LBB0_7:                                ; %Flow113
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s7, s7, exec_lo
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_mov_b32 s0, -1
	s_mov_b32 s6, -1
	s_and_saveexec_b32 s8, s7
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v4, s0, v4, 4
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_i32_e32 vcc_lo, v2, v1
	v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
	s_xor_b32 s6, exec_lo, -1
	s_or_not1_b32 s0, vcc_lo, exec_lo
; %bb.10:                               ; %Flow114
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_xor_b32 s6, s6, -1
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s0, s3
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s2, s6, exec_lo
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_4
; %bb.11:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v2, 1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s0, 0
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_and_saveexec_b32 s4, s2
	s_xor_b32 s2, exec_lo, s4
; %bb.12:                               ; %._crit_edge.loopexit
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v1, 31, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_mov_b32_e32 v2, v6
	s_mov_b32 s0, exec_lo
	v_mov_b32_e32 v3, v7
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_or_not1_b32 s3, vcc_lo, exec_lo
; %bb.13:                               ; %Flow116
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s2, s3, exec_lo
	s_or_not1_b32 s0, s0, exec_lo
.LBB0_14:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_17
; %bb.15:                               ; %._crit_edge
	s_xor_b32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_17
; %bb.16:
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, 1
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s29, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s30, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s31, v3, vcc_lo
	global_store_b8 v6, v6, s[24:25]
	global_store_b32 v[0:1], v4, off
	global_store_b32 v[2:3], v4, off
.LBB0_17:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8findhashPiS_S_S_PbS0_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8findhashPiS_S_S_PbS0_S_S_, .Lfunc_end0-_Z8findhashPiS_S_S_PbS0_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1684
; NumSgprs: 34
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7setdeg1PiS_S_Pb      ; -- Begin function _Z7setdeg1PiS_S_Pb
	.globl	_Z7setdeg1PiS_S_Pb
	.p2align	8
	.type	_Z7setdeg1PiS_S_Pb,@function
_Z7setdeg1PiS_S_Pb:                     ; @_Z7setdeg1PiS_S_Pb
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x2c
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s14
	s_load_b32 s2, s[6:7], 0x0
	s_and_b32 s3, s0, 0xffff
	s_add_i32 s1, s1, s15
	s_lshr_b32 s0, s0, 16
	v_mad_u64_u32 v[2:3], null, s1, s3, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s0, v[3:4]
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB1_10
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_10
; %bb.2:
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s1, -1
	s_mov_b32 s0, exec_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v2, v3
	s_cbranch_execz .LBB1_8
; %bb.3:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v4, 31, v2
	s_mov_b32 s1, 0
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr4
                                        ; implicit-def: $sgpr3
.LBB1_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v5, vcc_lo, s10, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
	s_or_b32 s3, s3, exec_lo
	s_or_b32 s4, s4, exec_lo
	s_mov_b32 s5, exec_lo
	global_load_u8 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0, v5
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=1
	v_add_co_u32 v2, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_and_not1_b32 s4, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v2, v3
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s6, vcc_lo, exec_lo
	s_or_b32 s4, s4, s6
; %bb.6:                                ; %Flow
                                        ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_xor_b32 s5, s3, -1
	s_and_b32 s6, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s6, s1
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s5, s5, exec_lo
	s_or_b32 s2, s2, s5
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_4
; %bb.7:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s1, s2, exec_lo
.LBB1_8:                                ; %Flow38
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_10
; %bb.9:                                ; %._crit_edge
	v_mov_b32_e32 v2, 1
	global_store_b32 v[0:1], v2, off
.LBB1_10:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7setdeg1PiS_S_Pb
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7setdeg1PiS_S_Pb, .Lfunc_end1-_Z7setdeg1PiS_S_Pb
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7puttoidPiS_S_S_PbS_S_ ; -- Begin function _Z7puttoidPiS_S_S_PbS_S_
	.globl	_Z7puttoidPiS_S_S_PbS_S_
	.p2align	8
	.type	_Z7puttoidPiS_S_S_PbS_S_,@function
_Z7puttoidPiS_S_S_PbS_S_:               ; @_Z7puttoidPiS_S_S_PbS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[16:23], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x44
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s14
	s_load_b32 s4, s[18:19], 0x0
	s_and_b32 s5, s3, 0xffff
	s_add_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_lshr_b32 s2, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB2_17
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b256 s[4:11], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s20, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s21, v4, vcc_lo
	global_load_b32 v5, v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_17
; %bb.2:
	v_add_co_u32 v3, vcc_lo, s16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s17, v4, vcc_lo
	v_mov_b32_e32 v5, 1
	v_mov_b32_e32 v6, 0
	s_mov_b32 s0, -1
	global_load_b64 v[3:4], v[3:4], off
	s_mov_b32 s2, -1
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v3, v4
	s_cbranch_execz .LBB2_14
; %bb.3:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v6, 31, v3
	v_mov_b32_e32 v5, v3
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v9, 0
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s10, 0x34386e
	v_lshlrev_b64 v[7:8], 2, v[5:6]
                                        ; implicit-def: $sgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
.LBB2_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v10, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v6, vcc_lo
	s_mov_b32 s13, -1
	s_mov_b32 s0, exec_lo
	global_load_u8 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u16_e32 0, v10
	s_cbranch_execz .LBB2_8
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=1
	global_load_b32 v10, v[7:8], off
	s_mov_b32 s11, 0
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 0, v10
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_4 Depth=1
	v_mad_i64_i32 v[11:12], null, v3, v10, 0
	s_add_u32 s13, 0x115c, s10
	s_addc_u32 s14, 0, 0
	v_add_co_u32 v13, s13, 0xf4200000, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s13, 0
	s_mov_b32 s11, exec_lo
	v_mad_u64_u32 v[9:10], null, 0x2717, v11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readfirstlane_b32 s13, v13
	s_addc_u32 s14, s14, 0x10c6
	s_mul_i32 s15, s14, 0xfff0bdbd
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_hi_u32 s16, s13, 0xfff0bdbd
	v_mov_b32_e32 v3, v10
	s_add_i32 s16, s16, s15
	s_mul_i32 s17, s13, 0xfff0bdbd
	s_sub_i32 s16, s16, s13
	s_mul_hi_u32 s15, s14, s17
	v_mad_u64_u32 v[10:11], null, 0x2717, v12, v[3:4]
	s_mul_i32 s18, s14, s17
	s_mul_hi_u32 s17, s13, s17
	s_mul_i32 s22, s13, s16
	s_mul_hi_u32 s13, s13, s16
	s_add_u32 s17, s17, s22
	s_addc_u32 s13, 0, s13
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v10
	s_mul_hi_u32 s19, s14, s16
	s_add_u32 s17, s17, s18
	v_mov_b32_e32 v3, v10
	s_addc_u32 s13, s13, s15
	s_mul_i32 s15, s14, s16
	v_add_co_u32 v9, vcc_lo, v9, v14
	s_addc_u32 s16, s19, 0
	s_add_u32 s13, s13, s15
	s_addc_u32 s15, 0, s16
	v_add_co_u32 v13, s13, v13, s13
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v14, vcc_lo
	v_xor_b32_e32 v15, v9, v14
	s_cmp_lg_u32 s13, 0
	s_addc_u32 s13, s14, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v17, v3, v14
	v_mad_u64_u32 v[9:10], null, v15, s13, 0
	v_mul_hi_u32 v16, v15, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, v17, v13, 0
	v_add_co_u32 v3, vcc_lo, v16, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v10, vcc_lo
	v_mad_u64_u32 v[9:10], null, v17, s13, 0
	v_add_co_u32 v3, vcc_lo, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, v13, v12, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xf4243, v3, 0
	v_mov_b32_e32 v3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[10:11], null, 0xf4243, v12, v[3:4]
	v_sub_co_u32 v3, vcc_lo, v15, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v9, vcc_lo, v17, v10, vcc_lo
	v_subrev_co_u32 v10, vcc_lo, 0xf4243, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0xf4242, v10
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_lt_u32_e32 vcc_lo, 0xf4242, v3
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v11, -1, v12 :: v_dual_add_nc_u32 v12, 0xfff0bdbd, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e32 v9, -1, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	v_cndmask_b32_e32 v10, v10, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_mov_b32_e32 v9, 1
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v14
	v_sub_nc_u32_e32 v3, v3, v14
.LBB2_7:                                ; %Flow103
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s13, s11, exec_lo
.LBB2_8:                                ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_mov_b32 s12, -1
	s_and_saveexec_b32 s11, s13
; %bb.9:                                ;   in Loop: Header=BB2_4 Depth=1
	v_add_co_u32 v5, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v7, s0, v7, 4
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_i32_e32 vcc_lo, v5, v4
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	s_xor_b32 s12, exec_lo, -1
	s_or_not1_b32 s0, vcc_lo, exec_lo
; %bb.10:                               ; %Flow104
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_xor_b32 s11, s12, -1
	s_and_b32 s0, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s0, s3
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s2, s11, exec_lo
	s_or_b32 s2, s0, s2
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_4
; %bb.11:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v5, 1
	v_mov_b32_e32 v6, 0
	s_mov_b32 s0, 0
	s_mov_b32 s3, -1
	s_and_saveexec_b32 s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s4
; %bb.12:                               ; %._crit_edge.loopexit
	v_ashrrev_i32_e32 v4, 31, v3
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_or_not1_b32 s3, vcc_lo, exec_lo
; %bb.13:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s2, s3, exec_lo
	s_or_not1_b32 s0, s0, exec_lo
.LBB2_14:                               ; %Flow105
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_17
; %bb.15:                               ; %._crit_edge
	s_xor_b32 s0, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_17
; %bb.16:
	v_lshlrev_b64 v[3:4], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_store_b32 v[1:2], v3, off
	global_store_b32 v[4:5], v0, off
.LBB2_17:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7puttoidPiS_S_S_PbS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z7puttoidPiS_S_S_PbS_S_, .Lfunc_end2-_Z7puttoidPiS_S_S_PbS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1224
; NumSgprs: 26
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text.unlikely.,"ax",@progbits
	.p2align	2                               ; -- Begin function __ockl_dm_alloc
	.type	__ockl_dm_alloc,@function
__ockl_dm_alloc:                        ; @__ockl_dm_alloc
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_or_saveexec_b32 s0, -1
	scratch_store_b32 off, v40, s32         ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s0
	v_writelane_b32 v40, s34, 0
	v_writelane_b32 v40, s35, 1
	v_writelane_b32 v40, s36, 2
	v_writelane_b32 v40, s37, 3
	v_writelane_b32 v40, s38, 4
	v_writelane_b32 v40, s39, 5
	v_writelane_b32 v40, s40, 6
	v_writelane_b32 v40, s41, 7
	v_writelane_b32 v40, s42, 8
	v_writelane_b32 v40, s43, 9
	v_writelane_b32 v40, s44, 10
	v_writelane_b32 v40, s30, 11
	v_writelane_b32 v40, s31, 12
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_ne_u64_e32 0, v[4:5]
	s_cbranch_execz .LBB3_702
; %bb.1:
	v_mbcnt_lo_u32_b32 v2, -1, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u64_e32 0xc01, v[4:5]
	s_xor_b32 s23, exec_lo, s0
	s_cbranch_execz .LBB3_668
; %bb.2:
	v_max_u32_e32 v0, 16, v4
	v_mov_b32_e32 v5, 0
	s_load_b64 s[10:11], s[8:9], 0x60
	v_dual_mov_b32 v118, 1 :: v_dual_mov_b32 v17, 0x1800
	s_delay_alu instid0(VALU_DEP_3)
	v_clz_i32_u32_e32 v1, v0
	v_mov_b32_e32 v20, 0x200000
	v_mov_b32_e32 v8, v5
	v_mov_b32_e32 v14, 1
	v_mov_b32_e32 v68, 0x100
	v_not_b32_e32 v3, v1
	v_lshlrev_b32_e32 v1, 1, v1
	v_mov_b32_e32 v13, 3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 15, v3
	v_lshlrev_b32_e64 v3, v3, 1
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s10, 0x1a800
	s_addc_u32 s13, s11, 0
	s_add_u32 s14, s10, 0x1a808
	v_lshrrev_b32_e32 v4, 1, v3
	v_cmp_gt_u32_e32 vcc_lo, v0, v3
	s_addc_u32 s15, s11, 0
	s_add_u32 s4, s10, 0x800
	s_addc_u32 s5, s11, 0
	v_or_b32_e32 v3, v4, v3
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __unnamed_1@rel32@lo+12
	s_addc_u32 s1, s1, __unnamed_1@rel32@hi+20
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+4
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+12
	s_add_u32 s6, s10, 0x1000
	v_cmp_gt_u32_e32 vcc_lo, v0, v3
	v_sub_nc_u32_e32 v1, v6, v1
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 54, v1, vcc_lo
	v_lshlrev_b64 v[0:1], 7, v[7:8]
	v_lshlrev_b64 v[3:4], 5, v[7:8]
	v_lshrrev_b64 v[8:9], v7, 0xbf
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v32, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v33, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v34, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v35, vcc_lo, s11, v1, vcc_lo
	v_add_co_u32 v36, vcc_lo, v3, s0
	v_add_co_ci_u32_e32 v37, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v38, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v39, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v48, vcc_lo, s6, v0
	s_add_u32 s0, s10, 0x2000
	v_add_co_ci_u32_e32 v49, vcc_lo, s7, v1, vcc_lo
	s_addc_u32 s1, s11, 0
	v_add_co_u32 v50, vcc_lo, s0, v0
	s_add_u32 s2, s10, 0x1800
	v_add_co_ci_u32_e32 v51, vcc_lo, s1, v1, vcc_lo
	s_addc_u32 s3, s11, 0
	v_add_co_u32 v52, vcc_lo, s2, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __unnamed_1@rel32@lo+24
	s_addc_u32 s1, s1, __unnamed_1@rel32@hi+32
	v_add_co_ci_u32_e32 v53, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v54, vcc_lo, v3, s0
	v_and_b32_e32 v0, 1, v8
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+20
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+28
	v_add_co_ci_u32_e32 v55, vcc_lo, s1, v4, vcc_lo
	v_add_co_u32 v64, vcc_lo, v3, s2
	v_mov_b32_e32 v9, v5
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, __unnamed_1@rel32@lo+28
	s_addc_u32 s5, s5, __unnamed_1@rel32@hi+36
	v_add_co_ci_u32_e32 v65, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v66, vcc_lo, v3, s4
	v_cmp_eq_u32_e64 s0, 1, v0
	v_mov_b32_e32 v0, 0
	v_add_co_ci_u32_e32 v67, vcc_lo, s5, v4, vcc_lo
	v_mov_b32_e32 v8, v5
	v_dual_mov_b32 v10, v5 :: v_dual_mov_b32 v1, 0
	v_mov_b32_e32 v3, v14
	s_add_u32 s24, s10, 0x100
	s_mov_b32 s4, 0
	s_addc_u32 s25, s11, 0
.LBB3_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_6 Depth 2
                                        ;       Child Loop BB3_11 Depth 3
                                        ;         Child Loop BB3_14 Depth 4
                                        ;         Child Loop BB3_43 Depth 4
                                        ;           Child Loop BB3_47 Depth 5
                                        ;           Child Loop BB3_75 Depth 5
                                        ;             Child Loop BB3_93 Depth 6
                                        ;             Child Loop BB3_101 Depth 6
                                        ;             Child Loop BB3_107 Depth 6
                                        ;             Child Loop BB3_116 Depth 6
                                        ;             Child Loop BB3_121 Depth 6
                                        ;             Child Loop BB3_123 Depth 6
                                        ;             Child Loop BB3_144 Depth 6
                                        ;             Child Loop BB3_152 Depth 6
                                        ;             Child Loop BB3_158 Depth 6
                                        ;             Child Loop BB3_167 Depth 6
                                        ;             Child Loop BB3_175 Depth 6
                                        ;             Child Loop BB3_178 Depth 6
                                        ;             Child Loop BB3_180 Depth 6
                                        ;             Child Loop BB3_182 Depth 6
                                        ;             Child Loop BB3_184 Depth 6
                                        ;             Child Loop BB3_186 Depth 6
                                        ;             Child Loop BB3_188 Depth 6
                                        ;             Child Loop BB3_210 Depth 6
                                        ;             Child Loop BB3_218 Depth 6
                                        ;             Child Loop BB3_224 Depth 6
                                        ;             Child Loop BB3_233 Depth 6
                                        ;             Child Loop BB3_240 Depth 6
                                        ;             Child Loop BB3_243 Depth 6
                                        ;             Child Loop BB3_248 Depth 6
                                        ;             Child Loop BB3_255 Depth 6
                                        ;             Child Loop BB3_288 Depth 6
                                        ;             Child Loop BB3_296 Depth 6
                                        ;             Child Loop BB3_302 Depth 6
                                        ;             Child Loop BB3_311 Depth 6
                                        ;           Child Loop BB3_320 Depth 5
                                        ;           Child Loop BB3_323 Depth 5
                                        ;           Child Loop BB3_325 Depth 5
                                        ;           Child Loop BB3_327 Depth 5
                                        ;           Child Loop BB3_329 Depth 5
                                        ;           Child Loop BB3_331 Depth 5
                                        ;           Child Loop BB3_333 Depth 5
                                        ;       Child Loop BB3_347 Depth 3
                                        ;         Child Loop BB3_351 Depth 4
                                        ;         Child Loop BB3_378 Depth 4
                                        ;           Child Loop BB3_396 Depth 5
                                        ;           Child Loop BB3_404 Depth 5
                                        ;           Child Loop BB3_410 Depth 5
                                        ;           Child Loop BB3_419 Depth 5
                                        ;           Child Loop BB3_424 Depth 5
                                        ;           Child Loop BB3_426 Depth 5
                                        ;           Child Loop BB3_447 Depth 5
                                        ;           Child Loop BB3_455 Depth 5
                                        ;           Child Loop BB3_461 Depth 5
                                        ;           Child Loop BB3_470 Depth 5
                                        ;           Child Loop BB3_478 Depth 5
                                        ;           Child Loop BB3_481 Depth 5
                                        ;           Child Loop BB3_483 Depth 5
                                        ;           Child Loop BB3_485 Depth 5
                                        ;           Child Loop BB3_487 Depth 5
                                        ;           Child Loop BB3_489 Depth 5
                                        ;           Child Loop BB3_491 Depth 5
                                        ;           Child Loop BB3_513 Depth 5
                                        ;           Child Loop BB3_521 Depth 5
                                        ;           Child Loop BB3_527 Depth 5
                                        ;           Child Loop BB3_536 Depth 5
                                        ;           Child Loop BB3_543 Depth 5
                                        ;           Child Loop BB3_546 Depth 5
                                        ;           Child Loop BB3_551 Depth 5
                                        ;           Child Loop BB3_558 Depth 5
                                        ;           Child Loop BB3_591 Depth 5
                                        ;           Child Loop BB3_599 Depth 5
                                        ;           Child Loop BB3_605 Depth 5
                                        ;           Child Loop BB3_614 Depth 5
                                        ;         Child Loop BB3_623 Depth 4
                                        ;         Child Loop BB3_626 Depth 4
                                        ;         Child Loop BB3_628 Depth 4
                                        ;         Child Loop BB3_630 Depth 4
                                        ;         Child Loop BB3_632 Depth 4
                                        ;         Child Loop BB3_634 Depth 4
                                        ;         Child Loop BB3_636 Depth 4
                                        ;       Child Loop BB3_649 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v119, v3
	v_mov_b32_e32 v3, v5
	s_mov_b32 s26, exec_lo
	;;#ASMSTART
	;;#ASMEND
	v_cmpx_ne_u32_e32 0, v119
	s_cbranch_execz .LBB3_666
; %bb.4:                                ;   in Loop: Header=BB3_3 Depth=1
	v_readfirstlane_b32 s1, v7
	s_mov_b32 s27, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e64 s1, v7
	s_cbranch_execz .LBB3_665
; %bb.5:                                ; %.preheader196.preheader
                                        ;   in Loop: Header=BB3_3 Depth=1
	v_mov_b32_e32 v3, 1
.LBB3_6:                                ; %.preheader196
                                        ;   Parent Loop BB3_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB3_11 Depth 3
                                        ;         Child Loop BB3_14 Depth 4
                                        ;         Child Loop BB3_43 Depth 4
                                        ;           Child Loop BB3_47 Depth 5
                                        ;           Child Loop BB3_75 Depth 5
                                        ;             Child Loop BB3_93 Depth 6
                                        ;             Child Loop BB3_101 Depth 6
                                        ;             Child Loop BB3_107 Depth 6
                                        ;             Child Loop BB3_116 Depth 6
                                        ;             Child Loop BB3_121 Depth 6
                                        ;             Child Loop BB3_123 Depth 6
                                        ;             Child Loop BB3_144 Depth 6
                                        ;             Child Loop BB3_152 Depth 6
                                        ;             Child Loop BB3_158 Depth 6
                                        ;             Child Loop BB3_167 Depth 6
                                        ;             Child Loop BB3_175 Depth 6
                                        ;             Child Loop BB3_178 Depth 6
                                        ;             Child Loop BB3_180 Depth 6
                                        ;             Child Loop BB3_182 Depth 6
                                        ;             Child Loop BB3_184 Depth 6
                                        ;             Child Loop BB3_186 Depth 6
                                        ;             Child Loop BB3_188 Depth 6
                                        ;             Child Loop BB3_210 Depth 6
                                        ;             Child Loop BB3_218 Depth 6
                                        ;             Child Loop BB3_224 Depth 6
                                        ;             Child Loop BB3_233 Depth 6
                                        ;             Child Loop BB3_240 Depth 6
                                        ;             Child Loop BB3_243 Depth 6
                                        ;             Child Loop BB3_248 Depth 6
                                        ;             Child Loop BB3_255 Depth 6
                                        ;             Child Loop BB3_288 Depth 6
                                        ;             Child Loop BB3_296 Depth 6
                                        ;             Child Loop BB3_302 Depth 6
                                        ;             Child Loop BB3_311 Depth 6
                                        ;           Child Loop BB3_320 Depth 5
                                        ;           Child Loop BB3_323 Depth 5
                                        ;           Child Loop BB3_325 Depth 5
                                        ;           Child Loop BB3_327 Depth 5
                                        ;           Child Loop BB3_329 Depth 5
                                        ;           Child Loop BB3_331 Depth 5
                                        ;           Child Loop BB3_333 Depth 5
                                        ;       Child Loop BB3_347 Depth 3
                                        ;         Child Loop BB3_351 Depth 4
                                        ;         Child Loop BB3_378 Depth 4
                                        ;           Child Loop BB3_396 Depth 5
                                        ;           Child Loop BB3_404 Depth 5
                                        ;           Child Loop BB3_410 Depth 5
                                        ;           Child Loop BB3_419 Depth 5
                                        ;           Child Loop BB3_424 Depth 5
                                        ;           Child Loop BB3_426 Depth 5
                                        ;           Child Loop BB3_447 Depth 5
                                        ;           Child Loop BB3_455 Depth 5
                                        ;           Child Loop BB3_461 Depth 5
                                        ;           Child Loop BB3_470 Depth 5
                                        ;           Child Loop BB3_478 Depth 5
                                        ;           Child Loop BB3_481 Depth 5
                                        ;           Child Loop BB3_483 Depth 5
                                        ;           Child Loop BB3_485 Depth 5
                                        ;           Child Loop BB3_487 Depth 5
                                        ;           Child Loop BB3_489 Depth 5
                                        ;           Child Loop BB3_491 Depth 5
                                        ;           Child Loop BB3_513 Depth 5
                                        ;           Child Loop BB3_521 Depth 5
                                        ;           Child Loop BB3_527 Depth 5
                                        ;           Child Loop BB3_536 Depth 5
                                        ;           Child Loop BB3_543 Depth 5
                                        ;           Child Loop BB3_546 Depth 5
                                        ;           Child Loop BB3_551 Depth 5
                                        ;           Child Loop BB3_558 Depth 5
                                        ;           Child Loop BB3_591 Depth 5
                                        ;           Child Loop BB3_599 Depth 5
                                        ;           Child Loop BB3_605 Depth 5
                                        ;           Child Loop BB3_614 Depth 5
                                        ;         Child Loop BB3_623 Depth 4
                                        ;         Child Loop BB3_626 Depth 4
                                        ;         Child Loop BB3_628 Depth 4
                                        ;         Child Loop BB3_630 Depth 4
                                        ;         Child Loop BB3_632 Depth 4
                                        ;         Child Loop BB3_634 Depth 4
                                        ;         Child Loop BB3_636 Depth 4
                                        ;       Child Loop BB3_649 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v128, v3 :: v_dual_mov_b32 v3, 0
	s_mov_b32 s28, exec_lo
	;;#ASMSTART
	;;#ASMEND
	v_cmpx_ne_u32_e32 0, v128
	s_cbranch_execz .LBB3_664
; %bb.7:                                ;   in Loop: Header=BB3_6 Depth=2
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB3_9
; %bb.8:                                ;   in Loop: Header=BB3_6 Depth=2
	global_load_b32 v3, v[32:33], off glc
.LBB3_9:                                ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s29, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_gt_u32 s29, 0x100ff
	s_cbranch_scc0 .LBB3_344
; %bb.10:                               ;   in Loop: Header=BB3_6 Depth=2
	v_mbcnt_lo_u32_b32 v129, exec_lo, 0
	v_mov_b32_e32 v4, v7
	s_mov_b32 s30, 0
	s_bcnt1_i32_b32 s31, exec_lo
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_11:                               ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB3_14 Depth 4
                                        ;         Child Loop BB3_43 Depth 4
                                        ;           Child Loop BB3_47 Depth 5
                                        ;           Child Loop BB3_75 Depth 5
                                        ;             Child Loop BB3_93 Depth 6
                                        ;             Child Loop BB3_101 Depth 6
                                        ;             Child Loop BB3_107 Depth 6
                                        ;             Child Loop BB3_116 Depth 6
                                        ;             Child Loop BB3_121 Depth 6
                                        ;             Child Loop BB3_123 Depth 6
                                        ;             Child Loop BB3_144 Depth 6
                                        ;             Child Loop BB3_152 Depth 6
                                        ;             Child Loop BB3_158 Depth 6
                                        ;             Child Loop BB3_167 Depth 6
                                        ;             Child Loop BB3_175 Depth 6
                                        ;             Child Loop BB3_178 Depth 6
                                        ;             Child Loop BB3_180 Depth 6
                                        ;             Child Loop BB3_182 Depth 6
                                        ;             Child Loop BB3_184 Depth 6
                                        ;             Child Loop BB3_186 Depth 6
                                        ;             Child Loop BB3_188 Depth 6
                                        ;             Child Loop BB3_210 Depth 6
                                        ;             Child Loop BB3_218 Depth 6
                                        ;             Child Loop BB3_224 Depth 6
                                        ;             Child Loop BB3_233 Depth 6
                                        ;             Child Loop BB3_240 Depth 6
                                        ;             Child Loop BB3_243 Depth 6
                                        ;             Child Loop BB3_248 Depth 6
                                        ;             Child Loop BB3_255 Depth 6
                                        ;             Child Loop BB3_288 Depth 6
                                        ;             Child Loop BB3_296 Depth 6
                                        ;             Child Loop BB3_302 Depth 6
                                        ;             Child Loop BB3_311 Depth 6
                                        ;           Child Loop BB3_320 Depth 5
                                        ;           Child Loop BB3_323 Depth 5
                                        ;           Child Loop BB3_325 Depth 5
                                        ;           Child Loop BB3_327 Depth 5
                                        ;           Child Loop BB3_329 Depth 5
                                        ;           Child Loop BB3_331 Depth 5
                                        ;           Child Loop BB3_333 Depth 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 7, v[4:5]
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s1, 0, v129
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_13
; %bb.12:                               ;   in Loop: Header=BB3_11 Depth=3
	v_add_co_u32 v18, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v16, vcc_lo
	global_load_b32 v6, v[18:19], off glc
.LBB3_13:                               ;   in Loop: Header=BB3_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b64 v[18:19], 5, v[4:5]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+8
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, v18, s2
	v_add_co_ci_u32_e32 v19, vcc_lo, s3, v19, vcc_lo
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v6
	global_load_b32 v3, v[18:19], off
	v_add_nc_u32_e32 v6, s2, v129
	s_mov_b32 s2, 0x10100
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, 0xff00ff01, v6
	v_lshrrev_b32_e32 v18, 16, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v18, 0x10100, v18
	v_sub_nc_u32_e32 v6, v6, v18
	v_add_co_u32 v18, vcc_lo, s10, v15
	v_add_co_ci_u32_e32 v19, vcc_lo, s11, v16, vcc_lo
.LBB3_14:                               ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr15_vgpr16
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_gt_u32_e32 0x100, v6
	s_xor_b32 s3, exec_lo, s3
; %bb.15:                               ;   in Loop: Header=BB3_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0x1800, v4, s[6:7]
	v_mad_u64_u32 v[15:16], null, v6, 24, v[21:22]
; %bb.16:                               ; %Flow1135
                                        ;   in Loop: Header=BB3_14 Depth=4
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB3_18
; %bb.17:                               ;   in Loop: Header=BB3_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	v_add_nc_u32_e32 v21, 0xffffff00, v6
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0x1800, v4, s[6:7]
	v_lshrrev_b32_e32 v23, 8, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, v23, 24, v[15:16]
	v_and_b32_e32 v23, 0xff, v6
	global_load_b64 v[21:22], v[21:22], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, v23, 24, v[21:22]
.LBB3_18:                               ;   in Loop: Header=BB3_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v15, v[15:16], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v15, v3
	s_cbranch_vccz .LBB3_20
; %bb.19:                               ;   in Loop: Header=BB3_14 Depth=4
	s_ctz_i32_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 2
	v_mov_b32_e32 v15, s3
	ds_bpermute_b32 v15, v15, v6
	s_branch .LBB3_21
.LBB3_20:                               ;   in Loop: Header=BB3_14 Depth=4
	v_mov_b32_e32 v15, -1
.LBB3_21:                               ;   in Loop: Header=BB3_14 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v15
	s_cmp_eq_u32 s5, -1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_24
; %bb.22:                               ;   in Loop: Header=BB3_14 Depth=4
	s_cmpk_lt_u32 s5, 0x100
	s_cbranch_scc0 .LBB3_25
; %bb.23:                               ;   in Loop: Header=BB3_14 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[21:22], null, 0x1800, v4, s[6:7]
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[15:16], null, s5, 24, v[21:22]
	s_branch .LBB3_26
.LBB3_24:                               ;   in Loop: Header=BB3_14 Depth=4
	s_mov_b32 s5, -1
                                        ; implicit-def: $vgpr15_vgpr16
	s_branch .LBB3_29
.LBB3_25:                               ;   in Loop: Header=BB3_14 Depth=4
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr15_vgpr16
.LBB3_26:                               ; %Flow1128
                                        ;   in Loop: Header=BB3_14 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_28
; %bb.27:                               ;   in Loop: Header=BB3_14 Depth=4
	s_add_i32 s6, s5, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s16, s6, 8
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_and_b32 s5, s5, 0xff
	v_mad_u64_u32 v[15:16], null, 0x1800, v4, s[6:7]
	v_mad_u64_u32 v[21:22], null, s16, 24, v[15:16]
	global_load_b64 v[21:22], v[21:22], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, s5, 24, v[21:22]
.LBB3_28:                               ; %Flow1129
                                        ;   in Loop: Header=BB3_14 Depth=4
	s_mov_b32 s5, 0
.LBB3_29:                               ; %Flow1131
                                        ;   in Loop: Header=BB3_14 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_33
; %bb.30:                               ;   in Loop: Header=BB3_14 Depth=4
	v_add_nc_u32_e32 v6, s31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, 0xff00ff01, v6
	v_lshrrev_b32_e32 v15, 16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_u32_u24_e32 v15, 0x10100, v15
	v_sub_nc_u32_e32 v6, v6, v15
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_32
; %bb.31:                               ;   in Loop: Header=BB3_14 Depth=4
	global_store_b32 v[18:19], v6, off
.LBB3_32:                               ;   in Loop: Header=BB3_14 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
	s_sub_i32 s2, s2, s31
.LBB3_33:                               ;   in Loop: Header=BB3_14 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB3_35
; %bb.34:                               ;   in Loop: Header=BB3_14 Depth=4
	s_mov_b32 s3, 0
	s_mov_b32 s5, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr6
	s_branch .LBB3_36
.LBB3_35:                               ;   in Loop: Header=BB3_14 Depth=4
	s_cmp_lt_i32 s2, 1
	s_mov_b32 s5, 0
	s_cselect_b32 s6, -1, 0
                                        ; implicit-def: $sgpr3
.LBB3_36:                               ; %Flow1137
                                        ;   in Loop: Header=BB3_14 Depth=4
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_14
; %bb.37:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB3_11 Depth=3
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_342
; %bb.38:                               ;   in Loop: Header=BB3_11 Depth=3
	v_and_b32_e32 v3, -2, v4
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e32 vcc_lo, v4, v7
	s_mov_b32 s3, 0
	v_cmp_gt_u32_e64 s2, 14, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s34, s2
	s_cbranch_execz .LBB3_341
; %bb.39:                               ;   in Loop: Header=BB3_11 Depth=3
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_41
; %bb.40:                               ;   in Loop: Header=BB3_11 Depth=3
	v_mov_b32_e32 v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[11:12], 7, v[3:4]
	v_add_co_u32 v11, vcc_lo, s24, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, s25, v12, vcc_lo
	global_load_b32 v4, v[11:12], off offset:2048 glc
.LBB3_41:                               ;   in Loop: Header=BB3_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s36, v4
	v_add_nc_u32_e32 v22, 2, v3
	s_mov_b32 s6, -1
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_gt_u32 s36, 0x100ff
	s_cbranch_scc1 .LBB3_340
; %bb.42:                               ;   in Loop: Header=BB3_11 Depth=3
	v_mov_b32_e32 v4, v5
	s_bcnt1_i32_b32 s35, exec_lo
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+76
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+84
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, __unnamed_1@rel32@lo+68
	s_addc_u32 s7, s7, __unnamed_1@rel32@hi+76
	s_add_u32 s1, s24, 0x800
	v_lshlrev_b64 v[11:12], 7, v[3:4]
	v_lshlrev_b64 v[3:4], 5, v[3:4]
	v_lshrrev_b64 v[15:16], v22, 0xbf
	v_mbcnt_lo_u32_b32 v130, exec_lo, 0
	v_mov_b32_e32 v23, v5
	v_mov_b32_e32 v24, v5
	v_add_co_u32 v70, vcc_lo, s24, v11
	v_add_co_ci_u32_e32 v71, vcc_lo, s25, v12, vcc_lo
	v_add_co_u32 v80, vcc_lo, v3, s2
	v_add_co_ci_u32_e32 v81, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v82, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v83, vcc_lo, s7, v4, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v84, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x1000
	v_add_co_ci_u32_e32 v85, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v86, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x2000
	v_add_co_ci_u32_e32 v87, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s2, s25, 0
	v_add_co_u32 v96, vcc_lo, s1, v11
	s_add_u32 s1, s24, 0x1800
	v_add_co_ci_u32_e32 v97, vcc_lo, s2, v12, vcc_lo
	s_addc_u32 s5, s25, 0
	v_add_co_u32 v98, vcc_lo, s1, v11
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+88
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+96
	v_add_co_ci_u32_e32 v99, vcc_lo, s5, v12, vcc_lo
	v_add_co_u32 v100, vcc_lo, v3, s2
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, __unnamed_1@rel32@lo+84
	s_addc_u32 s7, s7, __unnamed_1@rel32@hi+92
	v_add_co_ci_u32_e32 v101, vcc_lo, s3, v4, vcc_lo
	v_and_b32_e32 v6, 1, v15
	v_add_co_u32 v102, vcc_lo, v3, s6
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+92
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+100
	v_add_co_ci_u32_e32 v103, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v112, vcc_lo, v3, s2
	v_cmp_eq_u32_e64 s1, 1, v6
	v_add_co_ci_u32_e32 v113, vcc_lo, s3, v4, vcc_lo
	v_mov_b32_e32 v25, v5
                                        ; implicit-def: $vgpr114_vgpr115
.LBB3_43:                               ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB3_47 Depth 5
                                        ;           Child Loop BB3_75 Depth 5
                                        ;             Child Loop BB3_93 Depth 6
                                        ;             Child Loop BB3_101 Depth 6
                                        ;             Child Loop BB3_107 Depth 6
                                        ;             Child Loop BB3_116 Depth 6
                                        ;             Child Loop BB3_121 Depth 6
                                        ;             Child Loop BB3_123 Depth 6
                                        ;             Child Loop BB3_144 Depth 6
                                        ;             Child Loop BB3_152 Depth 6
                                        ;             Child Loop BB3_158 Depth 6
                                        ;             Child Loop BB3_167 Depth 6
                                        ;             Child Loop BB3_175 Depth 6
                                        ;             Child Loop BB3_178 Depth 6
                                        ;             Child Loop BB3_180 Depth 6
                                        ;             Child Loop BB3_182 Depth 6
                                        ;             Child Loop BB3_184 Depth 6
                                        ;             Child Loop BB3_186 Depth 6
                                        ;             Child Loop BB3_188 Depth 6
                                        ;             Child Loop BB3_210 Depth 6
                                        ;             Child Loop BB3_218 Depth 6
                                        ;             Child Loop BB3_224 Depth 6
                                        ;             Child Loop BB3_233 Depth 6
                                        ;             Child Loop BB3_240 Depth 6
                                        ;             Child Loop BB3_243 Depth 6
                                        ;             Child Loop BB3_248 Depth 6
                                        ;             Child Loop BB3_255 Depth 6
                                        ;             Child Loop BB3_288 Depth 6
                                        ;             Child Loop BB3_296 Depth 6
                                        ;             Child Loop BB3_302 Depth 6
                                        ;             Child Loop BB3_311 Depth 6
                                        ;           Child Loop BB3_320 Depth 5
                                        ;           Child Loop BB3_323 Depth 5
                                        ;           Child Loop BB3_325 Depth 5
                                        ;           Child Loop BB3_327 Depth 5
                                        ;           Child Loop BB3_329 Depth 5
                                        ;           Child Loop BB3_331 Depth 5
                                        ;           Child Loop BB3_333 Depth 5
	s_cmp_eq_u32 s36, 0
	s_mov_b32 s5, -1
	;;#ASMSTART
	;;#ASMEND
	s_cbranch_scc1 .LBB3_72
; %bb.44:                               ;   in Loop: Header=BB3_43 Depth=4
	v_cmp_eq_u32_e64 s2, 0, v130
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_46
; %bb.45:                               ;   in Loop: Header=BB3_43 Depth=4
	global_load_b32 v3, v[70:71], off glc
.LBB3_46:                               ;   in Loop: Header=BB3_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v6, v[80:81], off
	v_cvt_f32_u32_e32 v4, s36
	s_sub_i32 s3, 0, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, s3, v4
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s3, v3
	v_add_nc_u32_e32 v3, s3, v130
	s_mov_b32 s3, s36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v4, v11
	v_add_nc_u32_e32 v11, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v11
	v_mul_lo_u32 v4, v4, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v3, v4, vcc_lo
.LBB3_47:                               ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x100, v12
	s_xor_b32 s6, exec_lo, s6
; %bb.48:                               ;   in Loop: Header=BB3_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[3:4], null, v12, 24, v[15:16]
; %bb.49:                               ; %Flow952
                                        ;   in Loop: Header=BB3_47 Depth=5
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB3_51
; %bb.50:                               ;   in Loop: Header=BB3_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	v_add_nc_u32_e32 v15, 0xffffff00, v12
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_lshrrev_b32_e32 v18, 8, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v18, 24, v[3:4]
	v_and_b32_e32 v18, 0xff, v12
	global_load_b64 v[15:16], v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v18, 24, v[15:16]
.LBB3_51:                               ;   in Loop: Header=BB3_47 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b32 v3, v[3:4], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v6
	s_cbranch_vccz .LBB3_53
; %bb.52:                               ;   in Loop: Header=BB3_47 Depth=5
	s_ctz_i32_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s6, s6, 2
	v_mov_b32_e32 v3, s6
	ds_bpermute_b32 v3, v3, v12
	s_branch .LBB3_54
.LBB3_53:                               ;   in Loop: Header=BB3_47 Depth=5
	v_mov_b32_e32 v3, -1
.LBB3_54:                               ;   in Loop: Header=BB3_47 Depth=5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v3
	s_cmp_eq_u32 s7, -1
	s_cselect_b32 s6, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_57
; %bb.55:                               ;   in Loop: Header=BB3_47 Depth=5
	s_cmpk_lt_u32 s7, 0x100
	s_cbranch_scc0 .LBB3_58
; %bb.56:                               ;   in Loop: Header=BB3_47 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	s_mov_b32 s16, 0
	v_mad_u64_u32 v[15:16], null, s7, 24, v[3:4]
	s_branch .LBB3_59
.LBB3_57:                               ;   in Loop: Header=BB3_47 Depth=5
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr15_vgpr16
	s_branch .LBB3_62
.LBB3_58:                               ;   in Loop: Header=BB3_47 Depth=5
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr15_vgpr16
.LBB3_59:                               ; %Flow946
                                        ;   in Loop: Header=BB3_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_61
; %bb.60:                               ;   in Loop: Header=BB3_47 Depth=5
	s_add_i32 s16, s7, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s18, s16, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_and_b32 s7, s7, 0xff
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[15:16], null, s18, 24, v[3:4]
	global_load_b64 v[3:4], v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[15:16], null, s7, 24, v[3:4]
.LBB3_61:                               ; %Flow947
                                        ;   in Loop: Header=BB3_47 Depth=5
	s_mov_b32 s7, 0
.LBB3_62:                               ; %Flow948
                                        ;   in Loop: Header=BB3_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB3_66
; %bb.63:                               ;   in Loop: Header=BB3_47 Depth=5
	v_add_nc_u32_e32 v3, s35, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v11
	v_mul_lo_u32 v4, v4, s36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s36, v3
	v_cmp_le_u32_e32 vcc_lo, s36, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v3, v4, vcc_lo
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB3_65
; %bb.64:                               ;   in Loop: Header=BB3_47 Depth=5
	global_store_b32 v[70:71], v12, off
.LBB3_65:                               ;   in Loop: Header=BB3_47 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
	v_dual_mov_b32 v15, v114 :: v_dual_mov_b32 v16, v115
	s_sub_i32 s3, s3, s35
.LBB3_66:                               ;   in Loop: Header=BB3_47 Depth=5
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB3_68
; %bb.67:                               ;   in Loop: Header=BB3_47 Depth=5
	s_mov_b32 s6, 0
	s_mov_b32 s7, -1
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr12
	s_branch .LBB3_69
.LBB3_68:                               ;   in Loop: Header=BB3_47 Depth=5
	s_cmp_lt_i32 s3, 1
	s_mov_b32 s7, 0
	s_cselect_b32 s16, -1, 0
                                        ; implicit-def: $sgpr6
.LBB3_69:                               ; %Flow954
                                        ;   in Loop: Header=BB3_47 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_71
; %bb.70:                               ;   in Loop: Header=BB3_47 Depth=5
	v_dual_mov_b32 v115, v16 :: v_dual_mov_b32 v114, v15
	s_branch .LBB3_47
.LBB3_71:                               ; %loop.exit.guard903
                                        ;   in Loop: Header=BB3_43 Depth=4
	v_dual_mov_b32 v115, v16 :: v_dual_mov_b32 v114, v15
	s_xor_b32 s2, s7, -1
	s_branch .LBB3_73
.LBB3_72:                               ;   in Loop: Header=BB3_43 Depth=4
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr6
.LBB3_73:                               ; %Flow1121
                                        ;   in Loop: Header=BB3_43 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB3_314
; %bb.74:                               ; %.loopexit188
                                        ;   in Loop: Header=BB3_43 Depth=4
	v_mbcnt_lo_u32_b32 v131, exec_lo, 0
                                        ; implicit-def: $vgpr116_vgpr117
.LBB3_75:                               ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Loop Header: Depth=5
                                        ;             Child Loop BB3_93 Depth 6
                                        ;             Child Loop BB3_101 Depth 6
                                        ;             Child Loop BB3_107 Depth 6
                                        ;             Child Loop BB3_116 Depth 6
                                        ;             Child Loop BB3_121 Depth 6
                                        ;             Child Loop BB3_123 Depth 6
                                        ;             Child Loop BB3_144 Depth 6
                                        ;             Child Loop BB3_152 Depth 6
                                        ;             Child Loop BB3_158 Depth 6
                                        ;             Child Loop BB3_167 Depth 6
                                        ;             Child Loop BB3_175 Depth 6
                                        ;             Child Loop BB3_178 Depth 6
                                        ;             Child Loop BB3_180 Depth 6
                                        ;             Child Loop BB3_182 Depth 6
                                        ;             Child Loop BB3_184 Depth 6
                                        ;             Child Loop BB3_186 Depth 6
                                        ;             Child Loop BB3_188 Depth 6
                                        ;             Child Loop BB3_210 Depth 6
                                        ;             Child Loop BB3_218 Depth 6
                                        ;             Child Loop BB3_224 Depth 6
                                        ;             Child Loop BB3_233 Depth 6
                                        ;             Child Loop BB3_240 Depth 6
                                        ;             Child Loop BB3_243 Depth 6
                                        ;             Child Loop BB3_248 Depth 6
                                        ;             Child Loop BB3_255 Depth 6
                                        ;             Child Loop BB3_288 Depth 6
                                        ;             Child Loop BB3_296 Depth 6
                                        ;             Child Loop BB3_302 Depth 6
                                        ;             Child Loop BB3_311 Depth 6
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s2, 0, v131
	v_mov_b32_e32 v3, 0
	s_mov_b32 s18, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_77
; %bb.76:                               ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v3, v[84:85], off glc
.LBB3_77:                               ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s37, v3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_cmp_eq_u32 s37, 0x10100
	s_cbranch_scc1 .LBB3_137
; %bb.78:                               ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_80
; %bb.79:                               ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v69, v5
	global_atomic_cmpswap_b32 v3, v[86:87], v[68:69], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0x100, v3, vcc_lo
.LBB3_80:                               ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s38, v3
	s_cmp_lg_u32 s37, s38
	s_cbranch_scc1 .LBB3_138
; %bb.81:                               ;   in Loop: Header=BB3_75 Depth=5
	v_mbcnt_lo_u32_b32 v21, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB3_83
; %bb.82:                               ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v3, v[86:87], off glc
.LBB3_83:                               ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_mov_b32 s5, 2
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 0x10100
	s_cbranch_scc1 .LBB3_171
; %bb.84:                               ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB3_88
; %bb.85:                               ;   in Loop: Header=BB3_75 Depth=5
	global_load_b64 v[28:29], v[96:97], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, s3, s6, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v4, s3, s7, v29, s3
	v_cmp_lt_u64_e64 s3, 0x752f, v[3:4]
	v_mov_b32_e32 v3, 1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB3_87
; %bb.86:                               ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v26, s6 :: v_dual_mov_b32 v27, s7
	global_atomic_cmpswap_b64 v[3:4], v[96:97], v[26:29], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s3, v[3:4], v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 1, 2, s3
.LBB3_87:                               ; %Flow1110
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s16
.LBB3_88:                               ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_readfirstlane_b32 s39, v3
	s_mov_b32 s5, 1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s39, 1
	s_cbranch_scc1 .LBB3_171
; %bb.89:                               ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s21, vcc_lo
	s_cbranch_execz .LBB3_118
; %bb.90:                               ;   in Loop: Header=BB3_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s3, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_96
; %bb.91:                               ;   in Loop: Header=BB3_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB3_95
; %bb.92:                               ; %.preheader3.i.i.i117.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_93:                               ; %.preheader3.i.i.i117
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_93
; %bb.94:                               ; %Flow1104
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_95:                               ; %Flow1106
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_96:                               ; %.loopexit4.i.i.i112
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s40, s7, 24
	s_mul_hi_u32 s41, s6, 24
	s_mul_i32 s42, s6, 24
	s_and_saveexec_b32 s43, s3
	s_cbranch_execz .LBB3_98
; %bb.97:                               ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s41, s40
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s42
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_98:                               ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s43
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v15, v5
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v31, s7
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v29, s5
	v_mov_b32_e32 v30, s6
	v_mov_b32_e32 v28, s4
	s_clause 0x3
	global_store_b128 v[11:12], v[15:18], off
	global_store_b128 v[11:12], v[28:31], off offset:16
	global_store_b128 v[11:12], v[28:31], off offset:32
	global_store_b128 v[11:12], v[28:31], off offset:48
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_106
; %bb.99:                               ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s18 :: v_dual_mov_b32 v133, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB3_102
; %bb.100:                              ; %.preheader1.i.i.i115.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_101:                              ; %.preheader1.i.i.i115
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s18 :: v_dual_mov_b32 v29, s19
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[30:31]
	v_dual_mov_b32 v31, v16 :: v_dual_mov_b32 v30, v15
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_101
.LBB3_102:                              ; %Flow1102
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[15:16], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_104
; %bb.103:                              ;   in Loop: Header=BB3_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[15:16], v[4:5], off offset:8
.LBB3_104:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[18:19], v[15:16], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	s_cbranch_vccnz .LBB3_106
; %bb.105:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v4, v[15:16], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[18:19], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_106:                              ; %Flow1103
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s41, s41, s40
	v_add_co_u32 v3, vcc_lo, v26, s42
	v_add_co_ci_u32_e32 v4, vcc_lo, s41, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_107:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_109
; %bb.108:                              ;   in Loop: Header=BB3_107 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_109:                              ;   in Loop: Header=BB3_107 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_111
; %bb.110:                              ;   in Loop: Header=BB3_107 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_112
.LBB3_111:                              ;   in Loop: Header=BB3_107 Depth=6
	s_mov_b32 s5, -1
.LBB3_112:                              ; %Flow1097
                                        ;   in Loop: Header=BB3_107 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_107
; %bb.113:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_117
; %bb.114:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17] offset:24 glc
	global_load_b64 v[18:19], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v12, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v29, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[26:27]
	v_dual_cndmask_b32 v27, v27, v28 :: v_dual_cndmask_b32 v26, v26, v6
	v_mov_b32_e32 v28, v15
	v_and_b32_e32 v6, v27, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v26, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v6, vcc_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_117
; %bb.115:                              ; %.preheader.i.i.i114.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s3, 0
.LBB3_116:                              ; %.preheader.i.i.i114
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[11:12], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[28:29]
	v_dual_mov_b32 v29, v16 :: v_dual_mov_b32 v28, v15
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_116
.LBB3_117:                              ; %Flow1095
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_118:                              ; %Flow1107
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc1 .LBB3_170
; %bb.119:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s3, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v11, s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x300, v11
	s_cbranch_execz .LBB3_122
; %bb.120:                              ; %.preheader175.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_lshlrev_b32_e32 v3, 3, v11
	s_bcnt1_i32_b32 s6, s3
	s_mov_b32 s16, 0
	s_lshl_b32 s7, s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, s18, v3
	v_add_co_ci_u32_e64 v4, null, s19, 0, s3
.LBB3_121:                              ; %.preheader175
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v6, v5 :: v_dual_add_nc_u32 v11, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v11
	global_store_b64 v[3:4], v[5:6], off
	v_add_co_u32 v3, s3, v3, s7
	v_add_co_ci_u32_e64 v4, s3, 0, v4, s3
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB3_121
.LBB3_122:                              ; %Flow1089
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $sgpr5
.LBB3_123:                              ; %.loopexit176
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_mov_b32_e32 v3, s20
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB3_125
; %bb.124:                              ;   in Loop: Header=BB3_123 Depth=6
	global_load_b32 v3, v[86:87], off glc
.LBB3_125:                              ;   in Loop: Header=BB3_123 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s3, s5
	s_cmp_lg_u32 s20, 0x10100
	s_cbranch_scc0 .LBB3_132
; %bb.126:                              ;   in Loop: Header=BB3_123 Depth=6
	v_mov_b32_e32 v3, s39
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_130
; %bb.127:                              ;   in Loop: Header=BB3_123 Depth=6
	s_add_i32 s3, s20, 0xffffff00
	v_mov_b32_e32 v6, v5
	s_lshr_b32 s3, s3, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[16:17]
	v_mad_u64_u32 v[11:12], null, s3, 24, v[3:4]
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s3, 0, v[3:4]
	v_mov_b32_e32 v3, s39
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s7, s3
	s_cbranch_execz .LBB3_129
; %bb.128:                              ;   in Loop: Header=BB3_123 Depth=6
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[86:87], v68, off
	v_mov_b32_e32 v3, 0
.LBB3_129:                              ; %Flow1082
                                        ;   in Loop: Header=BB3_123 Depth=6
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_130:                              ;   in Loop: Header=BB3_123 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s3, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	s_cbranch_scc1 .LBB3_133
; %bb.131:                              ;   in Loop: Header=BB3_123 Depth=6
	s_mov_b32 s6, 0
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_sleep 2
                                        ; implicit-def: $sgpr39
	s_branch .LBB3_134
.LBB3_132:                              ;   in Loop: Header=BB3_123 Depth=6
	s_mov_b32 s16, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr7
	s_branch .LBB3_135
.LBB3_133:                              ;   in Loop: Header=BB3_123 Depth=6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr3
.LBB3_134:                              ; %Flow1086
                                        ;   in Loop: Header=BB3_123 Depth=6
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_mov_b32 s7, 0
	s_mov_b32 s16, 0
	s_or_b32 s5, s5, s17
.LBB3_135:                              ; %Flow1085
                                        ;   in Loop: Header=BB3_123 Depth=6
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_139
; %bb.136:                              ;   in Loop: Header=BB3_123 Depth=6
	s_mov_b32 s39, s3
	s_branch .LBB3_123
.LBB3_137:                              ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v117, v4 :: v_dual_mov_b32 v116, v3
	s_branch .LBB3_199
.LBB3_138:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr18
	s_branch .LBB3_191
.LBB3_139:                              ; %loop.exit.guard909
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_169
; %bb.140:                              ;   in Loop: Header=BB3_75 Depth=5
	s_and_saveexec_b32 s40, s5
	s_cbranch_execz .LBB3_168
; %bb.141:                              ;   in Loop: Header=BB3_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s3, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_147
; %bb.142:                              ;   in Loop: Header=BB3_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB3_146
; %bb.143:                              ; %.preheader3.i.i.i124.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_144:                              ; %.preheader3.i.i.i124
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_144
; %bb.145:                              ; %Flow1077
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_146:                              ; %Flow1079
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_147:                              ; %.loopexit4.i.i.i119
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s41, s7, 24
	s_mul_hi_u32 s42, s6, 24
	s_mul_i32 s43, s6, 24
	s_and_saveexec_b32 s44, s3
	s_cbranch_execz .LBB3_149
; %bb.148:                              ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s42, s41
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s43
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_149:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s44
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v12, s19
	v_dual_mov_b32 v31, s7 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v29, s5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[28:31], off offset:8
	global_store_b128 v[3:4], v[28:31], off offset:24
	global_store_b128 v[3:4], v[28:31], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_157
; %bb.150:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s20 :: v_dual_mov_b32 v133, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB3_153
; %bb.151:                              ; %.preheader1.i.i.i122.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_152:                              ; %.preheader1.i.i.i122
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s20 :: v_dual_mov_b32 v29, s21
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[30:31]
	v_dual_mov_b32 v31, v12 :: v_dual_mov_b32 v30, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_152
.LBB3_153:                              ; %Flow1075
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_155
; %bb.154:                              ;   in Loop: Header=BB3_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB3_155:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB3_157
; %bb.156:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_157:                              ; %Flow1076
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s42, s42, s41
	v_add_co_u32 v3, vcc_lo, v26, s43
	v_add_co_ci_u32_e32 v4, vcc_lo, s42, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_158:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s3
	s_cbranch_execz .LBB3_160
; %bb.159:                              ;   in Loop: Header=BB3_158 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_160:                              ;   in Loop: Header=BB3_158 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_162
; %bb.161:                              ;   in Loop: Header=BB3_158 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_163
.LBB3_162:                              ;   in Loop: Header=BB3_158 Depth=6
	s_mov_b32 s5, -1
.LBB3_163:                              ; %Flow1070
                                        ;   in Loop: Header=BB3_158 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_158
; %bb.164:                              ;   in Loop: Header=BB3_75 Depth=5
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB3_168
; %bb.165:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v28, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v29, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v27, v19, v21 :: v_dual_cndmask_b32 v26, v18, v6
	v_and_b32_e32 v4, v27, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v26, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_168
; %bb.166:                              ; %.preheader.i.i.i121.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s3, 0
.LBB3_167:                              ; %.preheader.i.i.i121
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[3:4], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_167
.LBB3_168:                              ; %Flow1080
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s40
	s_mov_b32 s7, s39
.LBB3_169:                              ; %Flow1081
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s39, s7
.LBB3_170:                              ; %Flow1091
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s39
.LBB3_171:                              ; %__ockl_devmem_request.exit125
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s5, 0
	s_cselect_b32 s3, -1, 0
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_190
; %bb.172:                              ;   in Loop: Header=BB3_75 Depth=5
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s18, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_189
; %bb.173:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b64 v[3:4], v[96:97], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s6, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_189
; %bb.174:                              ;   in Loop: Header=BB3_75 Depth=5
	v_sub_nc_u32_e32 v3, 0x7530, v3
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s7, s6, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s16, s6
	s_addc_u32 s7, s17, s7
.LBB3_175:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x659
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB3_178
; %bb.176:                              ; %.preheader11.i138
                                        ;   in Loop: Header=BB3_175 Depth=6
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB3_175
.LBB3_177:                              ; %.preheader9.i137
                                        ;   in Loop: Header=BB3_178 Depth=6
	s_sleep 63
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_178:                              ; %Flow1061
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x326
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_177
; %bb.179:                              ; %Flow1058
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_add_u32 s20, s16, 0x18c
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB3_182
.LBB3_180:                              ; %.preheader7.i136
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 31
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x18c
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB3_180
	s_branch .LBB3_182
.LBB3_181:                              ; %.preheader5.i135
                                        ;   in Loop: Header=BB3_182 Depth=6
	s_sleep 15
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_182:                              ; %.loopexit8.i128
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0xc0
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_181
	s_branch .LBB3_184
.LBB3_183:                              ; %.preheader3.i134
                                        ;   in Loop: Header=BB3_184 Depth=6
	s_sleep 7
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_184:                              ; %Flow1052
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 0x59
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_183
	s_branch .LBB3_186
.LBB3_185:                              ; %.preheader1.i133
                                        ;   in Loop: Header=BB3_186 Depth=6
	s_sleep 3
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_186:                              ; %Flow1049
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_waitcnt lgkmcnt(0)
	s_add_u32 s20, s16, 38
	s_addc_u32 s21, s17, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s19, s[6:7], s[20:21]
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_185
; %bb.187:                              ; %Flow1046
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_cmp_le_u64_e64 s16, s[6:7], s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_189
.LBB3_188:                              ; %.preheader.i132
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_sendmsg_rtn_b64 s[16:17], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s16, s[6:7], s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_188
.LBB3_189:                              ; %__ockl_rtcwait_u32.exit139
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
	s_cmp_lg_u32 s5, 2
	v_mov_b32_e32 v117, s4
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v116, 0, 1, s5
.LBB3_190:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s18, 0
.LBB3_191:                              ; %Flow1113
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB3_199
; %bb.192:                              ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_196
; %bb.193:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b64 v[28:29], v[98:99], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s6, v28
	v_sub_co_ci_u32_e32 v4, vcc_lo, s7, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[3:4]
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB3_195
; %bb.194:                              ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v26, s6 :: v_dual_mov_b32 v27, s7
	global_atomic_cmpswap_b64 v[3:4], v[98:99], v[26:29], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[28:29]
	v_mov_b32_e32 v4, s4
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
.LBB3_195:                              ; %Flow1040
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_196:                              ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s6, v3
	v_readfirstlane_b32 s7, v4
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB3_200
; %bb.197:                              ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
.LBB3_198:                              ; %Flow1039
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v117, v16 :: v_dual_mov_b32 v116, v15
.LBB3_199:                              ; %Flow1116
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_xor_b32 s2, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB3_75
	s_branch .LBB3_315
.LBB3_200:                              ;   in Loop: Header=BB3_75 Depth=5
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v15 :: v_dual_mov_b32 v4, v16
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_236
; %bb.201:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x1
	global_load_b64 v[3:4], v5, s[12:13] glc
	global_load_b64 v[11:12], v5, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_cbranch_vccnz .LBB3_205
; %bb.202:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s5, exec_lo
	s_mov_b32 s2, exec_lo
	v_mbcnt_lo_u32_b32 v6, s5, 0
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB3_204
; %bb.203:                              ;   in Loop: Header=BB3_75 Depth=5
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s5, s5, 21
	v_mov_b32_e32 v4, s5
	global_atomic_add_u64 v[3:4], v5, v[4:5], s[12:13] glc
.LBB3_204:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x200000, v6, s[6:7]
	v_cmp_ge_u64_e64 s2, v[3:4], v[11:12]
	s_branch .LBB3_206
.LBB3_205:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB3_206:                              ; %Flow1037
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB3_235
; %bb.207:                              ;   in Loop: Header=BB3_75 Depth=5
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_213
; %bb.208:                              ;   in Loop: Header=BB3_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB3_212
; %bb.209:                              ; %.preheader3.i.i.i145.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_210:                              ; %.preheader3.i.i.i145
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[16:17] offset:40
	global_load_b64 v[26:27], v5, s[16:17]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v18, v28
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v12 :: v_dual_and_b32 v6, v19, v29
	v_mad_u64_u32 v[18:19], null, v6, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v12, v18
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_210
; %bb.211:                              ; %Flow1033
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_212:                              ; %Flow1035
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_213:                              ; %.loopexit4.i.i.i140
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[16:17] offset:40
	global_load_b128 v[26:29], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s21, s7, 24
	s_mul_hi_u32 s39, s6, 24
	s_mul_i32 s40, s6, 24
	s_and_saveexec_b32 s41, s2
	s_cbranch_execz .LBB3_215
; %bb.214:                              ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s39, s21
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v26, s40
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[18:19], v[11:14], off offset:8
.LBB3_215:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s41
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v31, s7
	v_dual_mov_b32 v19, v5 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v29, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[18:21], off
	global_store_b128 v[11:12], v[28:31], off offset:16
	global_store_b128 v[11:12], v[28:31], off offset:32
	global_store_b128 v[11:12], v[28:31], off offset:48
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_223
; %bb.216:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x1
	global_load_b64 v[134:135], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v132, s18 :: v_dual_mov_b32 v133, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[134:135], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[132:135], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[134:135]
	s_cbranch_execz .LBB3_219
; %bb.217:                              ; %.preheader1.i.i.i143.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_218:                              ; %.preheader1.i.i.i143
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s18 :: v_dual_mov_b32 v29, s19
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[28:31], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[30:31]
	v_dual_mov_b32 v31, v19 :: v_dual_mov_b32 v30, v18
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_218
.LBB3_219:                              ; %Flow1031
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[18:19], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_221
; %bb.220:                              ;   in Loop: Header=BB3_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[18:19], v[4:5], off offset:8
.LBB3_221:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[28:29], v[18:19], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[28:29]
	s_cbranch_vccnz .LBB3_223
; %bb.222:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v4, v[18:19], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[28:29], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_223:                              ; %Flow1032
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s39, s39, s21
	v_add_co_u32 v3, vcc_lo, v26, s40
	v_add_co_ci_u32_e32 v4, vcc_lo, s39, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_224:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_226
; %bb.225:                              ;   in Loop: Header=BB3_224 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_226:                              ;   in Loop: Header=BB3_224 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_228
; %bb.227:                              ;   in Loop: Header=BB3_224 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_229
.LBB3_228:                              ;   in Loop: Header=BB3_224 Depth=6
	s_mov_b32 s5, -1
.LBB3_229:                              ; %Flow1026
                                        ;   in Loop: Header=BB3_224 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_224
; %bb.230:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_234
; %bb.231:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17] offset:24 glc
	global_load_b64 v[28:29], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v26, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[26:27]
	v_dual_cndmask_b32 v27, v27, v21 :: v_dual_cndmask_b32 v26, v26, v6
	v_and_b32_e32 v6, v27, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v26, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v28, v11
	v_mov_b32_e32 v28, v18
	v_add_co_ci_u32_e32 v12, vcc_lo, v29, v6, vcc_lo
	v_mov_b32_e32 v29, v19
	global_store_b64 v[11:12], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_234
; %bb.232:                              ; %.preheader.i.i.i142.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s2, 0
.LBB3_233:                              ; %.preheader.i.i.i142
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[11:12], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[26:29], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[28:29]
	v_dual_mov_b32 v29, v19 :: v_dual_mov_b32 v28, v18
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_233
.LBB3_234:                              ; %Flow1024
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_235:                              ; %Flow1038
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
.LBB3_236:                              ; %__ockl_devmem_request.exit146
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v3
	v_readfirstlane_b32 s17, v4
	s_cmp_eq_u64 s[16:17], 0
	s_cbranch_scc1 .LBB3_281
; %bb.237:                              ;   in Loop: Header=BB3_75 Depth=5
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b32 v6, v[82:83], off
	s_bcnt1_i32_b32 s3, exec_lo
	s_add_u32 s6, s16, 16
	s_addc_u32 s7, s17, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v3, 5, v3
	s_and_saveexec_b32 s2, s1
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB3_245
; %bb.238:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v15, v[100:101], off
	s_mov_b32 s18, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB3_241
; %bb.239:                              ; %.preheader172.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s19, s3, 2
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB3_240:                              ; %.preheader172
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_add_nc_u32_e32 v16, s3, v16
	global_store_b32 v[11:12], v5, off
	v_add_co_u32 v11, s2, v11, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s2, 0, v12, s2
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB3_240
.LBB3_241:                              ; %Flow1013
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
	global_load_b32 v16, v[102:103], off
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v15, v4, v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v6
	s_cbranch_execz .LBB3_244
; %bb.242:                              ; %.preheader170.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_mul_lo_u32 v12, v15, s3
	s_mov_b32 s18, 0
.LBB3_243:                              ; %.preheader170
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_lshlrev_b32_e64 v15, v11, 1
	v_lshrrev_b32_e32 v16, 3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v12
	v_and_b32_e32 v16, 0x1ffffffc, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v11, v6
	global_store_b32 v16, v15, s[6:7]
	s_or_b32 s18, vcc_lo, s18
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB3_243
.LBB3_244:                              ; %Flow1010
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_245:                              ; %Flow1018
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB3_250
; %bb.246:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s18, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB3_249
; %bb.247:                              ; %.preheader.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v15, v[112:113], off
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s19, s3, 2
	s_mov_b32 s20, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB3_248:                              ; %.preheader
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_add_nc_u32_e32 v16, s3, v16
	s_waitcnt vmcnt(0)
	global_store_b32 v[11:12], v15, off
	v_add_co_u32 v11, s2, v11, s19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s2, 0, v12, s2
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s20, vcc_lo, s20
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB3_248
.LBB3_249:                              ; %Flow1016
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s18
.LBB3_250:                              ; %.loopexit
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB3_254
; %bb.251:                              ;   in Loop: Header=BB3_75 Depth=5
	v_and_b32_e32 v6, 31, v6
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB3_253
; %bb.252:                              ;   in Loop: Header=BB3_75 Depth=5
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v6, -1, v6, v11
	global_store_b32 v[3:4], v6, off
.LBB3_253:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	global_store_b128 v5, v[22:25], s[16:17]
.LBB3_254:                              ; %Flow1007
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $sgpr5
.LBB3_255:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s2, 0, v131
	v_mov_b32_e32 v3, s37
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_257
; %bb.256:                              ;   in Loop: Header=BB3_255 Depth=6
	global_load_b32 v3, v[84:85], off glc
.LBB3_257:                              ;   in Loop: Header=BB3_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s37, v3
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s5, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s3, s5
	s_cmp_eq_u32 s37, 0x10100
	s_cbranch_scc1 .LBB3_264
; %bb.258:                              ;   in Loop: Header=BB3_255 Depth=6
	v_mov_b32_e32 v3, s38
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_260
; %bb.259:                              ;   in Loop: Header=BB3_255 Depth=6
	global_load_b32 v3, v[86:87], off glc
.LBB3_260:                              ;   in Loop: Header=BB3_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s38, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s37, s38
	s_cbranch_scc0 .LBB3_265
; %bb.261:                              ;   in Loop: Header=BB3_255 Depth=6
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_272
; %bb.262:                              ;   in Loop: Header=BB3_255 Depth=6
	s_cmpk_lt_u32 s37, 0x100
	s_cbranch_scc0 .LBB3_266
; %bb.263:                              ;   in Loop: Header=BB3_255 Depth=6
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[6:7]
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[11:12], null, s37, 24, v[3:4]
	s_branch .LBB3_267
.LBB3_264:                              ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b64 s[2:3], 0
	s_mov_b32 s20, -1
	s_mov_b32 s18, 0
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB3_277
.LBB3_265:                              ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b32 s18, -1
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB3_276
.LBB3_266:                              ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_267:                              ; %Flow999
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_269
; %bb.268:                              ;   in Loop: Header=BB3_255 Depth=6
	s_add_i32 s6, s37, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s18, s6, 8
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v22, s[6:7]
	s_and_b32 s6, s37, 0xff
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s18, 24, v[3:4]
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
.LBB3_269:                              ;   in Loop: Header=BB3_255 Depth=6
	v_dual_mov_b32 v15, s37 :: v_dual_mov_b32 v4, s17
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v6, v5
	global_store_b32 v5, v15, s[16:17] offset:4
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_271
; %bb.270:                              ;   in Loop: Header=BB3_255 Depth=6
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[84:85], v118, off
	v_dual_mov_b32 v3, v11 :: v_dual_mov_b32 v4, v12
.LBB3_271:                              ; %Flow997
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_272:                              ; %Flow1000
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v4
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB3_274
; %bb.273:                              ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr38
	s_branch .LBB3_275
.LBB3_274:                              ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b32 s19, 0
	s_and_not1_b32 s2, s2, exec_lo
	s_sleep 2
.LBB3_275:                              ; %Flow1005
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_mov_b32 s18, 0
.LBB3_276:                              ; %Flow1004
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_mov_b32 s20, 0
	s_or_b32 s5, s3, s2
                                        ; implicit-def: $sgpr2_sgpr3
.LBB3_277:                              ; %Flow1003
                                        ;   in Loop: Header=BB3_255 Depth=6
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_255
; %bb.278:                              ; %loop.exit.guard913
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v16, s3 :: v_dual_mov_b32 v15, s2
	s_and_b32 vcc_lo, exec_lo, s20
	s_cbranch_vccnz .LBB3_198
; %bb.279:                              ; %loop.exit.guard914
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_xor_b32 s2, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB3_282
; %bb.280:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s18, 0
	s_branch .LBB3_283
.LBB3_281:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s18, 0
	s_branch .LBB3_198
.LBB3_282:                              ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr6_sgpr7
.LBB3_283:                              ; %Flow994
                                        ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB3_198
; %bb.284:                              ;   in Loop: Header=BB3_75 Depth=5
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB3_313
; %bb.285:                              ;   in Loop: Header=BB3_75 Depth=5
	s_load_b64 s[18:19], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_291
; %bb.286:                              ;   in Loop: Header=BB3_75 Depth=5
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[28:29], v5, s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[18:19] offset:40
	global_load_b64 v[15:16], v5, s[18:19]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v29
	v_and_b32_e32 v6, v11, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[28:29]
	s_cbranch_execz .LBB3_290
; %bb.287:                              ; %.preheader3.i.i.i152.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_288:                              ; %.preheader3.i.i.i152
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[18:19] offset:40
	global_load_b64 v[18:19], v5, s[18:19]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v28
	v_and_b32_e32 v6, v16, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[26:27], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_288
; %bb.289:                              ; %Flow990
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_290:                              ; %Flow992
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_291:                              ; %.loopexit4.i.i.i147
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[18:19] offset:40
	global_load_b128 v[26:29], v5, s[18:19]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s37, s7, 24
	s_mul_hi_u32 s38, s6, 24
	s_mul_i32 s39, s6, 24
	s_and_saveexec_b32 s40, s2
	s_cbranch_execz .LBB3_293
; %bb.292:                              ;   in Loop: Header=BB3_75 Depth=5
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s38, s37
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v26, s39
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v27, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_293:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s40
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v28, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v29, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
	v_dual_mov_b32 v31, s7 :: v_dual_mov_b32 v30, s6
	v_dual_mov_b32 v29, s5 :: v_dual_mov_b32 v28, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[28:31], off offset:8
	global_store_b128 v[3:4], v[28:31], off offset:24
	global_store_b128 v[3:4], v[28:31], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_301
; %bb.294:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x1
	global_load_b64 v[133:134], v5, s[18:19] offset:32 glc
	global_load_b64 v[3:4], v5, s[18:19] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v131, s20 :: v_dual_mov_b32 v132, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v26, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v27, v4, vcc_lo
	global_store_b64 v[3:4], v[133:134], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[30:31], v5, v[131:134], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[30:31], v[133:134]
	s_cbranch_execz .LBB3_297
; %bb.295:                              ; %.preheader1.i.i.i150.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s7, 0
.LBB3_296:                              ; %.preheader1.i.i.i150
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_dual_mov_b32 v28, s20 :: v_dual_mov_b32 v29, s21
	s_sleep 1
	global_store_b64 v[3:4], v[30:31], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[28:31], s[18:19] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[30:31]
	v_dual_mov_b32 v31, v12 :: v_dual_mov_b32 v30, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_296
.LBB3_297:                              ; %Flow988
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[18:19] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_299
; %bb.298:                              ;   in Loop: Header=BB3_75 Depth=5
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB3_299:                              ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB3_301
; %bb.300:                              ;   in Loop: Header=BB3_75 Depth=5
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_301:                              ; %Flow989
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s38, s38, s37
	v_add_co_u32 v3, vcc_lo, v26, s39
	v_add_co_ci_u32_e32 v4, vcc_lo, s38, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_302:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_304
; %bb.303:                              ;   in Loop: Header=BB3_302 Depth=6
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_304:                              ;   in Loop: Header=BB3_302 Depth=6
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_306
; %bb.305:                              ;   in Loop: Header=BB3_302 Depth=6
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_307
.LBB3_306:                              ;   in Loop: Header=BB3_302 Depth=6
	s_mov_b32 s5, -1
.LBB3_307:                              ; %Flow983
                                        ;   in Loop: Header=BB3_302 Depth=6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_302
; %bb.308:                              ;   in Loop: Header=BB3_75 Depth=5
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_312
; %bb.309:                              ;   in Loop: Header=BB3_75 Depth=5
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[18:19] offset:40
	global_load_b64 v[11:12], v5, s[18:19] offset:24 glc
	global_load_b64 v[15:16], v5, s[18:19]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v28, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v29, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v27, v19, v21 :: v_dual_cndmask_b32 v26, v18, v6
	v_and_b32_e32 v4, v27, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v26, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[28:29], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[28:29], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_312
; %bb.310:                              ; %.preheader.i.i.i149.preheader
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_mov_b32 s2, 0
.LBB3_311:                              ; %.preheader.i.i.i149
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ;           Parent Loop BB3_75 Depth=5
                                        ; =>          This Inner Loop Header: Depth=6
	s_sleep 1
	global_store_b64 v[3:4], v[28:29], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[26:29], s[18:19] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[28:29]
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_311
.LBB3_312:                              ; %Flow981
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v131, 0
.LBB3_313:                              ; %Flow993
                                        ;   in Loop: Header=BB3_75 Depth=5
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mov_b32 v15, v116 :: v_dual_mov_b32 v16, v117
	s_mov_b32 s18, -1
	s_branch .LBB3_198
.LBB3_314:                              ;   in Loop: Header=BB3_43 Depth=4
                                        ; implicit-def: $vgpr114_vgpr115
                                        ; implicit-def: $sgpr36
                                        ; implicit-def: $vgpr130
	s_branch .LBB3_338
.LBB3_315:                              ;   in Loop: Header=BB3_43 Depth=4
	v_cmp_ne_u64_e64 s5, 1, v[116:117]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_317
; %bb.316:                              ;   in Loop: Header=BB3_43 Depth=4
	v_dual_mov_b32 v114, v116 :: v_dual_mov_b32 v115, v117
	s_branch .LBB3_337
.LBB3_317:                              ;   in Loop: Header=BB3_43 Depth=4
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s16, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_334
; %bb.318:                              ;   in Loop: Header=BB3_43 Depth=4
	global_load_b64 v[3:4], v[98:99], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_334
; %bb.319:                              ;   in Loop: Header=BB3_43 Depth=4
	v_sub_nc_u32_e32 v3, 0x4e20, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB3_320:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x659
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB3_323
; %bb.321:                              ; %.preheader11.i166
                                        ;   in Loop: Header=BB3_320 Depth=5
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB3_320
.LBB3_322:                              ; %.preheader9.i165
                                        ;   in Loop: Header=BB3_323 Depth=5
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_323:                              ; %Flow975
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x326
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB3_322
; %bb.324:                              ; %Flow972
                                        ;   in Loop: Header=BB3_43 Depth=4
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB3_327
.LBB3_325:                              ; %.preheader7.i164
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB3_325
	s_branch .LBB3_327
.LBB3_326:                              ; %.preheader5.i163
                                        ;   in Loop: Header=BB3_327 Depth=5
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_327:                              ; %.loopexit8.i156
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0xc0
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB3_326
	s_branch .LBB3_329
.LBB3_328:                              ; %.preheader3.i162
                                        ;   in Loop: Header=BB3_329 Depth=5
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_329:                              ; %Flow966
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x59
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB3_328
	s_branch .LBB3_331
.LBB3_330:                              ; %.preheader1.i161
                                        ;   in Loop: Header=BB3_331 Depth=5
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_331:                              ; %Flow963
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 38
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s17, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB3_330
; %bb.332:                              ; %Flow960
                                        ;   in Loop: Header=BB3_43 Depth=4
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_334
.LBB3_333:                              ; %.preheader.i160
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_11 Depth=3
                                        ;         Parent Loop BB3_43 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_333
.LBB3_334:                              ; %__ockl_rtcwait_u32.exit167
                                        ;   in Loop: Header=BB3_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s16
	v_mov_b32_e32 v3, s36
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v130
	s_cbranch_execz .LBB3_336
; %bb.335:                              ;   in Loop: Header=BB3_43 Depth=4
	global_load_b32 v3, v[84:85], off glc
.LBB3_336:                              ;   in Loop: Header=BB3_43 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s36, v3
.LBB3_337:                              ;   in Loop: Header=BB3_43 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v15, v114 :: v_dual_mov_b32 v16, v115
	s_mov_b32 s6, 0
.LBB3_338:                              ; %Flow1122
                                        ;   in Loop: Header=BB3_43 Depth=4
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_43
; %bb.339:                              ; %Flow1123
                                        ;   in Loop: Header=BB3_11 Depth=3
	v_mov_b32_e32 v22, v7
.LBB3_340:                              ; %Flow1124
                                        ;   in Loop: Header=BB3_11 Depth=3
	v_dual_mov_b32 v11, v15 :: v_dual_mov_b32 v12, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v4, v22
	s_and_b32 s3, s6, exec_lo
.LBB3_341:                              ; %Flow1126
                                        ;   in Loop: Header=BB3_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s34
.LBB3_342:                              ; %.loopexit187
                                        ;   in Loop: Header=BB3_11 Depth=3
	s_xor_b32 s1, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s30, s1, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB3_11
; %bb.343:                              ; %Flow1139
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_mov_b32 s1, 0
	s_branch .LBB3_345
.LBB3_344:                              ;   in Loop: Header=BB3_6 Depth=2
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_345:                              ; %Flow1321
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB3_642
; %bb.346:                              ;   in Loop: Header=BB3_6 Depth=2
	v_mbcnt_lo_u32_b32 v70, exec_lo, 0
	s_bcnt1_i32_b32 s30, exec_lo
                                        ; implicit-def: $vgpr28_vgpr29
.LBB3_347:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB3_351 Depth 4
                                        ;         Child Loop BB3_378 Depth 4
                                        ;           Child Loop BB3_396 Depth 5
                                        ;           Child Loop BB3_404 Depth 5
                                        ;           Child Loop BB3_410 Depth 5
                                        ;           Child Loop BB3_419 Depth 5
                                        ;           Child Loop BB3_424 Depth 5
                                        ;           Child Loop BB3_426 Depth 5
                                        ;           Child Loop BB3_447 Depth 5
                                        ;           Child Loop BB3_455 Depth 5
                                        ;           Child Loop BB3_461 Depth 5
                                        ;           Child Loop BB3_470 Depth 5
                                        ;           Child Loop BB3_478 Depth 5
                                        ;           Child Loop BB3_481 Depth 5
                                        ;           Child Loop BB3_483 Depth 5
                                        ;           Child Loop BB3_485 Depth 5
                                        ;           Child Loop BB3_487 Depth 5
                                        ;           Child Loop BB3_489 Depth 5
                                        ;           Child Loop BB3_491 Depth 5
                                        ;           Child Loop BB3_513 Depth 5
                                        ;           Child Loop BB3_521 Depth 5
                                        ;           Child Loop BB3_527 Depth 5
                                        ;           Child Loop BB3_536 Depth 5
                                        ;           Child Loop BB3_543 Depth 5
                                        ;           Child Loop BB3_546 Depth 5
                                        ;           Child Loop BB3_551 Depth 5
                                        ;           Child Loop BB3_558 Depth 5
                                        ;           Child Loop BB3_591 Depth 5
                                        ;           Child Loop BB3_599 Depth 5
                                        ;           Child Loop BB3_605 Depth 5
                                        ;           Child Loop BB3_614 Depth 5
                                        ;         Child Loop BB3_623 Depth 4
                                        ;         Child Loop BB3_626 Depth 4
                                        ;         Child Loop BB3_628 Depth 4
                                        ;         Child Loop BB3_630 Depth 4
                                        ;         Child Loop BB3_632 Depth 4
                                        ;         Child Loop BB3_634 Depth 4
                                        ;         Child Loop BB3_636 Depth 4
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_eq_u32 s29, 0
	s_mov_b32 s5, -1
	;;#ASMSTART
	;;#ASMEND
	s_cbranch_scc1 .LBB3_375
; %bb.348:                              ;   in Loop: Header=BB3_347 Depth=3
	v_cmp_eq_u32_e64 s1, 0, v70
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_350
; %bb.349:                              ;   in Loop: Header=BB3_347 Depth=3
	global_load_b32 v3, v[34:35], off glc
.LBB3_350:                              ;   in Loop: Header=BB3_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	global_load_b32 v6, v[36:37], off
	v_cvt_f32_u32_e32 v4, s29
	s_sub_i32 s2, 0, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, s2, v4
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s2, v3
	v_add_nc_u32_e32 v3, s2, v70
	s_mov_b32 s2, s29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v11, v4, v11
	v_add_nc_u32_e32 v15, v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v15
	v_mul_lo_u32 v4, v4, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v3, v4, vcc_lo
.LBB3_351:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x100, v16
	s_xor_b32 s3, exec_lo, s3
; %bb.352:                              ;   in Loop: Header=BB3_351 Depth=4
	s_add_u32 s6, s10, 0x2800
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0x1800, v7, s[6:7]
	v_mad_u64_u32 v[3:4], null, v16, 24, v[11:12]
; %bb.353:                              ; %Flow1148
                                        ;   in Loop: Header=BB3_351 Depth=4
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB3_355
; %bb.354:                              ;   in Loop: Header=BB3_351 Depth=4
	s_add_u32 s6, s10, 0x2800
	v_add_nc_u32_e32 v11, 0xffffff00, v16
	s_addc_u32 s7, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[6:7]
	v_lshrrev_b32_e32 v18, 8, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v18, 24, v[3:4]
	v_and_b32_e32 v18, 0xff, v16
	global_load_b64 v[11:12], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v18, 24, v[11:12]
.LBB3_355:                              ;   in Loop: Header=BB3_351 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b32 v3, v[3:4], off offset:16 glc
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v6
	s_cbranch_vccz .LBB3_357
; %bb.356:                              ;   in Loop: Header=BB3_351 Depth=4
	s_ctz_i32_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s3, s3, 2
	v_mov_b32_e32 v3, s3
	ds_bpermute_b32 v3, v3, v16
	s_branch .LBB3_358
.LBB3_357:                              ;   in Loop: Header=BB3_351 Depth=4
	v_mov_b32_e32 v3, -1
.LBB3_358:                              ;   in Loop: Header=BB3_351 Depth=4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v3
	s_cmp_eq_u32 s6, -1
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB3_361
; %bb.359:                              ;   in Loop: Header=BB3_351 Depth=4
	s_cmpk_lt_u32 s6, 0x100
	s_cbranch_scc0 .LBB3_362
; %bb.360:                              ;   in Loop: Header=BB3_351 Depth=4
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_mov_b32 s7, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
	s_branch .LBB3_363
.LBB3_361:                              ;   in Loop: Header=BB3_351 Depth=4
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr11_vgpr12
	s_branch .LBB3_366
.LBB3_362:                              ;   in Loop: Header=BB3_351 Depth=4
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_363:                              ; %Flow1141
                                        ;   in Loop: Header=BB3_351 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB3_365
; %bb.364:                              ;   in Loop: Header=BB3_351 Depth=4
	s_add_i32 s7, s6, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_lshr_b32 s7, s7, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_and_b32 s6, s6, 0xff
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s6, 24, v[3:4]
.LBB3_365:                              ; %Flow1142
                                        ;   in Loop: Header=BB3_351 Depth=4
	s_mov_b32 s6, 0
.LBB3_366:                              ; %Flow1144
                                        ;   in Loop: Header=BB3_351 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_370
; %bb.367:                              ;   in Loop: Header=BB3_351 Depth=4
	v_add_nc_u32_e32 v3, s30, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v4, v3, v15
	v_mul_lo_u32 v4, v4, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v4
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_subrev_nc_u32_e32 v4, s29, v3
	v_cmp_le_u32_e32 vcc_lo, s29, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v3, v4, vcc_lo
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB3_369
; %bb.368:                              ;   in Loop: Header=BB3_351 Depth=4
	global_store_b32 v[34:35], v16, off
.LBB3_369:                              ;   in Loop: Header=BB3_351 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	v_dual_mov_b32 v11, v28 :: v_dual_mov_b32 v12, v29
	s_sub_i32 s2, s2, s30
.LBB3_370:                              ;   in Loop: Header=BB3_351 Depth=4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB3_372
; %bb.371:                              ;   in Loop: Header=BB3_351 Depth=4
	s_mov_b32 s3, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr16
	s_branch .LBB3_373
.LBB3_372:                              ;   in Loop: Header=BB3_351 Depth=4
	s_cmp_lt_i32 s2, 1
	s_mov_b32 s3, 0
	s_cselect_b32 s6, -1, 0
.LBB3_373:                              ; %Flow1150
                                        ;   in Loop: Header=BB3_351 Depth=4
	v_dual_mov_b32 v29, v12 :: v_dual_mov_b32 v28, v11
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_351
; %bb.374:                              ; %loop.exit.guard922
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_xor_b32 s1, s3, -1
	s_branch .LBB3_376
.LBB3_375:                              ;   in Loop: Header=BB3_347 Depth=3
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_376:                              ; %Flow1317
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB3_617
; %bb.377:                              ; %.loopexit190
                                        ;   in Loop: Header=BB3_347 Depth=3
	v_mbcnt_lo_u32_b32 v71, exec_lo, 0
                                        ; implicit-def: $vgpr30_vgpr31
.LBB3_378:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB3_396 Depth 5
                                        ;           Child Loop BB3_404 Depth 5
                                        ;           Child Loop BB3_410 Depth 5
                                        ;           Child Loop BB3_419 Depth 5
                                        ;           Child Loop BB3_424 Depth 5
                                        ;           Child Loop BB3_426 Depth 5
                                        ;           Child Loop BB3_447 Depth 5
                                        ;           Child Loop BB3_455 Depth 5
                                        ;           Child Loop BB3_461 Depth 5
                                        ;           Child Loop BB3_470 Depth 5
                                        ;           Child Loop BB3_478 Depth 5
                                        ;           Child Loop BB3_481 Depth 5
                                        ;           Child Loop BB3_483 Depth 5
                                        ;           Child Loop BB3_485 Depth 5
                                        ;           Child Loop BB3_487 Depth 5
                                        ;           Child Loop BB3_489 Depth 5
                                        ;           Child Loop BB3_491 Depth 5
                                        ;           Child Loop BB3_513 Depth 5
                                        ;           Child Loop BB3_521 Depth 5
                                        ;           Child Loop BB3_527 Depth 5
                                        ;           Child Loop BB3_536 Depth 5
                                        ;           Child Loop BB3_543 Depth 5
                                        ;           Child Loop BB3_546 Depth 5
                                        ;           Child Loop BB3_551 Depth 5
                                        ;           Child Loop BB3_558 Depth 5
                                        ;           Child Loop BB3_591 Depth 5
                                        ;           Child Loop BB3_599 Depth 5
                                        ;           Child Loop BB3_605 Depth 5
                                        ;           Child Loop BB3_614 Depth 5
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, 0, v71
	v_mov_b32_e32 v3, 0
	s_mov_b32 s18, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_380
; %bb.379:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v3, v[32:33], off glc
.LBB3_380:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v3
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_cmp_eq_u32 s31, 0x10100
	s_cbranch_scc1 .LBB3_440
; %bb.381:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_383
; %bb.382:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v69, v5
	global_atomic_cmpswap_b32 v3, v[48:49], v[68:69], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, 0x100, v3, vcc_lo
.LBB3_383:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s34, v3
	s_cmp_lg_u32 s31, s34
	s_cbranch_scc1 .LBB3_441
; %bb.384:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mbcnt_lo_u32_b32 v27, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_386
; %bb.385:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v3, v[48:49], off glc
.LBB3_386:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_mov_b32 s16, 2
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s20, 0x10100
	s_cbranch_scc1 .LBB3_474
; %bb.387:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v3, 1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB3_391
; %bb.388:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b64 v[23:24], v[50:51], off glc
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, s2, s6, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v4, s2, s7, v24, s2
	v_cmp_lt_u64_e64 s2, 0x752f, v[3:4]
	v_mov_b32_e32 v3, 1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_390
; %bb.389:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v21, s6 :: v_dual_mov_b32 v22, s7
	global_atomic_cmpswap_b64 v[3:4], v[50:51], v[21:24], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s2, v[3:4], v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 1, 2, s2
.LBB3_390:                              ; %Flow1306
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_391:                              ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s16, 1
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s3, 1
	s_cbranch_scc1 .LBB3_474
; %bb.392:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s21, vcc_lo
	s_cbranch_execz .LBB3_421
; %bb.393:                              ;   in Loop: Header=BB3_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_399
; %bb.394:                              ;   in Loop: Header=BB3_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB3_398
; %bb.395:                              ; %.preheader3.i.i.i75.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_396:                              ; %.preheader3.i.i.i75
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_396
; %bb.397:                              ; %Flow1300
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_398:                              ; %Flow1302
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_399:                              ; %.loopexit4.i.i.i70
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s35, s7, 24
	s_mul_hi_u32 s36, s6, 24
	s_mul_i32 s37, s6, 24
	s_and_saveexec_b32 s38, s2
	s_cbranch_execz .LBB3_401
; %bb.400:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s36, s35
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s37
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_401:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s38
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v15, v5 :: v_dual_mov_b32 v26, s7
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v24, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[15:18], off
	global_store_b128 v[11:12], v[23:26], off offset:16
	global_store_b128 v[11:12], v[23:26], off offset:32
	global_store_b128 v[11:12], v[23:26], off offset:48
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_409
; %bb.402:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s18 :: v_dual_mov_b32 v81, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB3_405
; %bb.403:                              ; %.preheader1.i.i.i73.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_404:                              ; %.preheader1.i.i.i73
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v24, s19
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[25:26]
	v_dual_mov_b32 v26, v16 :: v_dual_mov_b32 v25, v15
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_404
.LBB3_405:                              ; %Flow1298
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[15:16], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_407
; %bb.406:                              ;   in Loop: Header=BB3_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[15:16], v[4:5], off offset:8
.LBB3_407:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[18:19], v[15:16], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	s_cbranch_vccnz .LBB3_409
; %bb.408:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v4, v[15:16], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[18:19], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_409:                              ; %Flow1299
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s36, s36, s35
	v_add_co_u32 v3, vcc_lo, v21, s37
	v_add_co_ci_u32_e32 v4, vcc_lo, s36, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_410:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_412
; %bb.411:                              ;   in Loop: Header=BB3_410 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_412:                              ;   in Loop: Header=BB3_410 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_414
; %bb.413:                              ;   in Loop: Header=BB3_410 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_415
.LBB3_414:                              ;   in Loop: Header=BB3_410 Depth=5
	s_mov_b32 s5, -1
.LBB3_415:                              ; %Flow1293
                                        ;   in Loop: Header=BB3_410 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_410
; %bb.416:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_420
; %bb.417:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17] offset:24 glc
	global_load_b64 v[18:19], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v12, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v24, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v22, vcc_lo, s19, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[21:22]
	v_dual_cndmask_b32 v22, v22, v23 :: v_dual_cndmask_b32 v21, v21, v6
	v_dual_mov_b32 v23, v15 :: v_dual_and_b32 v6, v22, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v21, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v18, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v6, vcc_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_420
; %bb.418:                              ; %.preheader.i.i.i72.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s2, 0
.LBB3_419:                              ; %.preheader.i.i.i72
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[11:12], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[23:24]
	v_dual_mov_b32 v24, v16 :: v_dual_mov_b32 v23, v15
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_419
.LBB3_420:                              ; %Flow1291
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_421:                              ; %Flow1303
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_cmp_eq_u64 s[18:19], 0
	s_cbranch_scc1 .LBB3_473
; %bb.422:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s2, exec_lo
	s_mov_b32 s5, exec_lo
	v_mbcnt_lo_u32_b32 v11, s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 0x300, v11
	s_cbranch_execz .LBB3_425
; %bb.423:                              ; %.preheader185.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_lshlrev_b32_e32 v3, 3, v11
	s_bcnt1_i32_b32 s6, s2
	s_mov_b32 s16, 0
	s_lshl_b32 s7, s6, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s2, s18, v3
	v_add_co_ci_u32_e64 v4, null, s19, 0, s2
.LBB3_424:                              ; %.preheader185
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v6, v5 :: v_dual_add_nc_u32 v11, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x2ff, v11
	global_store_b64 v[3:4], v[5:6], off
	v_add_co_u32 v3, s2, v3, s7
	v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB3_424
.LBB3_425:                              ; %Flow1285
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $sgpr5
.LBB3_426:                              ; %.loopexit186
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e32 vcc_lo, 0, v27
	v_mov_b32_e32 v3, s20
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_428
; %bb.427:                              ;   in Loop: Header=BB3_426 Depth=5
	global_load_b32 v3, v[48:49], off glc
.LBB3_428:                              ;   in Loop: Header=BB3_426 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s20, v3
	s_and_not1_b32 s2, s5, exec_lo
	s_and_b32 s5, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s2, s5
	s_cmp_lg_u32 s20, 0x10100
	s_cbranch_scc0 .LBB3_435
; %bb.429:                              ;   in Loop: Header=BB3_426 Depth=5
	v_mov_b32_e32 v3, s3
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_433
; %bb.430:                              ;   in Loop: Header=BB3_426 Depth=5
	s_add_i32 s2, s20, 0xffffff00
	v_mov_b32_e32 v6, v5
	s_lshr_b32 s2, s2, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	v_mad_u64_u32 v[11:12], null, s2, 24, v[3:4]
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e64 s2, 0, v[3:4]
	v_mov_b32_e32 v3, s3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB3_432
; %bb.431:                              ;   in Loop: Header=BB3_426 Depth=5
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[48:49], v68, off
	v_mov_b32_e32 v3, 0
.LBB3_432:                              ; %Flow1278
                                        ;   in Loop: Header=BB3_426 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_433:                              ;   in Loop: Header=BB3_426 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB3_436
; %bb.434:                              ;   in Loop: Header=BB3_426 Depth=5
	s_mov_b32 s6, 0
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_sleep 2
                                        ; implicit-def: $sgpr3
	s_branch .LBB3_437
.LBB3_435:                              ;   in Loop: Header=BB3_426 Depth=5
	s_mov_b32 s16, -1
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $sgpr7
	s_branch .LBB3_438
.LBB3_436:                              ;   in Loop: Header=BB3_426 Depth=5
	s_mov_b32 s6, -1
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr2
.LBB3_437:                              ; %Flow1282
                                        ;   in Loop: Header=BB3_426 Depth=5
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_mov_b32 s7, 0
	s_mov_b32 s16, 0
	s_or_b32 s5, s5, s17
.LBB3_438:                              ; %Flow1281
                                        ;   in Loop: Header=BB3_426 Depth=5
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_442
; %bb.439:                              ;   in Loop: Header=BB3_426 Depth=5
	s_mov_b32 s3, s2
	s_branch .LBB3_426
.LBB3_440:                              ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v30, v3
	s_branch .LBB3_502
.LBB3_441:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s5, -1
                                        ; implicit-def: $sgpr18
	s_branch .LBB3_494
.LBB3_442:                              ; %loop.exit.guard925
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_472
; %bb.443:                              ;   in Loop: Header=BB3_378 Depth=4
	s_and_saveexec_b32 s35, s5
	s_cbranch_execz .LBB3_471
; %bb.444:                              ;   in Loop: Header=BB3_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s2, s2, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_450
; %bb.445:                              ;   in Loop: Header=BB3_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB3_449
; %bb.446:                              ; %.preheader3.i.i.i82.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_447:                              ; %.preheader3.i.i.i82
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_447
; %bb.448:                              ; %Flow1273
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_449:                              ; %Flow1275
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_450:                              ; %.loopexit4.i.i.i77
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s20, v11
	v_readfirstlane_b32 s21, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[20:21], s[6:7]
	s_mul_i32 s36, s7, 24
	s_mul_hi_u32 s37, s6, 24
	s_mul_i32 s38, s6, 24
	s_and_saveexec_b32 s39, s2
	s_cbranch_execz .LBB3_452
; %bb.451:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s37, s36
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_452:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s39
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v12, s19
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[23:26], off offset:8
	global_store_b128 v[3:4], v[23:26], off offset:24
	global_store_b128 v[3:4], v[23:26], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_460
; %bb.453:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s20 :: v_dual_mov_b32 v81, s21
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s21, v4
	v_and_b32_e32 v3, s20, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB3_456
; %bb.454:                              ; %.preheader1.i.i.i80.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_455:                              ; %.preheader1.i.i.i80
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_455
.LBB3_456:                              ; %Flow1271
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_458
; %bb.457:                              ;   in Loop: Header=BB3_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB3_458:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB3_460
; %bb.459:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_460:                              ; %Flow1272
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s37, s37, s36
	v_add_co_u32 v3, vcc_lo, v21, s38
	v_add_co_ci_u32_e32 v4, vcc_lo, s37, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_461:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s2
	s_cbranch_execz .LBB3_463
; %bb.462:                              ;   in Loop: Header=BB3_461 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_463:                              ;   in Loop: Header=BB3_461 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_465
; %bb.464:                              ;   in Loop: Header=BB3_461 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_466
.LBB3_465:                              ;   in Loop: Header=BB3_461 Depth=5
	s_mov_b32 s5, -1
.LBB3_466:                              ; %Flow1266
                                        ;   in Loop: Header=BB3_461 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_461
; %bb.467:                              ;   in Loop: Header=BB3_378 Depth=4
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB3_471
; %bb.468:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s20
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v22, v19, v21 :: v_dual_cndmask_b32 v21, v18, v6
	v_and_b32_e32 v4, v22, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v21, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_471
; %bb.469:                              ; %.preheader.i.i.i79.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s2, 0
.LBB3_470:                              ; %.preheader.i.i.i79
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_470
.LBB3_471:                              ; %Flow1276
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
	s_mov_b32 s7, s3
.LBB3_472:                              ; %Flow1277
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, s7
.LBB3_473:                              ; %Flow1287
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s16, s3
.LBB3_474:                              ; %__ockl_devmem_request.exit83
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, 0
	s_cselect_b32 s5, -1, 0
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_493
; %bb.475:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s17, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_492
; %bb.476:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b64 v[3:4], v[50:51], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x7530, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_492
; %bb.477:                              ;   in Loop: Header=BB3_378 Depth=4
	v_sub_nc_u32_e32 v3, 0x7530, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB3_478:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x659
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB3_481
; %bb.479:                              ; %.preheader11.i
                                        ;   in Loop: Header=BB3_478 Depth=5
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB3_478
.LBB3_480:                              ; %.preheader9.i
                                        ;   in Loop: Header=BB3_481 Depth=5
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_481:                              ; %Flow1257
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x326
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB3_480
; %bb.482:                              ; %Flow1254
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB3_485
.LBB3_483:                              ; %.preheader7.i
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x18c
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB3_483
	s_branch .LBB3_485
.LBB3_484:                              ; %.preheader5.i
                                        ;   in Loop: Header=BB3_485 Depth=5
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_485:                              ; %.loopexit8.i
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0xc0
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB3_484
	s_branch .LBB3_487
.LBB3_486:                              ; %.preheader3.i
                                        ;   in Loop: Header=BB3_487 Depth=5
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_487:                              ; %Flow1248
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 0x59
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB3_486
	s_branch .LBB3_489
.LBB3_488:                              ; %.preheader1.i
                                        ;   in Loop: Header=BB3_489 Depth=5
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_489:                              ; %Flow1245
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s6, 38
	s_addc_u32 s19, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s18, s[2:3], s[18:19]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccz .LBB3_488
; %bb.490:                              ; %Flow1242
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_492
.LBB3_491:                              ; %.preheader.i
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_491
.LBB3_492:                              ; %__ockl_rtcwait_u32.exit
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
	s_cmp_lg_u32 s16, 2
	v_mov_b32_e32 v31, s4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v30, 0, 1, s2
.LBB3_493:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s18, 0
.LBB3_494:                              ; %Flow1309
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_502
; %bb.495:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_499
; %bb.496:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b64 v[23:24], v[52:53], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v23
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_u64_e32 vcc_lo, 0x4e1f, v[3:4]
	v_mov_b32_e32 v3, 1
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, vcc_lo
	s_cbranch_execz .LBB3_498
; %bb.497:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v21, s2 :: v_dual_mov_b32 v22, s3
	global_atomic_cmpswap_b64 v[3:4], v[52:53], v[21:24], off glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[3:4], v[23:24]
	v_mov_b32_e32 v4, s4
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
.LBB3_498:                              ; %Flow1236
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_499:                              ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_readfirstlane_b32 s2, v3
	v_readfirstlane_b32 s3, v4
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u64 s[2:3], 0
	s_cbranch_scc0 .LBB3_503
; %bb.500:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v16, s3 :: v_dual_mov_b32 v15, s2
.LBB3_501:                              ; %Flow1235
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v31, v16 :: v_dual_mov_b32 v30, v15
.LBB3_502:                              ; %Flow1312
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_xor_b32 s1, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_378
	s_branch .LBB3_618
.LBB3_503:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v15 :: v_dual_mov_b32 v4, v16
	s_and_saveexec_b32 s18, s1
	s_cbranch_execz .LBB3_539
; %bb.504:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x1
	global_load_b64 v[3:4], v5, s[12:13] glc
	global_load_b64 v[11:12], v5, s[14:15]
	s_waitcnt vmcnt(0)
	v_cmp_ge_u64_e32 vcc_lo, v[3:4], v[11:12]
	s_cbranch_vccnz .LBB3_508
; %bb.505:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s2, exec_lo
	s_mov_b32 s1, exec_lo
	v_mbcnt_lo_u32_b32 v6, s2, 0
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB3_507
; %bb.506:                              ;   in Loop: Header=BB3_378 Depth=4
	s_bcnt1_i32_b32 s2, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s2, 21
	v_mov_b32_e32 v4, s2
	global_atomic_add_u64 v[3:4], v5, v[4:5], s[12:13] glc
.LBB3_507:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s3, v4
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0x200000, v6, s[2:3]
	v_cmp_ge_u64_e64 s1, v[3:4], v[11:12]
	s_branch .LBB3_509
.LBB3_508:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr3_vgpr4
.LBB3_509:                              ; %Flow1233
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s19, s1
	s_cbranch_execz .LBB3_538
; %bb.510:                              ;   in Loop: Header=BB3_378 Depth=4
	s_load_b64 s[2:3], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s1, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_516
; %bb.511:                              ;   in Loop: Header=BB3_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[2:3] offset:40
	global_load_b64 v[18:19], v5, s[2:3]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB3_515
; %bb.512:                              ; %.preheader3.i.i.i89.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_513:                              ; %.preheader3.i.i.i89
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[2:3] offset:40
	global_load_b64 v[21:22], v5, s[2:3]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v18, v23
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v3, v12 :: v_dual_and_b32 v6, v19, v24
	v_mad_u64_u32 v[18:19], null, v6, 24, v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v12, v18
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_513
; %bb.514:                              ; %Flow1229
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_515:                              ; %Flow1231
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_516:                              ; %.loopexit4.i.i.i84
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[18:19], v5, s[2:3] offset:40
	global_load_b128 v[22:25], v5, s[2:3]
	v_readfirstlane_b32 s16, v11
	v_readfirstlane_b32 s17, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[16:17], s[6:7]
	s_mul_i32 s20, s7, 24
	s_mul_hi_u32 s21, s6, 24
	s_mul_i32 s35, s6, 24
	s_and_saveexec_b32 s36, s1
	s_cbranch_execz .LBB3_518
; %bb.517:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s21, s20
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v22, s35
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v23, vcc_lo
	global_store_b128 v[18:19], v[11:14], off offset:8
.LBB3_518:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s36
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v24, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v25, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v12, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v27, s7
	v_dual_mov_b32 v19, v5 :: v_dual_mov_b32 v26, s6
	v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v24, s4
	v_mov_b32_e32 v25, s5
	s_clause 0x3
	global_store_b128 v[11:12], v[18:21], off
	global_store_b128 v[11:12], v[24:27], off offset:16
	global_store_b128 v[11:12], v[24:27], off offset:32
	global_store_b128 v[11:12], v[24:27], off offset:48
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_526
; %bb.519:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[2:3] offset:32 glc
	global_load_b64 v[3:4], v5, s[2:3] offset:40
	s_mov_b32 s6, exec_lo
	v_dual_mov_b32 v80, s16 :: v_dual_mov_b32 v81, s17
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s17, v4
	v_and_b32_e32 v3, s16, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v22, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v23, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[26:27], v5, v[80:83], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[26:27], v[82:83]
	s_cbranch_execz .LBB3_522
; %bb.520:                              ; %.preheader1.i.i.i87.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_521:                              ; %.preheader1.i.i.i87
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v24, s16 :: v_dual_mov_b32 v25, s17
	s_sleep 1
	global_store_b64 v[3:4], v[26:27], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[24:27], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[26:27]
	v_dual_mov_b32 v27, v19 :: v_dual_mov_b32 v26, v18
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_521
.LBB3_522:                              ; %Flow1227
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[18:19], v5, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v3, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_524
; %bb.523:                              ;   in Loop: Header=BB3_378 Depth=4
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[18:19], v[4:5], off offset:8
.LBB3_524:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[24:25], v[18:19], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[24:25]
	s_cbranch_vccnz .LBB3_526
; %bb.525:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v4, v[18:19], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[24:25], v[4:5], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_526:                              ; %Flow1228
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s21, s21, s20
	v_add_co_u32 v3, vcc_lo, v22, s35
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_527:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_529
; %bb.528:                              ;   in Loop: Header=BB3_527 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_529:                              ;   in Loop: Header=BB3_527 Depth=5
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s5, v6
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB3_531
; %bb.530:                              ;   in Loop: Header=BB3_527 Depth=5
	s_mov_b32 s5, 0
	s_sleep 1
	s_branch .LBB3_532
.LBB3_531:                              ;   in Loop: Header=BB3_527 Depth=5
	s_mov_b32 s5, -1
.LBB3_532:                              ; %Flow1222
                                        ;   in Loop: Header=BB3_527 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB3_527
; %bb.533:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b64 v[3:4], v[11:12], off
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_537
; %bb.534:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x2
	global_load_b64 v[11:12], v5, s[2:3] offset:40
	global_load_b64 v[18:19], v5, s[2:3] offset:24 glc
	global_load_b64 v[23:24], v5, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v11, 1
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, v6, s16
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[21:22]
	v_dual_cndmask_b32 v22, v22, v25 :: v_dual_cndmask_b32 v21, v21, v6
	v_and_b32_e32 v6, v22, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v21, v11
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v11, 24
	v_mul_lo_u32 v11, v11, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v23, v11
	v_mov_b32_e32 v23, v18
	v_add_co_ci_u32_e32 v12, vcc_lo, v24, v6, vcc_lo
	v_mov_b32_e32 v24, v19
	global_store_b64 v[11:12], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_537
; %bb.535:                              ; %.preheader.i.i.i86.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s1, 0
.LBB3_536:                              ; %.preheader.i.i.i86
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[11:12], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v5, v[21:24], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[23:24]
	v_dual_mov_b32 v24, v19 :: v_dual_mov_b32 v23, v18
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_536
.LBB3_537:                              ; %Flow1220
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_538:                              ; %Flow1234
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s19
.LBB3_539:                              ; %__ockl_devmem_request.exit90
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s18
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v3
	v_readfirstlane_b32 s3, v4
	s_cmp_eq_u64 s[2:3], 0
	s_cbranch_scc1 .LBB3_584
; %bb.540:                              ;   in Loop: Header=BB3_378 Depth=4
	v_mbcnt_lo_u32_b32 v4, exec_lo, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b32 v6, v[38:39], off
	s_bcnt1_i32_b32 s5, exec_lo
	s_add_u32 s6, s2, 16
	s_addc_u32 s7, s3, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_lshrrev_b32_e32 v3, 5, v3
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s16, exec_lo, s1
	s_cbranch_execz .LBB3_548
; %bb.541:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v15, v[54:55], off
	s_mov_b32 s17, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB3_544
; %bb.542:                              ; %.preheader182.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s18, s5, 2
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB3_543:                              ; %.preheader182
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_add_nc_u32_e32 v16, s5, v16
	global_store_b32 v[11:12], v5, off
	v_add_co_u32 v11, s1, v11, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s1, 0, v12, s1
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB3_543
.LBB3_544:                              ; %Flow1209
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
	global_load_b32 v16, v[64:65], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, v15, v4, v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e64 v11, v6
	s_cbranch_execz .LBB3_547
; %bb.545:                              ; %.preheader180.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_mul_lo_u32 v12, v15, s5
	s_mov_b32 s17, 0
.LBB3_546:                              ; %.preheader180
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_lshlrev_b32_e64 v15, v11, 1
	v_lshrrev_b32_e32 v16, 3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v11, v12
	v_and_b32_e32 v16, 0x1ffffffc, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, v11, v6
	global_store_b32 v16, v15, s[6:7]
	s_or_b32 s17, vcc_lo, s17
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB3_546
.LBB3_547:                              ; %Flow1206
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_548:                              ; %Flow1214
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB3_553
; %bb.549:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s17, exec_lo
	v_cmpx_lt_u32_e64 v4, v3
	s_cbranch_execz .LBB3_552
; %bb.550:                              ; %.preheader178.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v15, v[66:67], off
	v_lshlrev_b64 v[11:12], 2, v[4:5]
	v_mov_b32_e32 v16, v4
	s_lshl_b32 s18, s5, 2
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB3_551:                              ; %.preheader178
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_add_nc_u32_e32 v16, s5, v16
	s_waitcnt vmcnt(0)
	global_store_b32 v[11:12], v15, off
	v_add_co_u32 v11, s1, v11, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v12, s1, 0, v12, s1
	v_cmp_ge_u32_e32 vcc_lo, v16, v3
	s_or_b32 s19, vcc_lo, s19
	s_and_not1_b32 exec_lo, exec_lo, s19
	s_cbranch_execnz .LBB3_551
.LBB3_552:                              ; %Flow1212
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s17
.LBB3_553:                              ; %.loopexit179
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s16
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB3_557
; %bb.554:                              ;   in Loop: Header=BB3_378 Depth=4
	v_and_b32_e32 v6, 31, v6
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v6
	s_cbranch_execz .LBB3_556
; %bb.555:                              ;   in Loop: Header=BB3_378 Depth=4
	v_add_nc_u32_e32 v4, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b32 v11, v[3:4], off
	s_waitcnt vmcnt(0)
	v_lshl_or_b32 v6, -1, v6, v11
	global_store_b32 v[3:4], v6, off
.LBB3_556:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s5
	global_store_b128 v5, v[7:10], s[2:3]
.LBB3_557:                              ; %Flow1203
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $sgpr5
.LBB3_558:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	;;#ASMSTART
	;;#ASMEND
	v_cmp_eq_u32_e64 s1, 0, v71
	v_mov_b32_e32 v3, s31
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB3_560
; %bb.559:                              ;   in Loop: Header=BB3_558 Depth=5
	global_load_b32 v3, v[32:33], off glc
.LBB3_560:                              ;   in Loop: Header=BB3_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v3
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s6, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s5, s5, s6
	s_cmp_eq_u32 s31, 0x10100
	s_cbranch_scc1 .LBB3_567
; %bb.561:                              ;   in Loop: Header=BB3_558 Depth=5
	v_mov_b32_e32 v3, s34
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB3_563
; %bb.562:                              ;   in Loop: Header=BB3_558 Depth=5
	global_load_b32 v3, v[48:49], off glc
.LBB3_563:                              ;   in Loop: Header=BB3_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s34, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_cmp_lg_u32 s31, s34
	s_cbranch_scc0 .LBB3_568
; %bb.564:                              ;   in Loop: Header=BB3_558 Depth=5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB3_575
; %bb.565:                              ;   in Loop: Header=BB3_558 Depth=5
	s_cmpk_lt_u32 s31, 0x100
	s_cbranch_scc0 .LBB3_569
; %bb.566:                              ;   in Loop: Header=BB3_558 Depth=5
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	s_mov_b32 s7, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s31, 24, v[3:4]
	s_branch .LBB3_570
.LBB3_567:                              ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b64 s[16:17], 0
	s_mov_b32 s1, -1
	s_mov_b32 s18, 0
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB3_580
.LBB3_568:                              ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b32 s18, -1
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
                                        ; implicit-def: $sgpr6_sgpr7
	s_branch .LBB3_579
.LBB3_569:                              ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b32 s7, -1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB3_570:                              ; %Flow1195
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB3_572
; %bb.571:                              ;   in Loop: Header=BB3_558 Depth=5
	s_add_i32 s7, s31, 0xffffff00
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s7, s7, 8
	s_add_u32 s16, s10, 0x2800
	s_addc_u32 s17, s11, 0
	v_mad_u64_u32 v[3:4], null, 0x1800, v7, s[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
	s_and_b32 s7, s31, 0xff
	global_load_b64 v[3:4], v[11:12], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[11:12], null, s7, 24, v[3:4]
.LBB3_572:                              ;   in Loop: Header=BB3_558 Depth=5
	v_dual_mov_b32 v15, s31 :: v_dual_mov_b32 v4, s3
	v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v6, v5
	global_store_b32 v5, v15, s[2:3] offset:4
	global_atomic_cmpswap_b64 v[3:4], v[11:12], v[3:6], off offset:8 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB3_574
; %bb.573:                              ;   in Loop: Header=BB3_558 Depth=5
	s_waitcnt_vscnt null, 0x0
	global_atomic_add_u32 v[32:33], v118, off
	v_dual_mov_b32 v3, v11 :: v_dual_mov_b32 v4, v12
.LBB3_574:                              ; %Flow1193
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_575:                              ; %Flow1196
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_readfirstlane_b32 s6, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v4
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB3_577
; %bb.576:                              ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b32 s19, -1
                                        ; implicit-def: $sgpr31
                                        ; implicit-def: $sgpr34
	s_branch .LBB3_578
.LBB3_577:                              ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b32 s19, 0
	s_and_not1_b32 s1, s1, exec_lo
	s_sleep 2
.LBB3_578:                              ; %Flow1201
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_mov_b32 s18, 0
.LBB3_579:                              ; %Flow1200
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s16, s1, exec_lo
	s_mov_b32 s1, 0
	s_or_b32 s5, s5, s16
                                        ; implicit-def: $sgpr16_sgpr17
.LBB3_580:                              ; %Flow1199
                                        ;   in Loop: Header=BB3_558 Depth=5
	s_and_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccz .LBB3_558
; %bb.581:                              ; %loop.exit.guard930
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v16, s17
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB3_501
; %bb.582:                              ; %loop.exit.guard931
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_xor_b32 s1, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB3_585
; %bb.583:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s18, 0
	s_branch .LBB3_586
.LBB3_584:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s18, 0
	s_branch .LBB3_501
.LBB3_585:                              ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr6_sgpr7
.LBB3_586:                              ; %Flow1190
                                        ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB3_501
; %bb.587:                              ;   in Loop: Header=BB3_378 Depth=4
	s_and_saveexec_b32 s20, s5
	s_cbranch_execz .LBB3_616
; %bb.588:                              ;   in Loop: Header=BB3_378 Depth=4
	s_load_b64 s[16:17], s[8:9], 0x50
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v4
	v_mov_b32_e32 v12, 0
	v_cmp_eq_u32_e64 s1, s1, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB3_594
; %bb.589:                              ;   in Loop: Header=BB3_378 Depth=4
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[23:24], v5, s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v5, s[16:17] offset:40
	global_load_b64 v[15:16], v5, s[16:17]
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v12, v24
	v_and_b32_e32 v6, v11, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v11, v6, 24
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v11, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v3, vcc_lo
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[11:12], v[23:24]
	s_cbranch_execz .LBB3_593
; %bb.590:                              ; %.preheader3.i.i.i96.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s7, 0
.LBB3_591:                              ; %.preheader3.i.i.i96
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b64 v[18:19], v5, s[16:17]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v15, v23
	v_and_b32_e32 v6, v16, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v3, 24, v[18:19]
	v_mov_b32_e32 v3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v6, 24, v[3:4]
	v_mov_b32_e32 v12, v15
	global_load_b64 v[21:22], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB3_591
; %bb.592:                              ; %Flow1186
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s7
.LBB3_593:                              ; %Flow1188
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_594:                              ; %.loopexit4.i.i.i91
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[15:16], v5, s[16:17] offset:40
	global_load_b128 v[21:24], v5, s[16:17]
	v_readfirstlane_b32 s18, v11
	v_readfirstlane_b32 s19, v12
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[18:19], s[6:7]
	s_mul_i32 s21, s7, 24
	s_mul_hi_u32 s31, s6, 24
	s_mul_i32 s34, s6, 24
	s_and_saveexec_b32 s35, s1
	s_cbranch_execz .LBB3_596
; %bb.595:                              ;   in Loop: Header=BB3_378 Depth=4
	v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, v5
	s_add_i32 s5, s31, s21
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v21, s34
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v22, vcc_lo
	global_store_b128 v[15:16], v[11:14], off offset:8
.LBB3_596:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[3:4], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v23, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v24, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v6, v3
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	v_dual_mov_b32 v12, s3 :: v_dual_mov_b32 v11, s2
	v_dual_mov_b32 v26, s7 :: v_dual_mov_b32 v25, s6
	v_dual_mov_b32 v24, s5 :: v_dual_mov_b32 v23, s4
	v_mov_b32_e32 v6, v5
	s_clause 0x4
	global_store_b64 v[3:4], v[11:12], off
	global_store_b128 v[3:4], v[23:26], off offset:8
	global_store_b128 v[3:4], v[23:26], off offset:24
	global_store_b128 v[3:4], v[23:26], off offset:40
	global_store_b64 v[3:4], v[5:6], off offset:56
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_604
; %bb.597:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x1
	global_load_b64 v[82:83], v5, s[16:17] offset:32 glc
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	s_mov_b32 s3, exec_lo
	v_dual_mov_b32 v80, s18 :: v_dual_mov_b32 v81, s19
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, s19, v4
	v_and_b32_e32 v3, s18, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v21, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v22, v4, vcc_lo
	global_store_b64 v[3:4], v[82:83], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[25:26], v5, v[80:83], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[25:26], v[82:83]
	s_cbranch_execz .LBB3_600
; %bb.598:                              ; %.preheader1.i.i.i94.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s5, 0
.LBB3_599:                              ; %.preheader1.i.i.i94
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v24, s19
	s_sleep 1
	global_store_b64 v[3:4], v[25:26], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[23:26], s[16:17] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[25:26]
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v25, v11
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_599
.LBB3_600:                              ; %Flow1184
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b64 v[11:12], v5, s[16:17] offset:16
	s_mov_b32 s5, exec_lo
	s_mov_b32 s3, exec_lo
	v_mbcnt_lo_u32_b32 v3, s5, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_602
; %bb.601:                              ;   in Loop: Header=BB3_378 Depth=4
	s_bcnt1_i32_b32 s5, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s5
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[11:12], v[4:5], off offset:8
.LBB3_602:                              ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	global_load_b64 v[15:16], v[11:12], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	s_cbranch_vccnz .LBB3_604
; %bb.603:                              ;   in Loop: Header=BB3_378 Depth=4
	global_load_b32 v4, v[11:12], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s3, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[15:16], v[4:5], off
	s_and_b32 m0, s3, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_604:                              ; %Flow1185
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s31, s31, s21
	v_add_co_u32 v3, vcc_lo, v21, s34
	v_add_co_ci_u32_e32 v4, vcc_lo, s31, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB3_605:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_607
; %bb.606:                              ;   in Loop: Header=BB3_605 Depth=5
	global_load_b32 v6, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB3_607:                              ;   in Loop: Header=BB3_605 Depth=5
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v6
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB3_609
; %bb.608:                              ;   in Loop: Header=BB3_605 Depth=5
	s_mov_b32 s2, 0
	s_sleep 1
	s_branch .LBB3_610
.LBB3_609:                              ;   in Loop: Header=BB3_605 Depth=5
	s_mov_b32 s2, -1
.LBB3_610:                              ; %Flow1179
                                        ;   in Loop: Header=BB3_605 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB3_605
; %bb.611:                              ;   in Loop: Header=BB3_378 Depth=4
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB3_615
; %bb.612:                              ;   in Loop: Header=BB3_378 Depth=4
	s_clause 0x2
	global_load_b64 v[3:4], v5, s[16:17] offset:40
	global_load_b64 v[11:12], v5, s[16:17] offset:24 glc
	global_load_b64 v[15:16], v5, s[16:17]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v6, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v4, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v23, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, v6, s18
	v_add_co_ci_u32_e32 v19, vcc_lo, s19, v21, vcc_lo
	v_mov_b32_e32 v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[18:19]
	v_dual_cndmask_b32 v22, v19, v21 :: v_dual_cndmask_b32 v21, v18, v6
	v_and_b32_e32 v4, v22, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v3, v21, v3
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v3, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v4, v6, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v15, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, v16, v4, vcc_lo
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[23:24], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[23:24], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_615
; %bb.613:                              ; %.preheader.i.i.i93.preheader
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_mov_b32 s1, 0
.LBB3_614:                              ; %.preheader.i.i.i93
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ;         Parent Loop BB3_378 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sleep 1
	global_store_b64 v[3:4], v[23:24], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v5, v[21:24], s[16:17] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[23:24]
	v_dual_mov_b32 v24, v12 :: v_dual_mov_b32 v23, v11
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB3_614
.LBB3_615:                              ; %Flow1177
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v71, 0
.LBB3_616:                              ; %Flow1189
                                        ;   in Loop: Header=BB3_378 Depth=4
	s_or_b32 exec_lo, exec_lo, s20
	v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v31
	s_mov_b32 s18, -1
	s_branch .LBB3_501
.LBB3_617:                              ;   in Loop: Header=BB3_347 Depth=3
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr29
                                        ; implicit-def: $vgpr70
	s_branch .LBB3_641
.LBB3_618:                              ;   in Loop: Header=BB3_347 Depth=3
	v_cmp_ne_u64_e64 s5, 1, v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_620
; %bb.619:                              ;   in Loop: Header=BB3_347 Depth=3
	v_dual_mov_b32 v28, v30 :: v_dual_mov_b32 v29, v31
	s_branch .LBB3_640
.LBB3_620:                              ;   in Loop: Header=BB3_347 Depth=3
	v_mbcnt_lo_u32_b32 v3, exec_lo, 0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB3_637
; %bb.621:                              ;   in Loop: Header=BB3_347 Depth=3
	global_load_b64 v[3:4], v[52:53], off glc
	s_sendmsg_rtn_b64 s[2:3], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_co_u32 v3, vcc_lo, s2, v3
	v_sub_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 0x4e20, v[3:4]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_637
; %bb.622:                              ;   in Loop: Header=BB3_347 Depth=3
	v_sub_nc_u32_e32 v3, 0x4e20, v3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	v_readfirstlane_b32 s2, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s6, s2
	s_addc_u32 s3, s7, s3
.LBB3_623:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x659
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_626
; %bb.624:                              ; %.preheader11.i110
                                        ;   in Loop: Header=BB3_623 Depth=4
	s_sleep 0x7f
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_branch .LBB3_623
.LBB3_625:                              ; %.preheader9.i109
                                        ;   in Loop: Header=BB3_626 Depth=4
	s_sleep 63
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_626:                              ; %Flow1171
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x326
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_625
; %bb.627:                              ; %Flow1168
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_add_u32 s16, s6, 0x18c
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_630
.LBB3_628:                              ; %.preheader7.i108
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 31
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x18c
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB3_628
	s_branch .LBB3_630
.LBB3_629:                              ; %.preheader5.i107
                                        ;   in Loop: Header=BB3_630 Depth=4
	s_sleep 15
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_630:                              ; %.loopexit8.i100
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0xc0
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_629
	s_branch .LBB3_632
.LBB3_631:                              ; %.preheader3.i106
                                        ;   in Loop: Header=BB3_632 Depth=4
	s_sleep 7
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_632:                              ; %Flow1162
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 0x59
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_631
	s_branch .LBB3_634
.LBB3_633:                              ; %.preheader1.i105
                                        ;   in Loop: Header=BB3_634 Depth=4
	s_sleep 3
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
.LBB3_634:                              ; %Flow1159
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, 38
	s_addc_u32 s17, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e64 s16, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccz .LBB3_633
; %bb.635:                              ; %Flow1156
                                        ;   in Loop: Header=BB3_347 Depth=3
	v_cmp_le_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_637
.LBB3_636:                              ; %.preheader.i104
                                        ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ;       Parent Loop BB3_347 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_sendmsg_rtn_b64 s[6:7], sendmsg(MSG_RTN_GET_REALTIME)
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e64 s6, s[2:3], s[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_636
.LBB3_637:                              ; %__ockl_rtcwait_u32.exit111
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, s29
	s_mov_b32 s1, exec_lo
	v_cmpx_eq_u32_e32 0, v70
	s_cbranch_execz .LBB3_639
; %bb.638:                              ;   in Loop: Header=BB3_347 Depth=3
	global_load_b32 v3, v[32:33], off glc
.LBB3_639:                              ;   in Loop: Header=BB3_347 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s29, v3
.LBB3_640:                              ; %Flow1173
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v11, v28 :: v_dual_mov_b32 v12, v29
.LBB3_641:                              ; %Flow1318
                                        ;   in Loop: Header=BB3_347 Depth=3
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB3_347
.LBB3_642:                              ; %.loopexit189
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v11
	v_readfirstlane_b32 s7, v12
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc1 .LBB3_663
; %bb.643:                              ;   in Loop: Header=BB3_6 Depth=2
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mbcnt_lo_u32_b32 v3, s5, 0
	;;#ASMSTART
	;;#ASMEND
	global_load_b64 v[0:1], v5, s[6:7] offset:8 glc
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_waitcnt vmcnt(0)
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s2, v4
	v_mov_b32_e32 v4, 0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB3_647
; %bb.644:                              ;   in Loop: Header=BB3_6 Depth=2
	s_mov_b32 s17, exec_lo
	s_bcnt1_i32_b32 s5, s5
	v_mbcnt_lo_u32_b32 v4, s17, 0
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB3_646
; %bb.645:                              ;   in Loop: Header=BB3_6 Depth=2
	s_bcnt1_i32_b32 s1, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s5, s1
	v_mov_b32_e32 v6, s1
	global_atomic_add_u32 v6, v[0:1], v6, off offset:8 glc
.LBB3_646:                              ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u32_u24 v4, s5, v4, s1
.LBB3_647:                              ; %Flow944
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s3, s4
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+4
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+12
	s_lshl_b64 s[16:17], s[2:3], 5
	v_mov_b32_e32 v11, 0
	s_add_u32 s18, s16, s18
	s_addc_u32 s19, s17, s19
	v_readfirstlane_b32 s1, v4
	s_load_b32 s5, s[18:19], 0x0
	v_mov_b32_e32 v12, 0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s5, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s3, 32
	s_cbranch_scc1 .LBB3_657
; %bb.648:                              ;   in Loop: Header=BB3_6 Depth=2
	v_cvt_f32_u32_e32 v4, s5
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+32
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+40
	s_lshr_b32 s3, s3, 5
	s_add_u32 s18, s16, s18
	s_addc_u32 s19, s17, s19
	v_rcp_iflag_f32_e32 v4, v4
	s_load_b32 s18, s[18:19], 0x0
	s_sub_i32 s19, 0, s5
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_add_nc_u32 v3, s1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v6, s19, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v3, s18, v3
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, __unnamed_1@rel32@lo+16
	s_addc_u32 s19, s19, __unnamed_1@rel32@hi+24
	s_add_u32 s16, s16, s18
	s_addc_u32 s17, s17, s19
	s_lshr_b32 s18, s2, 1
	s_add_i32 s19, s3, -1
	s_add_i32 s18, s18, 4
	v_mul_hi_u32 v6, v4, v6
	s_lshl_b32 s18, 1, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v4, v6
	v_cvt_f32_u32_e32 v6, s3
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v6, v6
	v_mul_lo_u32 v4, v4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v3, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v6
	v_subrev_nc_u32_e32 v6, s5, v3
	v_cmp_le_u32_e64 s1, s5, v3
	v_cvt_u32_f32_e32 v15, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v3, v6, s1
	s_sub_i32 s1, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v11, s1, v15
	v_add_co_u32 v3, s1, v0, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v6, s1, 0, v1, s1
	v_subrev_nc_u32_e32 v12, s5, v4
	v_cmp_le_u32_e64 s1, s5, v4
	s_mov_b32 s5, 0
	v_mul_hi_u32 v16, v15, v11
	v_cndmask_b32_e64 v4, v4, v12, s1
	v_mov_b32_e32 v11, 0
	s_bfe_i32 s1, s2, 0x10000
	s_lshr_b32 s2, s18, 1
	v_mov_b32_e32 v12, 0
	v_lshrrev_b32_e32 v4, 5, v4
	v_add_nc_u32_e32 v18, v15, v16
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s18, s1, s18
.LBB3_649:                              ;   Parent Loop BB3_3 Depth=1
                                        ;     Parent Loop BB3_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[15:16], 2, v[4:5]
	s_mov_b32 s2, -1
	s_mov_b32 s20, exec_lo
                                        ; implicit-def: $vgpr19
	v_add_co_u32 v15, s1, v3, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, s1, v6, v16, s1
	global_load_b32 v21, v[15:16], off glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e32 -1, v21
	s_cbranch_execz .LBB3_653
; %bb.650:                              ;   in Loop: Header=BB3_649 Depth=3
	v_not_b32_e32 v19, v21
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ctz_i32_b32_e32 v19, v19
	v_min_u32_e32 v21, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e64 v19, v21, 1
	global_atomic_or_b32 v15, v[15:16], v19, off glc
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v15, v15, v19
	v_mov_b32_e32 v19, 0
	v_cmp_ne_u32_e64 s1, 0, v15
	v_cmpx_eq_u32_e32 0, v15
	s_cbranch_execz .LBB3_652
; %bb.651:                              ;   in Loop: Header=BB3_649 Depth=3
	s_load_b32 s2, s[16:17], 0x0
	v_lshl_add_u32 v11, v4, 5, v21
	v_mov_b32_e32 v19, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v11, s18
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, s2, v0, s2
	v_add_co_ci_u32_e64 v15, s2, 0, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v11, s2, v12, v11
	v_add_co_ci_u32_e64 v12, s2, 0, v15, s2
.LBB3_652:                              ;   in Loop: Header=BB3_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_not1_b32 s2, s1, exec_lo
.LBB3_653:                              ; %Flow941
                                        ;   in Loop: Header=BB3_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	s_and_saveexec_b32 s20, s2
; %bb.654:                              ;   in Loop: Header=BB3_649 Depth=3
	v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, v4, v18
	v_mul_lo_u32 v15, v15, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v15
	v_subrev_nc_u32_e32 v15, s3, v4
	v_cmp_le_u32_e64 s1, s3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v15, s1
	v_subrev_nc_u32_e32 v15, s3, v4
	v_cmp_le_u32_e64 s1, s3, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v15, s1
; %bb.655:                              ;   in Loop: Header=BB3_649 Depth=3
	s_or_b32 exec_lo, exec_lo, s20
	v_cmp_ne_u32_e64 s1, 0, v19
	s_cmp_eq_u32 s19, 0
	s_cselect_b32 s2, -1, 0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s1, s1, s2
	s_and_b32 s1, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s1, s5
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB3_649
; %bb.656:                              ; %Flow942
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_657:                              ; %.loopexit193
                                        ;   in Loop: Header=BB3_6 Depth=2
	v_cmp_ne_u64_e64 s1, 0, v[11:12]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_660
; %bb.658:                              ;   in Loop: Header=BB3_6 Depth=2
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s3, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s5, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s5
	s_cbranch_execz .LBB3_660
; %bb.659:                              ;   in Loop: Header=BB3_6 Depth=2
	s_bcnt1_i32_b32 s1, s1
	s_bcnt1_i32_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s1, s1, s3
	v_mov_b32_e32 v0, s1
	global_atomic_add_u32 v5, v0, s[6:7] offset:16
.LBB3_660:                              ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u64_e32 0, v[11:12]
; %bb.661:                              ;   in Loop: Header=BB3_6 Depth=2
	v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v119, 0
	v_dual_mov_b32 v128, 0 :: v_dual_mov_b32 v1, v12
; %bb.662:                              ; %Flow
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v128 :: v_dual_mov_b32 v4, v119
.LBB3_663:                              ; %Flow945
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v119, v4
.LBB3_664:                              ; %Flow1324
                                        ;   in Loop: Header=BB3_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v3
	;;#ASMSTART
	;;#ASMEND
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB3_6
.LBB3_665:                              ; %Flow1326
                                        ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	v_mov_b32_e32 v3, v119
.LBB3_666:                              ; %.loopexit197
                                        ;   in Loop: Header=BB3_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v4, v3
	;;#ASMSTART
	;;#ASMEND
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB3_3
; %bb.667:                              ; %Flow1328
                                        ; implicit-def: $vgpr4_vgpr5
.LBB3_668:                              ; %Flow1347
	s_and_not1_saveexec_b32 s1, s23
	s_cbranch_execz .LBB3_701
; %bb.669:
	s_load_b64 s[2:3], s[8:9], 0x50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB3_675
; %bb.670:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[6:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v8
	v_and_b32_e32 v1, v1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v10, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[8:9]
	s_cbranch_execz .LBB3_674
; %bb.671:                              ; %.preheader3.i.i.i.preheader
	s_mov_b32 s6, 0
.LBB3_672:                              ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[6:7], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v6, v6, v8
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v6, 24, v[10:11]
	v_and_b32_e32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v10, 24, v[1:2]
	v_mov_b32_e32 v1, v6
	global_load_b64 v[6:7], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[6:9], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB3_672
; %bb.673:                              ; %Flow1343
	s_or_b32 exec_lo, exec_lo, s6
.LBB3_674:                              ; %Flow1345
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB3_675:                              ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s13, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[6:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s10, s7, 24
	s_mul_hi_u32 s11, s6, 24
	s_mul_i32 s12, s6, 24
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB3_677
; %bb.676:
	v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, v3
	s_add_i32 s13, s11, s10
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v7, vcc_lo
	v_dual_mov_b32 v12, 3 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB3_677:
	s_or_b32 exec_lo, exec_lo, s14
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v8, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v0
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
	v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_685
; %bb.678:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v10, s[2:3] offset:40
	v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v4, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v1, vcc_lo
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB3_681
; %bb.679:                              ; %.preheader1.i.i.i.preheader
	s_mov_b32 s13, 0
.LBB3_680:                              ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB3_680
.LBB3_681:                              ; %Flow1341
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s13, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s13, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB3_683
; %bb.682:
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s13
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB3_683:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB3_685
; %bb.684:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_685:                              ; %Flow1342
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s11, s11, s10
	v_add_co_u32 v0, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_686:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_688
; %bb.687:                              ;   in Loop: Header=BB3_686 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB3_688:                              ;   in Loop: Header=BB3_686 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB3_690
; %bb.689:                              ;   in Loop: Header=BB3_686 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB3_691
.LBB3_690:                              ;   in Loop: Header=BB3_686 Depth=1
	s_mov_b32 s6, -1
.LBB3_691:                              ; %Flow1336
                                        ;   in Loop: Header=BB3_686 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB3_686
; %bb.692:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB3_696
; %bb.693:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[2:3] offset:40
	global_load_b64 v[9:10], v8, s[2:3] offset:24 glc
	global_load_b64 v[6:7], v8, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_696
; %bb.694:                              ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB3_695:                              ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB3_695
.LBB3_696:                              ; %__ockl_devmem_request.exit
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB3_700
; %bb.697:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v2, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB3_700
; %bb.698:
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v2, s3, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_and_b32 s4, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s4
	s_cbranch_execz .LBB3_700
; %bb.699:
	s_load_b64 s[4:5], s[8:9], 0x60
	s_bcnt1_i32_b32 s2, s2
	s_bcnt1_i32_b32 s3, s3
	v_mov_b32_e32 v4, 0x1a000
	s_mul_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s2
	s_waitcnt lgkmcnt(0)
	global_atomic_add_u64 v4, v[2:3], s[4:5] offset:2184
.LBB3_700:
	s_or_b32 exec_lo, exec_lo, s0
.LBB3_701:                              ; %Flow1348
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB3_702:                              ; %.loopexit198
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_readlane_b32 s30, v40, 11
	v_readlane_b32 s31, v40, 12
	v_readlane_b32 s44, v40, 10
	v_readlane_b32 s43, v40, 9
	v_readlane_b32 s42, v40, 8
	v_readlane_b32 s41, v40, 7
	v_readlane_b32 s40, v40, 6
	v_readlane_b32 s39, v40, 5
	v_readlane_b32 s38, v40, 4
	v_readlane_b32 s37, v40, 3
	v_readlane_b32 s36, v40, 2
	v_readlane_b32 s35, v40, 1
	v_readlane_b32 s34, v40, 0
	s_or_saveexec_b32 s0, -1
	scratch_load_b32 v40, off, s32          ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end3:
	.size	__ockl_dm_alloc, .Lfunc_end3-__ockl_dm_alloc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 24288
; NumSgprs: 47
; NumVgprs: 136
; ScratchSize: 8
; MemoryBound: 1
	.text
	.p2align	2                               ; -- Begin function _Z8chechalliPbiiiPiS0_S0_iiPS0_
	.type	_Z8chechalliPbiiiPiS0_S0_iiPS0_,@function
_Z8chechalliPbiiiPiS0_S0_iiPS0_:        ; @_Z8chechalliPbiiiPiS0_S0_iiPS0_
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_mov_b32 s0, s33
	s_mov_b32 s33, s32
	s_or_saveexec_b32 s1, -1
	scratch_store_b32 off, v89, s33 offset:100 ; 4-byte Folded Spill
	s_mov_b32 exec_lo, s1
	v_writelane_b32 v89, s0, 16
	s_addk_i32 s32, 0x70
	s_clause 0x18
	scratch_store_b32 off, v40, s33 offset:96
	; meta instruction
	scratch_store_b32 off, v41, s33 offset:92
	; meta instruction
	scratch_store_b32 off, v42, s33 offset:88
	; meta instruction
	scratch_store_b32 off, v43, s33 offset:84
	; meta instruction
	scratch_store_b32 off, v44, s33 offset:80
	; meta instruction
	scratch_store_b32 off, v45, s33 offset:76
	; meta instruction
	scratch_store_b32 off, v46, s33 offset:72
	; meta instruction
	scratch_store_b32 off, v47, s33 offset:68
	; meta instruction
	scratch_store_b32 off, v56, s33 offset:64
	; meta instruction
	scratch_store_b32 off, v57, s33 offset:60
	; meta instruction
	scratch_store_b32 off, v58, s33 offset:56
	; meta instruction
	scratch_store_b32 off, v59, s33 offset:52
	; meta instruction
	scratch_store_b32 off, v60, s33 offset:48
	; meta instruction
	scratch_store_b32 off, v61, s33 offset:44
	; meta instruction
	scratch_store_b32 off, v62, s33 offset:40
	; meta instruction
	scratch_store_b32 off, v63, s33 offset:36
	; meta instruction
	scratch_store_b32 off, v72, s33 offset:32
	; meta instruction
	scratch_store_b32 off, v73, s33 offset:28
	; meta instruction
	scratch_store_b32 off, v74, s33 offset:24
	; meta instruction
	scratch_store_b32 off, v75, s33 offset:20
	; meta instruction
	scratch_store_b32 off, v76, s33 offset:16
	; meta instruction
	scratch_store_b32 off, v77, s33 offset:12
	; meta instruction
	scratch_store_b32 off, v78, s33 offset:8
	; meta instruction
	scratch_store_b32 off, v79, s33 offset:4
	; meta instruction
	scratch_store_b32 off, v88, s33
	v_writelane_b32 v89, s34, 0
	v_writelane_b32 v89, s35, 1
	v_writelane_b32 v89, s36, 2
	v_writelane_b32 v89, s37, 3
	v_writelane_b32 v89, s38, 4
	v_writelane_b32 v89, s39, 5
	v_writelane_b32 v89, s40, 6
	v_writelane_b32 v89, s41, 7
	v_writelane_b32 v89, s42, 8
	v_writelane_b32 v89, s43, 9
	v_writelane_b32 v89, s44, 10
	v_writelane_b32 v89, s45, 11
	v_writelane_b32 v89, s46, 12
	v_writelane_b32 v89, s47, 13
	v_writelane_b32 v89, s30, 14
	v_writelane_b32 v89, s31, 15
	v_dual_mov_b32 v63, v12 :: v_dual_mov_b32 v46, v10
	v_dual_mov_b32 v45, v9 :: v_dual_mov_b32 v42, v0
	v_dual_mov_b32 v62, v6 :: v_dual_mov_b32 v57, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v0, v63, v3
	v_dual_mov_b32 v59, v15 :: v_dual_mov_b32 v44, v8
	v_ashrrev_i32_e32 v43, 31, v42
	v_dual_mov_b32 v47, v11 :: v_dual_mov_b32 v72, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v1, 31, v0
	v_mov_b32_e32 v56, v5
	v_mov_b32_e32 v40, v4
	v_lshlrev_b64 v[4:5], 2, v[42:43]
	v_dual_mov_b32 v60, v14 :: v_dual_mov_b32 v61, v7
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mov_b32_e32 v58, v2
	v_sub_nc_u32_e32 v2, v72, v63
	s_mov_b32 s2, 0
                                        ; implicit-def: $sgpr1
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v44, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v45, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, -4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
	flat_load_b32 v0, v[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v46, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v47, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, v46, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v47, v5, vcc_lo
	s_clause 0x1
	flat_load_b32 v0, v[0:1]
	flat_load_b32 v1, v[4:5]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_lt_i32_e64 s34, v0, v1
	v_cmp_ge_i32_e32 vcc_lo, v0, v1
	v_cmpx_ne_u32_e64 v2, v3
	s_xor_b32 s35, exec_lo, s3
	s_cbranch_execz .LBB4_18
; %bb.1:
                                        ; implicit-def: $sgpr37
                                        ; implicit-def: $sgpr36
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s38, exec_lo, s0
	s_cbranch_execz .LBB4_3
; %bb.2:
	v_dual_mov_b32 v0, v42 :: v_dual_add_nc_u32 v3, 1, v3
	v_dual_mov_b32 v1, v57 :: v_dual_mov_b32 v2, v58
	v_dual_mov_b32 v4, v40 :: v_dual_mov_b32 v7, v61
	v_dual_mov_b32 v5, v56 :: v_dual_mov_b32 v6, v62
	v_dual_mov_b32 v8, v44 :: v_dual_mov_b32 v9, v45
	v_dual_mov_b32 v10, v46 :: v_dual_mov_b32 v11, v47
	v_dual_mov_b32 v12, v63 :: v_dual_mov_b32 v13, v72
	v_dual_mov_b32 v14, v60 :: v_dual_mov_b32 v15, v59
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@lo+4
	s_addc_u32 s1, s1, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_and_b32_e32 v0, 1, v0
	s_mov_b32 s36, 0
                                        ; implicit-def: $vgpr42
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr40
                                        ; implicit-def: $vgpr56
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr63
                                        ; implicit-def: $vgpr72
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr59
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr46_vgpr47
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
                                        ; implicit-def: $vgpr0
	s_and_b32 s37, vcc_lo, exec_lo
.LBB4_3:                                ; %Flow107
	s_and_not1_saveexec_b32 s38, s38
	s_cbranch_execz .LBB4_17
; %bb.4:                                ; %.preheader88
	s_mov_b32 s0, -1
	s_mov_b32 s39, exec_lo
                                        ; implicit-def: $sgpr1
	v_cmpx_lt_i32_e64 v40, v56
	s_cbranch_execz .LBB4_16
; %bb.5:                                ; %.lr.ph
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v41, 31, v40
	v_dual_mov_b32 v88, v40 :: v_dual_add_nc_u32 v43, 1, v3
	v_mov_b32_e32 v79, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[40:41]
	v_mov_b32_e32 v41, 1
	s_mov_b32 s40, 0
                                        ; implicit-def: $sgpr41
                                        ; implicit-def: $sgpr42
                                        ; implicit-def: $sgpr43
                                        ; implicit-def: $sgpr44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v73, vcc_lo, v60, v0
	v_add_co_ci_u32_e32 v74, vcc_lo, v59, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v75, vcc_lo, v62, v2
	v_add_co_ci_u32_e32 v76, vcc_lo, v61, v3, vcc_lo
.LBB4_6:                                ; =>This Inner Loop Header: Depth=1
	flat_load_b32 v0, v[75:76]
	s_mov_b32 s46, exec_lo
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v77, vcc_lo, v57, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v78, vcc_lo, v58, v1, vcc_lo
	flat_load_u8 v2, v[77:78]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u16_e64 s45, 0, v2
	v_cmpx_eq_u16_e32 0, v2
	s_cbranch_execz .LBB4_12
; %bb.7:                                ;   in Loop: Header=BB4_6 Depth=1
	flat_load_b64 v[2:3], v[73:74]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_mov_b32 s2, -1
	s_mov_b32 s47, exec_lo
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $sgpr1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
	flat_load_b32 v0, v[0:1]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB4_11
; %bb.8:                                ;   in Loop: Header=BB4_6 Depth=1
	v_dual_mov_b32 v0, v42 :: v_dual_mov_b32 v1, v57
	v_dual_mov_b32 v2, v58 :: v_dual_mov_b32 v3, v43
	v_dual_mov_b32 v4, v40 :: v_dual_mov_b32 v7, v61
	v_dual_mov_b32 v5, v56 :: v_dual_mov_b32 v6, v62
	v_dual_mov_b32 v8, v44 :: v_dual_mov_b32 v9, v45
	v_dual_mov_b32 v10, v46 :: v_dual_mov_b32 v11, v47
	v_dual_mov_b32 v12, v63 :: v_dual_mov_b32 v13, v72
	v_dual_mov_b32 v14, v60 :: v_dual_mov_b32 v15, v59
	flat_store_b8 v[77:78], v41
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@lo+4
	s_addc_u32 s1, s1, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_and_b32_e32 v0, 1, v0
	s_mov_b32 s0, 0
	s_mov_b32 s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	s_xor_b32 s3, vcc_lo, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB4_10
; %bb.9:                                ;   in Loop: Header=BB4_6 Depth=1
	s_mov_b32 s2, exec_lo
	flat_store_b8 v[77:78], v79
.LBB4_10:                               ; %Flow103
                                        ;   in Loop: Header=BB4_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, -1
	s_or_not1_b32 s2, s2, exec_lo
.LBB4_11:                               ; %Flow102
                                        ;   in Loop: Header=BB4_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s47
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s45, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s45, s3, s2
.LBB4_12:                               ; %Flow
                                        ;   in Loop: Header=BB4_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s46
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s44, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_and_not1_b32 s4, s43, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_mov_b32 s2, -1
	s_or_b32 s44, s3, s0
	s_or_b32 s43, s4, s1
	s_and_saveexec_b32 s1, s45
; %bb.13:                               ;   in Loop: Header=BB4_6 Depth=1
	v_add_nc_u32_e32 v88, 1, v88
	v_add_co_u32 v75, s0, v75, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v76, s0, 0, v76, s0
	v_cmp_ge_i32_e32 vcc_lo, v88, v56
	s_or_b32 s44, s44, exec_lo
	s_or_b32 s43, s43, exec_lo
	s_or_not1_b32 s2, vcc_lo, exec_lo
; %bb.14:                               ; %Flow104
                                        ;   in Loop: Header=BB4_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s2
	s_or_b32 s40, s0, s40
	s_and_not1_b32 s0, s42, exec_lo
	s_and_b32 s1, s44, exec_lo
	s_and_not1_b32 s2, s41, exec_lo
	s_and_b32 s3, s43, exec_lo
	s_or_b32 s42, s0, s1
	s_or_b32 s41, s2, s3
	s_and_not1_b32 exec_lo, exec_lo, s40
	s_cbranch_execnz .LBB4_6
; %bb.15:                               ; %Flow105
	s_or_b32 exec_lo, exec_lo, s40
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s42, exec_lo
	s_and_b32 s1, s41, exec_lo
.LBB4_16:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s39
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s37, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_and_not1_b32 s3, s36, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s37, s2, s1
	s_or_b32 s36, s3, s0
.LBB4_17:                               ; %.loopexit89
	s_or_b32 exec_lo, exec_lo, s38
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s37, exec_lo
	s_and_b32 s2, s36, exec_lo
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr57
                                        ; implicit-def: $vgpr58
                                        ; implicit-def: $vgpr40
                                        ; implicit-def: $vgpr56
                                        ; implicit-def: $vgpr62
                                        ; implicit-def: $vgpr61
                                        ; implicit-def: $vgpr60
                                        ; implicit-def: $vgpr59
.LBB4_18:                               ; %Flow111
	s_and_not1_saveexec_b32 s3, s35
	s_cbranch_execz .LBB4_30
; %bb.19:
	s_mov_b32 s5, -1
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s4, s34
	s_cbranch_execz .LBB4_29
; %bb.20:                               ; %.preheader
	s_mov_b32 s0, -1
	s_mov_b32 s6, -1
	s_mov_b32 s5, exec_lo
	v_cmpx_lt_i32_e64 v40, v56
	s_cbranch_execz .LBB4_28
; %bb.21:                               ; %.lr.ph96
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v41, 31, v40
	s_mov_b32 s6, 0
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v60, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v59, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v62, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, v61, v3, vcc_lo
.LBB4_22:                               ; =>This Inner Loop Header: Depth=1
	flat_load_b32 v4, v[2:3]
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $sgpr9
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v6, vcc_lo, v57, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v58, v5, vcc_lo
	flat_load_u8 v6, v[6:7]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_ne_u16_e64 s0, 0, v6
	v_cmpx_eq_u16_e32 0, v6
	s_cbranch_execz .LBB4_24
; %bb.23:                               ;   in Loop: Header=BB4_22 Depth=1
	flat_load_b64 v[6:7], v[0:1]
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_and_not1_b32 s0, s0, exec_lo
	s_mov_b32 s9, -1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
	flat_load_b32 v4, v[4:5]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
.LBB4_24:                               ; %Flow108
                                        ;   in Loop: Header=BB4_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_mov_b32 s11, -1
	s_mov_b32 s12, s9
	s_and_saveexec_b32 s10, s0
; %bb.25:                               ;   in Loop: Header=BB4_22 Depth=1
	v_add_nc_u32_e32 v40, 1, v40
	v_add_co_u32 v2, s0, v2, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	v_cmp_ge_i32_e32 vcc_lo, v40, v56
	s_and_not1_b32 s12, s9, exec_lo
	s_or_not1_b32 s11, vcc_lo, exec_lo
; %bb.26:                               ; %Flow109
                                        ;   in Loop: Header=BB4_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_xor_b32 s0, s12, -1
	s_and_b32 s10, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s6, s10, s6
	s_and_not1_b32 s8, s8, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s9, s9, exec_lo
	s_or_b32 s8, s8, s0
	s_or_b32 s7, s7, s9
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB4_22
; %bb.27:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s6, s7, exec_lo
	s_or_not1_b32 s0, s8, exec_lo
.LBB4_28:                               ; %Flow114
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s7, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_not1_b32 s5, s6, exec_lo
	s_or_b32 s0, s7, s0
.LBB4_29:                               ; %Flow113
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s4, s5, exec_lo
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s1, s1, s4
	s_or_b32 s2, s2, s0
.LBB4_30:                               ; %Flow112
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s0, s2
; %bb.31:                               ; %.loopexit
	s_and_not1_b32 s1, s1, exec_lo
; %bb.32:                               ; %.loopexit87
	s_or_b32 exec_lo, exec_lo, s0
	s_clause 0x18
	scratch_load_b32 v88, off, s33
	scratch_load_b32 v79, off, s33 offset:4
	scratch_load_b32 v78, off, s33 offset:8
	scratch_load_b32 v77, off, s33 offset:12
	scratch_load_b32 v76, off, s33 offset:16
	scratch_load_b32 v75, off, s33 offset:20
	scratch_load_b32 v74, off, s33 offset:24
	scratch_load_b32 v73, off, s33 offset:28
	scratch_load_b32 v72, off, s33 offset:32
	scratch_load_b32 v63, off, s33 offset:36
	scratch_load_b32 v62, off, s33 offset:40
	scratch_load_b32 v61, off, s33 offset:44
	scratch_load_b32 v60, off, s33 offset:48
	scratch_load_b32 v59, off, s33 offset:52
	scratch_load_b32 v58, off, s33 offset:56
	scratch_load_b32 v57, off, s33 offset:60
	scratch_load_b32 v56, off, s33 offset:64
	scratch_load_b32 v47, off, s33 offset:68
	scratch_load_b32 v46, off, s33 offset:72
	scratch_load_b32 v45, off, s33 offset:76
	scratch_load_b32 v44, off, s33 offset:80
	scratch_load_b32 v43, off, s33 offset:84
	scratch_load_b32 v42, off, s33 offset:88
	scratch_load_b32 v41, off, s33 offset:92
	scratch_load_b32 v40, off, s33 offset:96
	v_readlane_b32 s30, v89, 14
	v_cndmask_b32_e64 v0, 0, 1, s1
	v_readlane_b32 s31, v89, 15
	v_readlane_b32 s47, v89, 13
	v_readlane_b32 s46, v89, 12
	v_readlane_b32 s45, v89, 11
	v_readlane_b32 s44, v89, 10
	v_readlane_b32 s43, v89, 9
	v_readlane_b32 s42, v89, 8
	v_readlane_b32 s41, v89, 7
	v_readlane_b32 s40, v89, 6
	v_readlane_b32 s39, v89, 5
	v_readlane_b32 s38, v89, 4
	v_readlane_b32 s37, v89, 3
	v_readlane_b32 s36, v89, 2
	v_readlane_b32 s35, v89, 1
	v_readlane_b32 s34, v89, 0
	v_readlane_b32 s0, v89, 16
	s_or_saveexec_b32 s1, -1
	scratch_load_b32 v89, off, s33 offset:100 ; 4-byte Folded Reload
	s_mov_b32 exec_lo, s1
	s_addk_i32 s32, 0xff90
	s_mov_b32 s33, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end4:
	.size	_Z8chechalliPbiiiPiS0_S0_iiPS0_, .Lfunc_end4-_Z8chechalliPbiiiPiS0_S0_iiPS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2164
; NumSgprs: 50
; NumVgprs: 90
; ScratchSize: 112
; MemoryBound: 0
	.section	.text.unlikely.,"ax",@progbits
	.p2align	2                               ; -- Begin function __ockl_dm_dealloc
	.type	__ockl_dm_dealloc,@function
__ockl_dm_dealloc:                      ; @__ockl_dm_dealloc
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0xfff, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u64_e32 0, v[2:3]
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB5_12
; %bb.1:
	v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v4, 0xffe00000, v0
	s_load_b64 s[0:1], s[8:9], 0x60
	v_and_b32_e32 v15, 0x1fffff, v0
	global_load_b64 v[6:7], v[4:5], off
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 0x2800
	s_addc_u32 s1, s1, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __unnamed_1@rel32@lo+16
	s_addc_u32 s3, s3, __unnamed_1@rel32@hi+24
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v1, 1, v6
	v_bfe_i32 v2, v6, 0, 1
	v_and_b32_e32 v16, 0xff, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 4, v1
	v_lshlrev_b32_e64 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v8, 1, v1
	v_and_b32_e32 v2, v2, v8
	v_add_nc_u32_e32 v8, 0xffffff00, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, v2, v1
	v_mov_b32_e32 v2, v6
	v_lshrrev_b32_e32 v18, 8, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_u32_e32 v1, v14
	v_sub_nc_u32_e32 v0, 0, v14
	v_lshlrev_b64 v[12:13], 5, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_add_co_u32 v12, vcc_lo, v12, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v0, v17
	v_mad_u64_u32 v[0:1], null, 0x1800, v6, s[0:1]
	v_cmp_gt_u32_e64 s0, 0x100, v7
	v_mul_hi_u32 v2, v17, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v7, 24, v[0:1]
	v_mad_u64_u32 v[10:11], null, v18, 24, v[0:1]
	v_dual_mov_b32 v17, 1 :: v_dual_add_nc_u32 v2, v17, v2
.LBB5_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v0, v17
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	v_mov_b32_e32 v17, 0
	;;#ASMSTART
	;;#ASMEND
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB5_11
; %bb.3:                                ;   in Loop: Header=BB5_2 Depth=1
	v_readfirstlane_b32 s1, v6
	v_readfirstlane_b32 s2, v7
	v_mov_b32_e32 v17, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, s1, v6
	v_cmp_eq_u32_e64 s1, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s6, s1
	s_cbranch_execz .LBB5_10
; %bb.4:                                ;   in Loop: Header=BB5_2 Depth=1
	s_mov_b32 s7, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s7, 0
	v_cmp_ne_u32_e64 s1, 0, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, v9, 0, s1
	v_cndmask_b32_e64 v0, v8, 0, s1
	s_or_b32 s1, s1, s0
	s_xor_b32 s2, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB5_6
; %bb.5:                                ;   in Loop: Header=BB5_2 Depth=1
	global_load_b64 v[17:18], v[10:11], off glc
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v16, 24, v[17:18]
.LBB5_6:                                ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b32 v17, v[12:13], off
	v_readfirstlane_b32 s2, v0
	v_readfirstlane_b32 s3, v1
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v17, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, v17, v2
	v_mul_lo_u32 v19, v18, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, v17, v19
	v_add_nc_u32_e32 v19, 1, v18
	v_sub_nc_u32_e32 v20, v17, v14
	v_cmp_ge_u32_e64 s1, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v19, s1
	v_cndmask_b32_e64 v17, v17, v20, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v19, 1, v18
	v_cmp_ge_u32_e64 s1, v17, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v18, v19, s1
	v_lshrrev_b32_e32 v18, 3, v17
	v_lshlrev_b32_e64 v17, v17, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v18, 0x1ffffffc, v18
	v_not_b32_e32 v19, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s1, v4, v18
	v_add_co_ci_u32_e64 v18, s1, 0, v5, s1
	global_atomic_and_b32 v[17:18], v19, off offset:16
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB5_9
; %bb.7:                                ;   in Loop: Header=BB5_2 Depth=1
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s10, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s11, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s11
	s_cbranch_execz .LBB5_9
; %bb.8:                                ;   in Loop: Header=BB5_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s10
	v_mov_b32_e32 v0, s7
	global_atomic_sub_u32 v3, v0, s[2:3] offset:16
.LBB5_9:                                ; %Flow16
                                        ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v17, 0
.LBB5_10:                               ; %Flow18
                                        ;   in Loop: Header=BB5_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB5_11:                               ;   in Loop: Header=BB5_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_mov_b32_e32 v0, v17
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
                                        ; implicit-def: $vgpr0_vgpr1
	s_cbranch_vccnz .LBB5_2
.LBB5_12:                               ; %Flow40
	s_and_not1_saveexec_b32 s1, s4
	s_cbranch_execz .LBB5_45
; %bb.13:
	s_mov_b32 s10, exec_lo
	v_cmpx_ne_u64_e32 0, v[0:1]
	s_cbranch_execz .LBB5_44
; %bb.14:
	s_load_b64 s[2:3], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s0, v2
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB5_20
; %bb.15:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB5_19
; %bb.16:                               ; %.preheader3.i.i.i.preheader
	s_mov_b32 s6, 0
.LBB5_17:                               ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB5_17
; %bb.18:                               ; %Flow34
	s_or_b32 exec_lo, exec_lo, s6
.LBB5_19:                               ; %Flow36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB5_20:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s14, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s11, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s13, s6, 24
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB5_22
; %bb.21:
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, v3
	s_add_i32 s14, s12, s11
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v13, vcc_lo, s14, v5, vcc_lo
	v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB5_22:
	s_or_b32 exec_lo, exec_lo, s15
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, v8
	s_mov_b32 s17, s16
	s_mov_b32 s18, s16
	s_mov_b32 s19, s16
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v9, s19
	v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v8, s18
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB5_30
; %bb.23:
	v_mov_b32_e32 v8, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	v_dual_mov_b32 v9, s4 :: v_dual_mov_b32 v10, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, s5, v1
	v_and_b32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v2, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v2, v1
	v_add_co_u32 v6, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v5, v1, vcc_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB5_26
; %bb.24:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s14, 0
.LBB5_25:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB5_25
.LBB5_26:                               ; %Flow32
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s14, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s14, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB5_28
; %bb.27:
	s_bcnt1_i32_b32 s14, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s14
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB5_28:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB5_30
; %bb.29:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB5_30:                               ; %Flow33
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s12, s12, s11
	v_add_co_u32 v0, vcc_lo, v4, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB5_31:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB5_33
; %bb.32:                               ;   in Loop: Header=BB5_31 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB5_33:                               ;   in Loop: Header=BB5_31 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v2
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB5_35
; %bb.34:                               ;   in Loop: Header=BB5_31 Depth=1
	s_mov_b32 s6, 0
	s_sleep 1
	s_branch .LBB5_36
.LBB5_35:                               ;   in Loop: Header=BB5_31 Depth=1
	s_mov_b32 s6, -1
.LBB5_36:                               ; %Flow27
                                        ;   in Loop: Header=BB5_31 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccnz .LBB5_31
; %bb.37:
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB5_41
; %bb.38:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB5_41
; %bb.39:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB5_40:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB5_40
.LBB5_41:                               ; %__ockl_devmem_request.exit
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_mbcnt_lo_u32_b32 v0, s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s2, exec_lo, vcc_lo
	s_mov_b32 exec_lo, s2
	s_cbranch_execz .LBB5_44
; %bb.42:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB5_44
; %bb.43:
	s_load_b64 s[4:5], s[8:9], 0x60
	s_bcnt1_i32_b32 s0, s0
	s_bcnt1_i32_b32 s2, s2
	v_mov_b32_e32 v2, 0x1a000
	s_mul_i32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
	s_waitcnt lgkmcnt(0)
	global_atomic_sub_u64 v2, v[0:1], s[4:5] offset:2184
.LBB5_44:                               ; %Flow38
	s_or_b32 exec_lo, exec_lo, s10
.LBB5_45:                               ; %.loopexit
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end5:
	.size	__ockl_dm_dealloc, .Lfunc_end5-__ockl_dm_dealloc
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2296
; NumSgprs: 34
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z7findcvsiPiS_S_S_S_S_PS_ ; -- Begin function _Z7findcvsiPiS_S_S_S_S_PS_
	.globl	_Z7findcvsiPiS_S_S_S_S_PS_
	.p2align	8
	.type	_Z7findcvsiPiS_S_S_S_S_PS_,@function
_Z7findcvsiPiS_S_S_S_S_PS_:             ; @_Z7findcvsiPiS_S_S_S_S_PS_
; %bb.0:
	s_mov_b64 s[48:49], s[0:1]
	s_load_b32 s0, s[0:1], 0x44
	s_clause 0x1
	s_load_b256 s[52:59], s[48:49], 0x8
	s_load_b32 s1, s[48:49], 0x4c
	v_and_b32_e32 v1, 0x3ff, v0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s14
	s_load_b32 s0, s[54:55], 0x0
	s_and_b32 s3, s1, 0xffff
	s_add_i32 s2, s2, s15
	s_lshr_b32 s1, s1, 16
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s1, v[3:4]
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s0, v0
	s_cbranch_execz .LBB6_2
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b32 s46, s[48:49], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[42:43], 2, v[0:1]
	v_add_co_u32 v44, vcc_lo, s52, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v45, vcc_lo, s53, v43, vcc_lo
	global_load_b64 v[0:1], v[44:45], off
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s47, s46, 31
	s_lshl_b64 s[52:53], s[46:47], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s58, s58, s52
	s_addc_u32 s59, s59, s53
	s_load_b64 s[2:3], s[58:59], 0x0
	s_clause 0x1
	s_load_b128 s[60:63], s[48:49], 0x28
	s_load_b64 s[50:51], s[48:49], 0x38
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s1, s3, s2
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_i32_e32 vcc_lo, s1, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execnz .LBB6_3
.LBB6_2:
	s_endpgm
.LBB6_3:
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_add_u32 s8, s48, 64
	s_addc_u32 s9, s49, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, __ockl_dm_alloc@rel32@lo+4
	s_addc_u32 s3, s3, __ockl_dm_alloc@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_swappc_b64 s[30:31], s[2:3]
	v_dual_mov_b32 v40, v0 :: v_dual_mov_b32 v41, v1
	v_mov_b32_e32 v4, 0
	v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41
	global_load_b32 v2, v4, s[54:55]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[2:3]
	s_cbranch_vccnz .LBB6_5
.LBB6_4:                                ; %.lr.ph.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v2, vcc_lo, v2, -4
	v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
	v_add_co_u32 v0, s0, v0, 4
	v_cmp_lt_u64_e32 vcc_lo, 3, v[2:3]
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	s_cbranch_vccnz .LBB6_4
.LBB6_5:                                ; %NodeBlock77
	v_cmp_gt_i64_e32 vcc_lo, 2, v[2:3]
	s_cbranch_vccnz .LBB6_11
; %bb.6:                                ; %NodeBlock
	v_cmp_lt_i64_e32 vcc_lo, 2, v[2:3]
	s_mov_b32 s0, -1
	s_cbranch_vccz .LBB6_9
; %bb.7:                                ; %LeafBlock75
	v_cmp_eq_u64_e32 vcc_lo, 3, v[2:3]
	s_mov_b32 s0, 0
	s_cbranch_vccz .LBB6_9
; %bb.8:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s0, -1
	global_store_b8 v[0:1], v4, off offset:2
.LBB6_9:                                ; %Flow79
	s_mov_b32 s1, 0
	s_and_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_cbranch_vccz .LBB6_12
; %bb.10:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s0, -1
	global_store_b8 v[0:1], v4, off offset:1
	s_branch .LBB6_12
.LBB6_11:
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
.LBB6_12:                               ; %Flow
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB6_14
; %bb.13:                               ; %LeafBlock
	v_cmp_eq_u64_e64 s0, 1, v[2:3]
.LBB6_14:                               ; %Flow82
	s_delay_alu instid0(VALU_DEP_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_16
; %bb.15:
	v_mov_b32_e32 v2, 0
	global_store_b8 v[0:1], v2, off
.LBB6_16:                               ; %_ZL6memsetPvim.exit
	v_dual_mov_b32 v46, 0 :: v_dual_mov_b32 v1, v40
	v_dual_mov_b32 v0, s46 :: v_dual_mov_b32 v7, s57
	global_load_b64 v[4:5], v[44:45], off
	global_load_b64 v[12:13], v46, s[58:59]
	v_dual_mov_b32 v44, 1 :: v_dual_mov_b32 v3, 1
	v_dual_mov_b32 v2, v41 :: v_dual_mov_b32 v9, s61
	v_dual_mov_b32 v6, s56 :: v_dual_mov_b32 v11, s63
	v_dual_mov_b32 v8, s60 :: v_dual_mov_b32 v15, s51
	v_mov_b32_e32 v10, s62
	v_mov_b32_e32 v14, s50
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@lo+4
	s_addc_u32 s1, s1, _Z8chechalliPbiiiPiS0_S0_iiPS0_@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_and_b32_e32 v0, 1, v0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 1, v0
	s_cbranch_execz .LBB6_18
; %bb.17:
	s_add_u32 s2, s62, s52
	s_addc_u32 s3, s63, s53
	global_load_b32 v0, v46, s[2:3]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s50, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s51, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v0, v42
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v43, vcc_lo
	flat_store_b32 v[0:1], v44
.LBB6_18:
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41
	s_add_u32 s8, s48, 64
	s_addc_u32 s9, s49, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, __ockl_dm_dealloc@rel32@lo+4
	s_addc_u32 s1, s1, __ockl_dm_dealloc@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7findcvsiPiS_S_S_S_S_PS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 112
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 1
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 136
		.amdhsa_next_free_sgpr 64
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z7findcvsiPiS_S_S_S_S_PS_, .Lfunc_end6-_Z7findcvsiPiS_S_S_S_S_PS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 788
; NumSgprs: 66
; NumVgprs: 136
; ScratchSize: 112
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 66
; NumVGPRsForWavesPerEU: 136
; Occupancy: 10
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9puttolistPiS_S_      ; -- Begin function _Z9puttolistPiS_S_
	.globl	_Z9puttolistPiS_S_
	.p2align	8
	.type	_Z9puttolistPiS_S_,@function
_Z9puttolistPiS_S_:                     ; @_Z9puttolistPiS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x24
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s14
	s_load_b32 s4, s[4:5], 0x0
	s_and_b32 s5, s3, 0xffff
	s_add_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_lshr_b32 s2, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB7_3
; %bb.1:
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, v1, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB7_3
; %bb.2:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB7_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9puttolistPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z9puttolistPiS_S_, .Lfunc_end7-_Z9puttolistPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9checkpermPbPiS0_S0_S0_S0_S0_ ; -- Begin function _Z9checkpermPbPiS0_S0_S0_S0_S0_
	.globl	_Z9checkpermPbPiS0_S0_S0_S0_S0_
	.p2align	8
	.type	_Z9checkpermPbPiS0_S0_S0_S0_S0_,@function
_Z9checkpermPbPiS0_S0_S0_S0_S0_:        ; @_Z9checkpermPbPiS0_S0_S0_S0_S0_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x44
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s14
	s_load_b32 s8, s[8:9], 0x0
	s_and_b32 s9, s3, 0xffff
	s_add_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s9, v[1:2]
	v_bfe_u32 v3, v0, 10, 10
	s_lshr_b32 s2, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s8, v0
	s_cbranch_execz .LBB8_14
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x20
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v3, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB8_14
; %bb.2:                                ; %.lr.ph44
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s0, -1
	s_mov_b32 s1, exec_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v2, v3
	s_cbranch_execz .LBB8_12
; %bb.3:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v5, 31, v2
	v_mov_b32_e32 v4, v2
	v_mov_b32_e32 v6, v0
	s_mov_b32 s2, 0
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
.LBB8_4:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_5 Depth 2
	v_ashrrev_i32_e32 v7, 31, v6
	v_mov_b32_e32 v9, v2
	s_mov_b32 s12, 0
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_add_co_u32 v7, vcc_lo, s10, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v0, v[7:8], off
	v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v7, v4
.LBB8_5:                                ;   Parent Loop BB8_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v10, v[7:8], off
	s_or_b32 s14, s14, exec_lo
	s_or_b32 s15, s15, exec_lo
	s_mov_b32 s16, exec_lo
                                        ; implicit-def: $sgpr0
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v0, v10
; %bb.6:                                ;   in Loop: Header=BB8_5 Depth=2
	v_add_nc_u32_e32 v9, 1, v9
	v_add_co_u32 v7, s0, v7, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	v_cmp_ge_i32_e32 vcc_lo, v9, v3
	s_and_not1_b32 s15, s15, exec_lo
	s_mov_b32 s0, -1
	s_and_not1_b32 s14, s14, exec_lo
	s_and_b32 s17, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s15, s15, s17
; %bb.7:                                ; %Flow
                                        ;   in Loop: Header=BB8_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s16, exec_lo, s15
	s_or_b32 s12, s16, s12
	s_and_not1_b32 s9, s9, exec_lo
	s_and_b32 s16, s14, exec_lo
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s9, s9, s16
	s_or_b32 s13, s13, s0
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB8_5
; %bb.8:                                ; %loop.exit.guard68
                                        ;   in Loop: Header=BB8_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s8, s8, exec_lo
	s_and_b32 s12, s13, exec_lo
	s_mov_b32 s0, -1
	s_or_b32 s8, s8, s12
	s_and_saveexec_b32 s12, s9
	s_xor_b32 s9, exec_lo, s12
; %bb.9:                                ;   in Loop: Header=BB8_4 Depth=1
	v_add_nc_u32_e32 v6, 1, v6
	s_and_not1_b32 s8, s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v6, v1
	s_or_not1_b32 s0, vcc_lo, exec_lo
; %bb.10:                               ; %Flow69
                                        ;   in Loop: Header=BB8_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s0
	s_or_b32 s2, s0, s2
	s_and_not1_b32 s0, s3, exec_lo
	s_and_b32 s3, s8, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s0, s3
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB8_4
; %bb.11:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s3, exec_lo
.LBB8_12:                               ; %Flow70
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB8_14
; %bb.13:                               ; %.critedge
	v_mov_b32_e32 v0, 0
	global_store_b8 v0, v0, s[4:5]
.LBB8_14:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9checkpermPbPiS0_S0_S0_S0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z9checkpermPbPiS0_S0_S0_S0_S0_, .Lfunc_end8-_Z9checkpermPbPiS0_S0_S0_S0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 696
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z7findallPiS_S_S_S_S_S_S_PS_S_ ; -- Begin function _Z7findallPiS_S_S_S_S_S_S_PS_S_
	.globl	_Z7findallPiS_S_S_S_S_S_S_PS_S_
	.p2align	8
	.type	_Z7findallPiS_S_S_S_S_S_S_PS_S_,@function
_Z7findallPiS_S_S_S_S_S_S_PS_S_:        ; @_Z7findallPiS_S_S_S_S_S_S_PS_S_
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x50
	s_load_b64 s[4:5], s[0:1], 0x5c
	s_load_b512 s[16:31], s[0:1], 0x0
	v_bfe_u32 v1, v0, 20, 10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_lshr_b32 s6, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_load_b32 s12, s[22:23], 0x0
	s_mul_i32 s6, s6, s4
	s_and_b32 s5, s5, 0xffff
	v_mul_lo_u32 v5, s6, v1
	s_add_i32 s3, s3, s14
	v_mad_u32_u24 v4, v0, s4, v2
	s_mul_i32 s2, s3, s2
	s_mul_i32 s3, s6, s5
	s_load_b128 s[4:7], s[0:1], 0x40
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v4, v5
	v_add_co_ci_u32_e64 v1, null, 0, 0, s0
	s_mul_i32 s13, s2, s3
	s_mul_hi_u32 s1, s2, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, s13
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s12, 0
	s_cselect_b32 s14, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_cmp_lt_i32 s12, 1
	s_cbranch_scc1 .LBB9_3
; %bb.1:
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_mov_b64 s[2:3], s[20:21]
	s_mov_b32 s15, s12
.LBB9_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s8, s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v3
	v_add_co_u32 v2, vcc_lo, v2, v10
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v12, v2, v10
	v_xor_b32_e32 v11, v3, v10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[8:9], 2
	s_add_u32 s8, s6, s8
	s_addc_u32 s9, s7, s9
	s_load_b32 s0, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s8, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s10, s0, s8
	s_mov_b32 s9, s8
	s_addc_u32 s11, s8, s8
	s_xor_b64 s[10:11], s[10:11], s[8:9]
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v2, s10
	v_cvt_f32_u32_e32 v3, s11
	s_sub_u32 s0, 0, s10
	s_subb_u32 s9, 0, s11
	s_add_i32 s15, s15, -1
	s_add_u32 s2, s2, 4
	v_fmac_f32_e32 v2, 0x4f800000, v3
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s15, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x5f7ffffc, v2
	v_mul_f32_e32 v3, 0x2f800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v3, v3
	v_fmac_f32_e32 v2, 0xcf800000, v3
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v2, v2
	v_mul_lo_u32 v6, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, s0, v2
	v_mul_lo_u32 v9, s9, v2
	v_mul_lo_u32 v8, s0, v2
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v7, v2, v8
	v_mul_hi_u32 v13, v3, v8
	v_mul_lo_u32 v8, v3, v8
	v_add_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v9, v2, v6
	v_mul_hi_u32 v14, v2, v6
	v_mul_hi_u32 v15, v3, v6
	v_mul_lo_u32 v6, v3, v6
	v_add_co_u32 v7, vcc_lo, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v14, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v9, v13, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v6, vcc_lo, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
	v_mul_hi_u32 v7, s0, v2
	v_mul_lo_u32 v8, s9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, s0, v3
	v_mul_lo_u32 v6, s0, v2
	v_add_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v13, v3, v6
	v_mul_lo_u32 v14, v3, v6
	v_mul_hi_u32 v6, v2, v6
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, v2, v7
	v_mul_hi_u32 v9, v2, v7
	v_mul_hi_u32 v15, v3, v7
	v_mul_lo_u32 v7, v3, v7
	v_add_co_u32 v6, vcc_lo, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v8, v13, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v6, vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v3, v7, vcc_lo
	v_mul_hi_u32 v14, v12, v6
	v_mad_u64_u32 v[2:3], null, v11, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, v12, v13, 0
	v_mad_u64_u32 v[8:9], null, v11, v13, 0
	v_add_co_u32 v6, vcc_lo, v14, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v7, v3, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v8, s11, v6
	v_mad_u64_u32 v[2:3], null, s10, v6, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v14, s10, v7
	v_add_co_u32 v9, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v13, s0, v6, 2
	v_sub_co_u32 v2, vcc_lo, v12, v2
	v_add3_u32 v3, v3, v14, v8
	v_add_co_ci_u32_e64 v15, s0, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v11, v3
	v_subrev_co_ci_u32_e64 v8, s0, s11, v8, vcc_lo
	v_sub_co_ci_u32_e32 v3, vcc_lo, v11, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v2
	v_sub_co_u32 v12, s0, v2, s10
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v8, vcc_lo, 0, v8, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s10, v12
	v_cmp_le_u32_e64 s0, s11, v8
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, 0, -1, s0
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v8
	v_cndmask_b32_e32 v8, v12, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v14, v2, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_xor_b32_e32 v8, s8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 0, v2
	v_dual_cndmask_b32 v3, v16, v15 :: v_dual_cndmask_b32 v2, v9, v13
	v_cndmask_b32_e64 v3, v7, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v6, v2, s0
	v_xor_b32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v8
	v_sub_co_u32 v2, vcc_lo, v2, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v8, vcc_lo
	s_cbranch_scc1 .LBB9_2
.LBB9_3:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u64_e32 0, v[2:3]
	s_cbranch_execz .LBB9_26
; %bb.4:
	v_mov_b32_e32 v7, s12
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_ashr_i32 s8, s12, 31
	s_cbranch_vccnz .LBB9_7
; %bb.5:                                ; %.lr.ph100.preheader
	v_add_co_u32 v2, s0, s13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	s_mov_b32 s9, 0
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_mul_lo_u32 v6, v4, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s12
	v_mad_u64_u32 v[2:3], null, v4, s12, 0
	v_add3_u32 v3, v3, v6, v5
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, v1
	v_mov_b32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
.LBB9_6:                                ; %.lr.ph100
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v6, s[20:21]
	v_ashrrev_i32_e32 v13, 31, v5
	s_add_i32 s9, s9, 1
	s_add_u32 s20, s20, 4
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[7:8]
	v_add_co_u32 v9, vcc_lo, s6, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v13
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
	global_load_b32 v11, v[9:10], off
	v_xor_b32_e32 v15, v4, v13
	v_xor_b32_e32 v14, v5, v13
	v_lshlrev_b64 v[4:5], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v4
	v_readfirstlane_b32 s1, v5
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v11, v4
	v_add_co_ci_u32_e32 v7, vcc_lo, v4, v4, vcc_lo
	v_xor_b32_e32 v16, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v17, v7, v4
	v_cvt_f32_u32_e32 v4, v16
	v_sub_co_u32 v7, vcc_lo, 0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v17
	v_sub_co_ci_u32_e32 v8, vcc_lo, 0, v17, vcc_lo
	v_fmac_f32_e32 v4, 0x4f800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x5f7ffffc, v4
	v_mul_f32_e32 v5, 0x2f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v5, v5
	v_fmac_f32_e32 v4, 0xcf800000, v5
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v11, v7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v12, v7, v4
	v_mul_lo_u32 v19, v8, v4
	v_mul_lo_u32 v18, v7, v4
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v12, v4, v18
	v_mul_hi_u32 v20, v5, v18
	v_mul_lo_u32 v18, v5, v18
	v_add_nc_u32_e32 v11, v11, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v19, v4, v11
	v_mul_hi_u32 v21, v4, v11
	v_mul_hi_u32 v22, v5, v11
	v_mul_lo_u32 v11, v5, v11
	v_add_co_u32 v12, vcc_lo, v12, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v12, vcc_lo, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v19, v20, vcc_lo
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v22, vcc_lo
	v_add_co_u32 v11, vcc_lo, v12, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v12, vcc_lo
	v_mul_lo_u32 v11, v7, v4
	v_mul_hi_u32 v12, v7, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, v7, v5
	v_mul_lo_u32 v8, v8, v4
	v_mul_hi_u32 v18, v5, v11
	v_mul_lo_u32 v19, v5, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v12, v7
	v_mul_hi_u32 v11, v4, v11
	v_add_nc_u32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, v4, v7
	v_mul_hi_u32 v12, v4, v7
	v_mul_hi_u32 v20, v5, v7
	v_mul_lo_u32 v7, v5, v7
	v_add_co_u32 v8, vcc_lo, v11, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v11, v18, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v7, vcc_lo, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v7, vcc_lo, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, v5, v8, vcc_lo
	v_mul_hi_u32 v19, v15, v7
	v_mad_u64_u32 v[4:5], null, v14, v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, v15, v18, 0
	v_mad_u64_u32 v[11:12], null, v14, v18, 0
	v_add_co_u32 v7, vcc_lo, v19, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v5, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v7, vcc_lo, v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v11, v17, v7
	v_mad_u64_u32 v[4:5], null, v16, v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v16, v8
	v_sub_co_u32 v4, vcc_lo, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v7, v11
	v_sub_nc_u32_e32 v7, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v7, s0, v7, v17, vcc_lo
	v_sub_co_ci_u32_e32 v5, vcc_lo, v14, v5, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v4, v16
	v_sub_co_u32 v8, s0, v4, v16
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v12, vcc_lo, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v8, v16
	v_cmp_ge_u32_e64 s1, v12, v17
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_sub_co_ci_u32_e64 v7, vcc_lo, v7, v17, s0
	v_sub_co_u32 v16, vcc_lo, v8, v16
	v_cmp_ge_u32_e64 s0, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_cndmask_b32_e64 v20, 0, -1, s1
	v_cmp_eq_u32_e32 vcc_lo, v12, v17
	v_cndmask_b32_e64 v19, 0, -1, s0
	v_cmp_eq_u32_e64 s0, v5, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v20, v18, vcc_lo
	v_cndmask_b32_e64 v11, v19, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	v_cmp_ne_u32_e64 s0, 0, v11
	v_cndmask_b32_e32 v8, v8, v16, vcc_lo
	v_cndmask_b32_e32 v7, v12, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v8, s0
	v_cndmask_b32_e64 v5, v5, v7, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v13
	v_xor_b32_e32 v5, v5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v4, vcc_lo, v4, v13
	v_sub_co_ci_u32_e32 v5, vcc_lo, v5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v4, off
	global_load_b32 v4, v[9:10], off
	global_load_b32 v7, v6, s[22:23]
	v_add_co_u32 v2, s0, v2, 4
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v12, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, v12, v12, vcc_lo
	v_xor_b32_e32 v16, v4, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v17, v5, v12
	v_cvt_f32_u32_e32 v4, v16
	v_sub_co_u32 v8, vcc_lo, 0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v17
	v_sub_co_ci_u32_e32 v9, vcc_lo, 0, v17, vcc_lo
	v_fmac_f32_e32 v4, 0x4f800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x5f7ffffc, v4
	v_mul_f32_e32 v5, 0x2f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v5, v5
	v_fmac_f32_e32 v4, 0xcf800000, v5
	v_cvt_u32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v10, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, v8, v4
	v_mul_lo_u32 v19, v9, v4
	v_mul_lo_u32 v18, v8, v4
	v_add_nc_u32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v11, v4, v18
	v_mul_hi_u32 v20, v5, v18
	v_mul_lo_u32 v18, v5, v18
	v_add_nc_u32_e32 v10, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v19, v4, v10
	v_mul_hi_u32 v21, v4, v10
	v_mul_hi_u32 v22, v5, v10
	v_mul_lo_u32 v10, v5, v10
	v_add_co_u32 v11, vcc_lo, v11, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v11, vcc_lo, v11, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v19, v20, vcc_lo
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v22, vcc_lo
	v_add_co_u32 v10, vcc_lo, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v11, vcc_lo
	v_mul_lo_u32 v10, v8, v4
	v_mul_hi_u32 v11, v8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, v8, v5
	v_mul_lo_u32 v9, v9, v4
	v_mul_hi_u32 v18, v5, v10
	v_mul_lo_u32 v19, v5, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v11, v8
	v_mul_hi_u32 v10, v4, v10
	v_add_nc_u32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v9, v4, v8
	v_mul_hi_u32 v11, v4, v8
	v_mul_hi_u32 v20, v5, v8
	v_mul_lo_u32 v8, v5, v8
	v_add_co_u32 v9, vcc_lo, v10, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v10, v18, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v8, vcc_lo, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v8, vcc_lo, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, v5, v9, vcc_lo
	v_mul_hi_u32 v19, v15, v8
	v_mad_u64_u32 v[4:5], null, v14, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, v15, v18, 0
	v_mad_u64_u32 v[10:11], null, v14, v18, 0
	v_add_co_u32 v8, vcc_lo, v19, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v9, v5, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v10, v17, v8
	v_mad_u64_u32 v[4:5], null, v16, v8, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v19, v16, v9
	v_add_co_u32 v11, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v21, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v18, s1, v8, 2
	v_sub_co_u32 v4, vcc_lo, v15, v4
	v_add3_u32 v5, v5, v19, v10
	v_add_co_ci_u32_e64 v20, s1, 0, v9, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v14, v5
	v_sub_co_ci_u32_e64 v10, s1, v10, v17, vcc_lo
	v_sub_co_ci_u32_e32 v5, vcc_lo, v14, v5, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v4, v16
	v_sub_co_u32 v15, s1, v4, v16
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v10, vcc_lo, 0, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v15, v16
	v_cmp_ge_u32_e64 s1, v10, v17
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, 0, -1, s1
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v10, v17
	v_cndmask_b32_e32 v10, v15, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v5, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v16, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_xor_b32_e32 v10, v13, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s1, 0, v4
	v_dual_cndmask_b32 v5, v21, v20 :: v_dual_cndmask_b32 v4, v11, v18
	v_add_co_ci_u32_e64 v3, vcc_lo, 0, v3, s0
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s9, v7
	v_cndmask_b32_e64 v5, v9, v5, s1
	v_cndmask_b32_e64 v4, v8, v4, s1
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v10
	v_xor_b32_e32 v4, v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_u32 v4, s0, v4, v10
	v_sub_co_ci_u32_e64 v5, s0, v5, v10, s0
	s_cbranch_vccz .LBB9_6
.LBB9_7:                                ; %Flow190
	v_mul_lo_u32 v4, v1, s12
	v_mul_lo_u32 v5, v0, s8
	v_mad_u64_u32 v[2:3], null, v0, s12, 0
	v_max_i32_e32 v10, 0, v7
	v_mov_b32_e32 v13, 0
	s_mov_b32 s3, exec_lo
	s_mov_b32 s8, 0
	s_mov_b32 s4, 0
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $sgpr11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v3, v3, v5, v4
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s16, v2
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v3, vcc_lo
.LBB9_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB9_11 Depth 2
                                        ;       Child Loop BB9_13 Depth 3
	v_cmp_eq_u32_e32 vcc_lo, s4, v10
	s_mov_b32 s0, -1
	s_and_not1_b32 s11, s11, exec_lo
	s_or_b32 s5, s5, exec_lo
	s_cbranch_vccnz .LBB9_22
; %bb.9:                                ;   in Loop: Header=BB9_8 Depth=1
	s_mov_b32 s5, 0
	s_mov_b32 s11, s3
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_u32 s6, s26, s0
	s_addc_u32 s7, s27, s1
	global_load_b64 v[2:3], v13, s[6:7]
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	v_cmp_ge_i32_e32 vcc_lo, s6, v3
	s_cbranch_vccnz .LBB9_21
; %bb.10:                               ; %.lr.ph113
                                        ;   in Loop: Header=BB9_8 Depth=1
	v_add_co_u32 v4, vcc_lo, v11, s0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v12, vcc_lo
	s_mov_b32 s12, 0
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr14
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s28, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s29, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v7, 31, v4
	v_mov_b32_e32 v6, v4
	v_cmp_ge_i32_e32 vcc_lo, v4, v5
	v_cmp_lt_i32_e64 s0, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, s1, s30, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s1, s31, v7, s1
.LBB9_11:                               ;   Parent Loop BB9_8 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB9_13 Depth 3
	s_and_not1_b32 s1, s15, exec_lo
	s_and_b32 s2, vcc_lo, exec_lo
	s_and_not1_b32 s14, s14, exec_lo
	s_or_b32 s15, s1, s2
	s_or_b32 s13, s13, exec_lo
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB9_19
; %bb.12:                               ; %.lr.ph105.preheader
                                        ;   in Loop: Header=BB9_11 Depth=2
	s_ashr_i32 s7, s6, 31
	v_mov_b32_e32 v14, v4
	s_lshl_b64 s[20:21], s[6:7], 2
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s24, s20
	s_addc_u32 s21, s25, s21
	global_load_b32 v8, v13, s[20:21]
	s_mov_b32 s20, 0
                                        ; implicit-def: $sgpr21
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s1, v11, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, v12, v9, s1
	global_load_b32 v2, v[8:9], off
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
.LBB9_13:                               ; %.lr.ph105
                                        ;   Parent Loop BB9_8 Depth=1
                                        ;     Parent Loop BB9_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v15, v[8:9], off
	s_or_b32 s22, s22, exec_lo
	s_or_b32 s23, s23, exec_lo
	s_mov_b32 s34, exec_lo
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr2
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u32_e64 v2, v15
; %bb.14:                               ;   in Loop: Header=BB9_13 Depth=3
	v_add_nc_u32_e32 v14, 1, v14
	v_add_co_u32 v8, s2, v8, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
	v_cmp_ge_i32_e64 s1, v14, v5
	s_and_not1_b32 s23, s23, exec_lo
	s_mov_b32 s33, -1
	s_mov_b32 s2, 0
	s_and_not1_b32 s22, s22, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, s1
; %bb.15:                               ; %Flow183
                                        ;   in Loop: Header=BB9_13 Depth=3
	s_or_b32 exec_lo, exec_lo, s34
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s23
	s_or_b32 s20, s1, s20
	s_and_not1_b32 s1, s21, exec_lo
	s_and_b32 s21, s22, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_or_b32 s21, s1, s21
	s_and_b32 s1, s33, exec_lo
	s_and_not1_b32 s17, s17, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s7, s7, s1
	s_or_b32 s17, s17, s2
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB9_13
; %bb.16:                               ; %loop.exit.guard180
                                        ;   in Loop: Header=BB9_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_mov_b32 s1, -1
	s_and_saveexec_b32 s2, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
; %bb.17:                               ;   in Loop: Header=BB9_11 Depth=2
	s_add_i32 s6, s6, 1
	s_and_not1_b32 s17, s17, exec_lo
	v_cmp_ge_i32_e64 s1, s6, v3
	s_and_b32 s20, s3, exec_lo
	s_and_not1_b32 s7, s7, exec_lo
	s_and_b32 s21, vcc_lo, exec_lo
	s_or_b32 s17, s17, s20
	s_or_b32 s7, s7, s21
	s_or_not1_b32 s1, s1, exec_lo
; %bb.18:                               ; %Flow185
                                        ;   in Loop: Header=BB9_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s14, exec_lo
	s_and_b32 s14, s17, exec_lo
	s_and_b32 s7, s7, exec_lo
	s_or_b32 s14, s2, s14
	s_and_not1_b32 s2, s15, exec_lo
	s_and_not1_b32 s13, s13, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s15, s2, s7
	s_or_b32 s13, s13, s1
.LBB9_19:                               ; %Flow184
                                        ;   in Loop: Header=BB9_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s13
	s_or_b32 s12, s1, s12
	s_and_not1_b32 s1, s11, exec_lo
	s_and_b32 s2, s14, exec_lo
	s_and_not1_b32 s5, s5, exec_lo
	s_and_b32 s7, s15, exec_lo
	s_or_b32 s11, s1, s2
	s_or_b32 s5, s5, s7
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB9_11
; %bb.20:                               ; %Flow186
                                        ;   in Loop: Header=BB9_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB9_21:                               ; %.critedge
                                        ;   in Loop: Header=BB9_8 Depth=1
	s_add_i32 s4, s4, 1
	s_mov_b32 s0, 0
.LBB9_22:                               ; %Flow188
                                        ;   in Loop: Header=BB9_8 Depth=1
	s_and_b32 s1, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s1, s8
	s_and_not1_b32 s1, s3, exec_lo
	s_and_b32 s2, s11, exec_lo
	s_and_not1_b32 s6, s10, exec_lo
	s_or_b32 s1, s1, s2
	s_and_b32 s0, s0, exec_lo
	s_and_not1_b32 s2, s9, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s10, s6, s0
	s_or_b32 s9, s2, s3
	s_mov_b32 s3, s1
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB9_8
; %bb.23:                               ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s8
	s_and_saveexec_b32 s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB9_26
; %bb.24:
	s_and_b32 exec_lo, exec_lo, s9
	s_cbranch_execz .LBB9_26
; %bb.25:
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_mov_b32_e32 v2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB9_26:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7findallPiS_S_S_S_S_S_S_PS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z7findallPiS_S_S_S_S_S_S_PS_S_, .Lfunc_end9-_Z7findallPiS_S_S_S_S_S_S_PS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4016
; NumSgprs: 37
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.type	__unnamed_1,@object             ; @0
	.section	.rodata,"a",@progbits
	.p2align	2, 0x0
__unnamed_1:
	.long	130054                          ; 0x1fc06
	.long	129546                          ; 0x1fa0a
	.long	110114                          ; 0x1ae22
	.long	16288                           ; 0x3fa0
	.long	6                               ; 0x6
	.long	256                             ; 0x100
	.long	0                               ; 0x0
	.long	4195                            ; 0x1063
	.long	86927                           ; 0x1538f
	.long	86758                           ; 0x152e6
	.long	73744                           ; 0x12010
	.long	10904                           ; 0x2a98
	.long	399                             ; 0x18f
	.long	512                             ; 0x200
	.long	0                               ; 0x0
	.long	2804                            ; 0xaf4
	.long	65280                           ; 0xff00
	.long	64770                           ; 0xfd02
	.long	55054                           ; 0xd70e
	.long	8192                            ; 0x2000
	.long	0                               ; 0x0
	.long	128                             ; 0x80
	.long	0                               ; 0x0
	.long	2107                            ; 0x83b
	.long	43576                           ; 0xaa38
	.long	43406                           ; 0xa98e
	.long	36895                           ; 0x901f
	.long	5504                            ; 0x1580
	.long	56                              ; 0x38
	.long	256                             ; 0x100
	.long	0                               ; 0x0
	.long	1405                            ; 0x57d
	.long	32703                           ; 0x7fbf
	.long	32193                           ; 0x7dc1
	.long	27364                           ; 0x6ae4
	.long	4160                            ; 0x1040
	.long	63                              ; 0x3f
	.long	64                              ; 0x40
	.long	0                               ; 0x0
	.long	1054                            ; 0x41e
	.long	21816                           ; 0x5538
	.long	21646                           ; 0x548e
	.long	18399                           ; 0x47df
	.long	2816                            ; 0xb00
	.long	56                              ; 0x38
	.long	128                             ; 0x80
	.long	0                               ; 0x0
	.long	703                             ; 0x2bf
	.long	16367                           ; 0x3fef
	.long	15856                           ; 0x3df0
	.long	13477                           ; 0x34a5
	.long	2176                            ; 0x880
	.long	15                              ; 0xf
	.long	32                              ; 0x20
	.long	32768                           ; 0x8000
	.long	527                             ; 0x20f
	.long	10915                           ; 0x2aa3
	.long	10745                           ; 0x29f9
	.long	9133                            ; 0x23ad
	.long	1472                            ; 0x5c0
	.long	35                              ; 0x23
	.long	64                              ; 0x40
	.long	0                               ; 0x0
	.long	352                             ; 0x160
	.long	8187                            ; 0x1ffb
	.long	7676                            ; 0x1dfc
	.long	6524                            ; 0x197c
	.long	1280                            ; 0x500
	.long	11                              ; 0xb
	.long	16                              ; 0x10
	.long	134219776                       ; 0x8000800
	.long	265                             ; 0x109
	.long	5459                            ; 0x1553
	.long	5289                            ; 0x14a9
	.long	4495                            ; 0x118f
	.long	896                             ; 0x380
	.long	19                              ; 0x13
	.long	32                              ; 0x20
	.long	524288                          ; 0x80000
	.long	176                             ; 0xb0
	.long	4094                            ; 0xffe
	.long	3583                            ; 0xdff
	.long	3045                            ; 0xbe5
	.long	1024                            ; 0x400
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	1077952576                      ; 0x40404040
	.long	133                             ; 0x85
	.long	2730                            ; 0xaaa
	.long	2560                            ; 0xa00
	.long	2176                            ; 0x880
	.long	512                             ; 0x200
	.long	10                              ; 0xa
	.long	16                              ; 0x10
	.long	67109888                        ; 0x4000400
	.long	89                              ; 0x59
	.long	2047                            ; 0x7ff
	.long	1536                            ; 0x600
	.long	1305                            ; 0x519
	.long	1024                            ; 0x400
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	2290649224                      ; 0x88888888
	.long	66                              ; 0x42
	.long	1365                            ; 0x555
	.long	1195                            ; 0x4ab
	.long	1015                            ; 0x3f7
	.long	512                             ; 0x200
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	538976288                       ; 0x20202020
	.long	44                              ; 0x2c
	.long	1023                            ; 0x3ff
	.long	512                             ; 0x200
	.long	435                             ; 0x1b3
	.long	2048                            ; 0x800
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	2863311530                      ; 0xaaaaaaaa
	.long	34                              ; 0x22
	.long	682                             ; 0x2aa
	.long	512                             ; 0x200
	.long	435                             ; 0x1b3
	.long	2048                            ; 0x800
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	1145324612                      ; 0x44444444
	.long	35                              ; 0x23
	.size	__unnamed_1, 512

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7findallPiS_S_S_S_S_S_S_PS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     37
    .sgpr_spill_count: 0
    .symbol:         _Z7findallPiS_S_S_S_S_S_S_PS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
