#include "includes.h"
__global__ void THCudaTensor_kernel_copy(float *dst, long *dst_sz, long *dst_st, int dst_dim, float *src, long *src_sz, long *src_st, int src_dim, long n_elem, long innerdim)
{
long k = (blockIdx.z * gridDim.x * gridDim.y + blockIdx.y * gridDim.x + blockIdx.x)*blockDim.y + threadIdx.y;

long i_start = threadIdx.x * src_st[src_dim-1];
long i_step = blockDim.x * src_st[src_dim-1];

long o_start = threadIdx.x * dst_st[dst_dim-1];
long o_step = blockDim.x * dst_st[dst_dim-1];
long o_end = innerdim * dst_st[dst_dim-1];

if ( ((k+1) * innerdim) <= n_elem) // too safe
{
long dst_idx = 0;
long dst_rest = k * innerdim;
for(int dim = 0; dim < dst_dim; dim++)
{
dst_idx += (dst_rest/dst_sz[dim])*dst_st[dim];
dst_rest = dst_rest % dst_sz[dim];
}

long src_idx = 0;
long src_rest = k * innerdim;
for(int dim = 0; dim < src_dim; dim++)
{
src_idx += (src_rest/src_sz[dim])*src_st[dim];
src_rest = src_rest % src_sz[dim];
}

for (int i=i_start, o=o_start; o<o_end; i+=i_step, o+=o_step) {
dst[dst_idx + o] = src[src_idx + i];
}
}
}
	.file	"tmpxft_00219002_00000000-6_THCudaTensor_kernel_copy.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill
	.type	_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill, @function
_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 36(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill, .-_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill
	.globl	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.type	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, @function
_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_illPfPlS0_iS_S0_S0_ill
	.cfi_endproc
.LFE2033:
	.size	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, .-_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void THCudaTensor_kernel_copy(float *dst, long *dst_sz, long *dst_st, int dst_dim, float *src, long *src_sz, long *src_st, int src_dim, long n_elem, long innerdim)
{
long k = (blockIdx.z * gridDim.x * gridDim.y + blockIdx.y * gridDim.x + blockIdx.x)*blockDim.y + threadIdx.y;

long i_start = threadIdx.x * src_st[src_dim-1];
long i_step = blockDim.x * src_st[src_dim-1];

long o_start = threadIdx.x * dst_st[dst_dim-1];
long o_step = blockDim.x * dst_st[dst_dim-1];
long o_end = innerdim * dst_st[dst_dim-1];

if ( ((k+1) * innerdim) <= n_elem) // too safe
{
long dst_idx = 0;
long dst_rest = k * innerdim;
for(int dim = 0; dim < dst_dim; dim++)
{
dst_idx += (dst_rest/dst_sz[dim])*dst_st[dim];
dst_rest = dst_rest % dst_sz[dim];
}

long src_idx = 0;
long src_rest = k * innerdim;
for(int dim = 0; dim < src_dim; dim++)
{
src_idx += (src_rest/src_sz[dim])*src_st[dim];
src_rest = src_rest % src_sz[dim];
}

for (int i=i_start, o=o_start; o<o_end; i+=i_step, o+=o_step) {
dst[dst_idx + o] = src[src_idx + i];
}
}
}
	.text
	.file	"THCudaTensor_kernel_copy.hip"
	.globl	_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill # -- Begin function _Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.type	_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill,@function
_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill: # @_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, .Lfunc_end0-_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill,@object # @_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.section	.rodata,"a",@progbits
	.globl	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.p2align	3, 0x0
_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill:
	.quad	_Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.size	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill"
	.size	.L__unnamed_1, 48

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill ; -- Begin function _Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.globl	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
	.p2align	8
	.type	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill,@function
_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill: ; @_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
; %bb.0:
	s_clause 0x2
	s_load_b64 s[2:3], s[0:1], 0x50
	s_load_b32 s28, s[0:1], 0x5c
	s_load_b128 s[4:7], s[0:1], 0x40
	v_bfe_u32 v1, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s14
	s_mul_i32 s2, s3, s2
	s_lshr_b32 s3, s28, 16
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s2, s3, v[1:2]
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s6, v3, s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s7, v3, v[2:3]
	v_mov_b32_e32 v2, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_i64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_12
; %bb.1:
	s_clause 0x5
	s_load_b32 s16, s[0:1], 0x38
	s_load_b32 s20, s[0:1], 0x18
	s_load_b64 s[18:19], s[0:1], 0x30
	s_load_b64 s[22:23], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b128 s[12:15], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, v3, s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s7, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s17, s16, 31
	s_ashr_i32 s21, s20, 31
	s_lshl_b64 s[2:3], s[16:17], 3
	v_mov_b32_e32 v2, v4
	s_add_u32 s2, s18, s2
	s_addc_u32 s3, s19, s3
	s_add_u32 s2, s2, -8
	s_addc_u32 s3, s3, -1
	s_lshl_b64 s[4:5], s[20:21], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s22, s4
	s_addc_u32 s1, s23, s5
	s_add_u32 s0, s0, -8
	s_addc_u32 s1, s1, -1
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[0:1], 0x0
	v_cmp_lt_i64_e64 s0, s[20:21], 1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, v2
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v1
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b64 s[24:25], s[14:15], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v6
	s_load_b64 s[26:27], s[22:23], 0x0
	v_add_co_u32 v4, vcc_lo, v5, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, v6, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v4, v3
	v_xor_b32_e32 v13, v9, v3
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s0, s25, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_u32 s30, s24, s0
	s_mov_b32 s1, s0
	s_addc_u32 s31, s25, s0
	v_xor_b32_e32 v15, s0, v3
	s_xor_b64 s[30:31], s[30:31], s[0:1]
	v_cvt_f32_u32_e32 v3, s30
	v_cvt_f32_u32_e32 v4, s31
	s_sub_u32 s0, 0, s30
	s_subb_u32 s1, 0, s31
	s_add_i32 s20, s20, -1
	s_add_u32 s14, s14, 8
	v_fmac_f32_e32 v3, 0x4f800000, v4
	s_addc_u32 s15, s15, 0
	s_add_u32 s22, s22, 8
	s_addc_u32 s23, s23, 0
	s_cmp_eq_u32 s20, 0
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x5f7ffffc, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x2f800000, v3
	v_trunc_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, 0xcf800000, v4
	v_cvt_u32_f32_e32 v4, v4
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, s0, v4
	v_mul_hi_u32 v10, s0, v3
	v_mul_lo_u32 v12, s1, v3
	v_mul_lo_u32 v11, s0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v10, v9
	v_mul_hi_u32 v10, v3, v11
	v_mul_hi_u32 v16, v4, v11
	v_mul_lo_u32 v11, v4, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v9, v12
	v_mul_lo_u32 v12, v3, v9
	v_mul_hi_u32 v17, v3, v9
	v_mul_hi_u32 v18, v4, v9
	v_mul_lo_u32 v9, v4, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v16, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, s0, v3
	v_mul_lo_u32 v11, s1, v3
	v_mul_lo_u32 v12, s0, v4
	v_mul_lo_u32 v9, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v12
	v_mul_hi_u32 v16, v4, v9
	v_mul_lo_u32 v17, v4, v9
	v_mul_hi_u32 v9, v3, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v11, v3, v10
	v_mul_hi_u32 v12, v3, v10
	v_mul_hi_u32 v18, v4, v10
	v_mul_lo_u32 v10, v4, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v9, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v9, v17
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v16, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, v4, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v14, v9
	v_mad_u64_u32 v[3:4], null, v13, v9, 0
	v_mad_u64_u32 v[9:10], null, v14, v16, 0
	v_mad_u64_u32 v[11:12], null, v13, v16, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v17, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_add_co_ci_u32_e32 v3, vcc_lo, v10, v4, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v3, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v11, s31, v9
	v_mad_u64_u32 v[3:4], null, s30, v9, 0
	v_mul_lo_u32 v17, s30, v10
	v_add_co_u32 v12, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v16, s0, v9, 2
	v_sub_co_u32 v3, vcc_lo, v14, v3
	v_add3_u32 v4, v4, v17, v11
	v_add_co_ci_u32_e64 v18, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v13, v4
	v_subrev_co_ci_u32_e64 v11, s0, s31, v11, vcc_lo
	v_sub_co_ci_u32_e32 v4, vcc_lo, v13, v4, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s30, v3
	v_sub_co_u32 v14, s0, v3, s30
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v11, vcc_lo, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s30, v14
	v_cmp_le_u32_e64 s0, s31, v11
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s31, v4
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s31, v4
	v_cndmask_b32_e64 v4, 0, -1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v14, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s31, v11
	v_cmp_ne_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v13, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_dual_cndmask_b32 v4, v19, v18 :: v_dual_cndmask_b32 v3, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v10, v4, s0
	v_cndmask_b32_e64 v3, v9, v3, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v15
	v_xor_b32_e32 v3, v3, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v11, vcc_lo, v3, v15
	v_sub_co_ci_u32_e32 v3, vcc_lo, v4, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v13, s27, v11
	v_mul_lo_u32 v15, v11, s25
	v_mul_lo_u32 v12, s26, v3
	v_mul_lo_u32 v14, v3, s24
	v_mad_u64_u32 v[9:10], null, v11, s24, 0
	v_mad_u64_u32 v[3:4], null, s26, v11, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v10, v15, v14
	v_sub_co_u32 v5, vcc_lo, v5, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v13, v4, v12
	v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB0_5:                                ; %.preheader
	s_cmp_lt_i32 s16, 1
	s_cbranch_scc1 .LBB0_8
; %bb.6:                                ; %.lr.ph81.preheader
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
.LBB0_7:                                ; %.lr.ph81
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b64 s[14:15], s[10:11], 0x0
	v_ashrrev_i32_e32 v7, 31, v2
	s_load_b64 s[20:21], s[18:19], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v1, v7
	v_add_co_ci_u32_e32 v9, vcc_lo, v2, v7, vcc_lo
	v_xor_b32_e32 v14, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v13, v9, v7
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s0, s15, 31
	s_add_u32 s22, s14, s0
	s_mov_b32 s1, s0
	s_addc_u32 s23, s15, s0
	v_xor_b32_e32 v15, s0, v7
	s_xor_b64 s[22:23], s[22:23], s[0:1]
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cvt_f32_u32_e32 v7, s22
	v_cvt_f32_u32_e32 v8, s23
	s_sub_u32 s0, 0, s22
	s_subb_u32 s1, 0, s23
	s_add_i32 s16, s16, -1
	s_add_u32 s10, s10, 8
	v_fmac_f32_e32 v7, 0x4f800000, v8
	s_addc_u32 s11, s11, 0
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_eq_u32 s16, 0
	v_rcp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v7, 0x5f7ffffc, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, 0x2f800000, v7
	v_trunc_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, 0xcf800000, v8
	v_cvt_u32_f32_e32 v8, v8
	v_cvt_u32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, s0, v8
	v_mul_hi_u32 v10, s0, v7
	v_mul_lo_u32 v12, s1, v7
	v_mul_lo_u32 v11, s0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v10, v9
	v_mul_hi_u32 v10, v7, v11
	v_mul_hi_u32 v16, v8, v11
	v_mul_lo_u32 v11, v8, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, v9, v12
	v_mul_lo_u32 v12, v7, v9
	v_mul_hi_u32 v17, v7, v9
	v_mul_hi_u32 v18, v8, v9
	v_mul_lo_u32 v9, v8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v10, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, v12, v16, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, v9
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, s0, v7
	v_mul_lo_u32 v11, s1, v7
	v_mul_lo_u32 v12, s0, v8
	v_mul_lo_u32 v9, s0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v10, v12
	v_mul_hi_u32 v16, v8, v9
	v_mul_lo_u32 v17, v8, v9
	v_mul_hi_u32 v9, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v11
	v_mul_lo_u32 v11, v7, v10
	v_mul_hi_u32 v12, v7, v10
	v_mul_hi_u32 v18, v8, v10
	v_mul_lo_u32 v10, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v9, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v9, v17
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v16, vcc_lo
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, v9
	v_add_co_ci_u32_e32 v16, vcc_lo, v8, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v14, v9
	v_mad_u64_u32 v[7:8], null, v13, v9, 0
	v_mad_u64_u32 v[9:10], null, v14, v16, 0
	v_mad_u64_u32 v[11:12], null, v13, v16, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v17, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v9, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, v10, v8, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v7, v11
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v11, s23, v9
	v_mad_u64_u32 v[7:8], null, s22, v9, 0
	v_mul_lo_u32 v17, s22, v10
	v_add_co_u32 v12, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v16, s0, v9, 2
	v_sub_co_u32 v7, vcc_lo, v14, v7
	v_add3_u32 v8, v8, v17, v11
	v_add_co_ci_u32_e64 v18, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v11, v13, v8
	v_subrev_co_ci_u32_e64 v11, s0, s23, v11, vcc_lo
	v_sub_co_ci_u32_e32 v8, vcc_lo, v13, v8, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v7
	v_sub_co_u32 v14, s0, v7, s22
	v_cndmask_b32_e64 v7, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v11, vcc_lo, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s22, v14
	v_cmp_le_u32_e64 s0, s23, v11
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v8
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s23, v8
	v_cndmask_b32_e64 v8, 0, -1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v14, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s23, v11
	v_cmp_ne_u32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v8, v13, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_dual_cndmask_b32 v8, v19, v18 :: v_dual_cndmask_b32 v7, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v10, v8, s0
	v_cndmask_b32_e64 v7, v9, v7, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v15
	v_xor_b32_e32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v11, vcc_lo, v7, v15
	v_sub_co_ci_u32_e32 v7, vcc_lo, v8, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v13, s21, v11
	v_mul_lo_u32 v15, v11, s15
	v_mul_lo_u32 v12, s20, v7
	v_mul_lo_u32 v14, v7, s14
	v_mad_u64_u32 v[9:10], null, v11, s14, 0
	v_mad_u64_u32 v[7:8], null, s20, v11, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v5, v10, v15, v14
	v_sub_co_u32 v1, vcc_lo, v1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v8, v13, v8, v12
	v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v5, v7 :: v_dual_mov_b32 v6, v8
	s_cbranch_scc0 .LBB0_7
	s_branch .LBB0_9
.LBB0_8:
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
.LBB0_9:                                ; %._crit_edge
	v_and_b32_e32 v5, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s4, s7
	s_mul_hi_u32 s1, s4, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_i32 s0, s1, s0
	v_mul_lo_u32 v0, v5, s4
	s_mul_i32 s1, s5, s6
	s_mul_i32 s6, s4, s6
	s_add_i32 s7, s0, s1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[0:1]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.10:                               ; %.lr.ph86
	v_lshlrev_b64 v[6:7], 2, v[7:8]
	s_and_b32 s0, s28, 0xffff
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	v_add_nc_u32_e32 v3, s0, v5
	v_mul_lo_u32 v2, v5, s2
	s_mul_i32 s1, s0, s2
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_mul_lo_u32 v4, v3, s4
	v_add_co_u32 v8, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
	s_mul_i32 s2, s4, s0
	s_mov_b32 s3, 0
.LBB0_11:                               ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add_nc_u32_e32 v2, s1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, v6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v11, vcc_lo
	v_cmp_le_i64_e32 vcc_lo, s[6:7], v[4:5]
	global_load_b32 v3, v[10:11], off
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
	v_add_nc_u32_e32 v4, s2, v4
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, v8, v10
	v_add_co_ci_u32_e64 v11, s0, v9, v11, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[10:11], v3, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_11
.LBB0_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill, .Lfunc_end0-_Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2580
; NumSgprs: 34
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z24THCudaTensor_kernel_copyPfPlS0_iS_S0_S0_ill.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
