/* Cuda GPU Based Program that use GPU processor for finding cosine of numbers */

/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<cuda.h>

#define COS_THREAD_CNT 2
#define N 10

/* --------------------------- target code ------------------------------*/
struct cosParams {
	float *arg;
	float *res;
	int n;
	//int *threadIdx;
};

__global__ void cos_main(struct cosParams parms)
{
	int i;
	for (i = threadIdx.x; i < parms.n; i += COS_THREAD_CNT)
	{
		parms.res[i] = __cosf(parms.arg[i] );
		//parms.threadIdx[0] = (int)threadIdx.x;
	}
}

/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
	int 			i = 0;
	cudaError_t 	cudaStat;
	//int*			cosThreadIdx = 0;
	float* 			cosRes = 0;
	float*			cosArg = 0;
	//int*			threadIdx = (int *) malloc(N*sizeof(threadIdx));
	float* 			arg = (float *) malloc(N*sizeof(arg[0]));
	float*			res = (float *) malloc(N*sizeof(res[0]));
	struct cosParams funcParams;


	/* ... fill arguments array "arg" .... */
	for(i=0; i < N; i++ ){
		arg[i] = (float)i;
	}

	cudaStat = cudaMalloc ((void **)&cosArg, 	N * sizeof(cosArg[0]));
	cudaStat = cudaMalloc ((void **)&cosRes, 	N * sizeof(cosRes[0]));
	//cudaStat = cudaMalloc ((void **)&threadIdx, N * sizeof(threadIdx[0]));
	cudaStat = cudaMemcpy (	cosArg,
							arg,
							N * sizeof(arg[0]),
							cudaMemcpyHostToDevice);

	funcParams.res = cosRes;
	funcParams.arg = cosArg;
	funcParams.n = N;
	//funcParams.threadIdx = cosThreadIdx;
	cos_main<<<1,COS_THREAD_CNT>>>(funcParams);

	cudaStat = cudaMemcpy(	res,
							cosRes,
							N * sizeof(cosRes[0]),
							cudaMemcpyDeviceToHost);

	//cudaStat = cudaMemcpy(	threadIdx,
	//						cosThreadIdx,
	//						N * sizeof(cosThreadIdx[0]),
	//						cudaMemcpyDeviceToHost);

	for(i=0; i < N; i++ )
	{
		printf("%d: cosf(%f) = %f\n", arg[i], res[i]); //, threadIdx[i]);
	}
}

/* nvcc cosine.cu -use_fast_math */

	.file	"tmpxft_00372091_00000000-6_cosine_my.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
	.type	_Z35__device_stub__Z8cos_main9cosParamsR9cosParams, @function
_Z35__device_stub__Z8cos_main9cosParamsR9cosParams:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rcx
	movq	%rdi, 64(%rsp)
	movq	%rsp, %rdx
	movabsq	$4294967297, %rax
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8cos_main9cosParams(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L2:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z35__device_stub__Z8cos_main9cosParamsR9cosParams, .-_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
	.globl	_Z8cos_main9cosParams
	.type	_Z8cos_main9cosParams, @function
_Z8cos_main9cosParams:
.LFB2053:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	16(%rsp), %rdi
	call	_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z8cos_main9cosParams, .-_Z8cos_main9cosParams
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d: cosf(%f) = %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$40, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	call	malloc@PLT
	movl	$40, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%rax, %r12
	xorl	%eax, %eax
.L10:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$10, %rax
	jne	.L10
	leaq	16(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$40, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$40, %edx
	call	cudaMemcpy@PLT
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	addq	%rdx, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	8(%rsp), %rbx
	movq	16(%rsp), %r13
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	leaq	48(%rsp), %rdi
	movq	%r13, 48(%rsp)
	movq	%rbx, 56(%rsp)
	movl	$10, 64(%rsp)
	call	_Z35__device_stub__Z8cos_main9cosParamsR9cosParams
.L11:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%ebx, %ebx
	movl	$40, %edx
	leaq	.LC0(%rip), %r13
	call	cudaMemcpy@PLT
.L12:
	cvtss2sd	0(%rbp,%rbx), %xmm0
	cvtss2sd	(%r12,%rbx), %xmm1
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$2, %al
	addq	$4, %rbx
	call	__printf_chk@PLT
	cmpq	$40, %rbx
	jne	.L12
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC1:
	.string	"_Z8cos_main9cosParams"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8cos_main9cosParams(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Cuda GPU Based Program that use GPU processor for finding cosine of numbers */

/* --------------------------- header secton ----------------------------*/
#include<stdio.h>
#include<hip/hip_runtime.h>

#define COS_THREAD_CNT 2
#define N 10

/* --------------------------- target code ------------------------------*/
struct cosParams {
	float *arg;
	float *res;
	int n;
	//int *threadIdx;
};

__global__ void cos_main(struct cosParams parms)
{
	int i;
	for (i = threadIdx.x; i < parms.n; i += COS_THREAD_CNT)
	{
		parms.res[i] = __cosf(parms.arg[i] );
		//parms.threadIdx[0] = (int)threadIdx.x;
	}
}

/* --------------------------- host code ------------------------------*/
int main (int argc, char *argv[])
{
	int 			i = 0;
	hipError_t 	cudaStat;
	//int*			cosThreadIdx = 0;
	float* 			cosRes = 0;
	float*			cosArg = 0;
	//int*			threadIdx = (int *) malloc(N*sizeof(threadIdx));
	float* 			arg = (float *) malloc(N*sizeof(arg[0]));
	float*			res = (float *) malloc(N*sizeof(res[0]));
	struct cosParams funcParams;


	/* ... fill arguments array "arg" .... */
	for(i=0; i < N; i++ ){
		arg[i] = (float)i;
	}

	cudaStat = hipMalloc ((void **)&cosArg, 	N * sizeof(cosArg[0]));
	cudaStat = hipMalloc ((void **)&cosRes, 	N * sizeof(cosRes[0]));
	//cudaStat = cudaMalloc ((void **)&threadIdx, N * sizeof(threadIdx[0]));
	cudaStat = hipMemcpy (	cosArg,
							arg,
							N * sizeof(arg[0]),
							hipMemcpyHostToDevice);

	funcParams.res = cosRes;
	funcParams.arg = cosArg;
	funcParams.n = N;
	//funcParams.threadIdx = cosThreadIdx;
	cos_main<<<1,COS_THREAD_CNT>>>(funcParams);

	cudaStat = hipMemcpy(	res,
							cosRes,
							N * sizeof(cosRes[0]),
							hipMemcpyDeviceToHost);

	//cudaStat = cudaMemcpy(	threadIdx,
	//						cosThreadIdx,
	//						N * sizeof(cosThreadIdx[0]),
	//						cudaMemcpyDeviceToHost);

	for(i=0; i < N; i++ )
	{
		printf("%d: cosf(%f) = %f\n", arg[i], res[i]); //, threadIdx[i]);
	}
}

/* nvcc cosine.cu -use_fast_math */

	.text
	.file	"cosine_my.hip"
	.globl	_Z23__device_stub__cos_main9cosParams # -- Begin function _Z23__device_stub__cos_main9cosParams
	.type	_Z23__device_stub__cos_main9cosParams,@function
_Z23__device_stub__cos_main9cosParams:  # @_Z23__device_stub__cos_main9cosParams
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	112(%rsp), %rax
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8cos_main9cosParams, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__cos_main9cosParams, .Lfunc_end0-_Z23__device_stub__cos_main9cosParams
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%r15d, %r15d
	movq	%r15, 32(%rsp)
	movq	%r15, 40(%rsp)
	movl	$40, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$40, %edi
	callq	malloc
	movq	%rax, %r14
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB1_1
# %bb.2:
	leaq	40(%rsp), %r15
	movl	$40, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$40, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$40, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %r12
	movq	(%r15), %r15
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	1(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	%r15, 48(%rsp)
	movq	%r12, 56(%rsp)
	movl	$10, 64(%rsp)
	movq	64(%rsp), %rax
	movq	%rax, 16(%rsp)
	movups	48(%rsp), %xmm0
	movups	%xmm0, (%rsp)
	callq	_Z23__device_stub__cos_main9cosParams
.LBB1_4:
	movq	32(%rsp), %rsi
	movl	$40, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	xorps	%xmm1, %xmm1
	cvtss2sd	(%r14,%r15,4), %xmm1
	movl	$.L.str, %edi
	movb	$2, %al
	callq	printf
	incq	%r15
	cmpq	$10, %r15
	jne	.LBB1_5
# %bb.6:
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8cos_main9cosParams, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8cos_main9cosParams,@object   # @_Z8cos_main9cosParams
	.section	.rodata,"a",@progbits
	.globl	_Z8cos_main9cosParams
	.p2align	3, 0x0
_Z8cos_main9cosParams:
	.quad	_Z23__device_stub__cos_main9cosParams
	.size	_Z8cos_main9cosParams, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d: cosf(%f) = %f\n"
	.size	.L.str, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8cos_main9cosParams"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__cos_main9cosParams
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8cos_main9cosParams
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8cos_main9cosParams   ; -- Begin function _Z8cos_main9cosParams
	.globl	_Z8cos_main9cosParams
	.p2align	8
	.type	_Z8cos_main9cosParams,@function
_Z8cos_main9cosParams:                  ; @_Z8cos_main9cosParams
; %bb.0:
	s_load_b32 s2, s[0:1], 0x10
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 2, v0
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v1, s0, s4, v3
	v_add_co_ci_u32_e64 v2, null, s5, 0, s0
	v_add_co_u32 v3, s0, s6, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, null, s7, 0, s0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[1:2], off
	v_add_nc_u32_e32 v0, 2, v0
	v_add_co_u32 v1, vcc_lo, v1, 8
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, 0.15915494, v5
	v_cmp_le_i32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cos_f32_e32 v5, v5
	s_or_b32 s1, vcc_lo, s1
	global_store_b32 v[3:4], v5, off
	v_add_co_u32 v3, s0, v3, 8
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8cos_main9cosParams
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8cos_main9cosParams, .Lfunc_end0-_Z8cos_main9cosParams
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 10
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           24
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8cos_main9cosParams
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z8cos_main9cosParams.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
