#include <cstdio>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>


#define GIG 1000000000
#define PRINT_TIME 1
#define BLOCK 32 //blockDim
#define THREAD 32
#define SM_ARR_LEN 1024 //size of the matrix
#define THREADS_PER_BLOCK 64
#define THREADS_PER_DIM 16
#define TILING_DIM 20
#define MAX_MATRIX_SIZE_FOR_OUTPUT 64
#define QRD_SIMPLE_CALC_NORM2 128
#define QRD_SIMPLE_SCALE_COLUMN 128
#define QRD_SIMPLE_TRANSFORM_COLUMNS 128
#define QRD_OPTIMISED_NORM2_BLOCKSIZE 128
#define QRD_OPTIMISED_SCALE_COLUMN 128
#define QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM 512
#define IMUL(a, b) __mul24(a, b)

// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
  if (code != cudaSuccess) 
  {
    fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", cudaGetErrorString(code), file, line);
    if (abort) exit(code);
  }
}



typedef struct
{
    float *n; // Length: size = width*height
    float *d; // Length: height
    unsigned int width;
    unsigned int height;
    unsigned int size;
    bool hasPivot;
    int *pivot; // Length: height
} QRmatrix;



__global__ void qrd_optimised_calc_norm2(float *out_norms, float *qr, int k, int m, int n)
{
	// Shared memory
	extern __shared__ float s_qr[];
    unsigned int r = blockIdx.x * blockDim.x + threadIdx.x + k; // Get row index
	// Clear cache for threads that exceeds max + they should not influence result
	s_qr[threadIdx.x] = 0;
	if (r < m)
	{
		// Read value to shared memory
		float val = qr[r * n + k];
		s_qr[threadIdx.x] = val * val;

		// Sync threads to make sure all other also have loaded values
		__syncthreads();

		// Do the actual pivot finding
		for(unsigned int stride = blockDim.x/2; stride>0; stride>>=1)
		{
			if (threadIdx.x < stride && (stride+threadIdx.x+k) < m)
			{
				s_qr[threadIdx.x] += s_qr[threadIdx.x + stride]; // Update value
			}

			// Sync threads
			__syncthreads();
		}
		// The first thread should write result from block to output
		if (threadIdx.x == 0)
		{
			out_norms[blockIdx.x] = s_qr[0]; // Load sum to output
		}
	}
}
__global__ void qrd_optimised_calc_norm2_L2(float *val_norms, int max)
{
	// Shared memory
	extern __shared__ float s_qr[];
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	// Clear cache for threads that exceeds max + they should not influence result
	s_qr[threadIdx.x] = 0;
	if (tid < max)
	{
		// Read value to shared memory
		s_qr[threadIdx.x] = val_norms[tid];
		// Sync threads to make sure all other also have loaded values
		__syncthreads();
		// Do the actual pivot finding
		for(unsigned int stride = blockDim.x/2; stride>0; stride>>=1)
		{
			if (threadIdx.x < stride)
			{
				s_qr[threadIdx.x] += s_qr[threadIdx.x + stride]; // Update value
			}

			// Sync threads
			__syncthreads();
		}
		// The first thread should write result from block to output
		if (threadIdx.x == 0)
		{
			val_norms[blockIdx.x] = s_qr[0]; // Load sum to output
		}
	}
}
__global__ void qrd_optimised_calc_norm2_FINISH(float *val_norms, float *qr, float *qr_diag, float *qr_norms, int k, int n)
{
	// Square root to get raw norm
	float nrm = sqrtf(val_norms[0]);

	// Flip sign for norm depending on the value of kth row kth column
	nrm = qr[k * n + k] < 0 ? -nrm : nrm;

	// Save the actual norm
	val_norms[0] = nrm;
	qr_norms[k] = nrm;

	// Flip sign for norm and save to QR diagonale
	qr_diag[k] = -nrm;
}


float calc_norm2_optimised(float *d_qr, float *d_diag, float *d_norms, int k, int m, int n)
{
	int threads = m-k;
    int blocks = (threads + QRD_OPTIMISED_NORM2_BLOCKSIZE-1) / QRD_OPTIMISED_NORM2_BLOCKSIZE;

	dim3 dimBlock(QRD_OPTIMISED_NORM2_BLOCKSIZE, 1, 1);
    dim3 dimGrid(blocks, 1, 1);
    int smemSize = QRD_OPTIMISED_NORM2_BLOCKSIZE*sizeof(float);

	float *d_out;

	cudaMalloc( (void**) &d_out, sizeof(float) * dimGrid.x);

	// First run on a, subsequential will be on d_out
	qrd_optimised_calc_norm2<<< dimGrid, dimBlock, smemSize >>>(d_out, d_qr, k, m, n);

	while(blocks > 1)
	{
		// Adjust the number of required blocks, for the second round
		threads = blocks;
		blocks = threads > QRD_OPTIMISED_NORM2_BLOCKSIZE
			? (threads + QRD_OPTIMISED_NORM2_BLOCKSIZE-1) / QRD_OPTIMISED_NORM2_BLOCKSIZE
			: 1;

		dimGrid.x = blocks;	
		qrd_optimised_calc_norm2_L2<<< dimGrid, dimBlock, smemSize >>>(d_out, threads);
	}
	
	qrd_optimised_calc_norm2_FINISH<<< 1, 1 >>>(d_out, d_qr, d_diag, d_norms, k, n);
	cudaThreadSynchronize();
	float norm = 0.0;
	cudaMemcpy( &norm, d_out, sizeof(float), cudaMemcpyDeviceToHost);
	cudaFree( d_out );
	return norm;
}

void output_matrix(float *m, int height, int width) {

    int size = height*width;
    if (size > MAX_MATRIX_SIZE_FOR_OUTPUT) 
	{
        printf("Matrix to big to be outputted...");
        printf("M: %dx%d (%d)\n", height, width, size);
        return;
    }
    
    int row = 0;
    
    for(int i = 0; i < size; i++) 
	{
        int curRow = i/width;
        //int curCol = i%m->width;
        if (curRow > row) 
		{
            printf("\n");
            row = curRow;
        }
        else if (i > 0) 
		{
            printf("  ");
        }       
        printf("%f", m[i] );
    }  
    printf("\n");
}

void output_qr_matrix(QRmatrix *m)
{
	output_matrix(m->n, m->height, m->width);
	printf("\nD:\n");
	if (m->size > MAX_MATRIX_SIZE_FOR_OUTPUT)
	{
		printf("Total diagonale elements %d.", m->height);
	}
	else
	{
		for(unsigned int i = 0; i < m->height; i++)
		{
			if (i > 0) printf(", ");
			printf("%f", m->d[i] );
		}
	}
	printf("\n");
}


__global__ void qrd_optimised_scale_column(float *qr, float *qr_norms, int k, int m, int n)
{
	float norm = qr_norms[k];
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int r = k + tid;
	if (r < m)
	{
		qr[r * n + k] /= norm;
	}
	if (tid == 0)
	{
		qr[k * n + k] += 1.0;
	}
}



__global__ void qrd_optimised_transform_columns(float *qr, int k, int m, int n)
{
	// Declare cache
    extern __shared__ float v[];

	// Apply transformation to remaining columns.
	int c = blockIdx.x * blockDim.x + threadIdx.x + k + 1;
	if (c < n)
	{
		float s = 0.0, knk = qr[k * n + k];
		for (int i = k; i < m;)
        {
			// Guard for not exceeding height of QR matrix + load k column values to shared memory
			v[threadIdx.x] = i+threadIdx.x < m ? qr[(i+threadIdx.x) * n + k] : 0;
			__syncthreads();
			// For all k values loaded, calc s
			for(int vi = 0; vi < blockDim.y; vi++, i++)
				s += v[vi] * qr[i * n + c];
        }
		s = (-s) / knk;
		for (int i = k; i < m;)
        {
			// Guard for not exceeding height of QR matrix + load k column values to shared memory
			v[threadIdx.x] = i+threadIdx.x < m ? qr[(i+threadIdx.x) * n + k] : 0;
			__syncthreads();
			// For all k values loaded, calc s
			for(int vi = 0; vi < blockDim.y; vi++, i++)
				qr[i * n + c] += s * v[vi];
        }
	}
}


void scale_column_optimised(float *d_qr, float *d_norms, int k, int m, int n)
{
	int threads = m-k;
    int blocks = (threads + QRD_OPTIMISED_SCALE_COLUMN-1) / QRD_OPTIMISED_SCALE_COLUMN;
	qrd_optimised_scale_column<<< blocks, QRD_OPTIMISED_SCALE_COLUMN >>>( d_qr, d_norms, k, m, n );
}



void transform_columns_optimised(float *d_qr, int k, int m, int n)
{
	int threads = n-(k+1);
    int blocks = (threads + QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM-1) / QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM;
	dim3 dimBlock(QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM, 1, 1);
    dim3 dimGrid(blocks, 1, 1);
    int smemSize = QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM*sizeof(float);
	qrd_optimised_transform_columns<<< dimGrid, dimBlock, smemSize >>>( d_qr, k, m, n );
}

void randomInit(float* data, int size, float min, float max)
{   
    const float range = (max - min);    
    for (int i = 0; i < size; ++i) 
	{
        float rnd = rand()/(float)RAND_MAX; // Generate random value from 0.0 to 1.0
        data[i] = rnd*range + min;
    }
}



QRmatrix* gpu_qrd_optimised(QRmatrix *a, int blockDimension, int version, bool usePivot) 
{
  // GPU Timing variables
	cudaEvent_t start, stop;
	float elapsed_gpu;
	bool output = a->size < 50;
	int n = a->width;
	int m = a->height;
    
    QRmatrix *qr = (QRmatrix*) malloc (sizeof(QRmatrix));
    qr->height = a->height;
    qr->size = a->size;
    qr->width = a->width;
    qr->n = (float*) malloc (sizeof(float)*a->size);
    qr->d = (float*) malloc (sizeof(float)*a->height);
    qr->pivot = (int*) malloc (sizeof(int)*a->height);
    qr->hasPivot = false;

	// Check if block dimension is too big
	if (blockDimension > (int)a->width) blockDimension = a->width;


    // Declare kernel pointers
    float *d_qr, *d_diag, *d_norms; // QR + Diagonale + Norms
    
    // Allocate memory on GPU for LU matrix
    cudaMalloc( (void**) &d_qr, sizeof(float) * qr->size );
    cudaMalloc( (void**) &d_diag, sizeof(float) * qr->width );
    cudaMalloc( (void**) &d_norms, sizeof(float) * qr->width );
	

    // Copy matrix A vector values to the QR pointer on the GPU/device = A copy to QR (will be modified)
    cudaMemcpy( d_qr, a->n, sizeof(float) * a->size, cudaMemcpyHostToDevice);

    #if PRINT_TIME
	// Create the cuda events
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	// Record event on the default stream
	cudaEventRecord(start, 0);
	#endif
	// Execute kernels
	// Optimised QR
	// Core algorithm for QR Decomposition
	for (int k = 0; k < n; k++) // For each column
    {
        // Compute 2-norm of k-th column
		float nrm = calc_norm2_optimised(d_qr, d_diag, d_norms, k, m, n);
        if (nrm != 0.0)
        {
            // Form k-th Householder vector. (Performed on device)
			scale_column_optimised(d_qr, d_norms, k, m, n);

			if (output)
			{
				cudaMemcpy( qr->n, d_qr, qr->size * sizeof(float), cudaMemcpyDeviceToHost);
				cudaMemcpy( qr->d, d_diag, qr->width * sizeof(float), cudaMemcpyDeviceToHost);
				printf("\n\nDecompose Partly Column=%d\n--------------\n", k);
				output_qr_matrix(qr);
			}
            // Apply transformation to remaining columns.
			transform_columns_optimised(d_qr, k, m, n);
        }

		if (output)
		{
			cudaMemcpy( qr->n, d_qr, qr->size * sizeof(float), cudaMemcpyDeviceToHost);
			cudaMemcpy( qr->d, d_diag, qr->width * sizeof(float), cudaMemcpyDeviceToHost);	
			printf("\n\nDecompose Partly Column=%d\n--------------\n", k);
			output_qr_matrix(qr);
		}
    }
    cudaThreadSynchronize();
	#if PRINT_TIME
	// Stop and destroy the timer
	cudaEventRecord(stop,0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsed_gpu, start, stop);
	printf("\nGPU time: %f (msec)\n", elapsed_gpu);
	cudaEventDestroy(start);
	cudaEventDestroy(stop);
	#endif
    
    // Copy matrix members + value vector to host;
	cudaMemcpy( qr->n, d_qr, qr->size * sizeof(float), cudaMemcpyDeviceToHost);
	cudaMemcpy( qr->d, d_diag, qr->width * sizeof(float), cudaMemcpyDeviceToHost);

	// Release memory on device
    cudaFree( d_qr );
	cudaFree( d_diag );
	cudaFree( d_norms );
    cudaThreadExit();
    return qr;
}



void run_cuda_qr_decomposition(int aHeight, int aWidth, int type, int blockDimension, bool cpu_calc)
{
    // Declare matrices and allocate memory
    QRmatrix *a = (QRmatrix*) malloc (sizeof(QRmatrix));
    a->size = aHeight*aWidth;
    a->width = aWidth;
    a->height = aHeight;
    a->n = (float*) malloc (sizeof(float)*a->size);
    a->d = (float*) malloc (sizeof(float)*a->height);
    a->hasPivot = false;
	
	// Allocate memory for vector values
    randomInit(a->n, a->size, 0, 9);
    printf("Running QR Decomposition\n\n");
    printf("A: %dx%d (%d)\n", a->height, a->width, a->size);
    output_matrix(a->n, a->height, a->width);
    printf("\n");
        
    // Run matrix multiplication on GPU
    printf("Running on GPU...");
    QRmatrix *qr;
	bool pivot = false;
	qr = gpu_qrd_optimised(a, blockDimension, 1, false);
}




int main(int argc, char **argv)
{
    
    int type = 1;
    bool cpu = true;
  
	// Arrays on GPU global memory
	float *d_a, *d_b, *d_result;

	// Arrays on the host memory
	float *h_a, *h_b, *h_result, *h_judge;

	int arrLen = SM_ARR_LEN;

	printf("Length of the array = %d\n", arrLen);

	// Allocate GPU memory
	size_t allocSize = arrLen * arrLen * sizeof(float);
	CUDA_SAFE_CALL(cudaMalloc((void **)&d_a, allocSize));
	CUDA_SAFE_CALL(cudaMalloc((void **)&d_b, allocSize));
	CUDA_SAFE_CALL(cudaMalloc((void **)&d_result, allocSize));
    
	// Allocate arrays on host memory
	h_a                    = (float *) malloc(allocSize);
	h_b                    = (float *) malloc(allocSize);
	h_result               = (float *) malloc(allocSize);
	h_judge                = (float *) malloc(allocSize);
	// Transfer the arrays to the GPU memory
	CUDA_SAFE_CALL(cudaMemcpy(d_a, h_a, allocSize, cudaMemcpyHostToDevice));
	CUDA_SAFE_CALL(cudaMemcpy(d_b, h_b, allocSize, cudaMemcpyHostToDevice));
	dim3 globalGrid(BLOCK, BLOCK, 1);
	dim3 globalBlock(THREAD, THREAD, 1);	    
	run_cuda_qr_decomposition(SM_ARR_LEN, SM_ARR_LEN, type, 20, cpu);
	cudaDeviceSynchronize();
	// Check for errors during launch
	CUDA_SAFE_CALL(cudaPeekAtLastError());
  return 0;
}


	.file	"tmpxft_0024de14_00000000-6_testbench_for_gpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA_SAFE_CALL: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPcib
	.type	_Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Matrix to big to be outputted..."
.LC2:
	.string	"M: %dx%d (%d)\n"
.LC3:
	.string	"\n"
.LC4:
	.string	"  "
.LC5:
	.string	"%f"
	.text
	.globl	_Z13output_matrixPfii
	.type	_Z13output_matrixPfii, @function
_Z13output_matrixPfii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%esi, %r13d
	imull	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%r10
	.cfi_def_cfa_offset 64
	cmpl	$64, %r13d
	jle	.L18
	movl	%esi, %ebx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	popq	%r9
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%r13d, %r8d
	movl	%r12d, %ecx
	movl	%ebx, %edx
	leaq	.LC2(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L18:
	.cfi_restore_state
	movq	%rdi, %r14
	xorl	%ebx, %ebx
	xorl	%r15d, %r15d
.L13:
	movl	%ebx, %eax
	cmpl	%ebx, %r13d
	jle	.L23
	cltd
	idivl	%r12d
	movl	%eax, %ebp
	cmpl	%eax, %r15d
	jge	.L14
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L15
.L14:
	testq	%rbx, %rbx
	je	.L16
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L16:
	movl	%r15d, %ebp
.L15:
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	movb	$1, %al
	movl	%ebp, %r15d
	cvtss2sd	(%r14,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L13
.L23:
	popq	%rdx
	.cfi_def_cfa_offset 56
	leaq	.LC3(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z13output_matrixPfii, .-_Z13output_matrixPfii
	.section	.rodata.str1.1
.LC6:
	.string	"\nD:\n"
.LC7:
	.string	"Total diagonale elements %d."
.LC8:
	.string	", "
	.text
	.globl	_Z16output_qr_matrixP8QRmatrix
	.type	_Z16output_qr_matrixP8QRmatrix, @function
_Z16output_qr_matrixP8QRmatrix:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC8(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	movl	16(%rdi), %edx
	movl	20(%rdi), %esi
	movq	(%rdi), %rdi
	call	_Z13output_matrixPfii
	xorl	%eax, %eax
	movl	$2, %edi
	leaq	.LC6(%rip), %rsi
	call	__printf_chk@PLT
	cmpl	$64, 24(%rbx)
	jbe	.L25
	movl	20(%rbx), %edx
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	jmp	.L26
.L28:
	testl	%ebp, %ebp
	je	.L27
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L27:
	movq	8(%rbx), %rax
	movl	%ebp, %edx
	movl	$2, %edi
	incl	%ebp
	leaq	.LC5(%rip), %rsi
	cvtss2sd	(%rax,%rdx,4), %xmm0
	movb	$1, %al
	call	__printf_chk@PLT
.L25:
	cmpl	20(%rbx), %ebp
	jb	.L28
.L26:
	popq	%rbx
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rsi
	popq	%rbp
	.cfi_def_cfa_offset 16
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z16output_qr_matrixP8QRmatrix, .-_Z16output_qr_matrixP8QRmatrix
	.globl	_Z10randomInitPfiff
	.type	_Z10randomInitPfiff, @function
_Z10randomInitPfiff:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	subss	%xmm0, %xmm1
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movss	%xmm1, 8(%rsp)
.L37:
	cmpl	%ebx, %ebp
	jle	.L40
	movss	%xmm0, 12(%rsp)
	call	rand@PLT
	movss	12(%rsp), %xmm0
	cvtsi2ssl	%eax, %xmm1
	mulss	.LC9(%rip), %xmm1
	mulss	8(%rsp), %xmm1
	addss	%xmm0, %xmm1
	movss	%xmm1, (%r12,%rbx,4)
	incq	%rbx
	jmp	.L37
.L40:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z10randomInitPfiff, .-_Z10randomInitPfiff
	.globl	_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii
	.type	_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii, @function
_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24qrd_optimised_calc_norm2PfS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L41:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii, .-_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii
	.globl	_Z24qrd_optimised_calc_norm2PfS_iii
	.type	_Z24qrd_optimised_calc_norm2PfS_iii, @function
_Z24qrd_optimised_calc_norm2PfS_iii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii
	.cfi_endproc
.LFE2062:
	.size	_Z24qrd_optimised_calc_norm2PfS_iii, .-_Z24qrd_optimised_calc_norm2PfS_iii
	.globl	_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi
	.type	_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi, @function
_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z27qrd_optimised_calc_norm2_L2Pfi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L46:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi, .-_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi
	.globl	_Z27qrd_optimised_calc_norm2_L2Pfi
	.type	_Z27qrd_optimised_calc_norm2_L2Pfi, @function
_Z27qrd_optimised_calc_norm2_L2Pfi:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi
	.cfi_endproc
.LFE2064:
	.size	_Z27qrd_optimised_calc_norm2_L2Pfi, .-_Z27qrd_optimised_calc_norm2_L2Pfi
	.globl	_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii
	.type	_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii, @function
_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L51:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii, .-_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii
	.globl	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.type	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, @function
_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii
	.cfi_endproc
.LFE2066:
	.size	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, .-_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.globl	_Z20calc_norm2_optimisedPfS_S_iii
	.type	_Z20calc_norm2_optimisedPfS_S_iii, @function
_Z20calc_norm2_optimisedPfS_S_iii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 8(%rsp)
	leaq	16(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movl	%r8d, %eax
	movl	$1, 32(%rsp)
	subl	%ecx, %eax
	movl	$128, %ecx
	addl	$127, %eax
	cltd
	idivl	%ecx
	movl	%eax, %esi
	movl	$33554433, %eax
	salq	$7, %rax
	movq	%rsi, %rbx
	salq	$2, %rsi
	movq	%rax, 24(%rsp)
	subq	$127, %rax
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	movl	%ebx, 36(%rsp)
	movl	32(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movl	44(%rsp), %esi
	movl	$512, %r8d
	movq	36(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r13d, %r8d
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z49__device_stub__Z24qrd_optimised_calc_norm2PfS_iiiPfS_iii
	jmp	.L58
.L61:
	movl	$1, %r12d
	cmpl	$128, %ebx
	jle	.L59
	leal	127(%rbx), %r12d
	sarl	$7, %r12d
.L59:
	movl	32(%rsp), %ecx
	movl	44(%rsp), %esi
	movl	%r12d, 36(%rsp)
	xorl	%r9d, %r9d
	movq	24(%rsp), %rdx
	movq	36(%rsp), %rdi
	movl	$512, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L60
	movq	16(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z48__device_stub__Z27qrd_optimised_calc_norm2_L2PfiPfi
.L60:
	movl	%r12d, %ebx
.L58:
	cmpl	$1, %ebx
	jg	.L61
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 68(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 60(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r13d, %r9d
	movl	%ebp, %r8d
	movq	%r15, %rcx
	movq	%r14, %rdx
	call	_Z59__device_stub__Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_iiPfS_S_S_ii
.L62:
	call	cudaThreadSynchronize@PLT
	movq	16(%rsp), %rsi
	leaq	60(%rsp), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	movl	$0x00000000, 60(%rsp)
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movss	60(%rsp), %xmm0
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z20calc_norm2_optimisedPfS_S_iii, .-_Z20calc_norm2_optimisedPfS_S_iii
	.globl	_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii
	.type	_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii, @function
_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26qrd_optimised_scale_columnPfS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L66:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L68
	call	__stack_chk_fail@PLT
.L68:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii, .-_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii
	.globl	_Z26qrd_optimised_scale_columnPfS_iii
	.type	_Z26qrd_optimised_scale_columnPfS_iii, @function
_Z26qrd_optimised_scale_columnPfS_iii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii
	.cfi_endproc
.LFE2068:
	.size	_Z26qrd_optimised_scale_columnPfS_iii, .-_Z26qrd_optimised_scale_columnPfS_iii
	.globl	_Z22scale_column_optimisedPfS_iii
	.type	_Z22scale_column_optimisedPfS_iii, @function
_Z22scale_column_optimisedPfS_iii:
.LFB2031:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%edx, %r14d
	xorl	%r9d, %r9d
	subl	%edx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%r8d, %r13d
	xorl	%r8d, %r8d
	addl	$127, %eax
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	cltd
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%ecx, %ebx
	movl	$128, %ecx
	idivl	%ecx
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	movl	$33554433, %edx
	movl	$1, %ecx
	salq	$7, %rdx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	movl	%r13d, %r8d
	movl	%ebx, %ecx
	movl	%r14d, %edx
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%r12, %rsi
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z51__device_stub__Z26qrd_optimised_scale_columnPfS_iiiPfS_iii
.L71:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z22scale_column_optimisedPfS_iii, .-_Z22scale_column_optimisedPfS_iii
	.globl	_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii
	.type	_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii, @function
_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z31qrd_optimised_transform_columnsPfiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L74:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii, .-_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii
	.globl	_Z31qrd_optimised_transform_columnsPfiii
	.type	_Z31qrd_optimised_transform_columnsPfiii, @function
_Z31qrd_optimised_transform_columnsPfiii:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii
	.cfi_endproc
.LFE2070:
	.size	_Z31qrd_optimised_transform_columnsPfiii, .-_Z31qrd_optimised_transform_columnsPfiii
	.globl	_Z27transform_columns_optimisedPfiii
	.type	_Z27transform_columns_optimisedPfiii, @function
_Z27transform_columns_optimisedPfiii:
.LFB2032:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%edx, %r13d
	xorl	%r9d, %r9d
	subl	%esi, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	movl	$2048, %r8d
	addl	$510, %eax
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%ecx, %ebp
	movl	$512, %ecx
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%esi, %ebx
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebp, %ecx
	movl	%r13d, %edx
	movl	%ebx, %esi
	movq	%r12, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z54__device_stub__Z31qrd_optimised_transform_columnsPfiiiPfiii
.L79:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z27transform_columns_optimisedPfiii, .-_Z27transform_columns_optimisedPfiii
	.section	.rodata.str1.1
.LC11:
	.string	"\n\nDecompose Partly Column=%d\n--------------\n"
.LC12:
	.string	"\nGPU time: %f (msec)\n"
	.text
	.globl	_Z17gpu_qrd_optimisedP8QRmatrixiib
	.type	_Z17gpu_qrd_optimisedP8QRmatrixiib, @function
_Z17gpu_qrd_optimisedP8QRmatrixiib:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movl	24(%rdi), %r15d
	movl	20(%rdi), %r13d
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movl	16(%rdi), %r12d
	movl	$40, %edi
	call	malloc@PLT
	movq	%r15, %r14
	movl	%r15d, 24(%rax)
	salq	$2, %r15
	movq	%rax, %rbx
	movl	%r13d, 20(%rax)
	movq	%r15, %rdi
	movl	%r12d, 16(%rax)
	call	malloc@PLT
	movl	%r13d, %edi
	movq	%rax, (%rbx)
	salq	$2, %rdi
	movq	%rdi, 8(%rsp)
	call	malloc@PLT
	movq	8(%rsp), %rdi
	movq	%rax, 8(%rbx)
	call	malloc@PLT
	movb	$0, 28(%rbx)
	movq	%r15, %rsi
	leaq	48(%rsp), %rdi
	movq	%rax, 32(%rbx)
	leaq	.LC11(%rip), %r15
	call	cudaMalloc@PLT
	movl	16(%rbx), %esi
	leaq	56(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	16(%rbx), %esi
	leaq	64(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	24(%rbp), %edx
	movq	0(%rbp), %rsi
	movl	$1, %ecx
	movq	48(%rsp), %rdi
	xorl	%ebp, %ebp
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L83:
	cmpl	%r12d, %ebp
	jge	.L92
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	%r12d, %r9d
	movl	%r13d, %r8d
	movq	48(%rsp), %rdi
	movl	%ebp, %ecx
	call	_Z20calc_norm2_optimisedPfS_S_iii
	movaps	%xmm0, %xmm1
	xorps	%xmm0, %xmm0
	ucomiss	%xmm0, %xmm1
	jp	.L90
	je	.L84
.L90:
	movq	64(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	%r12d, %r8d
	movl	%r13d, %ecx
	movl	%ebp, %edx
	call	_Z22scale_column_optimisedPfS_iii
	cmpl	$49, %r14d
	ja	.L86
	movl	24(%rbx), %edx
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	(%rbx), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	16(%rbx), %edx
	movq	8(%rbx), %rdi
	movl	$2, %ecx
	movq	56(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$2, %edi
	movl	%ebp, %edx
	xorl	%eax, %eax
	leaq	.LC11(%rip), %rsi
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	_Z16output_qr_matrixP8QRmatrix
.L86:
	movq	48(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%r13d, %edx
	movl	%ebp, %esi
	call	_Z27transform_columns_optimisedPfiii
.L84:
	cmpl	$49, %r14d
	ja	.L87
	movl	24(%rbx), %edx
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	(%rbx), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	16(%rbx), %edx
	movq	8(%rbx), %rdi
	movl	$2, %ecx
	movq	56(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	$2, %edi
	movl	%ebp, %edx
	movq	%r15, %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	_Z16output_qr_matrixP8QRmatrix
.L87:
	incl	%ebp
	jmp	.L83
.L92:
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	28(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movl	24(%rbx), %edx
	movq	(%rbx), %rdi
	movl	$2, %ecx
	movq	48(%rsp), %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	16(%rbx), %edx
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rbx), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaThreadExit@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L89
	call	__stack_chk_fail@PLT
.L89:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z17gpu_qrd_optimisedP8QRmatrixiib, .-_Z17gpu_qrd_optimisedP8QRmatrixiib
	.section	.rodata.str1.1
.LC14:
	.string	"Running QR Decomposition\n\n"
.LC15:
	.string	"A: %dx%d (%d)\n"
.LC16:
	.string	"Running on GPU..."
	.text
	.globl	_Z25run_cuda_qr_decompositioniiiib
	.type	_Z25run_cuda_qr_decompositioniiiib, @function
_Z25run_cuda_qr_decompositioniiiib:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%ecx, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	movl	$40, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ebp, %r14d
	pushq	%rax
	.cfi_def_cfa_offset 64
	imull	%r12d, %r14d
	call	malloc@PLT
	movl	%r14d, %edi
	movl	%r14d, 24(%rax)
	salq	$2, %rdi
	movq	%rax, %rbx
	movl	%r12d, 16(%rax)
	movl	%ebp, 20(%rax)
	call	malloc@PLT
	movl	%ebp, %edi
	movq	%rax, (%rbx)
	salq	$2, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movb	$0, 28(%rbx)
	xorps	%xmm0, %xmm0
	movl	%r14d, %esi
	movq	%rax, 8(%rbx)
	movss	.LC13(%rip), %xmm1
	movq	%r13, %rdi
	call	_Z10randomInitPfiff
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%r14d, %r8d
	movl	%r12d, %ecx
	movl	%ebp, %edx
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%r12d, %edx
	movl	%ebp, %esi
	movq	%r13, %rdi
	call	_Z13output_matrixPfii
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	popq	%r8
	.cfi_def_cfa_offset 56
	movl	%r15d, %esi
	movq	%rbx, %rdi
	xorl	%ecx, %ecx
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	$1, %edx
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z17gpu_qrd_optimisedP8QRmatrixiib
	.cfi_endproc
.LFE2035:
	.size	_Z25run_cuda_qr_decompositioniiiib, .-_Z25run_cuda_qr_decompositioniiiib
	.section	.rodata.str1.1
.LC17:
	.string	"Length of the array = %d\n"
.LC18:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/shibaeff/EC527_Project_QR/master/QR/GPU_code/testbench_for_gpu.cu"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1024, %edx
	movl	$2, %edi
	leaq	.LC17(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	.LC18(%rip), %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rsp, %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$444, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$445, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$446, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	movl	$4194304, %edi
	call	malloc@PLT
	movl	$4194304, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4194304, %edx
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$454, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$4194304, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$455, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	movl	$20, %ecx
	movl	$1, %edx
	movl	$1024, %esi
	movl	$1024, %edi
	movl	$1, %r8d
	call	_Z25run_cuda_qr_decompositioniiiib
	call	cudaDeviceSynchronize@PLT
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$461, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPcib
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L96
	call	__stack_chk_fail@PLT
.L96:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	main, .-main
	.section	.rodata.str1.1
.LC19:
	.string	"_Z31qrd_optimised_transform_columnsPfiii"
.LC20:
	.string	"_Z26qrd_optimised_scale_columnPfS_iii"
.LC21:
	.string	"_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii"
.LC22:
	.string	"_Z27qrd_optimised_calc_norm2_L2Pfi"
.LC23:
	.string	"_Z24qrd_optimised_calc_norm2PfS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2072:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z31qrd_optimised_transform_columnsPfiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26qrd_optimised_scale_columnPfS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z27qrd_optimised_calc_norm2_L2Pfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24qrd_optimised_calc_norm2PfS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2072:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC9:
	.long	805306368
	.align 4
.LC13:
	.long	1091567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>


#define GIG 1000000000
#define PRINT_TIME 1
#define BLOCK 32 //blockDim
#define THREAD 32
#define SM_ARR_LEN 1024 //size of the matrix
#define THREADS_PER_BLOCK 64
#define THREADS_PER_DIM 16
#define TILING_DIM 20
#define MAX_MATRIX_SIZE_FOR_OUTPUT 64
#define QRD_SIMPLE_CALC_NORM2 128
#define QRD_SIMPLE_SCALE_COLUMN 128
#define QRD_SIMPLE_TRANSFORM_COLUMNS 128
#define QRD_OPTIMISED_NORM2_BLOCKSIZE 128
#define QRD_OPTIMISED_SCALE_COLUMN 128
#define QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM 512
#define IMUL(a, b) __mul24(a, b)

// Assertion to check for errors
#define CUDA_SAFE_CALL(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
  if (code != hipSuccess) 
  {
    fprintf(stderr,"CUDA_SAFE_CALL: %s %s %d\n", hipGetErrorString(code), file, line);
    if (abort) exit(code);
  }
}



typedef struct
{
    float *n; // Length: size = width*height
    float *d; // Length: height
    unsigned int width;
    unsigned int height;
    unsigned int size;
    bool hasPivot;
    int *pivot; // Length: height
} QRmatrix;



__global__ void qrd_optimised_calc_norm2(float *out_norms, float *qr, int k, int m, int n)
{
	// Shared memory
	extern __shared__ float s_qr[];
    unsigned int r = blockIdx.x * blockDim.x + threadIdx.x + k; // Get row index
	// Clear cache for threads that exceeds max + they should not influence result
	s_qr[threadIdx.x] = 0;
	if (r < m)
	{
		// Read value to shared memory
		float val = qr[r * n + k];
		s_qr[threadIdx.x] = val * val;

		// Sync threads to make sure all other also have loaded values
		__syncthreads();

		// Do the actual pivot finding
		for(unsigned int stride = blockDim.x/2; stride>0; stride>>=1)
		{
			if (threadIdx.x < stride && (stride+threadIdx.x+k) < m)
			{
				s_qr[threadIdx.x] += s_qr[threadIdx.x + stride]; // Update value
			}

			// Sync threads
			__syncthreads();
		}
		// The first thread should write result from block to output
		if (threadIdx.x == 0)
		{
			out_norms[blockIdx.x] = s_qr[0]; // Load sum to output
		}
	}
}
__global__ void qrd_optimised_calc_norm2_L2(float *val_norms, int max)
{
	// Shared memory
	extern __shared__ float s_qr[];
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	// Clear cache for threads that exceeds max + they should not influence result
	s_qr[threadIdx.x] = 0;
	if (tid < max)
	{
		// Read value to shared memory
		s_qr[threadIdx.x] = val_norms[tid];
		// Sync threads to make sure all other also have loaded values
		__syncthreads();
		// Do the actual pivot finding
		for(unsigned int stride = blockDim.x/2; stride>0; stride>>=1)
		{
			if (threadIdx.x < stride)
			{
				s_qr[threadIdx.x] += s_qr[threadIdx.x + stride]; // Update value
			}

			// Sync threads
			__syncthreads();
		}
		// The first thread should write result from block to output
		if (threadIdx.x == 0)
		{
			val_norms[blockIdx.x] = s_qr[0]; // Load sum to output
		}
	}
}
__global__ void qrd_optimised_calc_norm2_FINISH(float *val_norms, float *qr, float *qr_diag, float *qr_norms, int k, int n)
{
	// Square root to get raw norm
	float nrm = sqrtf(val_norms[0]);

	// Flip sign for norm depending on the value of kth row kth column
	nrm = qr[k * n + k] < 0 ? -nrm : nrm;

	// Save the actual norm
	val_norms[0] = nrm;
	qr_norms[k] = nrm;

	// Flip sign for norm and save to QR diagonale
	qr_diag[k] = -nrm;
}


float calc_norm2_optimised(float *d_qr, float *d_diag, float *d_norms, int k, int m, int n)
{
	int threads = m-k;
    int blocks = (threads + QRD_OPTIMISED_NORM2_BLOCKSIZE-1) / QRD_OPTIMISED_NORM2_BLOCKSIZE;

	dim3 dimBlock(QRD_OPTIMISED_NORM2_BLOCKSIZE, 1, 1);
    dim3 dimGrid(blocks, 1, 1);
    int smemSize = QRD_OPTIMISED_NORM2_BLOCKSIZE*sizeof(float);

	float *d_out;

	hipMalloc( (void**) &d_out, sizeof(float) * dimGrid.x);

	// First run on a, subsequential will be on d_out
	qrd_optimised_calc_norm2<<< dimGrid, dimBlock, smemSize >>>(d_out, d_qr, k, m, n);

	while(blocks > 1)
	{
		// Adjust the number of required blocks, for the second round
		threads = blocks;
		blocks = threads > QRD_OPTIMISED_NORM2_BLOCKSIZE
			? (threads + QRD_OPTIMISED_NORM2_BLOCKSIZE-1) / QRD_OPTIMISED_NORM2_BLOCKSIZE
			: 1;

		dimGrid.x = blocks;	
		qrd_optimised_calc_norm2_L2<<< dimGrid, dimBlock, smemSize >>>(d_out, threads);
	}
	
	qrd_optimised_calc_norm2_FINISH<<< 1, 1 >>>(d_out, d_qr, d_diag, d_norms, k, n);
	hipDeviceSynchronize();
	float norm = 0.0;
	hipMemcpy( &norm, d_out, sizeof(float), hipMemcpyDeviceToHost);
	hipFree( d_out );
	return norm;
}

void output_matrix(float *m, int height, int width) {

    int size = height*width;
    if (size > MAX_MATRIX_SIZE_FOR_OUTPUT) 
	{
        printf("Matrix to big to be outputted...");
        printf("M: %dx%d (%d)\n", height, width, size);
        return;
    }
    
    int row = 0;
    
    for(int i = 0; i < size; i++) 
	{
        int curRow = i/width;
        //int curCol = i%m->width;
        if (curRow > row) 
		{
            printf("\n");
            row = curRow;
        }
        else if (i > 0) 
		{
            printf("  ");
        }       
        printf("%f", m[i] );
    }  
    printf("\n");
}

void output_qr_matrix(QRmatrix *m)
{
	output_matrix(m->n, m->height, m->width);
	printf("\nD:\n");
	if (m->size > MAX_MATRIX_SIZE_FOR_OUTPUT)
	{
		printf("Total diagonale elements %d.", m->height);
	}
	else
	{
		for(unsigned int i = 0; i < m->height; i++)
		{
			if (i > 0) printf(", ");
			printf("%f", m->d[i] );
		}
	}
	printf("\n");
}


__global__ void qrd_optimised_scale_column(float *qr, float *qr_norms, int k, int m, int n)
{
	float norm = qr_norms[k];
	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int r = k + tid;
	if (r < m)
	{
		qr[r * n + k] /= norm;
	}
	if (tid == 0)
	{
		qr[k * n + k] += 1.0;
	}
}



__global__ void qrd_optimised_transform_columns(float *qr, int k, int m, int n)
{
	// Declare cache
    extern __shared__ float v[];

	// Apply transformation to remaining columns.
	int c = blockIdx.x * blockDim.x + threadIdx.x + k + 1;
	if (c < n)
	{
		float s = 0.0, knk = qr[k * n + k];
		for (int i = k; i < m;)
        {
			// Guard for not exceeding height of QR matrix + load k column values to shared memory
			v[threadIdx.x] = i+threadIdx.x < m ? qr[(i+threadIdx.x) * n + k] : 0;
			__syncthreads();
			// For all k values loaded, calc s
			for(int vi = 0; vi < blockDim.y; vi++, i++)
				s += v[vi] * qr[i * n + c];
        }
		s = (-s) / knk;
		for (int i = k; i < m;)
        {
			// Guard for not exceeding height of QR matrix + load k column values to shared memory
			v[threadIdx.x] = i+threadIdx.x < m ? qr[(i+threadIdx.x) * n + k] : 0;
			__syncthreads();
			// For all k values loaded, calc s
			for(int vi = 0; vi < blockDim.y; vi++, i++)
				qr[i * n + c] += s * v[vi];
        }
	}
}


void scale_column_optimised(float *d_qr, float *d_norms, int k, int m, int n)
{
	int threads = m-k;
    int blocks = (threads + QRD_OPTIMISED_SCALE_COLUMN-1) / QRD_OPTIMISED_SCALE_COLUMN;
	qrd_optimised_scale_column<<< blocks, QRD_OPTIMISED_SCALE_COLUMN >>>( d_qr, d_norms, k, m, n );
}



void transform_columns_optimised(float *d_qr, int k, int m, int n)
{
	int threads = n-(k+1);
    int blocks = (threads + QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM-1) / QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM;
	dim3 dimBlock(QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM, 1, 1);
    dim3 dimGrid(blocks, 1, 1);
    int smemSize = QRD_OPTIMISED_TRANSFORM_COLUMNS_DIM*sizeof(float);
	qrd_optimised_transform_columns<<< dimGrid, dimBlock, smemSize >>>( d_qr, k, m, n );
}

void randomInit(float* data, int size, float min, float max)
{   
    const float range = (max - min);    
    for (int i = 0; i < size; ++i) 
	{
        float rnd = rand()/(float)RAND_MAX; // Generate random value from 0.0 to 1.0
        data[i] = rnd*range + min;
    }
}



QRmatrix* gpu_qrd_optimised(QRmatrix *a, int blockDimension, int version, bool usePivot) 
{
  // GPU Timing variables
	hipEvent_t start, stop;
	float elapsed_gpu;
	bool output = a->size < 50;
	int n = a->width;
	int m = a->height;
    
    QRmatrix *qr = (QRmatrix*) malloc (sizeof(QRmatrix));
    qr->height = a->height;
    qr->size = a->size;
    qr->width = a->width;
    qr->n = (float*) malloc (sizeof(float)*a->size);
    qr->d = (float*) malloc (sizeof(float)*a->height);
    qr->pivot = (int*) malloc (sizeof(int)*a->height);
    qr->hasPivot = false;

	// Check if block dimension is too big
	if (blockDimension > (int)a->width) blockDimension = a->width;


    // Declare kernel pointers
    float *d_qr, *d_diag, *d_norms; // QR + Diagonale + Norms
    
    // Allocate memory on GPU for LU matrix
    hipMalloc( (void**) &d_qr, sizeof(float) * qr->size );
    hipMalloc( (void**) &d_diag, sizeof(float) * qr->width );
    hipMalloc( (void**) &d_norms, sizeof(float) * qr->width );
	

    // Copy matrix A vector values to the QR pointer on the GPU/device = A copy to QR (will be modified)
    hipMemcpy( d_qr, a->n, sizeof(float) * a->size, hipMemcpyHostToDevice);

    #if PRINT_TIME
	// Create the cuda events
	hipEventCreate(&start);
	hipEventCreate(&stop);
	// Record event on the default stream
	hipEventRecord(start, 0);
	#endif
	// Execute kernels
	// Optimised QR
	// Core algorithm for QR Decomposition
	for (int k = 0; k < n; k++) // For each column
    {
        // Compute 2-norm of k-th column
		float nrm = calc_norm2_optimised(d_qr, d_diag, d_norms, k, m, n);
        if (nrm != 0.0)
        {
            // Form k-th Householder vector. (Performed on device)
			scale_column_optimised(d_qr, d_norms, k, m, n);

			if (output)
			{
				hipMemcpy( qr->n, d_qr, qr->size * sizeof(float), hipMemcpyDeviceToHost);
				hipMemcpy( qr->d, d_diag, qr->width * sizeof(float), hipMemcpyDeviceToHost);
				printf("\n\nDecompose Partly Column=%d\n--------------\n", k);
				output_qr_matrix(qr);
			}
            // Apply transformation to remaining columns.
			transform_columns_optimised(d_qr, k, m, n);
        }

		if (output)
		{
			hipMemcpy( qr->n, d_qr, qr->size * sizeof(float), hipMemcpyDeviceToHost);
			hipMemcpy( qr->d, d_diag, qr->width * sizeof(float), hipMemcpyDeviceToHost);	
			printf("\n\nDecompose Partly Column=%d\n--------------\n", k);
			output_qr_matrix(qr);
		}
    }
    hipDeviceSynchronize();
	#if PRINT_TIME
	// Stop and destroy the timer
	hipEventRecord(stop,0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsed_gpu, start, stop);
	printf("\nGPU time: %f (msec)\n", elapsed_gpu);
	hipEventDestroy(start);
	hipEventDestroy(stop);
	#endif
    
    // Copy matrix members + value vector to host;
	hipMemcpy( qr->n, d_qr, qr->size * sizeof(float), hipMemcpyDeviceToHost);
	hipMemcpy( qr->d, d_diag, qr->width * sizeof(float), hipMemcpyDeviceToHost);

	// Release memory on device
    hipFree( d_qr );
	hipFree( d_diag );
	hipFree( d_norms );
    hipDeviceReset();
    return qr;
}



void run_cuda_qr_decomposition(int aHeight, int aWidth, int type, int blockDimension, bool cpu_calc)
{
    // Declare matrices and allocate memory
    QRmatrix *a = (QRmatrix*) malloc (sizeof(QRmatrix));
    a->size = aHeight*aWidth;
    a->width = aWidth;
    a->height = aHeight;
    a->n = (float*) malloc (sizeof(float)*a->size);
    a->d = (float*) malloc (sizeof(float)*a->height);
    a->hasPivot = false;
	
	// Allocate memory for vector values
    randomInit(a->n, a->size, 0, 9);
    printf("Running QR Decomposition\n\n");
    printf("A: %dx%d (%d)\n", a->height, a->width, a->size);
    output_matrix(a->n, a->height, a->width);
    printf("\n");
        
    // Run matrix multiplication on GPU
    printf("Running on GPU...");
    QRmatrix *qr;
	bool pivot = false;
	qr = gpu_qrd_optimised(a, blockDimension, 1, false);
}




int main(int argc, char **argv)
{
    
    int type = 1;
    bool cpu = true;
  
	// Arrays on GPU global memory
	float *d_a, *d_b, *d_result;

	// Arrays on the host memory
	float *h_a, *h_b, *h_result, *h_judge;

	int arrLen = SM_ARR_LEN;

	printf("Length of the array = %d\n", arrLen);

	// Allocate GPU memory
	size_t allocSize = arrLen * arrLen * sizeof(float);
	CUDA_SAFE_CALL(hipMalloc((void **)&d_a, allocSize));
	CUDA_SAFE_CALL(hipMalloc((void **)&d_b, allocSize));
	CUDA_SAFE_CALL(hipMalloc((void **)&d_result, allocSize));
    
	// Allocate arrays on host memory
	h_a                    = (float *) malloc(allocSize);
	h_b                    = (float *) malloc(allocSize);
	h_result               = (float *) malloc(allocSize);
	h_judge                = (float *) malloc(allocSize);
	// Transfer the arrays to the GPU memory
	CUDA_SAFE_CALL(hipMemcpy(d_a, h_a, allocSize, hipMemcpyHostToDevice));
	CUDA_SAFE_CALL(hipMemcpy(d_b, h_b, allocSize, hipMemcpyHostToDevice));
	dim3 globalGrid(BLOCK, BLOCK, 1);
	dim3 globalBlock(THREAD, THREAD, 1);	    
	run_cuda_qr_decomposition(SM_ARR_LEN, SM_ARR_LEN, type, 20, cpu);
	hipDeviceSynchronize();
	// Check for errors during launch
	CUDA_SAFE_CALL(hipPeekAtLastError());
  return 0;
}


	.text
	.file	"testbench_for_gpu.hip"
	.globl	_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii # -- Begin function _Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
	.type	_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii,@function
_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii: # @_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24qrd_optimised_calc_norm2PfS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii, .Lfunc_end0-_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi # -- Begin function _Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
	.type	_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi,@function
_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi: # @_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27qrd_optimised_calc_norm2_L2Pfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi, .Lfunc_end1-_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii # -- Begin function _Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.type	_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii,@function
_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii: # @_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, .Lfunc_end2-_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z20calc_norm2_optimisedPfS_S_iii # -- Begin function _Z20calc_norm2_optimisedPfS_S_iii
	.type	_Z20calc_norm2_optimisedPfS_S_iii,@function
_Z20calc_norm2_optimisedPfS_S_iii:      # @_Z20calc_norm2_optimisedPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 20(%rsp)                  # 4-byte Spill
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movabsq	$4294967296, %r13               # imm = 0x100000000
	movl	%r8d, %r14d
	subl	%ecx, %r14d
	leal	127(%r14), %r12d
	addl	$254, %r14d
	testl	%r12d, %r12d
	cmovnsl	%r12d, %r14d
	sarl	$7, %r14d
	movq	%r14, %rbx
	btsq	$32, %rbx
	leaq	(,%r14,4), %rsi
	leaq	8(%rsp), %rdi
	callq	hipMalloc
	leaq	128(%r13), %rdx
	movl	$512, %r8d                      # imm = 0x200
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	%ebp, %edx
	movl	%r15d, %ecx
	movl	20(%rsp), %r8d                  # 4-byte Reload
	callq	_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
.LBB3_2:
	cmpl	$256, %r12d                     # imm = 0x100
	jl	.LBB3_7
# %bb.3:                                # %.lr.ph.preheader
	leaq	128(%r13), %r15
.LBB3_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	leal	127(%r14), %ebx
	shrl	$7, %ebx
	cmpl	$129, %r14d
	movl	$1, %r12d
	cmovael	%ebx, %r12d
	movq	%r12, %rdi
	orq	%r13, %rdi
	movl	$512, %r8d                      # imm = 0x200
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=1
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	callq	_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
.LBB3_6:                                #   in Loop: Header=BB3_4 Depth=1
	movl	%ebx, %r14d
	cmpl	$1, %r12d
	ja	.LBB3_4
.LBB3_7:                                # %._crit_edge
	incq	%r13
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_9
# %bb.8:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movq	40(%rsp), %rcx                  # 8-byte Reload
	movl	%ebp, %r8d
	movl	20(%rsp), %r9d                  # 4-byte Reload
	callq	_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
.LBB3_9:
	callq	hipDeviceSynchronize
	leaq	52(%rsp), %rbx
	movl	$0, (%rbx)
	movq	8(%rsp), %rsi
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z20calc_norm2_optimisedPfS_S_iii, .Lfunc_end3-_Z20calc_norm2_optimisedPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z13output_matrixPfii           # -- Begin function _Z13output_matrixPfii
	.type	_Z13output_matrixPfii,@function
_Z13output_matrixPfii:                  # @_Z13output_matrixPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%edx, %ebp
	imull	%esi, %ebp
	cmpl	$64, %ebp
	jle	.LBB4_1
# %bb.5:
	movl	%esi, %r15d
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	movl	%ebp, %ecx
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	printf                          # TAILCALL
.LBB4_1:                                # %.preheader
	.cfi_def_cfa_offset 64
	testl	%ebp, %ebp
	jle	.LBB4_9
# %bb.2:                                # %.lr.ph.preheader
	movq	%rdi, %r14
	movl	%ebp, %r12d
	xorl	%r15d, %r15d
	xorl	%r13d, %r13d
.LBB4_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	cltd
	idivl	%ebx
	cmpl	%r13d, %eax
	jle	.LBB4_6
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=1
	movl	%eax, %ebp
	movl	$10, %edi
	callq	putchar@PLT
	movl	%ebp, %r13d
	jmp	.LBB4_8
.LBB4_6:                                #   in Loop: Header=BB4_3 Depth=1
	testq	%r15, %r15
	je	.LBB4_8
# %bb.7:                                #   in Loop: Header=BB4_3 Depth=1
	movl	$.L.str.3, %edi
	xorl	%eax, %eax
	callq	printf
.LBB4_8:                                #   in Loop: Header=BB4_3 Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB4_3
.LBB4_9:                                # %._crit_edge
	movl	$10, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end4:
	.size	_Z13output_matrixPfii, .Lfunc_end4-_Z13output_matrixPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z16output_qr_matrixP8QRmatrix  # -- Begin function _Z16output_qr_matrixP8QRmatrix
	.type	_Z16output_qr_matrixP8QRmatrix,@function
_Z16output_qr_matrixP8QRmatrix:         # @_Z16output_qr_matrixP8QRmatrix
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	movq	(%rdi), %rdi
	movl	20(%rbx), %esi
	movl	16(%rbx), %edx
	callq	_Z13output_matrixPfii
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	20(%rbx), %esi
	cmpl	$64, 24(%rbx)
	jbe	.LBB5_1
# %bb.7:
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	jmp	.LBB5_6
.LBB5_1:                                # %.preheader
	testl	%esi, %esi
	je	.LBB5_6
# %bb.2:                                # %.lr.ph
	xorl	%r14d, %r14d
.LBB5_3:                                # =>This Inner Loop Header: Depth=1
	testq	%r14, %r14
	je	.LBB5_5
# %bb.4:                                #   in Loop: Header=BB5_3 Depth=1
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
.LBB5_5:                                #   in Loop: Header=BB5_3 Depth=1
	movq	8(%rbx), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r14,4), %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	incq	%r14
	movl	20(%rbx), %eax
	cmpq	%rax, %r14
	jb	.LBB5_3
.LBB5_6:                                # %.loopexit
	movl	$10, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end5:
	.size	_Z16output_qr_matrixP8QRmatrix, .Lfunc_end5-_Z16output_qr_matrixP8QRmatrix
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__qrd_optimised_scale_columnPfS_iii # -- Begin function _Z41__device_stub__qrd_optimised_scale_columnPfS_iii
	.type	_Z41__device_stub__qrd_optimised_scale_columnPfS_iii,@function
_Z41__device_stub__qrd_optimised_scale_columnPfS_iii: # @_Z41__device_stub__qrd_optimised_scale_columnPfS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26qrd_optimised_scale_columnPfS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z41__device_stub__qrd_optimised_scale_columnPfS_iii, .Lfunc_end6-_Z41__device_stub__qrd_optimised_scale_columnPfS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z46__device_stub__qrd_optimised_transform_columnsPfiii # -- Begin function _Z46__device_stub__qrd_optimised_transform_columnsPfiii
	.type	_Z46__device_stub__qrd_optimised_transform_columnsPfiii,@function
_Z46__device_stub__qrd_optimised_transform_columnsPfiii: # @_Z46__device_stub__qrd_optimised_transform_columnsPfiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z31qrd_optimised_transform_columnsPfiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z46__device_stub__qrd_optimised_transform_columnsPfiii, .Lfunc_end7-_Z46__device_stub__qrd_optimised_transform_columnsPfiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22scale_column_optimisedPfS_iii # -- Begin function _Z22scale_column_optimisedPfS_iii
	.type	_Z22scale_column_optimisedPfS_iii,@function
_Z22scale_column_optimisedPfS_iii:      # @_Z22scale_column_optimisedPfS_iii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	%ecx, %edi
	subl	%edx, %edi
	leal	127(%rdi), %eax
	addl	$254, %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$7, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$128, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movl	%r14d, %edx
	movl	%ebp, %ecx
	movl	%ebx, %r8d
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z41__device_stub__qrd_optimised_scale_columnPfS_iii # TAILCALL
.Lfunc_end8:
	.size	_Z22scale_column_optimisedPfS_iii, .Lfunc_end8-_Z22scale_column_optimisedPfS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27transform_columns_optimisedPfiii # -- Begin function _Z27transform_columns_optimisedPfiii
	.type	_Z27transform_columns_optimisedPfiii,@function
_Z27transform_columns_optimisedPfiii:   # @_Z27transform_columns_optimisedPfiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %ebp
	movl	%esi, %r14d
	movq	%rdi, %r15
	movl	%ecx, %edi
	subl	%esi, %edi
	leal	510(%rdi), %eax
	addl	$1021, %edi                     # imm = 0x3FD
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$2048, %r8d                     # imm = 0x800
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB9_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB9_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z46__device_stub__qrd_optimised_transform_columnsPfiii # TAILCALL
.Lfunc_end9:
	.size	_Z27transform_columns_optimisedPfiii, .Lfunc_end9-_Z27transform_columns_optimisedPfiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z10randomInitPfiff
.LCPI10_0:
	.long	0x30000000                      # float 4.65661287E-10
	.text
	.globl	_Z10randomInitPfiff
	.type	_Z10randomInitPfiff,@function
_Z10randomInitPfiff:                    # @_Z10randomInitPfiff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	testl	%esi, %esi
	jle	.LBB10_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%rdi, %rbx
	movss	8(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	subss	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB10_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI10_0(%rip), %xmm0
	mulss	8(%rsp), %xmm0                  # 4-byte Folded Reload
	addss	12(%rsp), %xmm0                 # 4-byte Folded Reload
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB10_2
.LBB10_3:                               # %._crit_edge
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z10randomInitPfiff, .Lfunc_end10-_Z10randomInitPfiff
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z17gpu_qrd_optimisedP8QRmatrixiib
.LCPI11_0:
	.long	0x00000000                      # float 0
	.text
	.globl	_Z17gpu_qrd_optimisedP8QRmatrixiib
	.type	_Z17gpu_qrd_optimisedP8QRmatrixiib,@function
_Z17gpu_qrd_optimisedP8QRmatrixiib:     # @_Z17gpu_qrd_optimisedP8QRmatrixiib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, 72(%rsp)                  # 8-byte Spill
	movl	24(%rdi), %r14d
	movl	16(%rdi), %ebp
	movl	20(%rdi), %r15d
	movl	$40, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	%r15d, 20(%rax)
	movl	%r14d, 24(%rax)
	movl	%ebp, 16(%rax)
	movq	%r14, %r12
	shlq	$2, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%rax, (%rbx)
	movq	%r15, %r13
	shlq	$2, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	%rax, 8(%rbx)
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 32(%rbx)
	movb	$0, 28(%rbx)
	leaq	8(%rsp), %rdi
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	callq	hipMalloc
	movq	%rbp, %r13
	shlq	$2, %r13
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	72(%rsp), %rax                  # 8-byte Reload
	movq	(%rax), %rsi
	movl	24(%rax), %edx
	shlq	$2, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%ebp, %ebp
	jle	.LBB11_9
# %bb.1:                                # %.lr.ph.preheader
	xorl	%r12d, %r12d
.LBB11_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	%r12d, %ecx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	callq	_Z20calc_norm2_optimisedPfS_S_iii
	ucomiss	.LCPI11_0(%rip), %xmm0
	jne	.LBB11_3
	jnp	.LBB11_6
.LBB11_3:                               #   in Loop: Header=BB11_2 Depth=1
	movq	8(%rsp), %rdi
	movq	56(%rsp), %rsi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	callq	_Z22scale_column_optimisedPfS_iii
	cmpl	$49, %r14d
	ja	.LBB11_5
# %bb.4:                                #   in Loop: Header=BB11_2 Depth=1
	movq	8(%rsp), %rsi
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	callq	_Z16output_qr_matrixP8QRmatrix
.LBB11_5:                               #   in Loop: Header=BB11_2 Depth=1
	movq	8(%rsp), %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z27transform_columns_optimisedPfiii
.LBB11_6:                               #   in Loop: Header=BB11_2 Depth=1
	cmpl	$49, %r14d
	ja	.LBB11_8
# %bb.7:                                #   in Loop: Header=BB11_2 Depth=1
	movq	8(%rsp), %rsi
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	callq	_Z16output_qr_matrixP8QRmatrix
.LBB11_8:                               #   in Loop: Header=BB11_2 Depth=1
	incl	%r12d
	cmpl	%r12d, %ebp
	jne	.LBB11_2
.LBB11_9:                               # %._crit_edge
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	64(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	84(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movq	64(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rsi
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movq	48(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	movq	%rbx, %rax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z17gpu_qrd_optimisedP8QRmatrixiib, .Lfunc_end11-_Z17gpu_qrd_optimisedP8QRmatrixiib
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z25run_cuda_qr_decompositioniiiib
.LCPI12_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI12_1:
	.long	0x41100000                      # float 9
.LCPI12_2:
	.long	0x00000000                      # float 0
	.text
	.globl	_Z25run_cuda_qr_decompositioniiiib
	.type	_Z25run_cuda_qr_decompositioniiiib,@function
_Z25run_cuda_qr_decompositioniiiib:     # @_Z25run_cuda_qr_decompositioniiiib
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movl	%edi, %r14d
	movl	$40, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	%ebp, %r15d
	imull	%r14d, %r15d
	movl	%r15d, 24(%rax)
	movl	%ebp, 16(%rax)
	movl	%r14d, 20(%rax)
	leaq	(,%r15,4), %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rax, (%rbx)
	movl	%r14d, %edi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, 8(%rbx)
	movb	$0, 28(%rbx)
	testl	%r15d, %r15d
	jle	.LBB12_3
# %bb.1:                                # %.lr.ph.i.preheader
	xorl	%r13d, %r13d
.LBB12_2:                               # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI12_0(%rip), %xmm0
	mulss	.LCPI12_1(%rip), %xmm0
	addss	.LCPI12_2(%rip), %xmm0
	movss	%xmm0, (%r12,%r13,4)
	incq	%r13
	cmpq	%r13, %r15
	jne	.LBB12_2
.LBB12_3:                               # %_Z10randomInitPfiff.exit
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.L.str.11, %edi
	movl	%r14d, %esi
	movl	%ebp, %edx
	movl	%r15d, %ecx
	xorl	%eax, %eax
	callq	printf
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%ebp, %edx
	callq	_Z13output_matrixPfii
	movl	$10, %edi
	callq	putchar@PLT
	movl	$.L.str.12, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	xorl	%ecx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z17gpu_qrd_optimisedP8QRmatrixiib # TAILCALL
.Lfunc_end12:
	.size	_Z25run_cuda_qr_decompositioniiiib, .Lfunc_end12-_Z25run_cuda_qr_decompositioniiiib
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$.L.str.13, %edi
	movl	$1024, %esi                     # imm = 0x400
	xorl	%eax, %eax
	callq	printf
	leaq	8(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB13_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPcib.exit
	movq	%rsp, %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB13_4
# %bb.5:                                # %_Z9gpuAssert10hipError_tPcib.exit16
	leaq	16(%rsp), %rdi
	movl	$4194304, %esi                  # imm = 0x400000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB13_6
# %bb.7:                                # %_Z9gpuAssert10hipError_tPcib.exit18
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %rbx
	movl	$4194304, %edi                  # imm = 0x400000
	callq	malloc
	movq	%rax, %r14
	movq	8(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB13_8
# %bb.9:                                # %_Z9gpuAssert10hipError_tPcib.exit20
	movq	(%rsp), %rdi
	movl	$4194304, %edx                  # imm = 0x400000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB13_10
# %bb.11:                               # %_Z9gpuAssert10hipError_tPcib.exit22
	movl	$1024, %edi                     # imm = 0x400
	movl	$1024, %esi                     # imm = 0x400
	xorl	%r8d, %r8d
	callq	_Z25run_cuda_qr_decompositioniiiib
	callq	hipDeviceSynchronize
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB13_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPcib.exit24
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB13_1:
	.cfi_def_cfa_offset 48
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$446, %r8d                      # imm = 0x1BE
	jmp	.LBB13_2
.LBB13_4:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$447, %r8d                      # imm = 0x1BF
	jmp	.LBB13_2
.LBB13_6:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$448, %r8d                      # imm = 0x1C0
	jmp	.LBB13_2
.LBB13_8:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$456, %r8d                      # imm = 0x1C8
	jmp	.LBB13_2
.LBB13_10:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$457, %r8d                      # imm = 0x1C9
	jmp	.LBB13_2
.LBB13_12:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %esi
	movl	$.L.str.14, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$463, %r8d                      # imm = 0x1CF
.LBB13_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end13:
	.size	main, .Lfunc_end13-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB14_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB14_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24qrd_optimised_calc_norm2PfS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27qrd_optimised_calc_norm2_L2Pfi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26qrd_optimised_scale_columnPfS_iii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z31qrd_optimised_transform_columnsPfiii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end14:
	.size	__hip_module_ctor, .Lfunc_end14-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB15_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB15_2:
	retq
.Lfunc_end15:
	.size	__hip_module_dtor, .Lfunc_end15-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24qrd_optimised_calc_norm2PfS_iii,@object # @_Z24qrd_optimised_calc_norm2PfS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z24qrd_optimised_calc_norm2PfS_iii
	.p2align	3, 0x0
_Z24qrd_optimised_calc_norm2PfS_iii:
	.quad	_Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
	.size	_Z24qrd_optimised_calc_norm2PfS_iii, 8

	.type	_Z27qrd_optimised_calc_norm2_L2Pfi,@object # @_Z27qrd_optimised_calc_norm2_L2Pfi
	.globl	_Z27qrd_optimised_calc_norm2_L2Pfi
	.p2align	3, 0x0
_Z27qrd_optimised_calc_norm2_L2Pfi:
	.quad	_Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
	.size	_Z27qrd_optimised_calc_norm2_L2Pfi, 8

	.type	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii,@object # @_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.globl	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.p2align	3, 0x0
_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii:
	.quad	_Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.size	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Matrix to big to be outputted..."
	.size	.L.str, 33

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"M: %dx%d (%d)\n"
	.size	.L.str.1, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"  "
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%f"
	.size	.L.str.4, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Total diagonale elements %d."
	.size	.L.str.6, 29

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	", "
	.size	.L.str.7, 3

	.type	_Z26qrd_optimised_scale_columnPfS_iii,@object # @_Z26qrd_optimised_scale_columnPfS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z26qrd_optimised_scale_columnPfS_iii
	.p2align	3, 0x0
_Z26qrd_optimised_scale_columnPfS_iii:
	.quad	_Z41__device_stub__qrd_optimised_scale_columnPfS_iii
	.size	_Z26qrd_optimised_scale_columnPfS_iii, 8

	.type	_Z31qrd_optimised_transform_columnsPfiii,@object # @_Z31qrd_optimised_transform_columnsPfiii
	.globl	_Z31qrd_optimised_transform_columnsPfiii
	.p2align	3, 0x0
_Z31qrd_optimised_transform_columnsPfiii:
	.quad	_Z46__device_stub__qrd_optimised_transform_columnsPfiii
	.size	_Z31qrd_optimised_transform_columnsPfiii, 8

	.type	.L.str.8,@object                # @.str.8
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.8:
	.asciz	"\n\nDecompose Partly Column=%d\n--------------\n"
	.size	.L.str.8, 45

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\nGPU time: %f (msec)\n"
	.size	.L.str.9, 22

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"A: %dx%d (%d)\n"
	.size	.L.str.11, 15

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Running on GPU..."
	.size	.L.str.12, 18

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Length of the array = %d\n"
	.size	.L.str.13, 26

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/shibaeff/EC527_Project_QR/master/QR/GPU_code/testbench_for_gpu.hip"
	.size	.L.str.14, 129

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"CUDA_SAFE_CALL: %s %s %d\n"
	.size	.L.str.15, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z24qrd_optimised_calc_norm2PfS_iii"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z27qrd_optimised_calc_norm2_L2Pfi"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii"
	.size	.L__unnamed_3, 46

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z26qrd_optimised_scale_columnPfS_iii"
	.size	.L__unnamed_4, 38

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z31qrd_optimised_transform_columnsPfiii"
	.size	.L__unnamed_5, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\nD:"
	.size	.Lstr, 4

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Running QR Decomposition\n"
	.size	.Lstr.1, 26

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__qrd_optimised_calc_norm2PfS_iii
	.addrsig_sym _Z42__device_stub__qrd_optimised_calc_norm2_L2Pfi
	.addrsig_sym _Z46__device_stub__qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.addrsig_sym _Z41__device_stub__qrd_optimised_scale_columnPfS_iii
	.addrsig_sym _Z46__device_stub__qrd_optimised_transform_columnsPfiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24qrd_optimised_calc_norm2PfS_iii
	.addrsig_sym _Z27qrd_optimised_calc_norm2_L2Pfi
	.addrsig_sym _Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.addrsig_sym _Z26qrd_optimised_scale_columnPfS_iii
	.addrsig_sym _Z31qrd_optimised_transform_columnsPfiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24qrd_optimised_calc_norm2PfS_iii ; -- Begin function _Z24qrd_optimised_calc_norm2PfS_iii
	.globl	_Z24qrd_optimised_calc_norm2PfS_iii
	.p2align	8
	.type	_Z24qrd_optimised_calc_norm2PfS_iii,@function
_Z24qrd_optimised_calc_norm2PfS_iii:    ; @_Z24qrd_optimised_calc_norm2PfS_iii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b32 s3, s[0:1], 0x2c
	s_mov_b32 s2, s15
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v1, s8, v0
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
	v_lshl_add_u32 v3, v0, 2, 0
	ds_store_b32 v3, v4
	v_cmpx_gt_u32_e64 s9, v2
	s_cbranch_execz .LBB0_8
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[5:6], null, v2, s10, s[8:9]
	v_mov_b32_e32 v6, v4
	s_cmp_lt_u32 s3, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v2, v2
	ds_store_b32 v3, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_6
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_lshr_b32 s1, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, s1, v1
	v_cmp_gt_u32_e32 vcc_lo, s1, v0
	v_cmp_gt_u32_e64 s0, s9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, vcc_lo, s0
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshl_add_u32 v2, s1, 2, v3
	ds_load_b32 v2, v2
	ds_load_b32 v4, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v4
	ds_store_b32 v3, v2
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s1
	s_branch .LBB0_2
.LBB0_6:                                ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s3, 0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB0_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24qrd_optimised_calc_norm2PfS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24qrd_optimised_calc_norm2PfS_iii, .Lfunc_end0-_Z24qrd_optimised_calc_norm2PfS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z27qrd_optimised_calc_norm2_L2Pfi ; -- Begin function _Z27qrd_optimised_calc_norm2_L2Pfi
	.globl	_Z27qrd_optimised_calc_norm2_L2Pfi
	.p2align	8
	.type	_Z27qrd_optimised_calc_norm2_L2Pfi,@function
_Z27qrd_optimised_calc_norm2_L2Pfi:     ; @_Z27qrd_optimised_calc_norm2_L2Pfi
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x1c
	s_load_b32 s4, s[0:1], 0x8
	s_mov_b32 s2, s15
	v_lshl_add_u32 v3, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	ds_store_b32 v3, v2
	v_cmp_gt_i32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_u32 s3, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_6
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_lshr_b32 s4, s3, 1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB1_5
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	v_lshl_add_u32 v1, s4, 2, v3
	ds_load_b32 v1, v1
	ds_load_b32 v2, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	ds_store_b32 v3, v1
.LBB1_5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s4
	s_branch .LBB1_2
.LBB1_6:                                ; %._crit_edge
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s3, 0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.7:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB1_8:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27qrd_optimised_calc_norm2_L2Pfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z27qrd_optimised_calc_norm2_L2Pfi, .Lfunc_end1-_Z27qrd_optimised_calc_norm2_L2Pfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii ; -- Begin function _Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.globl	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
	.p2align	8
	.type	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii,@function
_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii: ; @_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_load_b32 s12, s[4:5], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v0, 0x4f800000, s12
	v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s12
	s_add_i32 s0, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mul_i32 s0, s0, s2
	v_cndmask_b32_e32 v0, s12, v0, vcc_lo
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	v_sqrt_f32_e32 v1, v0
	s_add_u32 s6, s6, s0
	s_addc_u32 s7, s7, s1
	s_ashr_i32 s3, s2, 31
	s_load_b32 s1, s[6:7], 0x0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, 1, v1
	v_add_nc_u32_e32 v2, -1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v1, v0
	v_fma_f32 v4, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v4
	v_cndmask_b32_e64 v1, v1, v2, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v5
	v_cndmask_b32_e64 v1, v1, v3, s0
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e64 s0, s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x37800000, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
	v_cndmask_b32_e64 v0, v0, -v0, s0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s2, s10, s0
	s_addc_u32 s3, s11, s1
	v_xor_b32_e32 v2, 0x80000000, v0
	s_add_u32 s0, s8, s0
	s_addc_u32 s1, s9, s1
	s_clause 0x2
	global_store_b32 v1, v0, s[4:5]
	global_store_b32 v1, v0, s[2:3]
	global_store_b32 v1, v2, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 13
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii, .Lfunc_end2-_Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 15
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 15
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26qrd_optimised_scale_columnPfS_iii ; -- Begin function _Z26qrd_optimised_scale_columnPfS_iii
	.globl	_Z26qrd_optimised_scale_columnPfS_iii
	.p2align	8
	.type	_Z26qrd_optimised_scale_columnPfS_iii,@function
_Z26qrd_optimised_scale_columnPfS_iii:  ; @_Z26qrd_optimised_scale_columnPfS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
	s_mov_b32 s7, exec_lo
	v_add_nc_u32_e32 v0, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s5, v0
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_mad_u64_u32 v[2:3], null, v0, s6, s[4:5]
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[8:9], s[4:5], 2
	s_add_u32 s2, s2, s8
	s_addc_u32 s3, s3, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_load_b32 s2, s[2:3], 0x0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f32 v4, null, s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v0, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v4, v4, v5, v7
	v_div_fixup_f32 v0, v4, s2, v0
	global_store_b32 v[2:3], v0, off
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB3_4
; %bb.3:
	s_add_i32 s2, s6, 1
	v_mov_b32_e32 v0, 0
	s_mul_i32 s2, s2, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_load_b32 v1, v0, s[0:1]
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, 1.0, v1
	global_store_b32 v0, v1, s[0:1]
.LBB3_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26qrd_optimised_scale_columnPfS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z26qrd_optimised_scale_columnPfS_iii, .Lfunc_end3-_Z26qrd_optimised_scale_columnPfS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z31qrd_optimised_transform_columnsPfiii ; -- Begin function _Z31qrd_optimised_transform_columnsPfiii
	.globl	_Z31qrd_optimised_transform_columnsPfiii
	.p2align	8
	.type	_Z31qrd_optimised_transform_columnsPfiii,@function
_Z31qrd_optimised_transform_columnsPfiii: ; @_Z31qrd_optimised_transform_columnsPfiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s2, s0, 24
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s15, s7
	s_add_i32 s7, s12, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v1, v0, s7, 1
	s_mov_b32 s7, exec_lo
	v_cmpx_gt_i32_e64 s6, v1
	s_cbranch_execz .LBB4_18
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_add_i32 s7, s6, 1
	v_mov_b32_e32 v4, 0
	s_mul_i32 s8, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s9, s8, 31
	s_lshl_b64 s[10:11], s[8:9], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	s_cmp_lt_i32 s4, s5
	s_load_b32 s7, s[10:11], 0x0
	s_cselect_b32 s9, -1, 0
	s_cmp_ge_i32 s4, s5
	s_cbranch_scc1 .LBB4_10
; %bb.2:                                ; %.lr.ph65
	s_load_b32 s10, s[2:3], 0xc
	v_lshl_add_u32 v5, v0, 2, 0
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s10, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_cselect_b32 s11, -1, 0
	s_add_i32 s12, s12, s8
	s_mul_i32 s8, s6, s10
	v_add3_u32 v7, s12, v0, 1
	s_mov_b32 s12, s4
.LBB4_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_7 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, s12, v0
	s_mov_b32 s13, exec_lo
	v_cmpx_gt_u32_e64 s5, v3
	s_cbranch_execz .LBB4_5
; %bb.4:                                ;   in Loop: Header=BB4_3 Depth=1
	v_mad_u64_u32 v[8:9], null, v3, s6, s[4:5]
	v_mov_b32_e32 v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[8:9]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
.LBB4_5:                                ;   in Loop: Header=BB4_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB4_9
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB4_3 Depth=1
	v_mov_b32_e32 v2, v7
	s_mov_b32 s13, 0
	s_mov_b32 s14, s10
.LBB4_7:                                ; %.lr.ph
                                        ;   Parent Loop BB4_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s14, s14, -1
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_nc_u32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	global_load_b32 v3, v[8:9], off
	v_mov_b32_e32 v8, s13
	s_add_i32 s13, s13, 4
	s_cmp_eq_u32 s14, 0
	ds_load_b32 v8, v8
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v4, v8, v3
	s_cbranch_scc0 .LBB4_7
; %bb.8:                                ; %.loopexit58.loopexit
                                        ;   in Loop: Header=BB4_3 Depth=1
	s_add_i32 s12, s12, s10
.LBB4_9:                                ; %.loopexit58
                                        ;   in Loop: Header=BB4_3 Depth=1
	v_add_nc_u32_e32 v7, s8, v7
	s_cmp_lt_i32 s12, s5
	s_cbranch_scc1 .LBB4_3
.LBB4_10:                               ; %._crit_edge
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB4_18
; %bb.11:                               ; %.lr.ph74
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v2, null, s7, s7, -v4
	v_div_scale_f32 v6, vcc_lo, -v4, s7, -v4
	s_load_b32 s2, s[2:3], 0xc
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v5, v3
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v3
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f32 v7, -v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v3
	v_fma_f32 v2, -v2, v5, v6
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v3, v5
	v_lshl_add_u32 v5, v0, 2, 0
	v_div_fixup_f32 v4, v2, s7, -v4
	s_mov_b32 s7, s4
.LBB4_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_16 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, s7, v0
	s_mov_b32 s8, exec_lo
	v_cmpx_gt_u32_e64 s5, v3
	s_cbranch_execz .LBB4_14
; %bb.13:                               ;   in Loop: Header=BB4_12 Depth=1
	v_mad_u64_u32 v[7:8], null, v3, s6, s[4:5]
	v_mov_b32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[7:8]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
.LBB4_14:                               ;   in Loop: Header=BB4_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB4_17
; %bb.15:                               ; %.lr.ph70.preheader
                                        ;   in Loop: Header=BB4_12 Depth=1
	v_mad_u64_u32 v[2:3], null, s6, s7, v[1:2]
	s_add_i32 s7, s2, s7
	s_mov_b32 s8, 0
	s_mov_b32 s9, s2
.LBB4_16:                               ; %.lr.ph70
                                        ;   Parent Loop BB4_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_mov_b32_e32 v9, s8
	s_add_i32 s9, s9, -1
	s_add_i32 s8, s8, 4
	s_cmp_eq_u32 s9, 0
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s6, v2
	ds_load_b32 v9, v9
	v_add_co_u32 v7, vcc_lo, s0, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v3, v4, v9
	global_store_b32 v[7:8], v3, off
	s_cbranch_scc0 .LBB4_16
.LBB4_17:                               ; %.loopexit
                                        ;   in Loop: Header=BB4_12 Depth=1
	s_cmp_ge_i32 s7, s5
	s_cbranch_scc0 .LBB4_12
.LBB4_18:                               ; %.loopexit57
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z31qrd_optimised_transform_columnsPfiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z31qrd_optimised_transform_columnsPfiii, .Lfunc_end4-_Z31qrd_optimised_transform_columnsPfiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 832
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         152
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24qrd_optimised_calc_norm2PfS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24qrd_optimised_calc_norm2PfS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         136
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27qrd_optimised_calc_norm2_L2Pfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z27qrd_optimised_calc_norm2_L2Pfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     15
    .sgpr_spill_count: 0
    .symbol:         _Z31qrd_optimised_calc_norm2_FINISHPfS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
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    .language:       OpenCL C
    .language_version:
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    .name:           _Z26qrd_optimised_scale_columnPfS_iii
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    .sgpr_spill_count: 0
    .symbol:         _Z26qrd_optimised_scale_columnPfS_iii.kd
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    .vgpr_count:     9
    .vgpr_spill_count: 0
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
