#include "includes.h"
__global__ void cuda_conv2D_updateDeltas(double* delta, double* biasDelta, const double* upStreamActivation, const double* err, double momentum, size_t kernelCount, size_t kernelRows, size_t kernelCols, size_t outputRows, size_t outputCols, size_t inputChannels, size_t inputRows, size_t inputCols, size_t padding, size_t stride)
{
// Do all values for i, j, and k in parallel
int id = blockIdx.x * blockDim.x + threadIdx.x;
size_t i = id % outputCols;
id /= outputCols;
size_t j = id % outputRows;
id /= outputRows;
if(id >= kernelCount)
return;
size_t k = id;

// Compute some intermediate values
size_t outChannelOffset = k * outputRows * outputCols;
size_t outRowOffset = j * outputCols;
int inRowOffset = j * stride - padding;

// This block of code is derived from the serial implementation
size_t kk = k * inputChannels * kernelRows * kernelCols;
size_t index = outChannelOffset + outRowOffset + i;
int inColOffset = i * stride - padding;
biasDelta[k] += err[index];
for(size_t z = 0; z < inputChannels; z++)
{
size_t kernelChannelOffset = z * kernelRows * kernelCols;
size_t inChannelOffset = z * inputRows * inputCols;
for(size_t y = 0; y < kernelRows; y++)
{
size_t kernelRowOffset = y * kernelCols;
int inRow = inRowOffset + y;
for(size_t x = 0; x < kernelCols; x++)
{
int inCol = inColOffset + x;
if(inRow >= 0 && inRow < (int)inputRows && inCol >= 0 && inCol < (int)inputRows)
{
size_t idx = inChannelOffset + inputCols * inRow + inCol;
delta[kk + kernelChannelOffset + kernelRowOffset + x] += err[index] * upStreamActivation[idx];
}
}
}
}
}
	.file	"tmpxft_0024d9b7_00000000-6_cuda_conv2D_updateDeltas.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm
	.type	_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm, @function
_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movsd	%xmm0, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	72(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 288
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm, .-_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm
	.globl	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.type	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, @function
_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmmPdS_PKdS1_dmmmmmmmmmm
	.cfi_endproc
.LFE2033:
	.size	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, .-_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_conv2D_updateDeltas(double* delta, double* biasDelta, const double* upStreamActivation, const double* err, double momentum, size_t kernelCount, size_t kernelRows, size_t kernelCols, size_t outputRows, size_t outputCols, size_t inputChannels, size_t inputRows, size_t inputCols, size_t padding, size_t stride)
{
// Do all values for i, j, and k in parallel
int id = blockIdx.x * blockDim.x + threadIdx.x;
size_t i = id % outputCols;
id /= outputCols;
size_t j = id % outputRows;
id /= outputRows;
if(id >= kernelCount)
return;
size_t k = id;

// Compute some intermediate values
size_t outChannelOffset = k * outputRows * outputCols;
size_t outRowOffset = j * outputCols;
int inRowOffset = j * stride - padding;

// This block of code is derived from the serial implementation
size_t kk = k * inputChannels * kernelRows * kernelCols;
size_t index = outChannelOffset + outRowOffset + i;
int inColOffset = i * stride - padding;
biasDelta[k] += err[index];
for(size_t z = 0; z < inputChannels; z++)
{
size_t kernelChannelOffset = z * kernelRows * kernelCols;
size_t inChannelOffset = z * inputRows * inputCols;
for(size_t y = 0; y < kernelRows; y++)
{
size_t kernelRowOffset = y * kernelCols;
int inRow = inRowOffset + y;
for(size_t x = 0; x < kernelCols; x++)
{
int inCol = inColOffset + x;
if(inRow >= 0 && inRow < (int)inputRows && inCol >= 0 && inCol < (int)inputRows)
{
size_t idx = inChannelOffset + inputCols * inRow + inCol;
delta[kk + kernelChannelOffset + kernelRowOffset + x] += err[index] * upStreamActivation[idx];
}
}
}
}
}
	.text
	.file	"cuda_conv2D_updateDeltas.hip"
	.globl	_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm # -- Begin function _Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.type	_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm,@function
_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm: # @_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	32(%rsp), %r10
	movq	%r8, (%r10)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, .Lfunc_end0-_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm,@object # @_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.section	.rodata,"a",@progbits
	.globl	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.p2align	3, 0x0
_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm:
	.quad	_Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.size	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm"
	.size	.L__unnamed_1, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm ; -- Begin function _Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.globl	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
	.p2align	8
	.type	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm,@function
_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm: ; @_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
; %bb.0:
	s_clause 0x1
	s_load_b512 s[16:31], s[0:1], 0x28
	s_load_b32 s2, s[0:1], 0x84
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s24
	v_cvt_f32_u32_e32 v2, s25
	v_cvt_f32_u32_e32 v3, s22
	v_cvt_f32_u32_e32 v6, s23
	s_and_b32 s2, s2, 0xffff
	s_sub_u32 s3, 0, s24
	v_fmac_f32_e32 v1, 0x4f800000, v2
	s_subb_u32 s4, 0, s25
	v_fmac_f32_e32 v3, 0x4f800000, v6
	s_sub_u32 s5, 0, s22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v1
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	v_mul_f32_e32 v3, 0x5f7ffffc, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, s3, v2
	v_mul_hi_u32 v5, s3, v1
	v_mul_lo_u32 v7, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_mul_lo_u32 v5, s3, v1
	v_add_nc_u32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v1, v5
	v_mul_lo_u32 v7, v1, v4
	v_mul_hi_u32 v8, v1, v4
	v_mul_hi_u32 v9, v2, v5
	v_mul_lo_u32 v5, v2, v5
	v_mul_hi_u32 v10, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_add_co_u32 v6, vcc_lo, v6, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v9, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	v_mul_f32_e32 v7, 0x2f800000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v6, v7
	v_add_co_u32 v4, vcc_lo, v1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, v2, v5, vcc_lo
	v_fmac_f32_e32 v3, 0xcf800000, v6
	v_cvt_u32_f32_e32 v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v6, s3, v4
	v_mul_lo_u32 v7, s3, v5
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_cvt_u32_f32_e32 v9, v3
	v_mul_lo_u32 v0, s4, v4
	v_mul_lo_u32 v2, s5, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_hi_u32 v3, s5, v9
	v_add_nc_u32_e32 v6, v6, v7
	v_mul_lo_u32 v7, s3, v4
	s_subb_u32 s3, 0, s23
	v_mul_lo_u32 v10, s5, v9
	v_mul_lo_u32 v11, s3, v9
	v_add_nc_u32_e32 v6, v6, v0
	v_ashrrev_i32_e32 v0, 31, v1
	v_add_nc_u32_e32 v2, v3, v2
	v_mul_hi_u32 v3, v4, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v12, v4, v6
	v_mul_hi_u32 v14, v4, v6
	v_mul_hi_u32 v16, v5, v7
	v_mul_lo_u32 v7, v5, v7
	v_mul_hi_u32 v17, v5, v6
	v_mul_lo_u32 v6, v5, v6
	v_mul_hi_u32 v13, v9, v10
	v_mul_hi_u32 v15, v8, v10
	v_add_co_u32 v3, vcc_lo, v3, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
	v_mul_lo_u32 v10, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, v7
	v_add_co_ci_u32_e32 v3, vcc_lo, v12, v16, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	v_add_nc_u32_e32 v7, v2, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, v5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v16, v9, v7
	v_mul_hi_u32 v17, v1, v11
	v_mul_hi_u32 v14, v9, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[2:3], null, v1, v12, 0
	v_mad_u64_u32 v[4:5], null, v0, v11, 0
	v_mul_hi_u32 v18, v8, v7
	v_mul_lo_u32 v19, v8, v7
	v_mad_u64_u32 v[6:7], null, v0, v12, 0
	v_add_co_u32 v2, vcc_lo, v17, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v11, vcc_lo, v13, v16
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, v2, v4
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v11, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, v2, v6
	v_add_co_ci_u32_e64 v6, s2, 0, v3, s2
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v15, vcc_lo
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, s25, v5
	v_mad_u64_u32 v[2:3], null, s24, v5, 0
	v_mul_lo_u32 v11, s24, v6
	v_add_co_u32 v4, vcc_lo, v4, v19
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, v9, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v3, v11, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_sub_nc_u32_e32 v16, v0, v3
	v_sub_co_u32 v2, vcc_lo, v1, v2
	v_add_co_u32 v9, s2, v5, 2
	v_mul_hi_u32 v13, s5, v4
	v_mul_lo_u32 v15, s5, v7
	v_add_co_ci_u32_e64 v12, s2, 0, v6, s2
	v_subrev_co_ci_u32_e64 v16, s2, s25, v16, vcc_lo
	v_sub_co_ci_u32_e32 v3, vcc_lo, v0, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s24, v2
	v_sub_co_u32 v19, s2, v2, s24
	v_add_nc_u32_e32 v13, v13, v15
	v_mul_lo_u32 v14, s3, v4
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v15, vcc_lo, 0, v16, s2
	v_cmp_le_u32_e32 vcc_lo, s24, v19
	v_mul_lo_u32 v8, s5, v4
	v_add_nc_u32_e32 v13, v13, v14
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s25, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_hi_u32 v17, v7, v8
	v_mul_lo_u32 v18, v7, v8
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s25, v15
	v_mul_hi_u32 v8, v4, v8
	v_mul_lo_u32 v20, v4, v13
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s25, v3
	v_mul_hi_u32 v3, v4, v13
	v_cndmask_b32_e32 v2, v14, v2, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s25, v15
	v_mul_hi_u32 v15, v7, v13
	v_mul_lo_u32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s3, 0, v2
	v_cndmask_b32_e32 v14, v19, v16, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, v20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cmp_ne_u32_e64 s2, 0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v18
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v11, v12, s2
	v_cndmask_b32_e64 v8, v10, v9, s2
	v_cndmask_b32_e64 v2, v6, v11, s3
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v9, vcc_lo, v3, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v5, v8, s3
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v4, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v3
	v_mul_hi_u32 v12, v3, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v3, v6, 0
	v_mad_u64_u32 v[8:9], null, v7, v10, 0
	v_mad_u64_u32 v[10:11], null, v7, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, v12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, v8
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v9, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v4, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, s23, v6
	v_mad_u64_u32 v[4:5], null, s22, v6, 0
	v_mul_lo_u32 v10, s22, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v4, vcc_lo, v3, v4
	v_add3_u32 v5, v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v7, v5
	v_subrev_co_ci_u32_e64 v9, s2, s23, v9, vcc_lo
	v_add_co_u32 v10, s2, v6, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v11, s2, 0, v8, s2
	v_sub_co_u32 v12, s2, v4, s22
	v_sub_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
	v_subrev_co_ci_u32_e64 v9, s2, 0, v9, s2
	v_cmp_le_u32_e32 vcc_lo, s22, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e64 s2, s23, v5
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v9
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v4
	v_cndmask_b32_e64 v4, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v5
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v14, v4, s2
	v_cndmask_b32_e32 v9, v13, v12, vcc_lo
	v_add_co_u32 v12, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v8, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v13, v11, vcc_lo
	v_cndmask_b32_e32 v9, v12, v10, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v6, v6, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v8, v5 :: v_dual_mov_b32 v9, v3
	v_mov_b32_e32 v4, v6
	v_ashrrev_i32_e32 v5, 31, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u64_e64 s[16:17], v[4:5]
	s_cbranch_execz .LBB0_12
; %bb.1:
	v_mul_lo_u32 v8, v8, s22
	v_mul_lo_u32 v12, v6, s23
	v_mad_u64_u32 v[10:11], null, v6, s22, 0
	s_load_b256 s[4:11], s[0:1], 0x0
	s_cmp_eq_u64 s[26:27], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v8, v11, v12, v8
	v_sub_co_u32 v6, vcc_lo, v9, v10
	v_mul_lo_u32 v10, v4, s23
	v_mul_lo_u32 v11, v5, s22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v7, vcc_lo, v7, v8, vcc_lo
	v_mul_lo_u32 v12, v3, s25
	v_mad_u64_u32 v[8:9], null, v4, s22, v[6:7]
	v_mul_lo_u32 v7, v2, s24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v11, v11, v9, v10
	v_mad_u64_u32 v[9:10], null, v3, s24, 0
	v_mul_lo_u32 v13, v8, s25
	v_mad_u64_u32 v[2:3], null, v8, s24, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v8, v11, s24
	v_add3_u32 v10, v10, v12, v7
	v_sub_co_u32 v7, vcc_lo, v1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v3, v3, v13, v8
	v_sub_co_ci_u32_e32 v8, vcc_lo, v0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v9, vcc_lo
	global_load_b64 v[8:9], v[0:1], off
	global_load_b64 v[10:11], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	global_store_b64 v[2:3], v[8:9], off
	s_cbranch_scc1 .LBB0_12
; %bb.2:                                ; %.lr.ph94
	s_load_b128 s[0:3], s[0:1], 0x68
	v_mul_lo_u32 v8, v5, s26
	v_mul_lo_u32 v9, v4, s27
	v_mad_u64_u32 v[2:3], null, v4, s26, 0
	s_cmp_lg_u64 s[18:19], 0
	s_mov_b64 s[6:7], 0
	s_waitcnt lgkmcnt(0)
	s_cselect_b32 s3, -1, 0
	s_cmp_lg_u64 s[20:21], 0
	s_cselect_b32 s16, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v3, v9, v8
	v_mad_u64_u32 v[4:5], null, v6, s2, 0
	v_mad_u64_u32 v[5:6], null, v7, s2, 0
	v_sub_co_u32 v8, null, v4, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_co_u32 v9, null, v5, s0
	v_mov_b32_e32 v5, 0
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_11
; %bb.4:                                ; %.lr.ph90
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
	s_mul_i32 s0, s6, s29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v4, s19
	s_mul_hi_u32 s1, s6, s28
	v_mul_lo_u32 v10, v6, s18
	v_mad_u64_u32 v[6:7], null, v4, s18, 0
	s_add_i32 s0, s1, s0
	s_mul_i32 s1, s7, s28
	s_mul_i32 s22, s6, s28
	s_add_i32 s17, s0, s1
	s_mov_b64 s[10:11], 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v7, v11, v10
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_10
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_5 Depth=2
	v_add_nc_u32_e32 v4, s10, v8
	v_add_co_u32 v14, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s0, v4, s22
	v_add_co_ci_u32_e64 v10, null, 0, s17, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v17, v13, s20
	v_mul_lo_u32 v16, v12, s31
	v_mul_lo_u32 v18, v14, s21
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v15, v10, s30
	v_mad_u64_u32 v[10:11], null, v12, s30, 0
	v_mad_u64_u32 v[12:13], null, v14, s20, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s0, s28, v4
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v11, v11, v16, v15
	v_add3_u32 v13, v13, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s8, v10
	v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s1, s4, v12
	v_add_co_ci_u32_e64 v13, s1, s5, v13, s1
.LBB0_7:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_co_u32 v4, null, s12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s1, -1, v4
	v_cmp_gt_i32_e64 s2, s28, v4
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=3
	v_lshlrev_b64 v[14:15], 3, v[4:5]
	s_lshl_b64 s[24:25], s[12:13], 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s1, v10, v14
	v_add_co_ci_u32_e64 v15, s1, v11, v15, s1
	v_add_co_u32 v16, s1, v12, s24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v17, s1, s25, v13, s1
	global_load_b64 v[18:19], v[0:1], off
	global_load_b64 v[14:15], v[14:15], off
	global_load_b64 v[20:21], v[16:17], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], v[18:19], v[14:15], v[20:21]
	global_store_b64 v[16:17], v[14:15], off
.LBB0_9:                                ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s2
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, -1
	s_addc_u32 s15, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[14:15], 0
	s_cbranch_scc0 .LBB0_7
.LBB0_10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[10:11], s[18:19]
	s_cbranch_scc0 .LBB0_5
.LBB0_11:                               ; %._crit_edge91
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u64 s[6:7], s[26:27]
	s_cbranch_scc0 .LBB0_3
.LBB0_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 376
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm, .Lfunc_end0-_Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2460
; NumSgprs: 34
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           8
        .value_kind:     by_value
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           8
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         124
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         128
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         132
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         134
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         136
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         138
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         140
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         142
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         176
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         184
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 376
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z24cuda_conv2D_updateDeltasPdS_PKdS1_dmmmmmmmmmm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
