/* This code illustrates the use of the GPU to perform vector addition on arbirarily large vectors. 
    Author: Naga Kandasamy
    Date modified: May 3, 2020
*/  
  
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <math.h>
#include <float.h>

/* Include kernel code during preprocessing step */
#include "vector_addition_kernel.cu"
  
#define THREAD_BLOCK_SIZE 128
#define NUM_THREAD_BLOCKS 240
  
void run_test(int);
void compute_on_device(float *, float *, float *, int);
void check_for_error(char const *);
extern "C" void compute_gold(float *, float *, float *, int);

int main(int argc, char **argv) 
{
    if (argc != 2) {
        fprintf(stderr, "Usage: %s num-elements\n", argv[0]);
        exit(EXIT_FAILURE);
    }

    int num_elements = atoi(argv[1]);
    run_test(num_elements);
	
    exit(EXIT_SUCCESS);
}

/* Perform vector addition on CPU and GPU */
void run_test(int num_elements)                
{
    float diff;
    int i;
		 			 
    /* Allocate memory on CPU for input vectors A and B, and output vector C */
     int vector_length = sizeof(float) * num_elements;
     float *A = (float *)malloc(vector_length);
     float *B = (float *)malloc(vector_length);
     float *gold_result = (float *)malloc(vector_length);	/* Result vector computed on CPU */
     float *gpu_result = (float *)malloc(vector_length);	/* Result vector computed on GPU */
			 
     /* Initialize input data to be integer values between 0 and 5 */ 
     for (i = 0; i < num_elements; i++) {
         A[i] = floorf(5 * (rand() / (float)RAND_MAX));
         B[i] = floorf(5 * (rand() / (float)RAND_MAX));
     } 
				
     /* Compute reference solution on CPU */
     fprintf(stderr, "Adding vectors on the CPU\n");
     compute_gold(A, B, gold_result, num_elements);
					 	  
     /* Compute result vector on GPU */ 
     compute_on_device(A, B, gpu_result, num_elements);
  
     /* Compute differences between the CPU and GPU results. */
     diff = 0.0;
     for (i = 0; i < num_elements; i++)
         diff += fabsf(gold_result[i] - gpu_result[i]);
	
     fprintf(stderr, "Difference between the CPU and GPU result: %f\n", diff);
  
     /* Free the data structures. */
     free((void *)A); 
     free((void *)B);
     free((void *)gold_result); 
     free((void *)gpu_result);
	
     exit(EXIT_SUCCESS);
}

/* Host side code. 
   
   Transfer vectors A and B from CPU to GPU, set up grid and 
   thread dimensions, execute kernel function, and copy result vector 
   back to CPU. 
 */
void compute_on_device(float *A_on_host, float *B_on_host, float *gpu_result, int num_elements)
{
    float *A_on_device = NULL;
    float *B_on_device = NULL;
    float *C_on_device = NULL;
	
    /* Allocate space on GPU for vectors A and B, and copy contents of vectors to GPU */
    cudaMalloc((void **)&A_on_device, num_elements * sizeof(float));
    cudaMemcpy(A_on_device, A_on_host, num_elements * sizeof(float), cudaMemcpyHostToDevice);
	
    cudaMalloc((void **)&B_on_device, num_elements * sizeof(float));
    cudaMemcpy(B_on_device, B_on_host, num_elements * sizeof(float), cudaMemcpyHostToDevice);
    
    /* Allocate space for result vector on GPU */
    cudaMalloc((void **)&C_on_device, num_elements * sizeof(float));
  
    /* Set up the execution grid on the GPU. */
    int num_thread_blocks = NUM_THREAD_BLOCKS;
    dim3 thread_block(THREAD_BLOCK_SIZE, 1, 1);	/* Set number of threads in the thread block */
    fprintf(stderr, "Setting up a (%d x 1) execution grid\n", num_thread_blocks);
    dim3 grid(num_thread_blocks, 1);
	
    fprintf(stderr, "Adding vectors on the GPU\n");
  
    /* Launch kernel with multiple thread blocks. The kernel call is non-blocking. */
    vector_addition_kernel<<< grid, thread_block >>>(A_on_device, B_on_device, C_on_device, num_elements);	 
    cudaDeviceSynchronize(); /* Force CPU to wait for GPU to complete */
    check_for_error("KERNEL FAILURE");
  
    /* Copy result vector back from GPU and store */
    cudaMemcpy(gpu_result, C_on_device, num_elements * sizeof(float), cudaMemcpyDeviceToHost);
  
	/* Free memory on GPU */	  
    cudaFree(A_on_device); 
    cudaFree(B_on_device); 
    cudaFree(C_on_device);
} 

/* Check for errors when executing the kernel */
void check_for_error(char const *msg)                
{
    cudaError_t err = cudaGetLastError();
    if (cudaSuccess != err) {
        fprintf(stderr, "CUDA ERROR: %s (%s). \n", msg, cudaGetErrorString(err));
        exit(EXIT_FAILURE);
    }
}



	.file	"tmpxft_002b67b1_00000000-6_vector_addition.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA ERROR: %s (%s). \n"
	.text
	.globl	_Z15check_for_errorPKc
	.type	_Z15check_for_errorPKc, @function
_Z15check_for_errorPKc:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L2
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	%rbx, %rcx
	leaq	.LC0(%rip), %rdx
	movq	%rax, %r8
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z15check_for_errorPKc, .-_Z15check_for_errorPKc
	.globl	_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
	.type	_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22vector_addition_kernelPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L6:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
	.globl	_Z22vector_addition_kernelPfS_S_i
	.type	_Z22vector_addition_kernelPfS_S_i, @function
_Z22vector_addition_kernelPfS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2056:
	.size	_Z22vector_addition_kernelPfS_S_i, .-_Z22vector_addition_kernelPfS_S_i
	.section	.rodata.str1.1
.LC1:
	.string	"Setting up a (%d x 1) execution grid\n"
.LC2:
	.string	"Adding vectors on the GPU\n"
.LC3:
	.string	"KERNEL FAILURE"
	.text
	.globl	_Z17compute_on_devicePfS_S_i
	.type	_Z17compute_on_devicePfS_S_i, @function
_Z17compute_on_devicePfS_S_i:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%ecx, %rbx
	movq	%rbx, %rbp
	salq	$2, %rbx
	movq	%rbx, %rsi
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	xorl	%eax, %eax
	movq	%rax, 8(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movl	$33554433, %eax
	movq	stderr(%rip), %rdi
	movl	$240, %ecx
	salq	$7, %rax
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	movl	$1, 40(%rsp)
	movq	%rax, 32(%rsp)
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$268435471, %eax
	movl	$2, %esi
	movq	stderr(%rip), %rdi
	salq	$4, %rax
	leaq	.LC2(%rip), %rdx
	movl	$1, 52(%rsp)
	movq	%rax, 44(%rsp)
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	40(%rsp), %ecx
	movl	52(%rsp), %esi
	xorl	%r9d, %r9d
	movq	32(%rsp), %rdx
	movq	44(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebp, %ecx
	movq	8(%rsp), %rdi
	call	_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
.L12:
	call	cudaDeviceSynchronize@PLT
	leaq	.LC3(%rip), %rdi
	call	_Z15check_for_errorPKc
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z17compute_on_devicePfS_S_i, .-_Z17compute_on_devicePfS_S_i
	.section	.rodata.str1.1
.LC7:
	.string	"Adding vectors on the CPU\n"
.LC9:
	.string	"Difference between the CPU and GPU result: %f\n"
	.text
	.globl	_Z8run_testi
	.type	_Z8run_testi, @function
_Z8run_testi:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leal	0(,%rdi,4), %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movslq	%r13d, %r13
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movq	%r13, %rdi
	pushq	%rax
	.cfi_def_cfa_offset 64
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movq	%r13, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	%rax, %r13
.L16:
	cmpl	%r15d, %ebx
	jle	.L21
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC5(%rip), %xmm0
	mulss	.LC6(%rip), %xmm0
	call	floorf@PLT
	movss	%xmm0, (%r12,%r15,4)
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC5(%rip), %xmm0
	mulss	.LC6(%rip), %xmm0
	call	floorf@PLT
	movss	%xmm0, 0(%rbp,%r15,4)
	incq	%r15
	jmp	.L16
.L21:
	movq	stderr(%rip), %rdi
	leaq	.LC7(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	%ebx, %ecx
	movq	%r14, %rdx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	call	compute_gold@PLT
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	call	_Z17compute_on_devicePfS_S_i
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
	movss	.LC8(%rip), %xmm2
.L18:
	cmpl	%eax, %ebx
	jle	.L22
	movss	(%r14,%rax,4), %xmm1
	subss	0(%r13,%rax,4), %xmm1
	incq	%rax
	andps	%xmm2, %xmm1
	addss	%xmm1, %xmm0
	jmp	.L18
.L22:
	movq	stderr(%rip), %rdi
	leaq	.LC9(%rip), %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__fprintf_chk@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	xorl	%edi, %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z8run_testi, .-_Z8run_testi
	.section	.rodata.str1.1
.LC10:
	.string	"Usage: %s num-elements\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	cmpl	$2, %edi
	je	.L24
	movq	(%rsi), %rcx
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC10(%rip), %rdx
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L24:
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %edi
	call	_Z8run_testi
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC11:
	.string	"_Z22vector_addition_kernelPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22vector_addition_kernelPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC5:
	.long	805306368
	.align 4
.LC6:
	.long	1084227584
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC8:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* This code illustrates the use of the GPU to perform vector addition on arbirarily large vectors. 
    Author: Naga Kandasamy
    Date modified: May 3, 2020
*/  
  

#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <math.h>
#include <float.h>

/* Include kernel code during preprocessing step */
#include "vector_addition_kernel.cu"
  
#define THREAD_BLOCK_SIZE 128
#define NUM_THREAD_BLOCKS 240
  
void run_test(int);
void compute_on_device(float *, float *, float *, int);
void check_for_error(char const *);
extern "C" void compute_gold(float *, float *, float *, int);

int main(int argc, char **argv) 
{
    if (argc != 2) {
        fprintf(stderr, "Usage: %s num-elements\n", argv[0]);
        exit(EXIT_FAILURE);
    }

    int num_elements = atoi(argv[1]);
    run_test(num_elements);
	
    exit(EXIT_SUCCESS);
}

/* Perform vector addition on CPU and GPU */
void run_test(int num_elements)                
{
    float diff;
    int i;
		 			 
    /* Allocate memory on CPU for input vectors A and B, and output vector C */
     int vector_length = sizeof(float) * num_elements;
     float *A = (float *)malloc(vector_length);
     float *B = (float *)malloc(vector_length);
     float *gold_result = (float *)malloc(vector_length);	/* Result vector computed on CPU */
     float *gpu_result = (float *)malloc(vector_length);	/* Result vector computed on GPU */
			 
     /* Initialize input data to be integer values between 0 and 5 */ 
     for (i = 0; i < num_elements; i++) {
         A[i] = floorf(5 * (rand() / (float)RAND_MAX));
         B[i] = floorf(5 * (rand() / (float)RAND_MAX));
     } 
				
     /* Compute reference solution on CPU */
     fprintf(stderr, "Adding vectors on the CPU\n");
     compute_gold(A, B, gold_result, num_elements);
					 	  
     /* Compute result vector on GPU */ 
     compute_on_device(A, B, gpu_result, num_elements);
  
     /* Compute differences between the CPU and GPU results. */
     diff = 0.0;
     for (i = 0; i < num_elements; i++)
         diff += fabsf(gold_result[i] - gpu_result[i]);
	
     fprintf(stderr, "Difference between the CPU and GPU result: %f\n", diff);
  
     /* Free the data structures. */
     free((void *)A); 
     free((void *)B);
     free((void *)gold_result); 
     free((void *)gpu_result);
	
     exit(EXIT_SUCCESS);
}

/* Host side code. 
   
   Transfer vectors A and B from CPU to GPU, set up grid and 
   thread dimensions, execute kernel function, and copy result vector 
   back to CPU. 
 */
void compute_on_device(float *A_on_host, float *B_on_host, float *gpu_result, int num_elements)
{
    float *A_on_device = NULL;
    float *B_on_device = NULL;
    float *C_on_device = NULL;
	
    /* Allocate space on GPU for vectors A and B, and copy contents of vectors to GPU */
    hipMalloc((void **)&A_on_device, num_elements * sizeof(float));
    hipMemcpy(A_on_device, A_on_host, num_elements * sizeof(float), hipMemcpyHostToDevice);
	
    hipMalloc((void **)&B_on_device, num_elements * sizeof(float));
    hipMemcpy(B_on_device, B_on_host, num_elements * sizeof(float), hipMemcpyHostToDevice);
    
    /* Allocate space for result vector on GPU */
    hipMalloc((void **)&C_on_device, num_elements * sizeof(float));
  
    /* Set up the execution grid on the GPU. */
    int num_thread_blocks = NUM_THREAD_BLOCKS;
    dim3 thread_block(THREAD_BLOCK_SIZE, 1, 1);	/* Set number of threads in the thread block */
    fprintf(stderr, "Setting up a (%d x 1) execution grid\n", num_thread_blocks);
    dim3 grid(num_thread_blocks, 1);
	
    fprintf(stderr, "Adding vectors on the GPU\n");
  
    /* Launch kernel with multiple thread blocks. The kernel call is non-blocking. */
    vector_addition_kernel<<< grid, thread_block >>>(A_on_device, B_on_device, C_on_device, num_elements);	 
    hipDeviceSynchronize(); /* Force CPU to wait for GPU to complete */
    check_for_error("KERNEL FAILURE");
  
    /* Copy result vector back from GPU and store */
    hipMemcpy(gpu_result, C_on_device, num_elements * sizeof(float), hipMemcpyDeviceToHost);
  
	/* Free memory on GPU */	  
    hipFree(A_on_device); 
    hipFree(B_on_device); 
    hipFree(C_on_device);
} 

/* Check for errors when executing the kernel */
void check_for_error(char const *msg)                
{
    hipError_t err = hipGetLastError();
    if (hipSuccess != err) {
        fprintf(stderr, "CUDA ERROR: %s (%s). \n", msg, hipGetErrorString(err));
        exit(EXIT_FAILURE);
    }
}



	.text
	.file	"vector_addition.hip"
	.globl	_Z37__device_stub__vector_addition_kernelPfS_S_i # -- Begin function _Z37__device_stub__vector_addition_kernelPfS_S_i
	.type	_Z37__device_stub__vector_addition_kernelPfS_S_i,@function
_Z37__device_stub__vector_addition_kernelPfS_S_i: # @_Z37__device_stub__vector_addition_kernelPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22vector_addition_kernelPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z37__device_stub__vector_addition_kernelPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	cmpl	$2, %edi
	jne	.LBB1_1
# %bb.2:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %edi
	callq	_Z8run_testi
.LBB1_1:
	movq	stderr(%rip), %rdi
	movq	(%rsi), %rdx
	movl	$.L.str, %esi
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8run_testi
.LCPI2_0:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI2_1:
	.long	0x40a00000                      # float 5
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI2_2:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	_Z8run_testi
	.type	_Z8run_testi,@function
_Z8run_testi:                           # @_Z8run_testi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %r13d
	leal	(,%r13,4), %eax
	movslq	%eax, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r12
	testl	%r13d, %r13d
	jle	.LBB2_7
# %bb.1:                                # %.lr.ph.preheader
	movq	%r13, (%rsp)                    # 8-byte Spill
	movl	%r13d, %ebp
	xorl	%r13d, %r13d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	callq	floorf@PLT
	movss	%xmm0, (%rbx,%r13,4)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI2_0(%rip), %xmm0
	mulss	.LCPI2_1(%rip), %xmm0
	callq	floorf@PLT
	movss	%xmm0, (%r14,%r13,4)
	incq	%r13
	cmpq	%r13, %rbp
	jne	.LBB2_2
# %bb.3:                                # %._crit_edge
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$26, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	(%rsp), %r13                    # 8-byte Reload
	movl	%r13d, %ecx
	callq	compute_gold
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	%r13d, %ecx
	callq	_Z17compute_on_devicePfS_S_i
	xorps	%xmm0, %xmm0
	testl	%r13d, %r13d
	jle	.LBB2_8
# %bb.4:                                # %.lr.ph38.preheader
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
	movaps	.LCPI2_2(%rip), %xmm1           # xmm1 = [NaN,NaN,NaN,NaN]
.LBB2_5:                                # %.lr.ph38
                                        # =>This Inner Loop Header: Depth=1
	movss	(%r15,%rax,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%r12,%rax,4), %xmm2
	andps	%xmm1, %xmm2
	addss	%xmm2, %xmm0
	incq	%rax
	cmpq	%rax, %rbp
	jne	.LBB2_5
# %bb.6:                                # %._crit_edge39.loopexit
	cvtss2sd	%xmm0, %xmm0
	jmp	.LBB2_8
.LBB2_7:                                # %._crit_edge39.critedge
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$26, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	%r13d, %ecx
	callq	compute_gold
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	%r13d, %ecx
	callq	_Z17compute_on_devicePfS_S_i
	xorps	%xmm0, %xmm0
.LBB2_8:                                # %._crit_edge39
	movq	stderr(%rip), %rdi
	movl	$.L.str.2, %esi
	movb	$1, %al
	callq	fprintf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	xorl	%edi, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z8run_testi, .Lfunc_end2-_Z8run_testi
	.cfi_endproc
                                        # -- End function
	.globl	_Z17compute_on_devicePfS_S_i    # -- Begin function _Z17compute_on_devicePfS_S_i
	.type	_Z17compute_on_devicePfS_S_i,@function
_Z17compute_on_devicePfS_S_i:           # @_Z17compute_on_devicePfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %r13
	xorl	%eax, %eax
	leaq	24(%rsp), %rbx
	movq	%rax, (%rbx)
	leaq	16(%rsp), %rbp
	movq	%rax, (%rbp)
	movq	%rsp, %r12
	movq	%rax, (%r12)
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movslq	%ecx, %r14
	shlq	$2, %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	stderr(%rip), %rdi
	movl	$.L.str.3, %esi
	movl	$240, %edx
	xorl	%eax, %eax
	callq	fprintf
	movq	stderr(%rip), %rcx
	movl	$.L.str.4, %edi
	movl	$26, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	112(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	callq	_Z37__device_stub__vector_addition_kernelPfS_S_i
.LBB3_2:
	callq	hipDeviceSynchronize
	movl	$.L.str.5, %edi
	callq	_Z15check_for_errorPKc
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z17compute_on_devicePfS_S_i, .Lfunc_end3-_Z17compute_on_devicePfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z15check_for_errorPKc          # -- Begin function _Z15check_for_errorPKc
	.type	_Z15check_for_errorPKc,@function
_Z15check_for_errorPKc:                 # @_Z15check_for_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 32
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.6, %esi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end4:
	.size	_Z15check_for_errorPKc, .Lfunc_end4-_Z15check_for_errorPKc
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22vector_addition_kernelPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22vector_addition_kernelPfS_S_i,@object # @_Z22vector_addition_kernelPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z22vector_addition_kernelPfS_S_i
	.p2align	3, 0x0
_Z22vector_addition_kernelPfS_S_i:
	.quad	_Z37__device_stub__vector_addition_kernelPfS_S_i
	.size	_Z22vector_addition_kernelPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Usage: %s num-elements\n"
	.size	.L.str, 24

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Adding vectors on the CPU\n"
	.size	.L.str.1, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Difference between the CPU and GPU result: %f\n"
	.size	.L.str.2, 47

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Setting up a (%d x 1) execution grid\n"
	.size	.L.str.3, 38

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Adding vectors on the GPU\n"
	.size	.L.str.4, 27

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"KERNEL FAILURE"
	.size	.L.str.5, 15

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"CUDA ERROR: %s (%s). \n"
	.size	.L.str.6, 23

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22vector_addition_kernelPfS_S_i"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__vector_addition_kernelPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22vector_addition_kernelPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22vector_addition_kernelPfS_S_i ; -- Begin function _Z22vector_addition_kernelPfS_S_i
	.globl	_Z22vector_addition_kernelPfS_S_i
	.p2align	8
	.type	_Z22vector_addition_kernelPfS_S_i,@function
_Z22vector_addition_kernelPfS_S_i:      ; @_Z22vector_addition_kernelPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s12, s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s12, v1
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[8:9], 2
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v6, v[6:7], off
	v_add_nc_u32_e32 v1, s8, v1
	v_add_co_u32 v4, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s10
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v6
	v_cmp_le_i32_e64 s0, s12, v1
	global_store_b32 v[4:5], v0, off
	s_or_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22vector_addition_kernelPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z22vector_addition_kernelPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22vector_addition_kernelPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22vector_addition_kernelPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
