#include <stdio.h>

static __global__ void generateFilter(float* filter, 
                                      float lambda, 
									  float theta, 
									  float psi, 
									  float sigma, 
									  float gamma,
									  int2 center,
									  int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float yPrime = -x * sin(theta) + y * cos(theta);
	float harmonic = 2.0 * M_PI * xPrime / lambda + psi;
	float exponential = -(xPrime * xPrime + gamma * gamma * yPrime * yPrime) /
	                    (2.0 * sigma * sigma);
	filter[yCoord * size.x + xCoord] = exp(exponential) * cos(harmonic);
}

static __global__ void gaussianKernel(float* filter,
                                      float theta,
                                      float sigma,
								      float gamma,
								      int2 center,
								      int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float yPrime = -x * sin(theta) + y * cos(theta);
	float exponent = -(xPrime * xPrime + gamma * gamma * yPrime * yPrime) /
	                 (2.0 * sigma * sigma);
	filter[yCoord * size.x + xCoord] = exp(exponent) / (2.0 * M_PI * sigma * sigma);
}

extern "C"
void gaussian(float* filter, float theta, float sigma, float gamma, int2 center, int2 size)
{
	int filterSize = size.x;
	dim3 blockDim(64, 64);
	dim3 gridDim(filterSize / 64, filterSize / 64);
	gaussianKernel<<<blockDim, gridDim>>>(filter, theta, sigma, gamma, center, size);
}

static __global__ void harmonicKernel(float* filter,
                                      float theta,
									  float lambda,
									  float psi,
									  int2 center,
									  int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float angle = 2.0 * M_PI * xPrime / lambda + psi;
	filter[(yCoord * size.x + xCoord) * 2] = cos(angle);
	filter[(yCoord * size.x + xCoord) * 2 + 1] = sin(angle);
}

extern "C"
void harmonic(float* filter, float theta, float lambda, float psi, int2 center, int2 size)
{
	int filterSize = size.x;
	dim3 blockDim(64, 64);
	dim3 gridDim(filterSize / 64, filterSize / 64);
	harmonicKernel<<<blockDim, gridDim>>>(filter, theta, lambda, psi, center, size);
}

static __global__ void multiplyRealComplexKernel(float* real, float* complex, float* result)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	result[complexIndex] = real[realIndex] * complex[complexIndex];
	result[complexIndex + 1] = real[realIndex] * complex[complexIndex + 1];
	//result[complexIndex] = real[realIndex];
	//result[complexIndex + 1] = 0;

}

extern "C"
void multiplyRealComplex(float* real, float* complex, float* result, int numElements)
{
	multiplyRealComplexKernel<<<numElements / 32, 32>>>(real, complex, result);
}

static __global__ void multiplyComplexComplexKernel(float* a, float* b, float* result)
{
	int realIndex = (blockIdx.x * blockDim.x + threadIdx.x) * 2;
	int imagIndex = realIndex + 1;
	float areal = a[realIndex];
	float acomplex = a[imagIndex];
	float breal = b[realIndex];
	float bcomplex = b[imagIndex];
	result[realIndex] = (areal * breal) - (acomplex * bcomplex);
	result[imagIndex] = (areal * bcomplex) + (breal * acomplex);
	//result[realIndex] = breal;
	//result[imagIndex] = bcomplex;
}

extern "C"
void multiplyComplexComplex(float* a, float* b, float* result, int numElements)
{
	multiplyComplexComplexKernel<<<numElements / 64, 64>>>(a, b, result);
}

static __global__ void centerKernel(float* data, int2 size)
{
	uint xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	uint yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	if ((xCoord + yCoord) & 1u)
	//if ((xCoord + yCoord) % 2 == 1)
	{
		data[(yCoord * size.x + xCoord) * 2] *= -1;
		data[(yCoord * size.x + xCoord) * 2 + 1] *= -1;
	}
}

extern "C"
void center(float* data, int2 size)
{
	dim3 blockDim(32, 32);
	dim3 gridDim(size.x / 32, size.y / 32);
	centerKernel<<<blockDim, gridDim>>>(data, size);
}

static __global__ void complexToMagnitudeKernel(float* complex, float* magnitude)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	float real = complex[complexIndex];
	float imag = complex[complexIndex + 1];
	magnitude[realIndex] = sqrt(real * real + imag * imag) * 0.5;
}

extern "C"
void complexToMagnitude(float* complex, float* magnitude, int numElements)
{
	complexToMagnitudeKernel<<<32, numElements / 32>>>(complex, magnitude);
}

static __global__ void complexToRealKernel(float* complex, float* real)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	real[realIndex] = complex[complexIndex];
}

extern "C"
void complextoReal(float* complex, float* real, int numElements)
{
	complexToRealKernel<<<32, numElements / 32>>>(complex, real);
}

static __global__ void realToComplexKernel(float* real, float* complex)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	complex[complexIndex] = real[realIndex];
	complex[complexIndex + 1] = 0.0;
}

extern "C"
void realToComplex(float* real, float* complex, int numElements)
{
	realToComplexKernel<<<32, numElements / 32>>>(real, complex);
}

//takes the absolute difference and normalizes assuming that the range is [0,512]
static __global__ void differenceImagesKernel(float* a, float* b, float* result, float scale)
{
	int index = (blockIdx.x * blockDim.x + threadIdx.x)*2;	
	//result[index] = abs( a[index] - b[index] ) * (1.0 / 512.0) * scale;
	//result[index] = abs( a[index] - b[index] ) * (1.0 / 255.0) * scale;
	result[index] = abs( a[index] - b[index] ) * (1.0f / 255.0f);
	//result[index] = abs( a[index]);
	result[index + 1] = 0.0f;
}

extern "C"
void differenceImages(float* a, float* b, float* result, int numElements)
{
	differenceImagesKernel<<<numElements / 64, 64>>>(a, b, result, (1.0f / (float)numElements));
}

static __global__ void computeAveragesKernel(float* a, float* result, int2 size, int2 pSize, int2 offset, float scale)
{
	extern __shared__ float tmpArr[];

	float total = 0.0f;
	int tmpArrIndex = threadIdx.x;
	int startIndex = 2*( pSize.x * (offset.y + size.y / gridDim.y * blockIdx.y + threadIdx.x) + offset.x + (size.x / gridDim.x * blockIdx.x) );
	int endIndex = startIndex + 2*(size.x / gridDim.x);

	for(int i=startIndex; i<endIndex; i+=2)
		//total += a[i];
		total += abs(a[i]);
	// Save partial average
	tmpArr[tmpArrIndex] = total / (float)(size.x / gridDim.x);

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		int tmpArrSize = blockDim.x;
		total = 0.0f;
		for(int i=0; i<tmpArrSize; i++)
		{
			total += tmpArr[i];
		}

		// Save average of partial averages
		//the index is for the smaller result grid
		float r = total * scale / (float)tmpArrSize;
		result[gridDim.x*blockIdx.y + blockIdx.x] = r < 0.0f? 0.0f : r > 1.0f? 1.0f: r; 
		//result[gridDim.x*blockIdx.y + blockIdx.x] = 0.5f + 0.5f * scale * total / (float)tmpArrSize;
	}
}

static __global__ void computeMinMaxKernel(float* a, float* minMax, int2 divFactor)
{
	extern __shared__ float tmpMinMaxArr[];

	int index = threadIdx.x * divFactor.x;
	int endIndex = index + divFactor.x;
	float min = a[index];
	float max = min;
	for(int i = index; i<endIndex; ++i)
	{
		if( a[i] < min )
			min = a[i];
		if( a[i] > max )
			max = a[i];
	}
	tmpMinMaxArr[threadIdx.x*2] = min;
	tmpMinMaxArr[threadIdx.x*2+1] = max;

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		min = tmpMinMaxArr[0];
		max = min;
		for(int i = 0; i<blockDim.x*2; ++i)
		{
			if( tmpMinMaxArr[i] < min )
				min = tmpMinMaxArr[i];
			if( tmpMinMaxArr[i] > max )
				max = tmpMinMaxArr[i];
		}
		minMax[0] = min / 256.0;
		minMax[1] = max / 256.0;
	}
}

static __global__ void computeMinMaxKernel2(float* a, float* minMax, int2 offset, int2 imageSize, int2 paddedSize)
{
	extern __shared__ float tmpMinMaxArr[];

	int index = ((threadIdx.x + offset.y) * paddedSize.x + offset.x) * 2;
	int endIndex = index + imageSize.x * 2;
	float min = a[index];
	float max = min;
	for(int i = index; i<endIndex; i+=2)
	{
		if( a[i] < min )
			min = a[i];
		if( a[i] > max )
			max = a[i];
	}
	tmpMinMaxArr[threadIdx.x*2] = min;
	tmpMinMaxArr[threadIdx.x*2+1] = max;

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		min = tmpMinMaxArr[0];
		max = min;
		for(int i = 0; i<blockDim.x*2; ++i)
		{
			if( tmpMinMaxArr[i] < min )
				min = tmpMinMaxArr[i];
			if( tmpMinMaxArr[i] > max )
				max = tmpMinMaxArr[i];
		}
		minMax[0] = min / 256.0 / 256.0;
		minMax[1] = max / 256.0 / 256.0;
	}
}

static __global__ void normalizeAveragesKernel(float* result, float* minMax)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;	
	result[index] = (result[index] - minMax[0]) / (minMax[1] - minMax[0]);
}

extern "C"
void computeProbabilities(float* a, float* result, int2 divFactor, int2 size, int2 pSize, int2 offset)
{
	printf("%d %d\n", pSize.x, pSize.y);
	int threadsPerBlock = size.y / divFactor.y;
	dim3 gridDim(divFactor.x, divFactor.y);
	// Compute the averages for each of the regions
	int sharedMemSize = sizeof(float) * size.y / divFactor.y;
	static float globalMin = 10e100;
	static float globalMax = -10e100;
	static float uselessAverage = 0.0f;
	static int count = 0;

#if 0 // print values to be averaged
	float* vals = new float[pSize.x * pSize.y * 2];
	cudaMemcpy(vals, a, sizeof(float) * pSize.x * pSize.y * 2, cudaMemcpyDeviceToHost);
	for(int i=0; i<pSize.x * pSize.y; i+=2)
		if( vals[i] > 20000.0f )
			printf("val[%d]: %f\n", i, vals[i]);	
#endif

#if 0 // print averages
	{
                // Calculate averages on host (for comparison)
                float* h = new float[divFactor.x * divFactor.y];
                float* vals = new float[pSize.x * pSize.y * 2];
                int blockStride = size.x / divFactor.x;
                int blockHeight = size.y / divFactor.y;
//              int valsPerRegion = size.x / divFactor.x * size.y / divFactor.y;
                cudaMemcpy(vals, a, sizeof(float) * pSize.x * pSize.y * 2, cudaMemcpyDeviceToHost);
                for(int i=0; i<divFactor.x; ++i)
                        for(int j=0; j<divFactor.y; ++j)
                        {
                                int startIndex = pSize.x * offset.y + offset.x; 
                                startIndex += pSize.x * blockHeight * j;
                                startIndex += blockStride * i;
                                startIndex *= 2;
				
                                int hIndex = divFactor.x * j + i;
                                h[hIndex] = 0.0f;
                                float pAvg = 0.0f;
                                for(int k=0; k<blockHeight; ++k)
                                {
					// Calculate and save partial average
                                        pAvg = 0.0f;
                                        for(int z=0; z<blockStride*2; z+=2)
                                        {
                                                pAvg += vals[startIndex + z];
                                        }
                                        startIndex += 2 * pSize.x;
                                        h[hIndex] += pAvg / (float) blockStride;
                                }       
				// Calculate average of partial averages
                                h[hIndex] /= (float)blockHeight;
                        }

		float* tmp = new float[divFactor.x * divFactor.y];	
		cudaMemcpy(tmp, result, sizeof(float)*divFactor.x*divFactor.y, cudaMemcpyDeviceToHost);
		// print out to compare: averages w/ CUDA and averages on Host (CPU)
		for(int i=0; i<divFactor.x*divFactor.y; ++i)
			printf("Avg[%d]: %f : %f %s\n", i, tmp[i], h[i], (tmp[i]==h[i]?"":"**MISMATCH**") );	
		printf("\n");
		delete tmp;
		delete h;
		delete vals;
	}
#endif

	// Compute the min/max of the averages
	float* minMax;
	cudaMalloc((void**)&minMax, sizeof(float)*2);
	//sharedMemSize = sizeof(float)*divFactor.y*2;
	//computeMinMaxKernel<<<1, divFactor.y, sharedMemSize>>>(result, minMax, divFactor);
	sharedMemSize = sizeof(float)*size.y*2;
	//computeMinMaxKernel<<<1, size.y, sharedMemSize>>>(a, minMax, size);
	computeMinMaxKernel2<<<1, size.y, sharedMemSize>>>(a, minMax, offset, size, pSize);

#if 1 // print min/max
	float shittyScalar;
	{
		//float* avgs = new float[divFactor.x * divFactor.y];	
		//cudaMemcpy(avgs, result, sizeof(float)*divFactor.x*divFactor.y, cudaMemcpyDeviceToHost);
		//int vals = divFactor.x * divFactor.y;
		//float min = avgs[0];
		//float max = avgs[0];
		//for(int i=0; i<vals; ++i)
		//{
		//	if( avgs[i] < min ) min = avgs[i];	
		//	if( avgs[i] > max ) max = avgs[i];	
		//}
		float tmp[2];
		cudaMemcpy( tmp, minMax, sizeof(float)*2, cudaMemcpyDeviceToHost);
		//printf("%f %f\n", tmp[0], tmp[1]);
		globalMin = tmp[0] < globalMin? tmp[0]: globalMin;
		globalMax = tmp[1] > globalMax? tmp[1]: globalMax;
		shittyScalar = tmp[1] / uselessAverage;
		uselessAverage = (uselessAverage * count + tmp[1]) / (count + 1);
		++count;
		printf("%f %f\n", globalMin, globalMax);
		tmp[0] = globalMin;
		tmp[1] = globalMax;
		cudaMemcpy(minMax, tmp, sizeof(float) * 2, cudaMemcpyHostToDevice);
		//printf("Min/Max: %f / %f : %f %f %s\n\n", tmp[0], tmp[1], min, max,
		//	(tmp[0]==min&&tmp[1]==max?"":"**MISMATCH**") );
		//delete avgs;
	}
#endif

	// Normalize each average based on min/max of the averages
	int nBlocks, blockSize;
	if( divFactor.x * divFactor.y < 4 )
	{
		nBlocks = 1;
		blockSize = divFactor.x * divFactor.y;
	}
	else // assuming that divFactor.x * divFactor.y is divisible by 4
	{
		nBlocks = divFactor.x * divFactor.y / 4;
		blockSize = divFactor.x * divFactor.y / nBlocks;
	}
	computeAveragesKernel<<<gridDim, threadsPerBlock, sharedMemSize>>>(a, result, size, pSize, offset, 1.0f / 256.0f / 256.0f);
	//normalizeAveragesKernel<<<nBlocks, blockSize>>>(result, minMax);
	cudaFree(minMax);
}


	.file	"tmpxft_0034e539_00000000-6_gabor.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2207:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2207:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.type	_ZL23normalizeAveragesKernelPfS_, @function
_ZL23normalizeAveragesKernelPfS_:
.LFB2088:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rax
	movq	%rdi, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%rax, 56(%rsp)
	leaq	8(%rsp), %rax
	leaq	16(%rsp), %rdx
	movq	%rsi, 8(%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL23normalizeAveragesKernelPfS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L3:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2088:
	.size	_ZL23normalizeAveragesKernelPfS_, .-_ZL23normalizeAveragesKernelPfS_
	.type	_ZL19computeMinMaxKernelPfS_4int2, @function
_ZL19computeMinMaxKernelPfS_4int2:
.LFB2084:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdx, 8(%rsp)
	leaq	48(%rsp), %rcx
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rax, 80(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rsi, 32(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL19computeMinMaxKernelPfS_4int2(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2084:
	.size	_ZL19computeMinMaxKernelPfS_4int2, .-_ZL19computeMinMaxKernelPfS_4int2
	.type	_ZL14generateFilterPffffff4int2S0_, @function
_ZL14generateFilterPffffff4int2S0_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rsi, 8(%rsp)
	leaq	56(%rsp), %rcx
	leaq	76(%rsp), %rsi
	movq	%rdx, (%rsp)
	leaq	48(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rax, 88(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 24(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 32(%rsp)
	movss	%xmm4, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_ZL14generateFilterPffffff4int2S0_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L12:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_ZL14generateFilterPffffff4int2S0_, .-_ZL14generateFilterPffffff4int2S0_
	.type	_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f, @function
_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f:
.LFB2081:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 104(%rsp)
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL21computeAveragesKernelPfS_4int2S0_S0_f(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L16:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2081:
	.size	_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f, .-_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f
	.type	_ZL21computeAveragesKernelPfS_4int2S0_S0_f, @function
_ZL21computeAveragesKernelPfS_4int2S0_S0_f:
.LFB2082:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdx, 24(%rsp)
	leaq	24(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	16(%rsp), %rcx
	movq	%r8, 8(%rsp)
	leaq	8(%rsp), %r8
	call	_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2082:
	.size	_ZL21computeAveragesKernelPfS_4int2S0_S0_f, .-_ZL21computeAveragesKernelPfS_4int2S0_S0_f
	.type	_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_, @function
_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_:
.LFB2085:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rsp)
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rdx, 80(%rsp)
	leaq	24(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	%rsp, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	movq	%rcx, 88(%rsp)
	leaq	32(%rsp), %rcx
	movq	%r8, 96(%rsp)
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL20computeMinMaxKernel2PfS_4int2S0_S0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L22:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2085:
	.size	_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_, .-_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_
	.type	_ZL20computeMinMaxKernel2PfS_4int2S0_S0_, @function
_ZL20computeMinMaxKernel2PfS_4int2S0_S0_:
.LFB2086:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdx, 24(%rsp)
	leaq	24(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	16(%rsp), %rcx
	movq	%r8, 8(%rsp)
	leaq	8(%rsp), %r8
	call	_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2086:
	.size	_ZL20computeMinMaxKernel2PfS_4int2S0_S0_, .-_ZL20computeMinMaxKernel2PfS_4int2S0_S0_
	.type	_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f, @function
_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f:
.LFB2079:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL22differenceImagesKernelPfS_S_f(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2079:
	.size	_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f, .-_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f
	.type	_ZL22differenceImagesKernelPfS_S_f, @function
_ZL22differenceImagesKernelPfS_S_f:
.LFB2080:
	.cfi_startproc
	endbr64
	jmp	_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f
	.cfi_endproc
.LFE2080:
	.size	_ZL22differenceImagesKernelPfS_S_f, .-_ZL22differenceImagesKernelPfS_S_f
	.type	_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_, @function
_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_:
.LFB2077:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL19realToComplexKernelPfS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L33:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_, .-_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_
	.type	_ZL19realToComplexKernelPfS_, @function
_ZL19realToComplexKernelPfS_:
.LFB2078:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_
	.cfi_endproc
.LFE2078:
	.size	_ZL19realToComplexKernelPfS_, .-_ZL19realToComplexKernelPfS_
	.type	_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_, @function
_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_:
.LFB2075:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL19complexToRealKernelPfS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L38:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_, .-_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_
	.type	_ZL19complexToRealKernelPfS_, @function
_ZL19complexToRealKernelPfS_:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_
	.cfi_endproc
.LFE2076:
	.size	_ZL19complexToRealKernelPfS_, .-_ZL19complexToRealKernelPfS_
	.type	_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_, @function
_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_:
.LFB2073:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL24complexToMagnitudeKernelPfS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L43:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_, .-_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_
	.type	_ZL24complexToMagnitudeKernelPfS_, @function
_ZL24complexToMagnitudeKernelPfS_:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_
	.cfi_endproc
.LFE2074:
	.size	_ZL24complexToMagnitudeKernelPfS_, .-_ZL24complexToMagnitudeKernelPfS_
	.type	_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2, @function
_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2:
.LFB2071:
	.cfi_startproc
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rsi, 64(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_ZL12centerKernelPf4int2(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L48:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2, .-_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2
	.type	_ZL12centerKernelPf4int2, @function
_ZL12centerKernelPf4int2:
.LFB2072:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, 8(%rsp)
	leaq	8(%rsp), %rsi
	call	_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2072:
	.size	_ZL12centerKernelPf4int2, .-_ZL12centerKernelPf4int2
	.type	_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_, @function
_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_:
.LFB2069:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL28multiplyComplexComplexKernelPfS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L54:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_, .-_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_
	.type	_ZL28multiplyComplexComplexKernelPfS_S_, @function
_ZL28multiplyComplexComplexKernelPfS_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_
	.cfi_endproc
.LFE2070:
	.size	_ZL28multiplyComplexComplexKernelPfS_S_, .-_ZL28multiplyComplexComplexKernelPfS_S_
	.type	_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_, @function
_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_:
.LFB2067:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL25multiplyRealComplexKernelPfS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_, .-_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_
	.type	_ZL25multiplyRealComplexKernelPfS_S_, @function
_ZL25multiplyRealComplexKernelPfS_S_:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_
	.cfi_endproc
.LFE2068:
	.size	_ZL25multiplyRealComplexKernelPfS_S_, .-_ZL25multiplyRealComplexKernelPfS_S_
	.type	_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_, @function
_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_:
.LFB2065:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rsi, 104(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rdx, 112(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL14harmonicKernelPffff4int2S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L64:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_, .-_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_
	.type	_ZL14harmonicKernelPffff4int2S0_, @function
_ZL14harmonicKernelPffff4int2S0_:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, 8(%rsp)
	leaq	8(%rsp), %rsi
	movq	%rdx, (%rsp)
	movq	%rsp, %rdx
	call	_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_ZL14harmonicKernelPffff4int2S0_, .-_ZL14harmonicKernelPffff4int2S0_
	.type	_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_, @function
_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_:
.LFB2063:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movss	%xmm0, 20(%rsp)
	movss	%xmm1, 16(%rsp)
	movss	%xmm2, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rsi, 104(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rdx, 112(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL14gaussianKernelPffff4int2S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L70:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L72
	call	__stack_chk_fail@PLT
.L72:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_, .-_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_
	.type	_ZL14gaussianKernelPffff4int2S0_, @function
_ZL14gaussianKernelPffff4int2S0_:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, 8(%rsp)
	leaq	8(%rsp), %rsi
	movq	%rdx, (%rsp)
	movq	%rsp, %rdx
	call	_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_ZL14gaussianKernelPffff4int2S0_, .-_ZL14gaussianKernelPffff4int2S0_
	.globl	gaussian
	.type	gaussian, @function
gaussian:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$64, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %r12
	movq	%rdi, %rbp
	movl	$1, %esi
	movabsq	$274877907008, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdx, %rbx
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movl	%edx, %eax
	cltd
	idivl	%ecx
	movl	$1, %ecx
	movl	%eax, 44(%rsp)
	movl	%eax, 48(%rsp)
	movq	44(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	movss	4(%rsp), %xmm2
	movss	8(%rsp), %xmm1
	testl	%eax, %eax
	movss	12(%rsp), %xmm0
	jne	.L76
	leaq	24(%rsp), %rdx
	leaq	16(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%r12, 16(%rsp)
	movq	%rbx, 24(%rsp)
	call	_ZL45__device_stub__Z14gaussianKernelPffff4int2S0_PffffR4int2S1_
.L76:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L78
	call	__stack_chk_fail@PLT
.L78:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	gaussian, .-gaussian
	.globl	harmonic
	.type	harmonic, @function
harmonic:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$64, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %r12
	movq	%rdi, %rbp
	movl	$1, %esi
	movabsq	$274877907008, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdx, %rbx
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movl	%edx, %eax
	cltd
	idivl	%ecx
	movl	$1, %ecx
	movl	%eax, 44(%rsp)
	movl	%eax, 48(%rsp)
	movq	44(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	movss	4(%rsp), %xmm2
	movss	8(%rsp), %xmm1
	testl	%eax, %eax
	movss	12(%rsp), %xmm0
	jne	.L80
	leaq	24(%rsp), %rdx
	leaq	16(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%r12, 16(%rsp)
	movq	%rbx, 24(%rsp)
	call	_ZL45__device_stub__Z14harmonicKernelPffff4int2S0_PffffR4int2S1_
.L80:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L82
	call	__stack_chk_fail@PLT
.L82:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	harmonic, .-harmonic
	.globl	multiplyRealComplex
	.type	multiplyRealComplex, @function
multiplyRealComplex:
.LFB2029:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r12
	xorl	%r9d, %r9d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	cltd
	movq	%rsi, %rbp
	movl	$32, %esi
	idivl	%esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, %rbx
	movl	$134217729, %edx
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL49__device_stub__Z25multiplyRealComplexKernelPfS_S_PfS_S_
.L84:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	multiplyRealComplex, .-multiplyRealComplex
	.globl	multiplyComplexComplex
	.type	multiplyComplexComplex, @function
multiplyComplexComplex:
.LFB2030:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdx, %r12
	xorl	%r9d, %r9d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	cltd
	movq	%rsi, %rbp
	movl	$64, %esi
	idivl	%esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, %rbx
	movl	$67108865, %edx
	xorl	%r8d, %r8d
	salq	$6, %rdx
	movl	$1, %ecx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L87
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_ZL52__device_stub__Z28multiplyComplexComplexKernelPfS_S_PfS_S_
.L87:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	multiplyComplexComplex, .-multiplyComplexComplex
	.globl	center
	.type	center, @function
center:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%r9d, %r9d
	movq	%rdi, %rbp
	xorl	%r8d, %r8d
	movabsq	$137438953504, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	movq	%rsi, %rax
	movl	$32, %esi
	shrq	$32, %rax
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	%ebx, %eax
	cltd
	movl	%ecx, 32(%rsp)
	movl	$1, %ecx
	idivl	%esi
	movl	$1, %esi
	movl	%eax, 28(%rsp)
	movq	28(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	leaq	8(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%rbx, 8(%rsp)
	call	_ZL37__device_stub__Z12centerKernelPf4int2PfR4int2
.L90:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L92
	call	__stack_chk_fail@PLT
.L92:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	center, .-center
	.globl	complexToMagnitude
	.type	complexToMagnitude, @function
complexToMagnitude:
.LFB2032:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	movl	$32, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%r9d, %r9d
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	movl	$134217729, %edi
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	%rsi, %rbp
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %esi
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movq	20(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZL46__device_stub__Z24complexToMagnitudeKernelPfS_PfS_
.L94:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	complexToMagnitude, .-complexToMagnitude
	.globl	complextoReal
	.type	complextoReal, @function
complextoReal:
.LFB2033:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	movl	$32, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%r9d, %r9d
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	movl	$134217729, %edi
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	%rsi, %rbp
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %esi
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movq	20(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L97
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z19complexToRealKernelPfS_PfS_
.L97:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	complextoReal, .-complextoReal
	.globl	realToComplex
	.type	realToComplex, @function
realToComplex:
.LFB2034:
	.cfi_startproc
	endbr64
	movl	%edx, %eax
	movl	$32, %ecx
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%r9d, %r9d
	cltd
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	movl	$134217729, %edi
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	%rsi, %rbp
	xorl	%r8d, %r8d
	salq	$5, %rdi
	movl	$1, %esi
	movl	%eax, 20(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movq	20(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L100
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z19realToComplexKernelPfS_PfS_
.L100:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	realToComplex, .-realToComplex
	.globl	differenceImages
	.type	differenceImages, @function
differenceImages:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdx, %r13
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%ecx, %ebx
	movl	$64, %ecx
	movl	%ebx, %eax
	cltd
	idivl	%ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	$67108865, %edx
	movl	$1, %ecx
	salq	$6, %rdx
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L103
	cvtsi2ssl	%ebx, %xmm1
	movq	%r13, %rdx
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movss	.LC0(%rip), %xmm0
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	divss	%xmm1, %xmm0
	jmp	_ZL47__device_stub__Z22differenceImagesKernelPfS_S_fPfS_S_f
.L103:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	differenceImages, .-differenceImages
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"%d %d\n"
.LC2:
	.string	"%f %f\n"
	.text
	.globl	computeProbabilities
	.type	computeProbabilities, @function
computeProbabilities:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r9, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	movq	%rcx, %r8
	sarq	$32, %r8
	movl	%r8d, %r14d
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 8(%rsp)
	movl	$2, %edi
	movq	%rsi, 16(%rsp)
	leaq	.LC1(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	movq	%rdx, %rax
	movl	%ebx, %edx
	movq	%r8, 24(%rsp)
	shrq	$32, %rax
	movl	%eax, %r13d
	movq	%rbx, %rax
	shrq	$32, %rax
	movl	%eax, %ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%r14d, %eax
	leaq	40(%rsp), %rdi
	movl	$8, %esi
	cltd
	movq	%r15, 76(%rsp)
	idivl	%r13d
	movl	$1, 84(%rsp)
	movl	%eax, %r14d
	call	cudaMalloc@PLT
	movq	24(%rsp), %r8
	xorl	%r9d, %r9d
	movabsq	$4294967297, %rdi
	movq	%rdi, 104(%rsp)
	movl	108(%rsp), %ecx
	movl	$1, %esi
	leal	0(,%r8,8), %r13d
	movl	%r8d, 100(%rsp)
	movq	100(%rsp), %rdx
	movslq	%r13d, %r13
	movq	%rdi, 88(%rsp)
	movq	%r13, %r8
	movl	$1, 96(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L107
	movq	40(%rsp), %rsi
	movq	8(%rsp), %rdi
	leaq	56(%rsp), %rcx
	leaq	48(%rsp), %rdx
	leaq	64(%rsp), %r8
	movq	%r12, 48(%rsp)
	movq	%rbp, 56(%rsp)
	movq	%rbx, 64(%rsp)
	call	_ZL53__device_stub__Z20computeMinMaxKernel2PfS_4int2S0_S0_PfS_R4int2S1_S1_
.L107:
	movq	40(%rsp), %rsi
	leaq	112(%rsp), %r15
	movl	$2, %ecx
	movl	$8, %edx
	movq	%r15, %rdi
	call	cudaMemcpy@PLT
	movl	_ZZ20computeProbabilitiesE5count(%rip), %edx
	movss	116(%rsp), %xmm3
	leaq	.LC2(%rip), %rsi
	movss	112(%rsp), %xmm0
	minss	_ZZ20computeProbabilitiesE9globalMin(%rip), %xmm0
	movl	$2, %edi
	cvtsi2ssl	%edx, %xmm2
	mulss	_ZZ20computeProbabilitiesE14uselessAverage(%rip), %xmm2
	leal	1(%rdx), %eax
	movaps	%xmm3, %xmm1
	maxss	_ZZ20computeProbabilitiesE9globalMax(%rip), %xmm1
	movl	%eax, _ZZ20computeProbabilitiesE5count(%rip)
	movss	%xmm0, _ZZ20computeProbabilitiesE9globalMin(%rip)
	cvtss2sd	%xmm0, %xmm0
	movss	%xmm1, _ZZ20computeProbabilitiesE9globalMax(%rip)
	cvtss2sd	%xmm1, %xmm1
	addss	%xmm3, %xmm2
	cvtsi2ssl	%eax, %xmm3
	movb	$2, %al
	divss	%xmm3, %xmm2
	movss	%xmm2, _ZZ20computeProbabilitiesE14uselessAverage(%rip)
	call	__printf_chk@PLT
	movss	_ZZ20computeProbabilitiesE9globalMin(%rip), %xmm0
	movq	40(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	movl	$8, %edx
	movss	%xmm0, 112(%rsp)
	movss	_ZZ20computeProbabilitiesE9globalMax(%rip), %xmm0
	movss	%xmm0, 116(%rsp)
	call	cudaMemcpy@PLT
	movl	%r14d, 100(%rsp)
	xorl	%r9d, %r9d
	movq	%r13, %r8
	movabsq	$4294967297, %rax
	movq	76(%rsp), %rdi
	movl	84(%rsp), %esi
	movq	%rax, 104(%rsp)
	movl	108(%rsp), %ecx
	movq	100(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L112
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	leaq	64(%rsp), %rcx
	leaq	56(%rsp), %rdx
	movss	.LC3(%rip), %xmm0
	leaq	88(%rsp), %r8
	movq	%rbp, 56(%rsp)
	movq	%rbx, 64(%rsp)
	movq	%r12, 88(%rsp)
	call	_ZL55__device_stub__Z21computeAveragesKernelPfS_4int2S0_S0_fPfS_R4int2S1_S1_f
.L112:
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L113
	call	__stack_chk_fail@PLT
.L113:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	computeProbabilities, .-computeProbabilities
	.section	.rodata.str1.1
.LC4:
	.string	"_Z23normalizeAveragesKernelPfS_"
.LC5:
	.string	"_Z20computeMinMaxKernel2PfS_4int2S0_S0_"
.LC6:
	.string	"_Z19computeMinMaxKernelPfS_4int2"
.LC7:
	.string	"_Z21computeAveragesKernelPfS_4int2S0_S0_f"
.LC8:
	.string	"_Z22differenceImagesKernelPfS_S_f"
.LC9:
	.string	"_Z19realToComplexKernelPfS_"
.LC10:
	.string	"_Z19complexToRealKernelPfS_"
.LC11:
	.string	"_Z24complexToMagnitudeKernelPfS_"
.LC12:
	.string	"_Z12centerKernelPf4int2"
.LC13:
	.string	"_Z28multiplyComplexComplexKernelPfS_S_"
.LC14:
	.string	"_Z25multiplyRealComplexKernelPfS_S_"
.LC15:
	.string	"_Z14harmonicKernelPffff4int2S0_"
.LC16:
	.string	"_Z14gaussianKernelPffff4int2S0_"
.LC17:
	.string	"_Z14generateFilterPffffff4int2S0_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZL23normalizeAveragesKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL20computeMinMaxKernel2PfS_4int2S0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL19computeMinMaxKernelPfS_4int2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL21computeAveragesKernelPfS_4int2S0_S0_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL22differenceImagesKernelPfS_S_f(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL19realToComplexKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL19complexToRealKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL24complexToMagnitudeKernelPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC12(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZL12centerKernelPf4int2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL28multiplyComplexComplexKernelPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL25multiplyRealComplexKernelPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL14harmonicKernelPffff4int2S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL14gaussianKernelPffff4int2S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZL14generateFilterPffffff4int2S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2090:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZZ20computeProbabilitiesE5count
	.comm	_ZZ20computeProbabilitiesE5count,4,4
	.local	_ZZ20computeProbabilitiesE14uselessAverage
	.comm	_ZZ20computeProbabilitiesE14uselessAverage,4,4
	.data
	.align 4
	.type	_ZZ20computeProbabilitiesE9globalMax, @object
	.size	_ZZ20computeProbabilitiesE9globalMax, 4
_ZZ20computeProbabilitiesE9globalMax:
	.long	-8388608
	.align 4
	.type	_ZZ20computeProbabilitiesE9globalMin, @object
	.size	_ZZ20computeProbabilitiesE9globalMin, 4
_ZZ20computeProbabilitiesE9globalMin:
	.long	2139095040
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1065353216
	.align 4
.LC3:
	.long	931135488
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

static __global__ void generateFilter(float* filter, 
                                      float lambda, 
									  float theta, 
									  float psi, 
									  float sigma, 
									  float gamma,
									  int2 center,
									  int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float yPrime = -x * sin(theta) + y * cos(theta);
	float harmonic = 2.0 * M_PI * xPrime / lambda + psi;
	float exponential = -(xPrime * xPrime + gamma * gamma * yPrime * yPrime) /
	                    (2.0 * sigma * sigma);
	filter[yCoord * size.x + xCoord] = exp(exponential) * cos(harmonic);
}

static __global__ void gaussianKernel(float* filter,
                                      float theta,
                                      float sigma,
								      float gamma,
								      int2 center,
								      int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float yPrime = -x * sin(theta) + y * cos(theta);
	float exponent = -(xPrime * xPrime + gamma * gamma * yPrime * yPrime) /
	                 (2.0 * sigma * sigma);
	filter[yCoord * size.x + xCoord] = exp(exponent) / (2.0 * M_PI * sigma * sigma);
}

extern "C"
void gaussian(float* filter, float theta, float sigma, float gamma, int2 center, int2 size)
{
	int filterSize = size.x;
	dim3 blockDim(64, 64);
	dim3 gridDim(filterSize / 64, filterSize / 64);
	gaussianKernel<<<blockDim, gridDim>>>(filter, theta, sigma, gamma, center, size);
}

static __global__ void harmonicKernel(float* filter,
                                      float theta,
									  float lambda,
									  float psi,
									  int2 center,
									  int2 size)
{
	int xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	int yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	float x = xCoord - center.x;
	float y = yCoord - center.y;
	float xPrime = x * cos(theta) + y * sin(theta);
	float angle = 2.0 * M_PI * xPrime / lambda + psi;
	filter[(yCoord * size.x + xCoord) * 2] = cos(angle);
	filter[(yCoord * size.x + xCoord) * 2 + 1] = sin(angle);
}

extern "C"
void harmonic(float* filter, float theta, float lambda, float psi, int2 center, int2 size)
{
	int filterSize = size.x;
	dim3 blockDim(64, 64);
	dim3 gridDim(filterSize / 64, filterSize / 64);
	harmonicKernel<<<blockDim, gridDim>>>(filter, theta, lambda, psi, center, size);
}

static __global__ void multiplyRealComplexKernel(float* real, float* complex, float* result)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	result[complexIndex] = real[realIndex] * complex[complexIndex];
	result[complexIndex + 1] = real[realIndex] * complex[complexIndex + 1];
	//result[complexIndex] = real[realIndex];
	//result[complexIndex + 1] = 0;

}

extern "C"
void multiplyRealComplex(float* real, float* complex, float* result, int numElements)
{
	multiplyRealComplexKernel<<<numElements / 32, 32>>>(real, complex, result);
}

static __global__ void multiplyComplexComplexKernel(float* a, float* b, float* result)
{
	int realIndex = (blockIdx.x * blockDim.x + threadIdx.x) * 2;
	int imagIndex = realIndex + 1;
	float areal = a[realIndex];
	float acomplex = a[imagIndex];
	float breal = b[realIndex];
	float bcomplex = b[imagIndex];
	result[realIndex] = (areal * breal) - (acomplex * bcomplex);
	result[imagIndex] = (areal * bcomplex) + (breal * acomplex);
	//result[realIndex] = breal;
	//result[imagIndex] = bcomplex;
}

extern "C"
void multiplyComplexComplex(float* a, float* b, float* result, int numElements)
{
	multiplyComplexComplexKernel<<<numElements / 64, 64>>>(a, b, result);
}

static __global__ void centerKernel(float* data, int2 size)
{
	uint xCoord = blockIdx.x * blockDim.x + threadIdx.x;
	uint yCoord = blockIdx.y * blockDim.y + threadIdx.y;
	if ((xCoord + yCoord) & 1u)
	//if ((xCoord + yCoord) % 2 == 1)
	{
		data[(yCoord * size.x + xCoord) * 2] *= -1;
		data[(yCoord * size.x + xCoord) * 2 + 1] *= -1;
	}
}

extern "C"
void center(float* data, int2 size)
{
	dim3 blockDim(32, 32);
	dim3 gridDim(size.x / 32, size.y / 32);
	centerKernel<<<blockDim, gridDim>>>(data, size);
}

static __global__ void complexToMagnitudeKernel(float* complex, float* magnitude)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	float real = complex[complexIndex];
	float imag = complex[complexIndex + 1];
	magnitude[realIndex] = sqrt(real * real + imag * imag) * 0.5;
}

extern "C"
void complexToMagnitude(float* complex, float* magnitude, int numElements)
{
	complexToMagnitudeKernel<<<32, numElements / 32>>>(complex, magnitude);
}

static __global__ void complexToRealKernel(float* complex, float* real)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	real[realIndex] = complex[complexIndex];
}

extern "C"
void complextoReal(float* complex, float* real, int numElements)
{
	complexToRealKernel<<<32, numElements / 32>>>(complex, real);
}

static __global__ void realToComplexKernel(float* real, float* complex)
{
	int realIndex = blockIdx.x * blockDim.x + threadIdx.x;
	int complexIndex = realIndex * 2;
	complex[complexIndex] = real[realIndex];
	complex[complexIndex + 1] = 0.0;
}

extern "C"
void realToComplex(float* real, float* complex, int numElements)
{
	realToComplexKernel<<<32, numElements / 32>>>(real, complex);
}

//takes the absolute difference and normalizes assuming that the range is [0,512]
static __global__ void differenceImagesKernel(float* a, float* b, float* result, float scale)
{
	int index = (blockIdx.x * blockDim.x + threadIdx.x)*2;	
	//result[index] = abs( a[index] - b[index] ) * (1.0 / 512.0) * scale;
	//result[index] = abs( a[index] - b[index] ) * (1.0 / 255.0) * scale;
	result[index] = abs( a[index] - b[index] ) * (1.0f / 255.0f);
	//result[index] = abs( a[index]);
	result[index + 1] = 0.0f;
}

extern "C"
void differenceImages(float* a, float* b, float* result, int numElements)
{
	differenceImagesKernel<<<numElements / 64, 64>>>(a, b, result, (1.0f / (float)numElements));
}

static __global__ void computeAveragesKernel(float* a, float* result, int2 size, int2 pSize, int2 offset, float scale)
{
	extern __shared__ float tmpArr[];

	float total = 0.0f;
	int tmpArrIndex = threadIdx.x;
	int startIndex = 2*( pSize.x * (offset.y + size.y / gridDim.y * blockIdx.y + threadIdx.x) + offset.x + (size.x / gridDim.x * blockIdx.x) );
	int endIndex = startIndex + 2*(size.x / gridDim.x);

	for(int i=startIndex; i<endIndex; i+=2)
		//total += a[i];
		total += abs(a[i]);
	// Save partial average
	tmpArr[tmpArrIndex] = total / (float)(size.x / gridDim.x);

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		int tmpArrSize = blockDim.x;
		total = 0.0f;
		for(int i=0; i<tmpArrSize; i++)
		{
			total += tmpArr[i];
		}

		// Save average of partial averages
		//the index is for the smaller result grid
		float r = total * scale / (float)tmpArrSize;
		result[gridDim.x*blockIdx.y + blockIdx.x] = r < 0.0f? 0.0f : r > 1.0f? 1.0f: r; 
		//result[gridDim.x*blockIdx.y + blockIdx.x] = 0.5f + 0.5f * scale * total / (float)tmpArrSize;
	}
}

static __global__ void computeMinMaxKernel(float* a, float* minMax, int2 divFactor)
{
	extern __shared__ float tmpMinMaxArr[];

	int index = threadIdx.x * divFactor.x;
	int endIndex = index + divFactor.x;
	float min = a[index];
	float max = min;
	for(int i = index; i<endIndex; ++i)
	{
		if( a[i] < min )
			min = a[i];
		if( a[i] > max )
			max = a[i];
	}
	tmpMinMaxArr[threadIdx.x*2] = min;
	tmpMinMaxArr[threadIdx.x*2+1] = max;

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		min = tmpMinMaxArr[0];
		max = min;
		for(int i = 0; i<blockDim.x*2; ++i)
		{
			if( tmpMinMaxArr[i] < min )
				min = tmpMinMaxArr[i];
			if( tmpMinMaxArr[i] > max )
				max = tmpMinMaxArr[i];
		}
		minMax[0] = min / 256.0;
		minMax[1] = max / 256.0;
	}
}

static __global__ void computeMinMaxKernel2(float* a, float* minMax, int2 offset, int2 imageSize, int2 paddedSize)
{
	extern __shared__ float tmpMinMaxArr[];

	int index = ((threadIdx.x + offset.y) * paddedSize.x + offset.x) * 2;
	int endIndex = index + imageSize.x * 2;
	float min = a[index];
	float max = min;
	for(int i = index; i<endIndex; i+=2)
	{
		if( a[i] < min )
			min = a[i];
		if( a[i] > max )
			max = a[i];
	}
	tmpMinMaxArr[threadIdx.x*2] = min;
	tmpMinMaxArr[threadIdx.x*2+1] = max;

	__syncthreads();

	if( threadIdx.x == 0 )
	{
		min = tmpMinMaxArr[0];
		max = min;
		for(int i = 0; i<blockDim.x*2; ++i)
		{
			if( tmpMinMaxArr[i] < min )
				min = tmpMinMaxArr[i];
			if( tmpMinMaxArr[i] > max )
				max = tmpMinMaxArr[i];
		}
		minMax[0] = min / 256.0 / 256.0;
		minMax[1] = max / 256.0 / 256.0;
	}
}

static __global__ void normalizeAveragesKernel(float* result, float* minMax)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x;	
	result[index] = (result[index] - minMax[0]) / (minMax[1] - minMax[0]);
}

extern "C"
void computeProbabilities(float* a, float* result, int2 divFactor, int2 size, int2 pSize, int2 offset)
{
	printf("%d %d\n", pSize.x, pSize.y);
	int threadsPerBlock = size.y / divFactor.y;
	dim3 gridDim(divFactor.x, divFactor.y);
	// Compute the averages for each of the regions
	int sharedMemSize = sizeof(float) * size.y / divFactor.y;
	static float globalMin = 10e100;
	static float globalMax = -10e100;
	static float uselessAverage = 0.0f;
	static int count = 0;

#if 0 // print values to be averaged
	float* vals = new float[pSize.x * pSize.y * 2];
	hipMemcpy(vals, a, sizeof(float) * pSize.x * pSize.y * 2, hipMemcpyDeviceToHost);
	for(int i=0; i<pSize.x * pSize.y; i+=2)
		if( vals[i] > 20000.0f )
			printf("val[%d]: %f\n", i, vals[i]);	
#endif

#if 0 // print averages
	{
                // Calculate averages on host (for comparison)
                float* h = new float[divFactor.x * divFactor.y];
                float* vals = new float[pSize.x * pSize.y * 2];
                int blockStride = size.x / divFactor.x;
                int blockHeight = size.y / divFactor.y;
//              int valsPerRegion = size.x / divFactor.x * size.y / divFactor.y;
                hipMemcpy(vals, a, sizeof(float) * pSize.x * pSize.y * 2, hipMemcpyDeviceToHost);
                for(int i=0; i<divFactor.x; ++i)
                        for(int j=0; j<divFactor.y; ++j)
                        {
                                int startIndex = pSize.x * offset.y + offset.x; 
                                startIndex += pSize.x * blockHeight * j;
                                startIndex += blockStride * i;
                                startIndex *= 2;
				
                                int hIndex = divFactor.x * j + i;
                                h[hIndex] = 0.0f;
                                float pAvg = 0.0f;
                                for(int k=0; k<blockHeight; ++k)
                                {
					// Calculate and save partial average
                                        pAvg = 0.0f;
                                        for(int z=0; z<blockStride*2; z+=2)
                                        {
                                                pAvg += vals[startIndex + z];
                                        }
                                        startIndex += 2 * pSize.x;
                                        h[hIndex] += pAvg / (float) blockStride;
                                }       
				// Calculate average of partial averages
                                h[hIndex] /= (float)blockHeight;
                        }

		float* tmp = new float[divFactor.x * divFactor.y];	
		hipMemcpy(tmp, result, sizeof(float)*divFactor.x*divFactor.y, hipMemcpyDeviceToHost);
		// print out to compare: averages w/ CUDA and averages on Host (CPU)
		for(int i=0; i<divFactor.x*divFactor.y; ++i)
			printf("Avg[%d]: %f : %f %s\n", i, tmp[i], h[i], (tmp[i]==h[i]?"":"**MISMATCH**") );	
		printf("\n");
		delete tmp;
		delete h;
		delete vals;
	}
#endif

	// Compute the min/max of the averages
	float* minMax;
	hipMalloc((void**)&minMax, sizeof(float)*2);
	//sharedMemSize = sizeof(float)*divFactor.y*2;
	//computeMinMaxKernel<<<1, divFactor.y, sharedMemSize>>>(result, minMax, divFactor);
	sharedMemSize = sizeof(float)*size.y*2;
	//computeMinMaxKernel<<<1, size.y, sharedMemSize>>>(a, minMax, size);
	computeMinMaxKernel2<<<1, size.y, sharedMemSize>>>(a, minMax, offset, size, pSize);

#if 1 // print min/max
	float shittyScalar;
	{
		//float* avgs = new float[divFactor.x * divFactor.y];	
		//cudaMemcpy(avgs, result, sizeof(float)*divFactor.x*divFactor.y, cudaMemcpyDeviceToHost);
		//int vals = divFactor.x * divFactor.y;
		//float min = avgs[0];
		//float max = avgs[0];
		//for(int i=0; i<vals; ++i)
		//{
		//	if( avgs[i] < min ) min = avgs[i];	
		//	if( avgs[i] > max ) max = avgs[i];	
		//}
		float tmp[2];
		hipMemcpy( tmp, minMax, sizeof(float)*2, hipMemcpyDeviceToHost);
		//printf("%f %f\n", tmp[0], tmp[1]);
		globalMin = tmp[0] < globalMin? tmp[0]: globalMin;
		globalMax = tmp[1] > globalMax? tmp[1]: globalMax;
		shittyScalar = tmp[1] / uselessAverage;
		uselessAverage = (uselessAverage * count + tmp[1]) / (count + 1);
		++count;
		printf("%f %f\n", globalMin, globalMax);
		tmp[0] = globalMin;
		tmp[1] = globalMax;
		hipMemcpy(minMax, tmp, sizeof(float) * 2, hipMemcpyHostToDevice);
		//printf("Min/Max: %f / %f : %f %f %s\n\n", tmp[0], tmp[1], min, max,
		//	(tmp[0]==min&&tmp[1]==max?"":"**MISMATCH**") );
		//delete avgs;
	}
#endif

	// Normalize each average based on min/max of the averages
	int nBlocks, blockSize;
	if( divFactor.x * divFactor.y < 4 )
	{
		nBlocks = 1;
		blockSize = divFactor.x * divFactor.y;
	}
	else // assuming that divFactor.x * divFactor.y is divisible by 4
	{
		nBlocks = divFactor.x * divFactor.y / 4;
		blockSize = divFactor.x * divFactor.y / nBlocks;
	}
	computeAveragesKernel<<<gridDim, threadsPerBlock, sharedMemSize>>>(a, result, size, pSize, offset, 1.0f / 256.0f / 256.0f);
	//normalizeAveragesKernel<<<nBlocks, blockSize>>>(result, minMax);
	hipFree(minMax);
}


	.text
	.file	"gabor.hip"
	.globl	gaussian                        # -- Begin function gaussian
	.type	gaussian,@function
gaussian:                               # @gaussian
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movss	%xmm2, 12(%rsp)                 # 4-byte Spill
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rdi, %r15
	leal	63(%rdx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$6, %eax
	movq	%rax, %rdx
	shlq	$32, %rdx
	orq	%rax, %rdx
	movabsq	$274877907008, %rdi             # imm = 0x4000000040
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movq	%r14, %rsi
	movq	%rbx, %rdx
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_ # TAILCALL
.Lfunc_end0:
	.size	gaussian, .Lfunc_end0-gaussian
	.cfi_endproc
                                        # -- End function
	.type	_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,@function # -- Begin function _ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_: # @_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rsi, (%rax)
	leaq	48(%rsp), %rcx
	movq	%rdx, (%rcx)
	leaq	40(%rsp), %rdx
	movq	%rdi, (%rdx)
	leaq	20(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	16(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	12(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rax, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_, .Lfunc_end1-_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.cfi_endproc
                                        # -- End function
	.globl	harmonic                        # -- Begin function harmonic
	.type	harmonic,@function
harmonic:                               # @harmonic
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movss	%xmm2, 12(%rsp)                 # 4-byte Spill
	movss	%xmm1, 8(%rsp)                  # 4-byte Spill
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%rdi, %r15
	leal	63(%rdx), %eax
	testl	%ebx, %ebx
	cmovnsl	%ebx, %eax
	sarl	$6, %eax
	movq	%rax, %rdx
	shlq	$32, %rdx
	orq	%rax, %rdx
	movabsq	$274877907008, %rdi             # imm = 0x4000000040
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movq	%r14, %rsi
	movq	%rbx, %rdx
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_ # TAILCALL
.Lfunc_end2:
	.size	harmonic, .Lfunc_end2-harmonic
	.cfi_endproc
                                        # -- End function
	.type	_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,@function # -- Begin function _ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_: # @_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rsi, (%rax)
	leaq	48(%rsp), %rcx
	movq	%rdx, (%rcx)
	leaq	40(%rsp), %rdx
	movq	%rdi, (%rdx)
	leaq	20(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	16(%rsp), %rdi
	movss	%xmm1, (%rdi)
	leaq	12(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rsi, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rax, 32(%rbx)
	movq	%rcx, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_, .Lfunc_end3-_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.cfi_endproc
                                        # -- End function
	.globl	multiplyRealComplex             # -- Begin function multiplyRealComplex
	.type	multiplyRealComplex,@function
multiplyRealComplex:                    # @multiplyRealComplex
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leal	31(%rcx), %edi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edi
	sarl	$5, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 32
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL40__device_stub__multiplyRealComplexKernelPfS_S_ # TAILCALL
.Lfunc_end4:
	.size	multiplyRealComplex, .Lfunc_end4-multiplyRealComplex
	.cfi_endproc
                                        # -- End function
	.type	_ZL40__device_stub__multiplyRealComplexKernelPfS_S_,@function # -- Begin function _ZL40__device_stub__multiplyRealComplexKernelPfS_S_
_ZL40__device_stub__multiplyRealComplexKernelPfS_S_: # @_ZL40__device_stub__multiplyRealComplexKernelPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL25multiplyRealComplexKernelPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZL40__device_stub__multiplyRealComplexKernelPfS_S_, .Lfunc_end5-_ZL40__device_stub__multiplyRealComplexKernelPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	multiplyComplexComplex          # -- Begin function multiplyComplexComplex
	.type	multiplyComplexComplex,@function
multiplyComplexComplex:                 # @multiplyComplexComplex
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
                                        # kill: def $ecx killed $ecx def $rcx
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leal	63(%rcx), %edi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edi
	sarl	$6, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 32
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_ # TAILCALL
.Lfunc_end6:
	.size	multiplyComplexComplex, .Lfunc_end6-multiplyComplexComplex
	.cfi_endproc
                                        # -- End function
	.type	_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_,@function # -- Begin function _ZL43__device_stub__multiplyComplexComplexKernelPfS_S_
_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_: # @_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL28multiplyComplexComplexKernelPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_, .Lfunc_end7-_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	center                          # -- Begin function center
	.type	center,@function
center:                                 # @center
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rsi, %rax
	shrq	$32, %rax
	leal	31(%rsi), %ecx
	testl	%ebx, %ebx
	cmovnsl	%ebx, %ecx
	sarl	$5, %ecx
	leal	31(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	movq	%rdi, %r14
	sarl	$5, %edx
	shlq	$32, %rdx
	orq	%rcx, %rdx
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE # TAILCALL
.Lfunc_end8:
	.size	center, .Lfunc_end8-center
	.cfi_endproc
                                        # -- End function
	.type	_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE,@function # -- Begin function _ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE
_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE: # @_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rsi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL12centerKernelPf15HIP_vector_typeIiLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE, .Lfunc_end9-_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	complexToMagnitude              # -- Begin function complexToMagnitude
	.type	complexToMagnitude,@function
complexToMagnitude:                     # @complexToMagnitude
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leal	31(%rdx), %eax
	testl	%edx, %edx
	cmovsl	%eax, %edx
	sarl	$5, %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$32, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB10_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB10_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZL39__device_stub__complexToMagnitudeKernelPfS_ # TAILCALL
.Lfunc_end10:
	.size	complexToMagnitude, .Lfunc_end10-complexToMagnitude
	.cfi_endproc
                                        # -- End function
	.type	_ZL39__device_stub__complexToMagnitudeKernelPfS_,@function # -- Begin function _ZL39__device_stub__complexToMagnitudeKernelPfS_
_ZL39__device_stub__complexToMagnitudeKernelPfS_: # @_ZL39__device_stub__complexToMagnitudeKernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL24complexToMagnitudeKernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_ZL39__device_stub__complexToMagnitudeKernelPfS_, .Lfunc_end11-_ZL39__device_stub__complexToMagnitudeKernelPfS_
	.cfi_endproc
                                        # -- End function
	.globl	complextoReal                   # -- Begin function complextoReal
	.type	complextoReal,@function
complextoReal:                          # @complextoReal
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leal	31(%rdx), %eax
	testl	%edx, %edx
	cmovsl	%eax, %edx
	sarl	$5, %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$32, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB12_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB12_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZL34__device_stub__complexToRealKernelPfS_ # TAILCALL
.Lfunc_end12:
	.size	complextoReal, .Lfunc_end12-complextoReal
	.cfi_endproc
                                        # -- End function
	.type	_ZL34__device_stub__complexToRealKernelPfS_,@function # -- Begin function _ZL34__device_stub__complexToRealKernelPfS_
_ZL34__device_stub__complexToRealKernelPfS_: # @_ZL34__device_stub__complexToRealKernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL19complexToRealKernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_ZL34__device_stub__complexToRealKernelPfS_, .Lfunc_end13-_ZL34__device_stub__complexToRealKernelPfS_
	.cfi_endproc
                                        # -- End function
	.globl	realToComplex                   # -- Begin function realToComplex
	.type	realToComplex,@function
realToComplex:                          # @realToComplex
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leal	31(%rdx), %eax
	testl	%edx, %edx
	cmovsl	%eax, %edx
	sarl	$5, %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$32, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB14_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB14_2:
	.cfi_def_cfa_offset 32
	movq	%r14, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZL34__device_stub__realToComplexKernelPfS_ # TAILCALL
.Lfunc_end14:
	.size	realToComplex, .Lfunc_end14-realToComplex
	.cfi_endproc
                                        # -- End function
	.type	_ZL34__device_stub__realToComplexKernelPfS_,@function # -- Begin function _ZL34__device_stub__realToComplexKernelPfS_
_ZL34__device_stub__realToComplexKernelPfS_: # @_ZL34__device_stub__realToComplexKernelPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL19realToComplexKernelPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_ZL34__device_stub__realToComplexKernelPfS_, .Lfunc_end15-_ZL34__device_stub__realToComplexKernelPfS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function differenceImages
.LCPI16_0:
	.long	0x3f800000                      # float 1
	.text
	.globl	differenceImages
	.type	differenceImages,@function
differenceImages:                       # @differenceImages
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %r12d
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leal	63(%r12), %edi
	testl	%ecx, %ecx
	cmovnsl	%ecx, %edi
	sarl	$6, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$64, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB16_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB16_2:
	.cfi_def_cfa_offset 48
	cvtsi2ss	%r12d, %xmm1
	movss	.LCPI16_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	divss	%xmm1, %xmm0
	movq	%r15, %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL37__device_stub__differenceImagesKernelPfS_S_f # TAILCALL
.Lfunc_end16:
	.size	differenceImages, .Lfunc_end16-differenceImages
	.cfi_endproc
                                        # -- End function
	.type	_ZL37__device_stub__differenceImagesKernelPfS_S_f,@function # -- Begin function _ZL37__device_stub__differenceImagesKernelPfS_S_f
_ZL37__device_stub__differenceImagesKernelPfS_S_f: # @_ZL37__device_stub__differenceImagesKernelPfS_S_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL22differenceImagesKernelPfS_S_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_ZL37__device_stub__differenceImagesKernelPfS_S_f, .Lfunc_end17-_ZL37__device_stub__differenceImagesKernelPfS_S_f
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function computeProbabilities
.LCPI18_0:
	.long	0x37800000                      # float 1.52587891E-5
	.text
	.globl	computeProbabilities
	.type	computeProbabilities,@function
computeProbabilities:                   # @computeProbabilities
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 32(%rsp)                   # 8-byte Spill
	movq	%r8, %r14
	movq	%rcx, %r15
	movq	%rdx, %rbp
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movabsq	$4294967296, %r12               # imm = 0x100000000
	movq	%rdx, %rbx
	shrq	$32, %rbx
	movq	%rcx, %r13
	shrq	$32, %r13
	movq	%r8, %rdx
	shrq	$32, %rdx
	movl	$.L.str, %edi
	movl	%r14d, %esi
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	printf
	movl	%r13d, %eax
	cltd
	idivl	%ebx
	movl	%eax, 20(%rsp)                  # 4-byte Spill
	leaq	8(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
	movq	%r15, %rax
	shrq	$29, %rax
	movslq	%eax, %rbx
	andq	$-8, %rbx
	btsq	$32, %r13
	leaq	1(%r12), %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	movq	%rbx, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB18_2
# %bb.1:
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	32(%rsp), %rdx                  # 8-byte Reload
	movq	%r15, %rcx
	movq	%r14, %r8
	callq	_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
.LBB18_2:
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %r13
	movl	$8, %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	4(%r13), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	minss	_ZZ20computeProbabilitiesE9globalMin(%rip), %xmm0
	movss	%xmm0, _ZZ20computeProbabilitiesE9globalMin(%rip)
	movl	_ZZ20computeProbabilitiesE5count(%rip), %eax
	cvtsi2ss	%eax, %xmm2
	mulss	_ZZ20computeProbabilitiesE14uselessAverage(%rip), %xmm2
	addss	%xmm1, %xmm2
	maxss	_ZZ20computeProbabilitiesE9globalMax(%rip), %xmm1
	movss	%xmm1, _ZZ20computeProbabilitiesE9globalMax(%rip)
	incl	%eax
	cvtsi2ss	%eax, %xmm3
	divss	%xmm3, %xmm2
	movss	%xmm2, _ZZ20computeProbabilitiesE14uselessAverage(%rip)
	movl	%eax, _ZZ20computeProbabilitiesE5count(%rip)
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	movl	$.L.str.1, %edi
	movb	$2, %al
	callq	printf
	movss	_ZZ20computeProbabilitiesE9globalMin(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r13)
	movss	_ZZ20computeProbabilitiesE9globalMax(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 4(%r13)
	movq	8(%rsp), %rdi
	movl	$8, %edx
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	20(%rsp), %edx                  # 4-byte Reload
	movabsq	$4294967296, %rax               # imm = 0x100000000
	orq	%rax, %rdx
	movq	%rbp, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	movq	%rbx, %r8
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB18_4
# %bb.3:
	movss	.LCPI18_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movq	%r14, %rcx
	movq	32(%rsp), %r8                   # 8-byte Reload
	callq	_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
.LBB18_4:
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	computeProbabilities, .Lfunc_end18-computeProbabilities
	.cfi_endproc
                                        # -- End function
	.type	_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,@function # -- Begin function _ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_: # @_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdx, (%rax)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%rdi, (%r8)
	leaq	24(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	96(%rsp), %rbx
	movq	%r8, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_, .Lfunc_end19-_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.cfi_endproc
                                        # -- End function
	.type	_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,@function # -- Begin function _ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f: # @_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdx, (%rax)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%rdi, (%r8)
	leaq	24(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%r8, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%rsi, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f, .Lfunc_end20-_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB21_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB21_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL25multiplyRealComplexKernelPfS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL28multiplyComplexComplexKernelPfS_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL12centerKernelPf15HIP_vector_typeIiLj2EE, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL24complexToMagnitudeKernelPfS_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL19complexToRealKernelPfS_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL19realToComplexKernelPfS_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL22differenceImagesKernelPfS_S_f, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end21:
	.size	__hip_module_ctor, .Lfunc_end21-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB22_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB22_2:
	retq
.Lfunc_end22:
	.size	__hip_module_dtor, .Lfunc_end22-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,@object # @_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_:
	.quad	_ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.size	_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_, 8

	.type	_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,@object # @_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.p2align	3, 0x0
_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_:
	.quad	_ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.size	_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_, 8

	.type	_ZL25multiplyRealComplexKernelPfS_S_,@object # @_ZL25multiplyRealComplexKernelPfS_S_
	.p2align	3, 0x0
_ZL25multiplyRealComplexKernelPfS_S_:
	.quad	_ZL40__device_stub__multiplyRealComplexKernelPfS_S_
	.size	_ZL25multiplyRealComplexKernelPfS_S_, 8

	.type	_ZL28multiplyComplexComplexKernelPfS_S_,@object # @_ZL28multiplyComplexComplexKernelPfS_S_
	.p2align	3, 0x0
_ZL28multiplyComplexComplexKernelPfS_S_:
	.quad	_ZL43__device_stub__multiplyComplexComplexKernelPfS_S_
	.size	_ZL28multiplyComplexComplexKernelPfS_S_, 8

	.type	_ZL12centerKernelPf15HIP_vector_typeIiLj2EE,@object # @_ZL12centerKernelPf15HIP_vector_typeIiLj2EE
	.p2align	3, 0x0
_ZL12centerKernelPf15HIP_vector_typeIiLj2EE:
	.quad	_ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE
	.size	_ZL12centerKernelPf15HIP_vector_typeIiLj2EE, 8

	.type	_ZL24complexToMagnitudeKernelPfS_,@object # @_ZL24complexToMagnitudeKernelPfS_
	.p2align	3, 0x0
_ZL24complexToMagnitudeKernelPfS_:
	.quad	_ZL39__device_stub__complexToMagnitudeKernelPfS_
	.size	_ZL24complexToMagnitudeKernelPfS_, 8

	.type	_ZL19complexToRealKernelPfS_,@object # @_ZL19complexToRealKernelPfS_
	.p2align	3, 0x0
_ZL19complexToRealKernelPfS_:
	.quad	_ZL34__device_stub__complexToRealKernelPfS_
	.size	_ZL19complexToRealKernelPfS_, 8

	.type	_ZL19realToComplexKernelPfS_,@object # @_ZL19realToComplexKernelPfS_
	.p2align	3, 0x0
_ZL19realToComplexKernelPfS_:
	.quad	_ZL34__device_stub__realToComplexKernelPfS_
	.size	_ZL19realToComplexKernelPfS_, 8

	.type	_ZL22differenceImagesKernelPfS_S_f,@object # @_ZL22differenceImagesKernelPfS_S_f
	.p2align	3, 0x0
_ZL22differenceImagesKernelPfS_S_f:
	.quad	_ZL37__device_stub__differenceImagesKernelPfS_S_f
	.size	_ZL22differenceImagesKernelPfS_S_f, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d %d\n"
	.size	.L.str, 7

	.type	_ZZ20computeProbabilitiesE9globalMin,@object # @_ZZ20computeProbabilitiesE9globalMin
	.data
	.p2align	2, 0x0
_ZZ20computeProbabilitiesE9globalMin:
	.long	0x7f800000                      # float +Inf
	.size	_ZZ20computeProbabilitiesE9globalMin, 4

	.type	_ZZ20computeProbabilitiesE9globalMax,@object # @_ZZ20computeProbabilitiesE9globalMax
	.p2align	2, 0x0
_ZZ20computeProbabilitiesE9globalMax:
	.long	0xff800000                      # float -Inf
	.size	_ZZ20computeProbabilitiesE9globalMax, 4

	.type	_ZZ20computeProbabilitiesE14uselessAverage,@object # @_ZZ20computeProbabilitiesE14uselessAverage
	.local	_ZZ20computeProbabilitiesE14uselessAverage
	.comm	_ZZ20computeProbabilitiesE14uselessAverage,4,4
	.type	_ZZ20computeProbabilitiesE5count,@object # @_ZZ20computeProbabilitiesE5count
	.local	_ZZ20computeProbabilitiesE5count
	.comm	_ZZ20computeProbabilitiesE5count,4,4
	.type	_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,@object # @_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_:
	.quad	_ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.size	_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%f %f\n"
	.size	.L.str.1, 7

	.type	_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,@object # @_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f:
	.quad	_ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.size	_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_"
	.size	.L__unnamed_1, 52

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_"
	.size	.L__unnamed_2, 52

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZL25multiplyRealComplexKernelPfS_S_"
	.size	.L__unnamed_3, 37

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL28multiplyComplexComplexKernelPfS_S_"
	.size	.L__unnamed_4, 40

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZL12centerKernelPf15HIP_vector_typeIiLj2EE"
	.size	.L__unnamed_5, 44

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_ZL24complexToMagnitudeKernelPfS_"
	.size	.L__unnamed_6, 34

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_ZL19complexToRealKernelPfS_"
	.size	.L__unnamed_7, 29

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_ZL19realToComplexKernelPfS_"
	.size	.L__unnamed_8, 29

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_ZL22differenceImagesKernelPfS_S_f"
	.size	.L__unnamed_9, 35

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_"
	.size	.L__unnamed_10, 60

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f"
	.size	.L__unnamed_11, 62

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL29__device_stub__gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.addrsig_sym _ZL29__device_stub__harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.addrsig_sym _ZL40__device_stub__multiplyRealComplexKernelPfS_S_
	.addrsig_sym _ZL43__device_stub__multiplyComplexComplexKernelPfS_S_
	.addrsig_sym _ZL27__device_stub__centerKernelPf15HIP_vector_typeIiLj2EE
	.addrsig_sym _ZL39__device_stub__complexToMagnitudeKernelPfS_
	.addrsig_sym _ZL34__device_stub__complexToRealKernelPfS_
	.addrsig_sym _ZL34__device_stub__realToComplexKernelPfS_
	.addrsig_sym _ZL37__device_stub__differenceImagesKernelPfS_S_f
	.addrsig_sym _ZL35__device_stub__computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.addrsig_sym _ZL36__device_stub__computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.addrsig_sym _ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.addrsig_sym _ZL25multiplyRealComplexKernelPfS_S_
	.addrsig_sym _ZL28multiplyComplexComplexKernelPfS_S_
	.addrsig_sym _ZL12centerKernelPf15HIP_vector_typeIiLj2EE
	.addrsig_sym _ZL24complexToMagnitudeKernelPfS_
	.addrsig_sym _ZL19complexToRealKernelPfS_
	.addrsig_sym _ZL19realToComplexKernelPfS_
	.addrsig_sym _ZL22differenceImagesKernelPfS_S_f
	.addrsig_sym _ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.addrsig_sym _ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_,comdat
	.globl	_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_ ; -- Begin function _ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_
	.p2align	8
	.type	_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_,@function
_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_: ; @_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s2, 0x48000000, |s5|
	s_and_b32 s12, s5, 0x7fffffff
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_2
; %bb.1:
	s_and_b32 s3, s12, 0x7fffff
	s_lshr_b32 s8, s12, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s3, 0xfe5163ab
	s_mul_i32 s10, s3, 0x3c439041
	s_mul_hi_u32 s11, s3, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0xdb629599
	s_mul_hi_u32 s13, s3, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s13
	s_mul_i32 s13, s3, 0xf534ddc0
	s_mul_hi_u32 s16, s3, 0xf534ddc0
	s_add_u32 s11, s11, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s3, 0xfc2757d1
	s_mul_hi_u32 s17, s3, 0xfc2757d1
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s3, 0x4e441529
	s_mul_hi_u32 s18, s3, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s18, s3, 0xfe5163ab
	s_mul_hi_u32 s19, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s20, s10, s13
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s18, s10
	s_add_u32 s3, s17, s3
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s16
	s_cselect_b32 s3, s13, s3
	s_cselect_b32 s13, s16, s17
	s_add_i32 s18, s18, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s16, s11, s3
	s_cselect_b32 s3, s3, s13
	s_cselect_b32 s11, s20, s11
	s_cselect_b32 s13, s9, s20
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s3, s16, s3
	s_cselect_b32 s16, s11, s16
	s_cselect_b32 s11, s13, s11
	s_cselect_b32 s9, s9, s13
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v1, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v2, s3, s16, v1
	v_alignbit_b32 v3, s16, s11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v2
	v_cndmask_b32_e64 v2, v3, s16, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s3, s3, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, s3, v2, 30
	s_bfe_u32 s8, s3, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s13, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v3, s13, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v4, v3
	v_min_u32_e32 v4, 32, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 23, v4
	v_alignbit_b32 v1, s11, s9, v1
	v_sub_nc_u32_e32 v5, 31, v4
	v_cndmask_b32_e64 v1, v1, s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v2, v2, v1, 30
	v_alignbit_b32 v1, v1, s9, 30
	s_lshr_b32 s9, s3, 29
	s_lshl_b32 s9, s9, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, s13, v2
	v_xor_b32_e32 v1, s13, v1
	s_or_b32 s10, s9, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, s10, v6
	v_alignbit_b32 v3, v3, v2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v1, v2, v1, v5
	v_alignbit_b32 v2, v3, v1, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v5, v2
	v_min_u32_e32 v5, 32, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, 31, v5
	v_alignbit_b32 v1, v2, v1, v7
	v_lshrrev_b32_e32 v2, 9, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v1, 9, v1
	v_or_b32_e32 v2, v2, v6
	v_add_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v3, 23, v4
	v_sub_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x3fc90fda, v2
	v_add_nc_u32_e32 v1, 0x33000000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0x3fc90fda, v2, -v3
	v_or_b32_e32 v1, s9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v2, v2, 0x33a22168, v4
	s_lshr_b32 s9, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s8, s8, s9
	v_fmac_f32_e32 v2, 0x3fc90fda, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v1, v3, v2
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr1
.LBB0_3:                                ; %Flow93
	v_mov_b32_e32 v2, s8
	v_mul_f32_e64 v4, 0x3f22f983, |s5|
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v4
	v_fma_f32 v1, 0xbfc90fda, v2, |s5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0xb3a22168, v1
	v_fmamk_f32 v1, v2, 0xa7c234c4, v1
	v_cvt_i32_f32_e32 v2, v2
.LBB0_5:                                ; %_ZL3cosf.exit
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_7
; %bb.6:
	s_and_b32 s3, s12, 0x7fffff
	s_lshr_b32 s8, s12, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s3, 0xfe5163ab
	s_mul_i32 s10, s3, 0x3c439041
	s_mul_hi_u32 s11, s3, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0xdb629599
	s_mul_hi_u32 s13, s3, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s13
	s_mul_i32 s13, s3, 0xf534ddc0
	s_mul_hi_u32 s16, s3, 0xf534ddc0
	s_add_u32 s11, s11, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s3, 0xfc2757d1
	s_mul_hi_u32 s17, s3, 0xfc2757d1
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s3, 0x4e441529
	s_mul_hi_u32 s18, s3, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s18, s3, 0xfe5163ab
	s_mul_hi_u32 s19, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s20, s10, s13
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s18, s10
	s_add_u32 s3, s17, s3
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s16
	s_cselect_b32 s3, s13, s3
	s_cselect_b32 s13, s16, s17
	s_add_i32 s18, s18, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s16, s11, s3
	s_cselect_b32 s3, s3, s13
	s_cselect_b32 s11, s20, s11
	s_cselect_b32 s13, s9, s20
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s3, s16, s3
	s_cselect_b32 s16, s11, s16
	s_cselect_b32 s11, s13, s11
	s_cselect_b32 s9, s9, s13
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v3, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v5, s3, s16, v3
	v_alignbit_b32 v6, s16, s11, v3
	v_alignbit_b32 v3, s11, s9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s8, v5
	v_cndmask_b32_e64 v5, v6, s16, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, s11, s10
	s_cselect_b32 s3, s3, s8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s3, v5, 30
	s_bfe_u32 s8, s3, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v3, 30
	s_sub_i32 s13, 0, s8
	v_alignbit_b32 v3, v3, s9, 30
	v_xor_b32_e32 v6, s13, v6
	s_lshr_b32 s9, s3, 29
	v_xor_b32_e32 v5, s13, v5
	s_lshl_b32 s9, s9, 31
	v_xor_b32_e32 v3, s13, v3
	v_clz_i32_u32_e32 v7, v6
	s_or_b32 s10, s9, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v7, 32, v7
	v_sub_nc_u32_e32 v8, 31, v7
	v_lshlrev_b32_e32 v9, 23, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v5, v8
	v_alignbit_b32 v3, v5, v3, v8
	v_sub_nc_u32_e32 v9, s10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v6, v3, 9
	v_clz_i32_u32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v8, 32, v8
	v_sub_nc_u32_e32 v10, 31, v8
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v5, v3, v10
	v_lshrrev_b32_e32 v5, 9, v6
	v_lshlrev_b32_e32 v6, 23, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v3, v6
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 0x33000000, v3
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, s9, v3
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_lshr_b32 s9, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s8, s8, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0x3fc90fda, v3
	v_add_f32_e32 v6, v6, v5
	s_branch .LBB0_8
.LBB0_7:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr6
.LBB0_8:                                ; %Flow92
	v_mov_b32_e32 v7, s8
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_10
; %bb.9:
	v_rndne_f32_e32 v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v5, 0xbfc90fda, v3, |s5|
	v_cvt_i32_f32_e32 v7, v3
	v_fmamk_f32 v5, v3, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v6, v3, 0xa7c234c4, v5
.LBB0_10:                               ; %_ZL3sinf.exit
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_12
; %bb.11:
	s_and_b32 s3, s12, 0x7fffff
	s_lshr_b32 s8, s12, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s3, 0xfe5163ab
	s_mul_i32 s10, s3, 0x3c439041
	s_mul_hi_u32 s11, s3, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s3, 0xdb629599
	s_mul_hi_u32 s13, s3, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s13
	s_mul_i32 s13, s3, 0xf534ddc0
	s_mul_hi_u32 s16, s3, 0xf534ddc0
	s_add_u32 s11, s11, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s3, 0xfc2757d1
	s_mul_hi_u32 s17, s3, 0xfc2757d1
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s3, 0x4e441529
	s_mul_hi_u32 s18, s3, 0x4e441529
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s18, s3, 0xfe5163ab
	s_mul_hi_u32 s19, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s20, s10, s13
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s18, s10
	s_add_u32 s3, s17, s3
	s_addc_u32 s17, 0, s19
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s18, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s16
	s_cselect_b32 s3, s13, s3
	s_cselect_b32 s13, s16, s17
	s_add_i32 s18, s18, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s18, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s16, s11, s3
	s_cselect_b32 s3, s3, s13
	s_cselect_b32 s11, s20, s11
	s_cselect_b32 s13, s9, s20
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s3, s16, s3
	s_cselect_b32 s16, s11, s16
	s_cselect_b32 s11, s13, s11
	s_cselect_b32 s9, s9, s13
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v3, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v5, s3, s16, v3
	v_alignbit_b32 v8, s16, s11, v3
	v_alignbit_b32 v3, s11, s9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_readfirstlane_b32 s8, v5
	v_cndmask_b32_e64 v5, v8, s16, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, s11, s10
	s_cselect_b32 s3, s3, s8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, s3, v5, 30
	s_bfe_u32 s8, s3, 0x1001d
	s_delay_alu instid0(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v3, 30
	s_sub_i32 s13, 0, s8
	v_alignbit_b32 v3, v3, s9, 30
	v_xor_b32_e32 v8, s13, v8
	s_lshr_b32 s9, s3, 29
	v_xor_b32_e32 v5, s13, v5
	s_lshl_b32 s9, s9, 31
	v_xor_b32_e32 v3, s13, v3
	v_clz_i32_u32_e32 v9, v8
	s_or_b32 s10, s9, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v9, 32, v9
	v_sub_nc_u32_e32 v10, 31, v9
	v_lshlrev_b32_e32 v11, 23, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v8, v5, v10
	v_alignbit_b32 v3, v5, v3, v10
	v_sub_nc_u32_e32 v11, s10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v8, v3, 9
	v_clz_i32_u32_e32 v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v12, 31, v10
	v_add_nc_u32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v5, v3, v12
	v_lshrrev_b32_e32 v5, 9, v8
	v_lshlrev_b32_e32 v8, 23, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v3, 9, v3
	v_or_b32_e32 v5, v5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v8
	v_add_nc_u32_e32 v3, 0x33000000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or_b32_e32 v3, s9, v3
	v_mul_f32_e32 v8, 0x3fc90fda, v5
	s_lshr_b32 s9, s3, 30
	s_mov_b32 s3, 0
	s_add_i32 s13, s8, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, 0x3fc90fda, v5, -v8
	v_fmamk_f32 v5, v5, 0x33a22168, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0x3fc90fda, v3
	v_add_f32_e32 v3, v8, v5
	s_branch .LBB0_13
.LBB0_12:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $vgpr3
.LBB0_13:                               ; %Flow91
	s_load_b128 s[8:11], s[0:1], 0x20
	v_mov_b32_e32 v5, s13
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_15
; %bb.14:
	v_rndne_f32_e32 v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, 0xbfc90fda, v5, |s5|
	v_fmamk_f32 v3, v5, 0xb3a22168, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v3, v5, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v5, v5
.LBB0_15:                               ; %_ZL3sinf.exit41
	s_waitcnt lgkmcnt(0)
	s_load_b32 s11, s[0:1], 0x18
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_17
; %bb.16:
	s_and_b32 s2, s12, 0x7fffff
	s_lshr_b32 s3, s12, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s13, s2, 0xfe5163ab
	s_mul_i32 s16, s2, 0x3c439041
	s_mul_hi_u32 s17, s2, 0x3c439041
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s2, 0xdb629599
	s_mul_hi_u32 s18, s2, 0xdb629599
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s2, 0xf534ddc0
	s_mul_hi_u32 s19, s2, 0xf534ddc0
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_mul_i32 s19, s2, 0xfc2757d1
	s_mul_hi_u32 s20, s2, 0xfc2757d1
	s_add_u32 s18, s18, s19
	s_addc_u32 s19, 0, s20
	s_mul_i32 s20, s2, 0x4e441529
	s_mul_hi_u32 s21, s2, 0x4e441529
	s_add_u32 s19, s19, s20
	s_addc_u32 s20, 0, s21
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s21, s2, 0xfe5163ab
	s_mul_hi_u32 s22, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s23, s16, s18
	s_cselect_b32 s13, s13, s17
	s_cselect_b32 s16, s21, s16
	s_add_u32 s2, s20, s2
	s_addc_u32 s20, 0, s22
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s21, 0xffffffc0, 0
	s_cselect_b32 s17, s17, s19
	s_cselect_b32 s2, s18, s2
	s_cselect_b32 s18, s19, s20
	s_add_i32 s21, s21, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s21, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s19, s17, s2
	s_cselect_b32 s2, s2, s18
	s_cselect_b32 s17, s23, s17
	s_cselect_b32 s18, s13, s23
	s_cselect_b32 s13, s16, s13
	s_add_i32 s3, s3, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s16, 0xffffffe0, 0
	s_cselect_b32 s2, s19, s2
	s_cselect_b32 s19, s17, s19
	s_cselect_b32 s17, s18, s17
	s_cselect_b32 s13, s13, s18
	s_add_i32 s16, s16, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s16
	s_cmp_eq_u32 s16, 0
	v_mov_b32_e32 v8, s3
	s_cselect_b32 s16, -1, 0
	v_alignbit_b32 v9, s2, s19, v8
	v_alignbit_b32 v10, s19, s17, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v9
	v_cndmask_b32_e64 v9, v10, s19, s16
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v10, s2, v9, 30
	s_bfe_u32 s18, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s3, 0, s18
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v10, s3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v10
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v8, s17, s13, v8
	v_sub_nc_u32_e32 v12, 31, v11
	v_cndmask_b32_e64 v8, v8, s17, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v8, v8, s13, 30
	v_xor_b32_e32 v9, s3, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v8, s3, v8
	s_lshr_b32 s3, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s3, s3, 31
	v_alignbit_b32 v10, v10, v9, v12
	v_alignbit_b32 v8, v9, v8, v12
	s_or_b32 s13, s3, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, s13, v13
	s_add_i32 s13, s18, s2
	v_alignbit_b32 v9, v10, v8, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v12, v9
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v12
	v_alignbit_b32 v8, v9, v8, v14
	v_lshrrev_b32_e32 v9, 9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v8, 9, v8
	v_or_b32_e32 v9, v9, v13
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v10, 23, v11
	v_sub_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v9
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3fc90fda, v9, -v10
	v_or_b32_e32 v8, s3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v9, v9, 0x33a22168, v11
	s_mov_b32 s3, 0
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v9
	s_branch .LBB0_18
.LBB0_17:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr13
                                        ; implicit-def: $vgpr8
.LBB0_18:                               ; %Flow90
	s_load_b32 s2, s[0:1], 0x3c
	v_mov_b32_e32 v9, s13
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_20
; %bb.19:
	v_rndne_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0xbfc90fda, v4, |s5|
	v_cvt_i32_f32_e32 v9, v4
	v_fmamk_f32 v8, v4, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v4, 0xa7c234c4, v8
.LBB0_20:                               ; %_ZL3cosf.exit47
	v_dual_mul_f32 v10, v1, v1 :: v_dual_mul_f32 v11, v6, v6
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s13, 0x37d75334
	v_and_b32_e32 v4, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v12, s3, v10, 0x3c0881c4
	v_dual_fmaak_f32 v13, s13, v10, 0xbab64f3b :: v_dual_fmaak_f32 v16, s13, v11, 0xbab64f3b
	v_dual_fmaak_f32 v14, s3, v11, 0x3c0881c4 :: v_dual_and_b32 v15, 1, v2
	v_dual_fmaak_f32 v12, v10, v12, 0xbe2aaa9d :: v_dual_lshlrev_b32 v17, 30, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v13, v10, v13, 0x3d2aabf7 :: v_dual_fmaak_f32 v2, v11, v16, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f32_e32 v12, v10, v12
	v_fmaak_f32 v14, v11, v14, 0xbe2aaa9d
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s2, 0xffff
	v_fmaak_f32 v2, v11, v2, 0xbf000004
	s_lshr_b32 s2, s2, 16
	v_fmac_f32_e32 v1, v1, v12
	v_dual_fmaak_f32 v13, v10, v13, 0xbf000004 :: v_dual_mul_f32 v14, v11, v14
	v_lshlrev_b32_e32 v12, 30, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v10, v10, v13, 1.0
	v_fmac_f32_e32 v6, v6, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v1, v10, vcc_lo
	v_and_b32_e32 v1, 1, v7
	v_fma_f32 v7, v11, v2, 1.0
	v_and_b32_e32 v11, 0x80000000, v12
	v_bfe_u32 v2, v0, 10, 10
	v_cvt_f64_f32_e32 v[12:13], s4
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
	v_cndmask_b32_e32 v6, v7, v6, vcc_lo
	v_xor_b32_e32 v7, s12, v11
	v_mad_u64_u32 v[1:2], null, s14, s16, v[4:5]
	v_and_b32_e32 v11, 0x80000000, v17
	v_cmp_class_f32_e64 s2, s5, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v2, v7, v6
	v_subrev_nc_u32_e32 v6, s9, v0
	v_xor_b32_e32 v4, v11, v10
	v_subrev_nc_u32_e32 v7, s8, v1
	s_delay_alu instid0(VALU_DEP_4)
	v_xor_b32_e32 v2, s5, v2
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x401921fb
	v_cndmask_b32_e64 v10, 0x7fc00000, v4, s2
	v_cvt_f32_i32_e32 v4, v6
	v_cndmask_b32_e64 v2, 0x7fc00000, v2, s2
	v_cvt_f32_i32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v2, v4
	v_fmac_f32_e32 v6, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[10:11], v6
	v_mul_f64 v[10:11], v[10:11], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], v[10:11]
	v_div_scale_f64 v[20:21], vcc_lo, v[10:11], v[12:13], v[10:11]
	v_rcp_f64_e32 v[16:17], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	v_mul_f64 v[18:19], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[14:15], v[18:19], v[20:21]
	v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[10:11], v[14:15], v[12:13], v[10:11]
	v_cvt_f64_f32_e32 v[12:13], s6
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v2, v[10:11]
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s6, exec_lo, s4
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v17, 0x7fffffff, v2
	s_mov_b32 s3, 0x7fffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_or_b32 v20, v17, s3, 0x800000
	v_lshrrev_b32_e32 v17, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v20, 0
	v_add_nc_u32_e32 v18, 0xffffff88, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v18
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v20, v[11:12]
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v14
	v_add_nc_u32_e32 v19, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v20, v[11:12]
	v_cmp_lt_u32_e64 s3, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s3
	v_dual_mov_b32 v11, v15 :: v_dual_cndmask_b32 v10, v14, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v21, v21, v19
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s4, 31, v21
	v_mov_b32_e32 v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, v15, v13, vcc_lo
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v13, v10, s3
	v_mov_b32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v20, v[11:12]
	v_mov_b32_e32 v11, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v20, v[11:12]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s4
	v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v11, v11, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
	v_cndmask_b32_e32 v16, v16, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v18, v12, s3
	v_cndmask_b32_e64 v17, v17, v18, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v16, s3
	v_sub_nc_u32_e32 v18, 32, v11
	v_cndmask_b32_e64 v16, v16, v13, s3
	v_cndmask_b32_e64 v17, v17, v15, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v12, s4
	v_cndmask_b32_e64 v12, v12, v16, s4
	v_cndmask_b32_e64 v10, v16, v10, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v17, v15, v18
	v_alignbit_b32 v14, v15, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v11, v19, v17, vcc_lo
	v_alignbit_b32 v17, v12, v10, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v14, v15, vcc_lo
	v_bfe_u32 v14, v11, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v17, v12, vcc_lo
	v_alignbit_b32 v15, v11, v13, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v16, 0, v14
	v_alignbit_b32 v13, v13, v12, 30
	v_alignbit_b32 v10, v12, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v15, v16
	v_xor_b32_e32 v12, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v16
	v_clz_i32_u32_e32 v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v13, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v15, v15, v12, v13
	v_alignbit_b32 v10, v12, v10, v13
	v_lshrrev_b32_e32 v13, 29, v11
	v_alignbit_b32 v12, v15, v10, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v13, 31, v13
	v_lshrrev_b32_e32 v15, 9, v15
	v_clz_i32_u32_e32 v16, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v18, 0.5, v13
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, v18, v19
	v_sub_nc_u32_e32 v20, 31, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v12, v10, v20
	v_or_b32_e32 v12, v15, v18
	v_add_lshl_u32 v15, v16, v17, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_mul_f32_e32 v16, 0x3fc90fda, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v15
	v_fma_f32 v15, 0x3fc90fda, v12, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fmamk_f32 v12, v12, 0x33a22168, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v10, v10, v13
	v_fmac_f32_e32 v12, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v16, v12
	v_lshrrev_b32_e32 v11, 30, v11
	v_add_nc_u32_e32 v11, v14, v11
.LBB0_22:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s6
; %bb.23:
	v_mul_f32_e64 v10, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v11, v10
	v_fma_f32 v10, 0xbfc90fda, v11, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v10, v11, 0xb3a22168, v10
	v_fmamk_f32 v10, v11, 0xa7c234c4, v10
	v_cvt_i32_f32_e32 v11, v11
; %bb.24:                               ; %_ZL3cosf.exit53
	s_or_b32 exec_lo, exec_lo, s3
	v_dual_mul_f32 v14, v3, v3 :: v_dual_mul_f32 v17, v8, v8
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s4, 0x37d75334
	v_cvt_f64_f32_e32 v[12:13], s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, s3, v14, 0x3c0881c4 :: v_dual_lshlrev_b32 v18, 30, v5
	v_fmaak_f32 v20, s3, v17, 0x3c0881c4
	v_dual_fmaak_f32 v16, s4, v14, 0xbab64f3b :: v_dual_and_b32 v5, 1, v5
	v_fmaak_f32 v15, v14, v15, 0xbe2aaa9d
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3)
	v_fmaak_f32 v20, v17, v20, 0xbe2aaa9d
	v_fmaak_f32 v19, s4, v17, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_dual_mul_f32 v15, v14, v15 :: v_dual_and_b32 v18, 0x80000000, v18
	v_lshlrev_b32_e32 v5, 30, v9
	v_and_b32_e32 v9, 1, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v3, v3, v15
	v_xor_b32_e32 v15, s12, v18
	v_mul_f32_e32 v18, v17, v20
	v_dual_fmaak_f32 v16, v14, v16, 0x3d2aabf7 :: v_dual_fmaak_f32 v19, v17, v19, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v8, v18
	v_fmaak_f32 v16, v14, v16, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, v14, v16, 1.0
	v_fmaak_f32 v16, v17, v19, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v14, v3, vcc_lo
	v_fma_f32 v16, v17, v16, 1.0
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v15, v3
	v_add_f64 v[14:15], v[12:13], v[12:13]
	v_cndmask_b32_e64 v8, -v8, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, s5, v3
	v_cndmask_b32_e64 v3, 0x7fc00000, v3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v3, v7
	v_mul_f32_e64 v7, s11, s11
	v_and_b32_e32 v5, 0x80000000, v5
	v_xor_b32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0x7fc00000, v5, s2
	v_fma_f32 v3, v5, v4, -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v7, v3
	v_mul_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v3, v6, v6
	v_mul_f64 v[5:6], v[14:15], v[12:13]
	v_cvt_f64_f32_e64 v[3:4], -v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
	v_div_scale_f64 v[16:17], vcc_lo, v[3:4], v[5:6], v[3:4]
	v_rcp_f64_e32 v[12:13], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[7:8], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_fma_f64 v[14:15], -v[7:8], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_mul_f64 v[14:15], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[14:15], v[16:17]
	v_div_fmas_f64 v[7:8], v[7:8], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[7:8], v[5:6], v[3:4]
	v_cvt_f32_f64_e32 v5, v[3:4]
	v_mul_f32_e32 v4, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, s3, v4, 0x3c0881c4
	v_fmaak_f32 v8, v4, v8, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x3fb8aa3b, v5
	v_fma_f32 v6, 0x3fb8aa3b, v5, -v3
	v_rndne_f32_e32 v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmamk_f32 v6, v5, 0x32a5705f, v6 :: v_dual_sub_f32 v3, v3, v7
	v_dual_add_f32 v3, v3, v6 :: v_dual_mul_f32 v6, v4, v8
	v_fmaak_f32 v9, s4, v4, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v12, v3
	v_dual_fmac_f32 v10, v10, v6 :: v_dual_fmaak_f32 v9, v4, v9, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v8, v4, v9, 0xbf000004 :: v_dual_and_b32 v9, 1, v11
	v_lshlrev_b32_e32 v11, 30, v11
	v_fma_f32 v6, v4, v8, 1.0
	v_mad_u64_u32 v[3:4], null, v0, s10, v[1:2]
	v_cvt_i32_f32_e32 v0, v7
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_and_b32_e32 v1, 0x80000000, v11
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v0, v12, v0
	v_cndmask_b32_e64 v4, -v10, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v1, v1, v4
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v2, 0x7fc00000, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
	v_cndmask_b32_e32 v5, 0x7f800000, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, v5, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_,comdat
.Lfunc_end0:
	.size	_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_, .Lfunc_end0-_ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4984
; NumSgprs: 26
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,comdat
	.globl	_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_ ; -- Begin function _ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
	.p2align	8
	.type	_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,@function
_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_: ; @_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s2, 0x48000000, |s4|
	s_and_b32 s3, s4, 0x7fffffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_mov_b32 vcc_lo, s2
	s_cbranch_vccz .LBB1_2
; %bb.1:
	s_and_b32 s7, s3, 0x7fffff
	s_lshr_b32 s8, s3, 23
	s_bitset1_b32 s7, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s7, 0xfe5163ab
	s_mul_i32 s10, s7, 0x3c439041
	s_mul_hi_u32 s11, s7, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s7, 0xdb629599
	s_mul_hi_u32 s12, s7, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s7, 0xf534ddc0
	s_mul_hi_u32 s13, s7, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s7, 0xfc2757d1
	s_mul_hi_u32 s16, s7, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s7, 0x4e441529
	s_mul_hi_u32 s17, s7, 0x4e441529
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s17, s7, 0xfe5163ab
	s_mul_hi_u32 s18, s7, 0xa2f9836e
	s_mul_i32 s7, s7, 0xa2f9836e
	s_cselect_b32 s19, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s17, s10
	s_add_u32 s7, s16, s7
	s_addc_u32 s16, 0, s18
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s17, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s7, s12, s7
	s_cselect_b32 s12, s13, s16
	s_add_i32 s17, s17, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s17, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s7
	s_cselect_b32 s7, s7, s12
	s_cselect_b32 s11, s19, s11
	s_cselect_b32 s12, s9, s19
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v1, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v2, s7, s13, v1
	v_alignbit_b32 v3, s13, s11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v2
	v_cndmask_b32_e64 v2, v3, s13, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s7, s7, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, s7, v2, 30
	s_bfe_u32 s12, s7, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v3, s8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v4, v3
	v_min_u32_e32 v4, 32, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 23, v4
	v_alignbit_b32 v1, s11, s9, v1
	v_sub_nc_u32_e32 v5, 31, v4
	v_cndmask_b32_e64 v1, v1, s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v2, v2, v1, 30
	v_alignbit_b32 v1, v1, s9, 30
	v_xor_b32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v1, s8, v1
	s_lshr_b32 s8, s7, 29
	s_lshr_b32 s7, s7, 30
	s_lshl_b32 s8, s8, 31
	v_alignbit_b32 v3, v3, v2, v5
	v_alignbit_b32 v1, v2, v1, v5
	s_or_b32 s9, s8, 0.5
	s_add_i32 s7, s12, s7
	v_sub_nc_u32_e32 v6, s9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v2, v3, v1, 9
	v_clz_i32_u32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v5, 32, v5
	v_sub_nc_u32_e32 v7, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v1, v2, v1, v7
	v_lshrrev_b32_e32 v2, 9, v3
	v_lshrrev_b32_e32 v1, 9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v6
	v_add_nc_u32_e32 v4, v5, v4
	v_lshlrev_b32_e32 v3, 23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v1, v1, v3
	v_mul_f32_e32 v3, 0x3fc90fda, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0x33000000, v1
	v_fma_f32 v4, 0x3fc90fda, v2, -v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v1, s8, v1
	v_fmamk_f32 v2, v2, 0x33a22168, v4
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3fc90fda, v1
	v_add_f32_e32 v1, v3, v2
	s_branch .LBB1_3
.LBB1_2:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr1
.LBB1_3:                                ; %Flow75
	v_mul_f32_e64 v3, 0x3f22f983, |s4|
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB1_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v3
	v_fma_f32 v1, 0xbfc90fda, v2, |s4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, v2, 0xb3a22168, v1
	v_fmamk_f32 v1, v2, 0xa7c234c4, v1
	v_cvt_i32_f32_e32 v2, v2
	s_branch .LBB1_6
.LBB1_5:
	v_mov_b32_e32 v2, s7
.LBB1_6:                                ; %_ZL3cosf.exit
	s_mov_b32 vcc_lo, s2
	s_cbranch_vccz .LBB1_8
; %bb.7:
	s_and_b32 s7, s3, 0x7fffff
	s_lshr_b32 s8, s3, 23
	s_bitset1_b32 s7, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s7, 0xfe5163ab
	s_mul_i32 s10, s7, 0x3c439041
	s_mul_hi_u32 s11, s7, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s7, 0xdb629599
	s_mul_hi_u32 s12, s7, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s7, 0xf534ddc0
	s_mul_hi_u32 s13, s7, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s7, 0xfc2757d1
	s_mul_hi_u32 s16, s7, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s7, 0x4e441529
	s_mul_hi_u32 s17, s7, 0x4e441529
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s17, s7, 0xfe5163ab
	s_mul_hi_u32 s18, s7, 0xa2f9836e
	s_mul_i32 s7, s7, 0xa2f9836e
	s_cselect_b32 s19, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s17, s10
	s_add_u32 s7, s16, s7
	s_addc_u32 s16, 0, s18
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s17, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s7, s12, s7
	s_cselect_b32 s12, s13, s16
	s_add_i32 s17, s17, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s17, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s7
	s_cselect_b32 s7, s7, s12
	s_cselect_b32 s11, s19, s11
	s_cselect_b32 s12, s9, s19
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v4, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v5, s7, s13, v4
	v_alignbit_b32 v6, s13, s11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v5
	v_cndmask_b32_e64 v5, v6, s13, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s7, s7, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s7, v5, 30
	s_bfe_u32 s12, s7, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v6, s8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v7, v6
	v_min_u32_e32 v7, 32, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v4, s11, s9, v4
	v_sub_nc_u32_e32 v8, 31, v7
	v_cndmask_b32_e64 v4, v4, s11, s10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v4, v4, s9, 30
	v_xor_b32_e32 v5, s8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v4, s8, v4
	s_lshr_b32 s8, s7, 29
	s_lshr_b32 s7, s7, 30
	s_lshl_b32 s8, s8, 31
	v_alignbit_b32 v6, v6, v5, v8
	v_alignbit_b32 v4, v5, v4, v8
	s_or_b32 s9, s8, 0.5
	s_add_i32 s7, s12, s7
	v_sub_nc_u32_e32 v9, s9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v5, v6, v4, 9
	v_clz_i32_u32_e32 v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v8, 32, v8
	v_sub_nc_u32_e32 v10, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v4, v5, v4, v10
	v_lshrrev_b32_e32 v5, 9, v6
	v_lshrrev_b32_e32 v4, 9, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v7, v8, v7
	v_lshlrev_b32_e32 v6, 23, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v4, v4, v6
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 0x33000000, v4
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v4, s8, v4
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	v_add_f32_e32 v4, v6, v5
	s_branch .LBB1_9
.LBB1_8:
	s_mov_b32 s8, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr4
.LBB1_9:                                ; %Flow74
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccnz .LBB1_11
; %bb.10:
	v_rndne_f32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, 0xbfc90fda, v5, |s4|
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
	s_branch .LBB1_12
.LBB1_11:
	v_mov_b32_e32 v5, s7
.LBB1_12:                               ; %_ZL3sinf.exit
	s_mov_b32 vcc_lo, s2
	s_cbranch_vccz .LBB1_14
; %bb.13:
	s_and_b32 s7, s3, 0x7fffff
	s_lshr_b32 s8, s3, 23
	s_bitset1_b32 s7, 23
	s_addk_i32 s8, 0xff88
	s_mul_hi_u32 s9, s7, 0xfe5163ab
	s_mul_i32 s10, s7, 0x3c439041
	s_mul_hi_u32 s11, s7, 0x3c439041
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s7, 0xdb629599
	s_mul_hi_u32 s12, s7, 0xdb629599
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s7, 0xf534ddc0
	s_mul_hi_u32 s13, s7, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s7, 0xfc2757d1
	s_mul_hi_u32 s16, s7, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s7, 0x4e441529
	s_mul_hi_u32 s17, s7, 0x4e441529
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_cmp_gt_u32 s8, 63
	s_mul_i32 s17, s7, 0xfe5163ab
	s_mul_hi_u32 s18, s7, 0xa2f9836e
	s_mul_i32 s7, s7, 0xa2f9836e
	s_cselect_b32 s19, s10, s12
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s10, s17, s10
	s_add_u32 s7, s16, s7
	s_addc_u32 s16, 0, s18
	s_cmp_gt_u32 s8, 63
	s_cselect_b32 s17, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s7, s12, s7
	s_cselect_b32 s12, s13, s16
	s_add_i32 s17, s17, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s17, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s7
	s_cselect_b32 s7, s7, s12
	s_cselect_b32 s11, s19, s11
	s_cselect_b32 s12, s9, s19
	s_cselect_b32 s9, s10, s9
	s_add_i32 s8, s8, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s8, 31
	s_cselect_b32 s10, 0xffffffe0, 0
	s_cselect_b32 s7, s13, s7
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s9, s9, s12
	s_add_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 32, s10
	s_cmp_eq_u32 s10, 0
	v_mov_b32_e32 v6, s8
	s_cselect_b32 s10, -1, 0
	v_alignbit_b32 v7, s7, s13, v6
	v_alignbit_b32 v8, s13, s11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v7
	v_cndmask_b32_e64 v7, v8, s13, s10
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s7, s7, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, s7, v7, 30
	s_bfe_u32 s8, s7, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s8
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v8, s12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v9, v8
	v_min_u32_e32 v9, 32, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 23, v9
	v_alignbit_b32 v6, s11, s9, v6
	v_sub_nc_u32_e32 v10, 31, v9
	v_cndmask_b32_e64 v6, v6, s11, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v7, v7, v6, 30
	v_alignbit_b32 v6, v6, s9, 30
	s_lshr_b32 s9, s7, 29
	s_lshr_b32 s7, s7, 30
	s_lshl_b32 s9, s9, 31
	v_xor_b32_e32 v7, s12, v7
	v_xor_b32_e32 v6, s12, v6
	s_or_b32 s10, s9, 0.5
	s_mov_b32 s12, 0
	v_sub_nc_u32_e32 v11, s10, v11
	v_alignbit_b32 v8, v8, v7, v10
	v_alignbit_b32 v6, v7, v6, v10
	s_add_i32 s7, s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v7, v8, v6, 9
	v_clz_i32_u32_e32 v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v12, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v7, v6, v12
	v_lshrrev_b32_e32 v7, 9, v8
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v7, v7, v11
	v_add_nc_u32_e32 v9, v10, v9
	v_lshlrev_b32_e32 v8, 23, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v6, v6, v8
	v_mul_f32_e32 v8, 0x3fc90fda, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fma_f32 v9, 0x3fc90fda, v7, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v6, s9, v6
	v_fmamk_f32 v7, v7, 0x33a22168, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, 0x3fc90fda, v6
	v_add_f32_e32 v6, v8, v7
	s_branch .LBB1_15
.LBB1_14:
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr6
.LBB1_15:                               ; %Flow73
	s_load_b128 s[8:11], s[0:1], 0x18
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_17
; %bb.16:
	v_rndne_f32_e32 v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0xbfc90fda, v7, |s4|
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
	s_branch .LBB1_18
.LBB1_17:
	v_mov_b32_e32 v7, s7
.LBB1_18:                               ; %_ZL3sinf.exit39
	s_mov_b32 vcc_lo, s2
	s_cbranch_vccz .LBB1_20
; %bb.19:
	s_and_b32 s2, s3, 0x7fffff
	s_lshr_b32 s7, s3, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s7, 0xff88
	s_waitcnt lgkmcnt(0)
	s_mul_hi_u32 s11, s2, 0xfe5163ab
	s_mul_i32 s12, s2, 0x3c439041
	s_mul_hi_u32 s13, s2, 0x3c439041
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s2, 0xdb629599
	s_mul_hi_u32 s16, s2, 0xdb629599
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s2, 0xf534ddc0
	s_mul_hi_u32 s17, s2, 0xf534ddc0
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s2, 0xfc2757d1
	s_mul_hi_u32 s18, s2, 0xfc2757d1
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s2, 0x4e441529
	s_mul_hi_u32 s19, s2, 0x4e441529
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_cmp_gt_u32 s7, 63
	s_mul_i32 s19, s2, 0xfe5163ab
	s_mul_hi_u32 s20, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s21, s12, s16
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s12, s19, s12
	s_add_u32 s2, s18, s2
	s_addc_u32 s18, 0, s20
	s_cmp_gt_u32 s7, 63
	s_cselect_b32 s19, 0xffffffc0, 0
	s_cselect_b32 s13, s13, s17
	s_cselect_b32 s2, s16, s2
	s_cselect_b32 s16, s17, s18
	s_add_i32 s19, s19, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s19, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s17, s13, s2
	s_cselect_b32 s2, s2, s16
	s_cselect_b32 s13, s21, s13
	s_cselect_b32 s16, s11, s21
	s_cselect_b32 s11, s12, s11
	s_add_i32 s7, s7, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s7, 31
	s_cselect_b32 s12, 0xffffffe0, 0
	s_cselect_b32 s2, s17, s2
	s_cselect_b32 s17, s13, s17
	s_cselect_b32 s13, s16, s13
	s_cselect_b32 s11, s11, s16
	s_add_i32 s12, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s7, 32, s12
	s_cmp_eq_u32 s12, 0
	v_mov_b32_e32 v8, s7
	s_cselect_b32 s12, -1, 0
	v_alignbit_b32 v9, s2, s17, v8
	v_alignbit_b32 v10, s17, s13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v9
	v_cndmask_b32_e64 v9, v10, s17, s12
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v10, s2, v9, 30
	s_bfe_u32 s7, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s16, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v10, s16, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v10
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v8, s13, s11, v8
	v_sub_nc_u32_e32 v12, 31, v11
	v_cndmask_b32_e64 v8, v8, s13, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v9, v9, v8, 30
	v_alignbit_b32 v8, v8, s11, 30
	s_lshr_b32 s11, s2, 29
	s_lshr_b32 s2, s2, 30
	s_lshl_b32 s11, s11, 31
	v_xor_b32_e32 v9, s16, v9
	v_xor_b32_e32 v8, s16, v8
	s_or_b32 s12, s11, 0.5
	s_add_i32 s7, s7, s2
	v_sub_nc_u32_e32 v13, s12, v13
	v_alignbit_b32 v10, v10, v9, v12
	v_alignbit_b32 v8, v9, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v9, v10, v8, 9
	v_clz_i32_u32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v12, 32, v12
	v_sub_nc_u32_e32 v14, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v9, v8, v14
	v_lshrrev_b32_e32 v9, 9, v10
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, v9, v13
	v_add_nc_u32_e32 v11, v12, v11
	v_lshlrev_b32_e32 v10, 23, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v8, v8, v10
	v_mul_f32_e32 v10, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 0x33000000, v8
	v_fma_f32 v11, 0x3fc90fda, v9, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v8, s11, v8
	v_fmamk_f32 v9, v9, 0x33a22168, v11
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0x3fc90fda, v8
	v_add_f32_e32 v8, v10, v9
	s_branch .LBB1_21
.LBB1_20:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s11, -1
                                        ; implicit-def: $sgpr7
                                        ; implicit-def: $vgpr8
.LBB1_21:                               ; %Flow
	s_load_b32 s2, s[0:1], 0x34
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_23
; %bb.22:
	v_rndne_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, 0xbfc90fda, v3, |s4|
	v_fmamk_f32 v8, v3, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v8, v3, 0xa7c234c4, v8
	v_cvt_i32_f32_e32 v3, v3
	s_branch .LBB1_24
.LBB1_23:
	v_mov_b32_e32 v3, s7
.LBB1_24:                               ; %_ZL3cosf.exit45
	v_dual_mul_f32 v9, v6, v6 :: v_dual_lshlrev_b32 v12, 30, v7
	s_mov_b32 s7, 0xb94c1982
	s_mov_b32 s11, 0x37d75334
	v_mul_f32_e32 v15, v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v10, s7, v9, 0x3c0881c4 :: v_dual_and_b32 v7, 1, v7
	v_dual_fmaak_f32 v11, s11, v9, 0xbab64f3b :: v_dual_and_b32 v14, 1, v2
	v_lshlrev_b32_e32 v13, 30, v2
	v_fmaak_f32 v10, v9, v10, 0xbe2aaa9d
	v_and_b32_e32 v2, 0x3ff, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_dual_fmaak_f32 v16, s7, v15, 0x3c0881c4 :: v_dual_lshlrev_b32 v19, 30, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v10, v9, v10
	v_fmaak_f32 v11, v9, v11, 0x3d2aabf7
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_bfe_u32 v0, v0, 10, 10
	v_fmac_f32_e32 v6, v6, v10
	v_fmaak_f32 v10, s11, v15, 0xbab64f3b
	v_and_b32_e32 v13, 0x80000000, v13
	s_load_b64 s[0:1], s[0:1], 0x0
	v_and_b32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v17, v15, v10, 0x3d2aabf7
	v_fmaak_f32 v11, v9, v11, 0xbf000004
	v_fma_f32 v9, v9, v11, 1.0
	v_and_b32_e32 v12, 0x80000000, v12
	v_mul_f32_e32 v11, v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v9, v6, vcc_lo
	v_xor_b32_e32 v12, s3, v12
	v_cvt_f64_f32_e32 v[6:7], s5
	v_cmp_class_f32_e64 vcc_lo, s4, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v12, v9
	v_mad_u64_u32 v[9:10], null, s14, s2, v[2:3]
	v_fmaak_f32 v2, v15, v16, 0xbe2aaa9d
	v_cmp_eq_u32_e64 s2, 0, v5
	v_xor_b32_e32 v12, s4, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v18, v15, v2
	v_mul_f32_e32 v2, v8, v8
	v_fmaak_f32 v10, v15, v17, 0xbf000004
	v_fmaak_f32 v17, s11, v11, 0xbab64f3b
	v_fmaak_f32 v20, s7, v2, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v15, v10, 1.0
	v_fmaak_f32 v20, v2, v20, 0xbe2aaa9d
	v_fmaak_f32 v16, s7, v11, 0x3c0881c4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmaak_f32 v15, v11, v16, 0xbe2aaa9d
	v_cndmask_b32_e32 v12, 0x7fc00000, v12, vcc_lo
	v_fmaak_f32 v16, v11, v17, 0x3d2aabf7
	v_subrev_nc_u32_e32 v17, s8, v9
	v_mul_f32_e32 v15, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v21, s11, v2, 0xbab64f3b :: v_dual_fmac_f32 v4, v4, v15
	v_fmaak_f32 v15, v2, v21, 0x3d2aabf7
	v_fmaak_f32 v16, v11, v16, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v11, v16, 1.0
	v_dual_mul_f32 v19, v2, v20 :: v_dual_and_b32 v16, 0x80000000, v19
	v_cndmask_b32_e64 v5, v11, v4, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, s3, v16
	v_fmaak_f32 v4, v2, v15, 0xbf000004
	v_and_b32_e32 v15, 1, v3
	v_fmac_f32_e32 v8, v8, v19
	v_xor_b32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v4, v2, v4, 1.0
	v_cmp_eq_u32_e64 s2, 0, v15
	v_cvt_f32_i32_e32 v15, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, s4, v5
	v_lshlrev_b32_e32 v16, 30, v3
	v_mad_u64_u32 v[2:3], null, s15, s12, v[0:1]
	v_cndmask_b32_e64 v0, -v8, v4, s2
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	v_add_f64 v[3:4], v[6:7], v[6:7]
	v_dual_fmac_f32 v1, v1, v18 :: v_dual_and_b32 v8, 0x80000000, v16
	v_cmp_eq_u32_e64 s2, 0, v14
	v_subrev_nc_u32_e32 v11, s9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v8, v0
	v_cndmask_b32_e64 v1, -v1, v10, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v8, v11
	s_mov_b32 s2, 0x54442d18
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_mov_b32 s3, 0x401921fb
	v_xor_b32_e32 v1, v13, v1
	v_dual_mul_f32 v10, v12, v15 :: v_dual_mul_f32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_fma_f32 v0, v0, v8, -v10
	v_mul_f32_e64 v10, s6, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v5, v1, v15 :: v_dual_mul_f32 v8, v10, v0
	v_mul_f32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, v5, v5
	v_mul_f64 v[3:4], v[3:4], v[6:7]
	v_cvt_f64_f32_e64 v[0:1], -v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[10:11], null, v[3:4], v[3:4], v[0:1]
	v_div_scale_f64 v[16:17], vcc_lo, v[0:1], v[3:4], v[0:1]
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_mul_f64 v[14:15], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[10:11], v[3:4], v[0:1]
	v_cvt_f32_f64_e32 v3, v[0:1]
	v_mul_f64 v[0:1], v[6:7], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v4, 0x3fb8aa3b, v3
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
	v_mul_f64 v[0:1], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v5, 0x3fb8aa3b, v3, -v4
	v_rndne_f32_e32 v8, v4
	v_dual_fmamk_f32 v5, v3, 0x32a5705f, v5 :: v_dual_sub_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v5
	v_cvt_i32_f32_e32 v5, v8
	v_exp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
	v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[3:4], v3
	v_div_scale_f64 v[5:6], null, v[0:1], v[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[10:11], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[10:11], v[7:8]
	v_div_scale_f64 v[10:11], vcc_lo, v[3:4], v[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[10:11], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[12:13]
	v_div_fixup_f64 v[0:1], v[5:6], v[0:1], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v3, v[0:1]
	v_mad_u64_u32 v[0:1], null, v2, s10, v[9:10]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_,comdat
.Lfunc_end1:
	.size	_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_, .Lfunc_end1-_ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4064
; NumSgprs: 24
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,comdat
	.globl	_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_ ; -- Begin function _ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
	.p2align	8
	.type	_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,@function
_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_: ; @_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s3, 0x48000000, |s8|
	s_and_b32 s2, s8, 0x7fffffff
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_2
; %bb.1:
	s_and_b32 s4, s2, 0x7fffff
	s_lshr_b32 s5, s2, 23
	s_bitset1_b32 s4, 23
	s_addk_i32 s5, 0xff88
	s_mul_hi_u32 s6, s4, 0xfe5163ab
	s_mul_i32 s7, s4, 0x3c439041
	s_mul_hi_u32 s11, s4, 0x3c439041
	s_add_u32 s6, s6, s7
	s_addc_u32 s7, 0, s11
	s_mul_i32 s11, s4, 0xdb629599
	s_mul_hi_u32 s12, s4, 0xdb629599
	s_add_u32 s7, s7, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s4, 0xf534ddc0
	s_mul_hi_u32 s13, s4, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s4, 0xfc2757d1
	s_mul_hi_u32 s16, s4, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s4, 0x4e441529
	s_mul_hi_u32 s17, s4, 0x4e441529
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_cmp_gt_u32 s5, 63
	s_mul_i32 s17, s4, 0xfe5163ab
	s_mul_hi_u32 s18, s4, 0xa2f9836e
	s_mul_i32 s4, s4, 0xa2f9836e
	s_cselect_b32 s19, s7, s12
	s_cselect_b32 s6, s6, s11
	s_cselect_b32 s7, s17, s7
	s_add_u32 s4, s16, s4
	s_addc_u32 s16, 0, s18
	s_cmp_gt_u32 s5, 63
	s_cselect_b32 s17, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s4, s12, s4
	s_cselect_b32 s12, s13, s16
	s_add_i32 s17, s17, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s17, 31
	s_cselect_b32 s5, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s4
	s_cselect_b32 s4, s4, s12
	s_cselect_b32 s11, s19, s11
	s_cselect_b32 s12, s6, s19
	s_cselect_b32 s6, s7, s6
	s_add_i32 s5, s5, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s5, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s4, s13, s4
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s6, s6, s12
	s_add_i32 s7, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s5, 32, s7
	s_cmp_eq_u32 s7, 0
	v_mov_b32_e32 v1, s5
	s_cselect_b32 s7, -1, 0
	v_alignbit_b32 v2, s4, s13, v1
	v_alignbit_b32 v3, s13, s11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s5, v2
	v_cndmask_b32_e64 v2, v3, s13, s7
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s4, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v3, s4, v2, 30
	s_bfe_u32 s5, s4, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v3, s12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v4, v3
	v_min_u32_e32 v4, 32, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 23, v4
	v_alignbit_b32 v1, s11, s6, v1
	v_sub_nc_u32_e32 v5, 31, v4
	v_cndmask_b32_e64 v1, v1, s11, s7
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_alignbit_b32 v2, v2, v1, 30
	v_alignbit_b32 v1, v1, s6, 30
	s_lshr_b32 s6, s4, 29
	s_lshr_b32 s4, s4, 30
	s_lshl_b32 s6, s6, 31
	v_xor_b32_e32 v2, s12, v2
	v_xor_b32_e32 v1, s12, v1
	s_or_b32 s7, s6, 0.5
	s_add_i32 s12, s5, s4
	v_sub_nc_u32_e32 v6, s7, v6
	v_alignbit_b32 v3, v3, v2, v5
	v_alignbit_b32 v1, v2, v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v2, v3, v1, 9
	v_clz_i32_u32_e32 v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v5, 32, v5
	v_sub_nc_u32_e32 v7, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v1, v2, v1, v7
	v_lshrrev_b32_e32 v2, 9, v3
	v_lshrrev_b32_e32 v1, 9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v6
	v_add_nc_u32_e32 v4, v5, v4
	v_lshlrev_b32_e32 v3, 23, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v1, v1, v3
	v_mul_f32_e32 v3, 0x3fc90fda, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, 0x33000000, v1
	v_fma_f32 v4, 0x3fc90fda, v2, -v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v1, s6, v1
	v_fmamk_f32 v2, v2, 0x33a22168, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3fc90fda, v1
	v_add_f32_e32 v3, v3, v2
	s_branch .LBB2_3
.LBB2_2:
	s_mov_b32 s11, -1
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $vgpr3
.LBB2_3:                                ; %Flow68
	s_load_b128 s[4:7], s[0:1], 0x18
	v_mov_b32_e32 v1, s12
	v_mul_f32_e64 v2, 0x3f22f983, |s8|
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB2_5
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v1, v2
	v_fma_f32 v3, 0xbfc90fda, v1, |s8|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v3, v1, 0xb3a22168, v3
	v_fmamk_f32 v3, v1, 0xa7c234c4, v3
	v_cvt_i32_f32_e32 v1, v1
.LBB2_5:                                ; %_ZL3cosf.exit
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_7
; %bb.6:
	s_and_b32 s3, s2, 0x7fffff
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s2, 23
	s_bitset1_b32 s3, 23
	s_addk_i32 s7, 0xff88
	s_mul_hi_u32 s11, s3, 0xfe5163ab
	s_mul_i32 s12, s3, 0x3c439041
	s_mul_hi_u32 s13, s3, 0x3c439041
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s3, 0xdb629599
	s_mul_hi_u32 s16, s3, 0xdb629599
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s16
	s_mul_i32 s16, s3, 0xf534ddc0
	s_mul_hi_u32 s17, s3, 0xf534ddc0
	s_add_u32 s13, s13, s16
	s_addc_u32 s16, 0, s17
	s_mul_i32 s17, s3, 0xfc2757d1
	s_mul_hi_u32 s18, s3, 0xfc2757d1
	s_add_u32 s16, s16, s17
	s_addc_u32 s17, 0, s18
	s_mul_i32 s18, s3, 0x4e441529
	s_mul_hi_u32 s19, s3, 0x4e441529
	s_add_u32 s17, s17, s18
	s_addc_u32 s18, 0, s19
	s_cmp_gt_u32 s7, 63
	s_mul_i32 s19, s3, 0xfe5163ab
	s_mul_hi_u32 s20, s3, 0xa2f9836e
	s_mul_i32 s3, s3, 0xa2f9836e
	s_cselect_b32 s21, s12, s16
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s12, s19, s12
	s_add_u32 s3, s18, s3
	s_addc_u32 s18, 0, s20
	s_cmp_gt_u32 s7, 63
	s_cselect_b32 s19, 0xffffffc0, 0
	s_cselect_b32 s13, s13, s17
	s_cselect_b32 s3, s16, s3
	s_cselect_b32 s16, s17, s18
	s_add_i32 s19, s19, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s19, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s17, s13, s3
	s_cselect_b32 s3, s3, s16
	s_cselect_b32 s13, s21, s13
	s_cselect_b32 s16, s11, s21
	s_cselect_b32 s11, s12, s11
	s_add_i32 s7, s7, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s7, 31
	s_cselect_b32 s12, 0xffffffe0, 0
	s_cselect_b32 s3, s17, s3
	s_cselect_b32 s17, s13, s17
	s_cselect_b32 s13, s16, s13
	s_cselect_b32 s11, s11, s16
	s_add_i32 s12, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s7, 32, s12
	s_cmp_eq_u32 s12, 0
	v_mov_b32_e32 v4, s7
	s_cselect_b32 s12, -1, 0
	v_alignbit_b32 v5, s3, s17, v4
	v_alignbit_b32 v6, s17, s13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v5
	v_cndmask_b32_e64 v5, v6, s17, s12
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s3, s3, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s3, v5, 30
	s_bfe_u32 s16, s3, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, 0, s16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v6, s7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v7, v6
	v_min_u32_e32 v7, 32, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v4, s13, s11, v4
	v_sub_nc_u32_e32 v8, 31, v7
	v_cndmask_b32_e64 v4, v4, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v4, v4, s11, 30
	v_xor_b32_e32 v5, s7, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v4, s7, v4
	s_lshr_b32 s7, s3, 29
	s_lshr_b32 s3, s3, 30
	s_lshl_b32 s7, s7, 31
	v_alignbit_b32 v6, v6, v5, v8
	v_alignbit_b32 v4, v5, v4, v8
	s_or_b32 s11, s7, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, s11, v9
	s_add_i32 s11, s16, s3
	v_alignbit_b32 v5, v6, v4, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v5
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, 31, v8
	v_alignbit_b32 v4, v5, v4, v10
	v_lshrrev_b32_e32 v5, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v4, 9, v4
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 23, v7
	v_sub_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	v_add_nc_u32_e32 v4, 0x33000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	v_or_b32_e32 v4, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_mov_b32 s7, 0
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v5
	s_branch .LBB2_8
.LBB2_7:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s7, -1
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $vgpr4
.LBB2_8:                                ; %Flow67
	s_load_b32 s3, s[0:1], 0x34
	v_mov_b32_e32 v5, s11
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB2_10
; %bb.9:
	v_rndne_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0xbfc90fda, v2, |s8|
	v_cvt_i32_f32_e32 v5, v2
	v_fmamk_f32 v4, v2, 0xb3a22168, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v4, v2, 0xa7c234c4, v4
.LBB2_10:                               ; %_ZL3sinf.exit
	v_dual_mul_f32 v7, v3, v3 :: v_dual_and_b32 v6, 0x3ff, v0
	s_mov_b32 s11, 0xb94c1982
	s_mov_b32 s12, 0x37d75334
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s3, 0xffff
	v_dual_fmaak_f32 v2, s11, v7, 0x3c0881c4 :: v_dual_mul_f32 v9, v4, v4
	v_dual_fmaak_f32 v8, s12, v7, 0xbab64f3b :: v_dual_lshlrev_b32 v11, 30, v1
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v2, v7, v2, 0xbe2aaa9d
	v_fmaak_f32 v13, s12, v9, 0xbab64f3b
	v_fmaak_f32 v12, s11, v9, 0x3c0881c4
	s_lshr_b32 s3, s3, 16
	s_xor_b32 s2, s2, s8
	v_mul_f32_e32 v14, v7, v2
	v_fmaak_f32 v8, v7, v8, 0x3d2aabf7
	v_and_b32_e32 v10, 1, v1
	v_mad_u64_u32 v[1:2], null, s14, s7, v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v3, v3, v14
	v_fmaak_f32 v8, v7, v8, 0xbf000004
	v_fmaak_f32 v2, v9, v12, 0xbe2aaa9d
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v7, v8, 1.0
	v_fmaak_f32 v7, v9, v13, 0x3d2aabf7
	v_and_b32_e32 v8, 0x80000000, v11
	v_cndmask_b32_e64 v6, -v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v3, v9, v7, 0xbf000004
	v_lshlrev_b32_e32 v7, 30, v5
	v_dual_mul_f32 v2, v9, v2 :: v_dual_and_b32 v5, 1, v5
	v_fma_f32 v9, v9, v3, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v7, 0x80000000, v7
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v4, v4, v2
	v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
	v_xor_b32_e32 v3, s2, v7
	s_mov_b32 s2, 0x54442d18
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v9, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, s8, 0x1f8
	v_xor_b32_e32 v4, v8, v6
	s_mov_b32 s3, 0x401921fb
	v_subrev_nc_u32_e32 v5, s5, v2
	v_xor_b32_e32 v0, v3, v0
	v_subrev_nc_u32_e32 v3, s4, v1
	v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v5, v5
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v3
	v_mul_f32_e32 v0, v0, v5
	v_cvt_f64_f32_e32 v[5:6], s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v4, v3
	v_cvt_f64_f32_e32 v[3:4], v0
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], s[2:3]
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
	v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
	v_div_fixup_f64 v[3:4], v[7:8], v[5:6], v[3:4]
	v_cvt_f64_f32_e32 v[5:6], s10
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_cvt_f32_f64_e32 v3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, 0x7fffffff, v3
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v3|
	v_lshrrev_b32_e32 v5, 23, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s4
	s_xor_b32 s5, exec_lo, s2
	s_cbranch_execz .LBB2_12
; %bb.11:
	s_mov_b32 s2, 0x7fffff
	v_mov_b32_e32 v8, 0
	v_and_or_b32 v0, v4, s2, 0x800000
	v_add_nc_u32_e32 v14, 0xffffff88, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v0, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v14
	v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v0, v[7:8]
	v_add_nc_u32_e32 v15, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v10
	v_cmp_lt_u32_e64 s2, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v0, v[7:8]
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v7, v11 :: v_dual_add_nc_u32 v16, v16, v15
	v_cndmask_b32_e32 v6, v10, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v16
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v0, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v12
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v0, v[7:8]
	v_mov_b32_e32 v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v0, v[7:8]
	v_mov_b32_e32 v7, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v0, v[7:8]
	v_cndmask_b32_e64 v0, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v7, v13, v11 :: v_dual_add_nc_u32 v0, v0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v14, v12 :: v_dual_cndmask_b32 v13, v15, v13
	v_cndmask_b32_e32 v12, v12, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v8, v7, s2
	v_cndmask_b32_e64 v8, v13, v8, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v12, s2
	v_sub_nc_u32_e32 v13, 32, v0
	v_cndmask_b32_e64 v12, v12, v9, s2
	v_cndmask_b32_e64 v8, v8, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v7, s3
	v_cndmask_b32_e64 v7, v7, v12, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v14, v8, v11, v13
	v_alignbit_b32 v10, v11, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v14, v8, vcc_lo
	v_cndmask_b32_e32 v8, v10, v11, vcc_lo
	v_cndmask_b32_e64 v6, v9, v6, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v9, v0, 29, 1
	v_alignbit_b32 v10, v0, v8, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v12, v6, s3
	v_sub_nc_u32_e32 v11, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v7, v6, v13
	v_xor_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v12, v7, vcc_lo
	v_clz_i32_u32_e32 v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v8, v7, 30
	v_alignbit_b32 v6, v7, v6, 30
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v8, v11
	v_xor_b32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, 31, v12
	v_lshlrev_b32_e32 v14, 23, v12
	v_alignbit_b32 v10, v10, v7, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v7, v6, v8
	v_lshrrev_b32_e32 v8, 29, v0
	v_alignbit_b32 v7, v10, v6, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v8, 31, v8
	v_lshrrev_b32_e32 v10, 9, v10
	v_clz_i32_u32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v13, 0.5, v8
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, v13, v14
	v_sub_nc_u32_e32 v15, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v7, v6, v15
	v_or_b32_e32 v7, v10, v13
	v_add_lshl_u32 v10, v11, v12, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v11, 0x3fc90fda, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v10
	v_fma_f32 v10, 0x3fc90fda, v7, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v7, v7, 0x33a22168, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v8
	v_fmac_f32_e32 v7, 0x3fc90fda, v6
	v_lshrrev_b32_e32 v6, 30, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v0, v11, v7 :: v_dual_add_nc_u32 v7, v9, v6
.LBB2_12:                               ; %Flow66
	s_or_saveexec_b32 s2, s5
	v_mul_f32_e64 v6, 0x3f22f983, |v3|
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.13:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v6
	v_fma_f32 v0, 0xbfc90fda, v7, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v7, 0xb3a22168, v0
	v_fmamk_f32 v0, v7, 0xa7c234c4, v0
	v_cvt_i32_f32_e32 v7, v7
; %bb.14:                               ; %_ZL3cosf.exit30
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, v0, v0 :: v_dual_and_b32 v11, 1, v7
	s_mov_b32 s2, 0xb94c1982
	s_mov_b32 s3, 0x37d75334
	v_mul_lo_u32 v2, v2, s6
	v_fmaak_f32 v9, s2, v8, 0x3c0881c4
	s_load_b64 s[0:1], s[0:1], 0x0
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_lshlrev_b32_e32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmaak_f32 v9, v8, v9, 0xbe2aaa9d
	v_fmaak_f32 v10, s3, v8, 0xbab64f3b
	v_add_lshl_u32 v1, v2, v1, 1
	v_and_b32_e32 v7, 0x80000000, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v9, v8, v9
	v_fmaak_f32 v10, v8, v10, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_fmac_f32_e32 v0, v0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v10, v8, v10, 0xbf000004
	v_fma_f32 v8, v8, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, -v0, v8, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
	v_xor_b32_e32 v7, v7, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0x7fc00000, v7, vcc_lo
                                        ; implicit-def: $vgpr7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v1, s0, s1, v1, s0
	global_store_b32 v[0:1], v2, off
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB2_16
; %bb.15:
	s_mov_b32 s0, 0x7fffff
	v_add_nc_u32_e32 v5, 0xffffff88, v5
	v_and_or_b32 v2, v4, s0, 0x800000
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s0, 63, v5
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, s0
	v_mad_u64_u32 v[9:10], null, 0x3c439041, v2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v14, v5
	v_cmp_lt_u32_e64 s1, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v10
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xdb629599, v2, v[7:8]
	v_add_nc_u32_e32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v7, v11
	v_cmp_lt_u32_e64 s2, 31, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v10, v6, s0
	v_mad_u64_u32 v[11:12], null, 0xf534ddc0, v2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v12
	v_mad_u64_u32 v[12:13], null, 0xfc2757d1, v2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v13
	v_mad_u64_u32 v[13:14], null, 0x4e441529, v2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v14
	v_mad_u64_u32 v[14:15], null, 0xa2f9836e, v2, v[7:8]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v13, v11, s0
	v_add_nc_u32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v14, v12, s0
	v_cndmask_b32_e64 v13, v15, v13, s0
	v_cndmask_b32_e64 v12, v12, v10, s0
	v_cndmask_b32_e64 v5, v11, v9, s0
	v_sub_nc_u32_e32 v11, 32, v2
	v_cndmask_b32_e64 v9, v8, v7, s1
	v_cndmask_b32_e64 v8, v13, v8, s1
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v12, v12, v5, s1
	v_cmp_eq_u32_e64 s0, 0, v2
	v_cndmask_b32_e64 v5, v5, v6, s1
	v_cndmask_b32_e64 v8, v8, v9, s2
	v_cndmask_b32_e64 v9, v9, v7, s2
	v_cndmask_b32_e64 v7, v7, v12, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v12, v5, s2
	v_alignbit_b32 v13, v8, v9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v9, v7, v11
	v_alignbit_b32 v11, v7, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v13, v8, s0
	v_cndmask_b32_e64 v6, v10, v9, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, v11, v7, s0
	v_bfe_u32 v8, v2, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v2, v6, 30
	v_alignbit_b32 v6, v6, v7, 30
	v_alignbit_b32 v5, v7, v5, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, 0, v8
	v_xor_b32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v10
	v_xor_b32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v9
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, 31, v11
	v_lshlrev_b32_e32 v13, 23, v11
	v_alignbit_b32 v9, v9, v6, v7
	v_alignbit_b32 v5, v6, v5, v7
	v_lshrrev_b32_e32 v7, 29, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v9, v5, 9
	v_lshlrev_b32_e32 v7, 31, v7
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v10, v6
	v_or_b32_e32 v12, 0.5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v10
	v_alignbit_b32 v5, v6, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v6, v9, v12
	v_add_lshl_u32 v9, v10, v11, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fc90fda, v6, -v10
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v6, v6, 0x33a22168, v9
	v_or_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0x3fc90fda, v5
	v_lshrrev_b32_e32 v5, 30, v2
	v_dual_add_f32 v2, v10, v6 :: v_dual_add_nc_u32 v7, v8, v5
                                        ; implicit-def: $vgpr6
.LBB2_16:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s3
; %bb.17:
	v_rndne_f32_e32 v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0xbfc90fda, v5, |v3|
	v_cvt_i32_f32_e32 v7, v5
	v_fmamk_f32 v2, v5, 0xb3a22168, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v2, v5, 0xa7c234c4, v2
; %bb.18:                               ; %_ZL3sinf.exit38
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v9, 1, v7
	v_lshlrev_b32_e32 v7, 30, v7
	v_mul_f32_e32 v5, v2, v2
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, s0, v5, 0x3c0881c4
	v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v6
	v_fmac_f32_e32 v2, v2, v6
	v_and_b32_e32 v6, 0x80000000, v7
	v_fmaak_f32 v8, s1, v5, 0xbab64f3b
	v_cmp_eq_u32_e64 s0, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v8, v5, v8, 0x3d2aabf7
	v_fmaak_f32 v8, v5, v8, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v5, v8, 1.0
	v_cndmask_b32_e64 v2, v5, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v2, v3, v6, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	global_store_b32 v[0:1], v2, off offset:4
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,"axG",@progbits,_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_,comdat
.Lfunc_end2:
	.size	_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_, .Lfunc_end2-_ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3988
; NumSgprs: 24
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL25multiplyRealComplexKernelPfS_S_,"axG",@progbits,_ZL25multiplyRealComplexKernelPfS_S_,comdat
	.globl	_ZL25multiplyRealComplexKernelPfS_S_ ; -- Begin function _ZL25multiplyRealComplexKernelPfS_S_
	.p2align	8
	.type	_ZL25multiplyRealComplexKernelPfS_S_,@function
_ZL25multiplyRealComplexKernelPfS_S_:   ; @_ZL25multiplyRealComplexKernelPfS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_lshlrev_b32_e32 v3, 1, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	global_load_b32 v6, v[0:1], off
	global_load_b32 v7, v[4:5], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v6, v7
	global_store_b32 v[2:3], v6, off
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v1
	global_store_b32 v[2:3], v0, off offset:4
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL25multiplyRealComplexKernelPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL25multiplyRealComplexKernelPfS_S_,"axG",@progbits,_ZL25multiplyRealComplexKernelPfS_S_,comdat
.Lfunc_end3:
	.size	_ZL25multiplyRealComplexKernelPfS_S_, .Lfunc_end3-_ZL25multiplyRealComplexKernelPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL28multiplyComplexComplexKernelPfS_S_,"axG",@progbits,_ZL28multiplyComplexComplexKernelPfS_S_,comdat
	.globl	_ZL28multiplyComplexComplexKernelPfS_S_ ; -- Begin function _ZL28multiplyComplexComplexKernelPfS_S_
	.p2align	8
	.type	_ZL28multiplyComplexComplexKernelPfS_S_,@function
_ZL28multiplyComplexComplexKernelPfS_S_: ; @_ZL28multiplyComplexComplexKernelPfS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	v_add_lshl_u32 v0, s15, v0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v3, v5
	v_mul_f32_e32 v6, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v2, v4, -v7
	v_fmac_f32_e32 v6, v3, v4
	global_store_b64 v[0:1], v[5:6], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL28multiplyComplexComplexKernelPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL28multiplyComplexComplexKernelPfS_S_,"axG",@progbits,_ZL28multiplyComplexComplexKernelPfS_S_,comdat
.Lfunc_end4:
	.size	_ZL28multiplyComplexComplexKernelPfS_S_, .Lfunc_end4-_ZL28multiplyComplexComplexKernelPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL12centerKernelPf15HIP_vector_typeIiLj2EE,"axG",@progbits,_ZL12centerKernelPf15HIP_vector_typeIiLj2EE,comdat
	.globl	_ZL12centerKernelPf15HIP_vector_typeIiLj2EE ; -- Begin function _ZL12centerKernelPf15HIP_vector_typeIiLj2EE
	.p2align	8
	.type	_ZL12centerKernelPf15HIP_vector_typeIiLj2EE,@function
_ZL12centerKernelPf15HIP_vector_typeIiLj2EE: ; @_ZL12centerKernelPf15HIP_vector_typeIiLj2EE
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v0
	v_and_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 1, v2
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v2, s2, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v0, v2, v0, 1
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v2, 0x80000000, v2
	v_xor_b32_e32 v3, 0x80000000, v3
	global_store_b64 v[0:1], v[2:3], off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL12centerKernelPf15HIP_vector_typeIiLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL12centerKernelPf15HIP_vector_typeIiLj2EE,"axG",@progbits,_ZL12centerKernelPf15HIP_vector_typeIiLj2EE,comdat
.Lfunc_end5:
	.size	_ZL12centerKernelPf15HIP_vector_typeIiLj2EE, .Lfunc_end5-_ZL12centerKernelPf15HIP_vector_typeIiLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL24complexToMagnitudeKernelPfS_,"axG",@progbits,_ZL24complexToMagnitudeKernelPfS_,comdat
	.globl	_ZL24complexToMagnitudeKernelPfS_ ; -- Begin function _ZL24complexToMagnitudeKernelPfS_
	.p2align	8
	.type	_ZL24complexToMagnitudeKernelPfS_,@function
_ZL24complexToMagnitudeKernelPfS_:      ; @_ZL24complexToMagnitudeKernelPfS_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v0, v2, v2
	v_mul_f32_e32 v2, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_sqrt_f32_e32 v2, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v2
	v_add_nc_u32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v2, v0
	v_fma_f32 v6, -v4, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v5
	v_cndmask_b32_e64 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v6
	v_cndmask_b32_e64 v2, v2, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, 0x37800000, v2
	v_cndmask_b32_e32 v3, v2, v3, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v0, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0.5, v3
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL24complexToMagnitudeKernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL24complexToMagnitudeKernelPfS_,"axG",@progbits,_ZL24complexToMagnitudeKernelPfS_,comdat
.Lfunc_end6:
	.size	_ZL24complexToMagnitudeKernelPfS_, .Lfunc_end6-_ZL24complexToMagnitudeKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL19complexToRealKernelPfS_,"axG",@progbits,_ZL19complexToRealKernelPfS_,comdat
	.globl	_ZL19complexToRealKernelPfS_    ; -- Begin function _ZL19complexToRealKernelPfS_
	.p2align	8
	.type	_ZL19complexToRealKernelPfS_,@function
_ZL19complexToRealKernelPfS_:           ; @_ZL19complexToRealKernelPfS_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v2, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL19complexToRealKernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL19complexToRealKernelPfS_,"axG",@progbits,_ZL19complexToRealKernelPfS_,comdat
.Lfunc_end7:
	.size	_ZL19complexToRealKernelPfS_, .Lfunc_end7-_ZL19complexToRealKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL19realToComplexKernelPfS_,"axG",@progbits,_ZL19realToComplexKernelPfS_,comdat
	.globl	_ZL19realToComplexKernelPfS_    ; -- Begin function _ZL19realToComplexKernelPfS_
	.p2align	8
	.type	_ZL19realToComplexKernelPfS_,@function
_ZL19realToComplexKernelPfS_:           ; @_ZL19realToComplexKernelPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_lshlrev_b32_e32 v1, 1, v1
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b32 v0, v[2:3], off
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL19realToComplexKernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL19realToComplexKernelPfS_,"axG",@progbits,_ZL19realToComplexKernelPfS_,comdat
.Lfunc_end8:
	.size	_ZL19realToComplexKernelPfS_, .Lfunc_end8-_ZL19realToComplexKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL22differenceImagesKernelPfS_S_f,"axG",@progbits,_ZL22differenceImagesKernelPfS_S_f,comdat
	.globl	_ZL22differenceImagesKernelPfS_S_f ; -- Begin function _ZL22differenceImagesKernelPfS_S_f
	.p2align	8
	.type	_ZL22differenceImagesKernelPfS_S_f,@function
_ZL22differenceImagesKernelPfS_S_f:     ; @_ZL22differenceImagesKernelPfS_S_f
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s2
	v_add_lshl_u32 v0, s15, v0, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e64 v2, 0x3b808081, |v2|
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL22differenceImagesKernelPfS_S_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL22differenceImagesKernelPfS_S_f,"axG",@progbits,_ZL22differenceImagesKernelPfS_S_f,comdat
.Lfunc_end9:
	.size	_ZL22differenceImagesKernelPfS_S_f, .Lfunc_end9-_ZL22differenceImagesKernelPfS_S_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,"axG",@progbits,_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,comdat
	.globl	_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f ; -- Begin function _ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
	.p2align	8
	.type	_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,@function
_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f: ; @_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
; %bb.0:
	s_clause 0x1
	s_load_b64 s[12:13], s[0:1], 0x30
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s16, s0, 48
	s_addc_u32 s17, s1, 0
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v1, s13
	v_cvt_f32_u32_e32 v2, s12
	s_sub_i32 s3, 0, s13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s2, v1
	v_mul_f32_e32 v1, 0x4f7ffffe, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s3, s2
	v_cvt_u32_f32_e32 v1, v1
	s_mul_hi_u32 s3, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s2, s2, s3
	v_readfirstlane_b32 s19, v1
	s_mul_hi_u32 s11, s9, s2
	s_load_b128 s[0:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s11, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s3, s9, s3
	s_add_i32 s9, s11, 1
	s_sub_i32 s18, s3, s13
	s_cmp_ge_u32 s3, s13
	s_cselect_b32 s9, s9, s11
	s_cselect_b32 s3, s18, s3
	s_add_i32 s11, s9, 1
	s_cmp_ge_u32 s3, s13
	s_cselect_b32 s3, s11, s9
	s_sub_i32 s9, 0, s12
	s_mul_i32 s3, s3, s15
	s_mul_i32 s9, s9, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s9, s19, s9
	s_add_i32 s19, s19, s9
	v_add3_u32 v1, s3, s1, v0
	s_mul_hi_u32 s9, s8, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s11, s9, s12
	s_add_i32 s3, s9, 1
	s_sub_i32 s1, s8, s11
	v_mul_lo_u32 v1, v1, s10
	s_sub_i32 s8, s1, s12
	s_cmp_ge_u32 s1, s12
	s_cselect_b32 s3, s3, s9
	s_cselect_b32 s1, s8, s1
	s_add_i32 s8, s3, 1
	s_cmp_ge_u32 s1, s12
	s_cselect_b32 s1, s8, s3
	s_mov_b32 s8, 0
	s_mul_i32 s3, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v2, s3, s0, v1
	s_mov_b32 s3, exec_lo
	v_lshlrev_b32_e32 v1, 1, v2
	v_add_lshl_u32 v5, v2, s1, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v1, v5
	s_cbranch_execz .LBB10_4
; %bb.1:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB10_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[2:3], off
	v_add_nc_u32_e32 v1, 2, v1
	v_add_co_u32 v2, vcc_lo, v2, 8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v1, v5
	s_or_b32 s8, s0, s8
	s_waitcnt vmcnt(0)
	v_add_f32_e64 v4, v4, |v6|
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB10_2
; %bb.3:                                ; %Flow74
	s_or_b32 exec_lo, exec_lo, s8
.LBB10_4:                               ; %Flow75
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_cvt_f32_u32_e32 v1, s1
	s_mov_b32 s0, exec_lo
	v_div_scale_f32 v2, null, v1, v1, v4
	v_div_scale_f32 v6, vcc_lo, v4, v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v3
	v_fma_f32 v7, -v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v3
	v_fma_f32 v2, -v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v3, v5
	v_lshl_add_u32 v3, v0, 2, 0
	v_div_fixup_f32 v1, v2, v1, v4
	ds_store_b32 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB10_9
; %bb.5:
	s_load_b32 s0, s[16:17], 0xc
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB10_8
; %bb.6:                                ; %.lr.ph44.preheader
	s_mov_b32 s1, 0
	s_mov_b32 s3, s0
.LBB10_7:                               ; %.lr.ph44
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s1
	s_add_i32 s3, s3, -1
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s3, 0
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v0, v0, v1
	s_cbranch_scc0 .LBB10_7
.LBB10_8:                               ; %Flow72
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, s2, v0
	v_cvt_f32_u32_e32 v1, s0
	s_mul_i32 s0, s12, s15
	s_mov_b32 s1, 0
	s_add_i32 s0, s0, s14
	v_div_scale_f32 v2, null, v1, v1, v0
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s0, s6, s0
	v_rcp_f32_e32 v3, v2
	s_addc_u32 s1, s7, s1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v3
	v_div_scale_f32 v5, vcc_lo, v0, v1, v0
	v_mul_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v4, v5
	v_fmac_f32_e32 v4, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v4, v5
	v_div_fmas_f32 v2, v2, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v2, v1, v0
	v_cmp_nlt_f32_e32 vcc_lo, 1.0, v0
	v_cndmask_b32_e32 v1, 1.0, v0, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v0, 0, v1 :: v_dual_mov_b32 v1, 0
	global_store_b32 v1, v0, s[0:1]
.LBB10_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,"axG",@progbits,_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f,comdat
.Lfunc_end10:
	.size	_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f, .Lfunc_end10-_ZL21computeAveragesKernelPfS_15HIP_vector_typeIiLj2EES1_S1_f
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 824
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE,"axG",@progbits,_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE,comdat
	.globl	_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE ; -- Begin function _ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE
	.p2align	8
	.type	_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE,@function
_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE: ; @_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s2, v0
	s_cmp_lt_i32 s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[4:5], off
	s_cbranch_scc1 .LBB11_4
; %bb.1:                                ; %.lr.ph.preheader
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v5, v4 :: v_dual_add_nc_u32 v6, s2, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_mov_b32 s3, 0
.LBB11_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[2:3], off
	v_add_nc_u32_e32 v1, 1, v1
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v6
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e64 s2, v7, v5
	v_cndmask_b32_e64 v5, v5, v7, s2
	v_cmp_gt_f32_e64 s2, v7, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v7, s2
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB11_2
; %bb.3:                                ; %Flow68
	s_or_b32 exec_lo, exec_lo, s3
	s_branch .LBB11_5
.LBB11_4:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v4
.LBB11_5:                               ; %Flow69
	v_lshl_add_u32 v1, v0, 3, 0
	s_mov_b32 s2, exec_lo
	ds_store_2addr_b32 v1, v5, v4 offset1:1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB11_10
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_load_b32 s0, s[0:1], 0x24
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_mov_b32 s0, 0
	s_cmp_eq_u32 s1, 0
	v_mov_b32_e32 v1, v0
	s_cbranch_scc1 .LBB11_9
; %bb.7:                                ; %.lr.ph53.preheader
	s_lshl_b32 s1, s1, 1
.LBB11_8:                               ; %.lr.ph53
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, s0
	s_add_i32 s1, s1, -1
	s_add_i32 s0, s0, 4
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v2, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v2, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_cbranch_scc0 .LBB11_8
.LBB11_9:                               ; %Flow66
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v2, 0x3b800000, v0
	v_mul_f32_e32 v1, 0x3b800000, v1
	global_store_b64 v3, v[1:2], s[6:7]
.LBB11_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE,"axG",@progbits,_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE,comdat
.Lfunc_end11:
	.size	_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE, .Lfunc_end11-_ZL19computeMinMaxKernelPfS_15HIP_vector_typeIiLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 10
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,"axG",@progbits,_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,comdat
	.globl	_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_ ; -- Begin function _ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
	.p2align	8
	.type	_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,@function
_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_: ; @_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x20
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v1, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s2, v1, s[8:9]
	v_lshlrev_b32_e32 v1, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[6:7], off
	v_add_lshl_u32 v6, v5, s10, 1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e64 v1, v6
	s_cbranch_execz .LBB12_4
; %bb.1:                                ; %.lr.ph.preheader
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	v_mov_b32_e32 v5, v4
	s_mov_b32 s4, 0
.LBB12_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[2:3], off
	v_add_nc_u32_e32 v1, 2, v1
	v_add_co_u32 v2, vcc_lo, v2, 8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, v1, v6
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e64 s2, v7, v5
	v_cndmask_b32_e64 v5, v5, v7, s2
	v_cmp_gt_f32_e64 s2, v7, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v7, s2
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB12_2
; %bb.3:                                ; %Flow76
	s_or_b32 exec_lo, exec_lo, s4
.LBB12_4:                               ; %Flow77
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 3, 0
	s_mov_b32 s2, exec_lo
	ds_store_2addr_b32 v1, v5, v4 offset1:1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB12_9
; %bb.5:
	v_mov_b32_e32 v0, 0
	s_load_b32 s0, s[0:1], 0x34
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s0, 0xffff
	s_mov_b32 s0, 0
	s_cmp_eq_u32 s1, 0
	v_mov_b32_e32 v1, v0
	s_cbranch_scc1 .LBB12_8
; %bb.6:                                ; %.lr.ph56.preheader
	s_lshl_b32 s1, s1, 1
.LBB12_7:                               ; %.lr.ph56
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, s0
	s_add_i32 s1, s1, -1
	s_add_i32 s0, s0, 4
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v2, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v2, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_cbranch_scc0 .LBB12_7
.LBB12_8:                               ; %Flow74
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[1:2], v1
	v_cvt_f64_f32_e32 v[3:4], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[0:1], v[1:2], -8
	v_ldexp_f64 v[2:3], v[3:4], -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[0:1], v[0:1], -8
	v_ldexp_f64 v[2:3], v[2:3], -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v0, v[0:1]
	v_cvt_f32_f64_e32 v1, v[2:3]
	v_mov_b32_e32 v2, 0
	global_store_b64 v2, v[0:1], s[6:7]
.LBB12_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 12
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,"axG",@progbits,_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_,comdat
.Lfunc_end12:
	.size	_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_, .Lfunc_end12-_ZL20computeMinMaxKernel2PfS_15HIP_vector_typeIiLj2EES1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 468
; NumSgprs: 14
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL23normalizeAveragesKernelPfS_,"axG",@progbits,_ZL23normalizeAveragesKernelPfS_,comdat
	.globl	_ZL23normalizeAveragesKernelPfS_ ; -- Begin function _ZL23normalizeAveragesKernelPfS_
	.p2align	8
	.type	_ZL23normalizeAveragesKernelPfS_,@function
_ZL23normalizeAveragesKernelPfS_:       ; @_ZL23normalizeAveragesKernelPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_load_b64 s[0:1], s[2:3], 0x0
	global_load_b32 v2, v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e64 v3, s1, s0
	s_waitcnt vmcnt(0)
	v_subrev_f32_e32 v2, s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v4, null, v3, v3, v2
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v2, v3, v2
	v_mul_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v4, v7, v6
	v_fmac_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v7, v6
	v_div_fmas_f32 v4, v4, v5, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v2, v4, v3, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL23normalizeAveragesKernelPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL23normalizeAveragesKernelPfS_,"axG",@progbits,_ZL23normalizeAveragesKernelPfS_,comdat
.Lfunc_end13:
	.size	_ZL23normalizeAveragesKernelPfS_, .Lfunc_end13-_ZL23normalizeAveragesKernelPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
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        .size:           2
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        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _ZL14generateFilterPffffff15HIP_vector_typeIiLj2EES1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .size:           2
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    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _ZL14gaussianKernelPffff15HIP_vector_typeIiLj2EES1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
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    .workgroup_processor_mode: 1
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    .language:       OpenCL C
    .language_version:
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    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _ZL14harmonicKernelPffff15HIP_vector_typeIiLj2EES1_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
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...

	.end_amdgpu_metadata
