#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <time.h>

/*
 * Monte Carlo Pi Estimation Algorithm in CUDA
 *
 * This Project uses Cuda and thread
 * topology to estimate Pi.
 *
 * Author: Clayton Glenn
 */

#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0

/** Kernel Function
  * First finds the Thread ID within the block of GPU Threads
  * and if the Thread is Correct, it Encrypts the corresponding
  * Character in the String.
 **/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {

  //Get Thread id
  int tid = blockIdx.x * blockDim.x + threadIdx.x;

  // Loop N/Threads times plus one
  for(int i = 0; i < (n/t + 1); i++){

    // If looped id count is less than n, grab rand x
    // and y and check within unit. Increment if so
    if((i*t+tid) < n){
      if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
    }
  }
}

/**
  * Helper Function
  * Prints an string to standard error showing help
  * for valid arguments in the executable
 **/
void printerror(){
  fprintf(stderr, "Invalid Arguments\n");
  fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
  exit(0);
}
/**
  * Main Program
  * This Program is for Homework 6 to encrypt some text or show
  * the encryption method of text that is 2 to the power of N
  * characters long all initialized to zero.
 **/
int main(int argc, char **argv) {

  // Declare a buffer of max size to start
  int N       = MIN_THREAD;
  int THREADS = MIN_THREAD;
  int BLOCKS  = 256;

  // Check for immediate errors in args
  if (argc < 3 || argc > 3) printerror();

  // Get Thread Count Per Block
  THREADS = strtol(argv[1], NULL, 10);
  THREADS = ((int)pow(2, THREADS));
  if(THREADS < BLOCKS) BLOCKS = 1;
  else THREADS = THREADS / BLOCKS;

  // Get N Coordinates
  N = strtol(argv[2], NULL, 10);
  N = (int)pow(2, N);

  // Print N and Threads for distinguish
  printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);

  //Set Array of Size Thread
  int flags[BLOCKS*THREADS];
  float randx[N];
  float randy[N];
  srand( time( NULL ) );
  for(int i = 0; i < N; i++){
    if(i < BLOCKS*THREADS)flags[i] = 0;
    randx[i] = ( float )rand()/RAND_MAX;
    randy[i] = ( float )rand()/RAND_MAX;
  }

  // Init all other variables
  int *dev_flags;
  float *dev_randx;
  float *dev_randy;
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  float final_time = 0.0;

  // Allocate memory in the GPU for the int array
  cudaMalloc(&dev_randx, N*sizeof(float));
  cudaMalloc(&dev_randy, N*sizeof(float));
  cudaMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));

  // Copy the Memory from the array to the array pointers
  cudaMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyHostToDevice);
  cudaMemcpy(dev_randx, randx, N*sizeof(float), cudaMemcpyHostToDevice);
  cudaMemcpy(dev_randy, randy, N*sizeof(float), cudaMemcpyHostToDevice);

  // Total Time Record
  cudaEventRecord(start);
  monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
  cudaEventRecord(stop);

  // Copy the results from GPU to the CPU
  cudaMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), cudaMemcpyDeviceToHost);

  // Count total successes for each thread
  int success = 0;
  for(int i = 0; i < BLOCKS*THREADS; i++){
    if(flags[i] > 0) success += flags[i];
  }

  // Print Successes, failures, and estimation
  //printf("Success: %d\n", success);
  //printf("Failure: %d\n", (N - success));
  printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);

  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&final_time, start, stop);
  printf("Time in Kernel: %1.10f\n\n", final_time/1000);

  cudaFree(dev_flags);
  cudaFree(dev_randx);
  cudaFree(dev_randy);
}

	.file	"tmpxft_002369b1_00000000-6_Monte_CUDA.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Invalid Arguments\n"
.LC1:
	.string	"Correct Form: ./monte [# threads] [# points]\n"
	.text
	.globl	_Z10printerrorv
	.type	_Z10printerrorv, @function
_Z10printerrorv:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	stderr(%rip), %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z10printerrorv, .-_Z10printerrorv
	.globl	_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
	.type	_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, @function
_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z5montePiPfS0_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii, .-_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
	.globl	_Z5montePiPfS0_ii
	.type	_Z5montePiPfS0_ii, @function
_Z5montePiPfS0_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
	.cfi_endproc
.LFE2054:
	.size	_Z5montePiPfS0_ii, .-_Z5montePiPfS0_ii
	.section	.rodata.str1.1
.LC3:
	.string	"(Threads: %d) (N: %d)\n"
.LC7:
	.string	"Estimation of Pi: %1.6f\n"
.LC9:
	.string	"Time in Kernel: %1.10f\n\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$136, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	cmpl	$3, %edi
	je	.L11
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	jne	.L42
	call	_Z10printerrorv
.L11:
	movq	8(%rsi), %rdi
	movl	$10, %edx
	movq	%rsi, %rbx
	xorl	%esi, %esi
	movl	$1, %r15d
	call	__isoc23_strtol@PLT
	movsd	.LC2(%rip), %xmm0
	cvtsi2sdl	%eax, %xmm1
	call	pow@PLT
	cvttsd2sil	%xmm0, %r13d
	cmpl	$255, %r13d
	jle	.L13
	sarl	$8, %r13d
	movl	$256, %r15d
.L13:
	movq	16(%rbx), %rdi
	movl	$10, %edx
	xorl	%esi, %esi
	movl	%r13d, %r12d
	imull	%r15d, %r12d
	call	__isoc23_strtol@PLT
	movsd	.LC2(%rip), %xmm0
	cvtsi2sdl	%eax, %xmm1
	call	pow@PLT
	movl	%r12d, %edx
	movl	$2, %edi
	xorl	%eax, %eax
	cvttsd2sil	%xmm0, %ebx
	leaq	.LC3(%rip), %rsi
	movl	%ebx, %ecx
	call	__printf_chk@PLT
	movslq	%r12d, %rax
	movq	%rsp, %rcx
	salq	$2, %rax
	leaq	15(%rax), %rdx
	movq	%rax, -144(%rbp)
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L14:
	cmpq	%rcx, %rsp
	je	.L15
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L14
.L15:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L16
	orq	$0, -8(%rsp,%rax)
.L16:
	movslq	%ebx, %rax
	movq	%rsp, -152(%rbp)
	movq	%rsp, %rcx
	salq	$2, %rax
	movq	%rax, -136(%rbp)
	addq	$15, %rax
	movq	%rax, %rsi
	movq	%rax, %rdx
	andq	$-4096, %rsi
	andq	$-16, %rdx
	subq	%rsi, %rcx
.L17:
	cmpq	%rcx, %rsp
	je	.L18
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L17
.L18:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L19
	orq	$0, -8(%rsp,%rdx)
.L19:
	movq	%rsp, -160(%rbp)
	movq	%rax, %rdx
	movq	%rsp, %rcx
	andq	$-4096, %rax
	andq	$-16, %rdx
	subq	%rax, %rcx
.L20:
	cmpq	%rcx, %rsp
	je	.L21
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L20
.L21:
	movq	%rdx, %rax
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L22
	orq	$0, -8(%rsp,%rax)
.L22:
	xorl	%edi, %edi
	movq	%rsp, -168(%rbp)
	xorl	%r14d, %r14d
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
.L23:
	cmpl	%r14d, %ebx
	jle	.L43
	cmpl	%r14d, %r12d
	jle	.L24
	movq	-152(%rbp), %rax
	xorl	%edx, %edx
	movl	%edx, (%rax,%r14,4)
.L24:
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC4(%rip), %xmm0
	movq	-160(%rbp), %rax
	movss	%xmm0, (%rax,%r14,4)
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	mulss	.LC4(%rip), %xmm0
	movq	-168(%rbp), %rax
	movss	%xmm0, (%rax,%r14,4)
	incq	%r14
	jmp	.L23
.L43:
	leaq	-96(%rbp), %rdi
	call	cudaEventCreate@PLT
	leaq	-88(%rbp), %rdi
	call	cudaEventCreate@PLT
	movq	-136(%rbp), %rsi
	leaq	-112(%rbp), %rdi
	movl	$0x00000000, -124(%rbp)
	call	cudaMalloc@PLT
	movq	-136(%rbp), %rsi
	leaq	-104(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-144(%rbp), %rsi
	leaq	-120(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	-144(%rbp), %rdx
	movq	-120(%rbp), %rdi
	movl	$1, %ecx
	movq	-152(%rbp), %rsi
	call	cudaMemcpy@PLT
	movq	-136(%rbp), %rdx
	movq	-112(%rbp), %rdi
	movl	$1, %ecx
	movq	-160(%rbp), %rsi
	call	cudaMemcpy@PLT
	movq	-136(%rbp), %rdx
	movq	-104(%rbp), %rdi
	movl	$1, %ecx
	movq	-168(%rbp), %rsi
	call	cudaMemcpy@PLT
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r13d, -68(%rbp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	%r15d, -80(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	%rax, -76(%rbp)
	movq	-68(%rbp), %rdx
	movq	-80(%rbp), %rdi
	movl	-72(%rbp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	-104(%rbp), %rdx
	movq	-112(%rbp), %rsi
	movl	%ebx, %r8d
	movl	%r12d, %ecx
	movq	-120(%rbp), %rdi
	call	_Z31__device_stub__Z5montePiPfS0_iiPiPfS0_ii
.L26:
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-144(%rbp), %rdx
	movq	-120(%rbp), %rsi
	movl	$2, %ecx
	movq	-152(%rbp), %rdi
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorl	%edx, %edx
.L27:
	cmpl	%eax, %r12d
	jle	.L44
	movq	-152(%rbp), %rcx
	movl	(%rcx,%rax,4), %ecx
	testl	%ecx, %ecx
	jle	.L28
	addl	%ecx, %edx
.L28:
	incq	%rax
	jmp	.L27
.L44:
	cvtsi2ssl	%ebx, %xmm1
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2ssl	%edx, %xmm0
	divss	%xmm1, %xmm0
	mulss	.LC6(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	-88(%rbp), %rdi
	call	cudaEventSynchronize@PLT
	movq	-88(%rbp), %rdx
	movq	-96(%rbp), %rsi
	leaq	-124(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	movss	-124(%rbp), %xmm0
	divss	.LC8(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	-120(%rbp), %rdi
	call	cudaFree@PLT
	movq	-112(%rbp), %rdi
	call	cudaFree@PLT
	movq	-104(%rbp), %rdi
	call	cudaFree@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L30
.L42:
	call	__stack_chk_fail@PLT
.L30:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z5montePiPfS0_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5montePiPfS0_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1073741824
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	805306368
	.align 4
.LC6:
	.long	1082130432
	.align 4
.LC8:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <time.h>

/*
 * Monte Carlo Pi Estimation Algorithm in CUDA
 *
 * This Project uses Cuda and thread
 * topology to estimate Pi.
 *
 * Author: Clayton Glenn
 */

#define MAX_THREAD 16
#define MIN_THREAD 8
#define MAX_N 20
#define MIN_N 8
#define BLOCK_SIZE 256
#define DEBUG 0

/** Kernel Function
  * First finds the Thread ID within the block of GPU Threads
  * and if the Thread is Correct, it Encrypts the corresponding
  * Character in the String.
 **/
__global__
void monte(int *flags, float *x_vals, float *y_vals, int t, int n) {

  //Get Thread id
  int tid = blockIdx.x * blockDim.x + threadIdx.x;

  // Loop N/Threads times plus one
  for(int i = 0; i < (n/t + 1); i++){

    // If looped id count is less than n, grab rand x
    // and y and check within unit. Increment if so
    if((i*t+tid) < n){
      if((pow(x_vals[(i*t+tid)], 2) + pow(y_vals[(i*t+tid)],2)) <= 1) flags[(tid)]++;
    }
  }
}

/**
  * Helper Function
  * Prints an string to standard error showing help
  * for valid arguments in the executable
 **/
void printerror(){
  fprintf(stderr, "Invalid Arguments\n");
  fprintf(stderr, "Correct Form: ./monte [# threads] [# points]\n");
  exit(0);
}
/**
  * Main Program
  * This Program is for Homework 6 to encrypt some text or show
  * the encryption method of text that is 2 to the power of N
  * characters long all initialized to zero.
 **/
int main(int argc, char **argv) {

  // Declare a buffer of max size to start
  int N       = MIN_THREAD;
  int THREADS = MIN_THREAD;
  int BLOCKS  = 256;

  // Check for immediate errors in args
  if (argc < 3 || argc > 3) printerror();

  // Get Thread Count Per Block
  THREADS = strtol(argv[1], NULL, 10);
  THREADS = ((int)pow(2, THREADS));
  if(THREADS < BLOCKS) BLOCKS = 1;
  else THREADS = THREADS / BLOCKS;

  // Get N Coordinates
  N = strtol(argv[2], NULL, 10);
  N = (int)pow(2, N);

  // Print N and Threads for distinguish
  printf("(Threads: %d) (N: %d)\n", THREADS * BLOCKS, N);

  //Set Array of Size Thread
  int flags[BLOCKS*THREADS];
  float randx[N];
  float randy[N];
  srand( time( NULL ) );
  for(int i = 0; i < N; i++){
    if(i < BLOCKS*THREADS)flags[i] = 0;
    randx[i] = ( float )rand()/RAND_MAX;
    randy[i] = ( float )rand()/RAND_MAX;
  }

  // Init all other variables
  int *dev_flags;
  float *dev_randx;
  float *dev_randy;
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  float final_time = 0.0;

  // Allocate memory in the GPU for the int array
  hipMalloc(&dev_randx, N*sizeof(float));
  hipMalloc(&dev_randy, N*sizeof(float));
  hipMalloc(&dev_flags, BLOCKS*THREADS*sizeof(int));

  // Copy the Memory from the array to the array pointers
  hipMemcpy(dev_flags, flags, BLOCKS*THREADS*sizeof(int), hipMemcpyHostToDevice);
  hipMemcpy(dev_randx, randx, N*sizeof(float), hipMemcpyHostToDevice);
  hipMemcpy(dev_randy, randy, N*sizeof(float), hipMemcpyHostToDevice);

  // Total Time Record
  hipEventRecord(start);
  monte<<<BLOCKS, THREADS>>>(dev_flags, dev_randx, dev_randy, BLOCKS*THREADS, N);
  hipEventRecord(stop);

  // Copy the results from GPU to the CPU
  hipMemcpy(flags, dev_flags, BLOCKS*THREADS*sizeof(int), hipMemcpyDeviceToHost);

  // Count total successes for each thread
  int success = 0;
  for(int i = 0; i < BLOCKS*THREADS; i++){
    if(flags[i] > 0) success += flags[i];
  }

  // Print Successes, failures, and estimation
  //printf("Success: %d\n", success);
  //printf("Failure: %d\n", (N - success));
  printf("Estimation of Pi: %1.6f\n", ((float)success/N)*4);

  hipEventSynchronize(stop);
  hipEventElapsedTime(&final_time, start, stop);
  printf("Time in Kernel: %1.10f\n\n", final_time/1000);

  hipFree(dev_flags);
  hipFree(dev_randx);
  hipFree(dev_randy);
}

	.text
	.file	"Monte_CUDA.hip"
	.globl	_Z20__device_stub__montePiPfS0_ii # -- Begin function _Z20__device_stub__montePiPfS0_ii
	.type	_Z20__device_stub__montePiPfS0_ii,@function
_Z20__device_stub__montePiPfS0_ii:      # @_Z20__device_stub__montePiPfS0_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5montePiPfS0_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__montePiPfS0_ii, .Lfunc_end0-_Z20__device_stub__montePiPfS0_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10printerrorv                 # -- Begin function _Z10printerrorv
	.type	_Z10printerrorv,@function
_Z10printerrorv:                        # @_Z10printerrorv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$18, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$45, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	xorl	%edi, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z10printerrorv, .Lfunc_end1-_Z10printerrorv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x3ff0000000000000              # double 1
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x30000000                      # float 4.65661287E-10
.LCPI2_2:
	.long	0x40800000                      # float 4
.LCPI2_3:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$72, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$3, %edi
	jne	.LBB2_14
# %bb.1:
	movq	%rsi, %rbx
	movq	8(%rsi), %rdi
	xorl	%esi, %esi
	movl	$10, %edx
	callq	__isoc23_strtol
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%eax, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %eax
	movl	%eax, %r12d
	shrl	$8, %r12d
	cmpl	$256, %eax                      # imm = 0x100
	setge	%r15b
	movl	%eax, -84(%rbp)                 # 4-byte Spill
	cmovll	%eax, %r12d
	movq	16(%rbx), %rdi
	xorl	%esi, %esi
	movl	$10, %edx
	callq	__isoc23_strtol
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%eax, %edi
	callq	ldexp@PLT
	cvttsd2si	%xmm0, %r14d
	shlb	$3, %r15b
	movl	%r12d, -88(%rbp)                # 4-byte Spill
                                        # kill: def $r12d killed $r12d def $r12
	movl	%r15d, %ecx
	shll	%cl, %r12d
	movl	$.L.str.2, %edi
	movl	%r12d, %esi
	movl	%r14d, %edx
	xorl	%eax, %eax
	callq	printf
	leaq	15(,%r12,4), %rax
	andq	$-16, %rax
	movq	%rsp, %r15
	subq	%rax, %r15
	movq	%r15, %rsp
	leaq	15(,%r14,4), %rax
	andq	$-16, %rax
	movq	%rsp, %rbx
	subq	%rax, %rbx
	movq	%rbx, %rsp
	movq	%rsp, %r13
	subq	%rax, %r13
	movq	%r13, %rsp
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movq	%r12, -112(%rbp)                # 8-byte Spill
	movslq	%r12d, %r12
	movq	%r14, -48(%rbp)                 # 8-byte Spill
	testl	%r14d, %r14d
	jle	.LBB2_6
# %bb.2:                                # %.lr.ph.preheader
	xorl	%r14d, %r14d
.LBB2_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpq	%r12, %r14
	jge	.LBB2_5
# %bb.4:                                #   in Loop: Header=BB2_3 Depth=1
	movl	$0, (%r15,%r14,4)
.LBB2_5:                                #   in Loop: Header=BB2_3 Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	mulss	.LCPI2_1(%rip), %xmm0
	movss	%xmm0, (%r13,%r14,4)
	incq	%r14
	cmpq	%r14, -48(%rbp)                 # 8-byte Folded Reload
	jne	.LBB2_3
.LBB2_6:                                # %._crit_edge
	leaq	-104(%rbp), %rdi
	callq	hipEventCreate
	leaq	-64(%rbp), %rdi
	callq	hipEventCreate
	movl	$0, -92(%rbp)
	movslq	-48(%rbp), %r14                 # 4-byte Folded Reload
	shlq	$2, %r14
	leaq	-80(%rbp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	-72(%rbp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	shlq	$2, %r12
	leaq	-56(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	-56(%rbp), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-80(%rbp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-72(%rbp), %rax
	movq	(%rax), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-104(%rbp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpl	$256, -84(%rbp)                 # 4-byte Folded Reload
                                        # imm = 0x100
	movl	$1, %eax
	movl	$256, %edi                      # imm = 0x100
	cmovlq	%rax, %rdi
	btsq	$32, %rdi
	movl	-88(%rbp), %edx                 # 4-byte Reload
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	-112(%rbp), %r14                # 8-byte Reload
	jne	.LBB2_8
# %bb.7:
	movq	-56(%rbp), %rdi
	movq	-80(%rbp), %rsi
	movq	-72(%rbp), %rdx
	movl	%r14d, %ecx
	movq	-48(%rbp), %r8                  # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z20__device_stub__montePiPfS0_ii
.LBB2_8:
	movq	-64(%rbp), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-56(%rbp), %rsi
	movq	%r15, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%r14d, %r14d
	jle	.LBB2_9
# %bb.12:                               # %.lr.ph70.preheader
	xorl	%ecx, %ecx
	xorl	%eax, %eax
.LBB2_13:                               # %.lr.ph70
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r15,%rcx,4), %edx
	testl	%edx, %edx
	cmovlel	%ebx, %edx
	addl	%edx, %eax
	incq	%rcx
	cmpq	%rcx, %r14
	jne	.LBB2_13
# %bb.10:                               # %._crit_edge71.loopexit
	cvtsi2ss	%eax, %xmm0
	jmp	.LBB2_11
.LBB2_9:
	xorpd	%xmm0, %xmm0
.LBB2_11:                               # %._crit_edge71
	cvtsi2ssl	-48(%rbp), %xmm1        # 4-byte Folded Reload
	divss	%xmm1, %xmm0
	mulss	.LCPI2_2(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	-64(%rbp), %rdi
	callq	hipEventSynchronize
	movq	-104(%rbp), %rsi
	movq	-64(%rbp), %rdx
	leaq	-92(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movss	(%rbx), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI2_3(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movq	-56(%rbp), %rdi
	callq	hipFree
	movq	-80(%rbp), %rdi
	callq	hipFree
	movq	-72(%rbp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.LBB2_14:
	.cfi_def_cfa %rbp, 16
	callq	_Z10printerrorv
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5montePiPfS0_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5montePiPfS0_ii,@object       # @_Z5montePiPfS0_ii
	.section	.rodata,"a",@progbits
	.globl	_Z5montePiPfS0_ii
	.p2align	3, 0x0
_Z5montePiPfS0_ii:
	.quad	_Z20__device_stub__montePiPfS0_ii
	.size	_Z5montePiPfS0_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Invalid Arguments\n"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Correct Form: ./monte [# threads] [# points]\n"
	.size	.L.str.1, 46

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"(Threads: %d) (N: %d)\n"
	.size	.L.str.2, 23

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Estimation of Pi: %1.6f\n"
	.size	.L.str.3, 25

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Time in Kernel: %1.10f\n\n"
	.size	.L.str.4, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5montePiPfS0_ii"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__montePiPfS0_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5montePiPfS0_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5montePiPfS0_ii       ; -- Begin function _Z5montePiPfS0_ii
	.globl	_Z5montePiPfS0_ii
	.p2align	8
	.type	_Z5montePiPfS0_ii,@function
_Z5montePiPfS0_ii:                      ; @_Z5montePiPfS0_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s2, 31
	s_ashr_i32 s8, s3, 31
	s_add_i32 s5, s2, s4
	s_add_i32 s9, s3, s8
	s_xor_b32 s5, s5, s4
	s_xor_b32 s9, s9, s8
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s7, 0, s5
	s_xor_b32 s4, s8, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s6, v1
	s_mul_i32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s6, s7
	s_add_i32 s6, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s9, s6
	s_mul_i32 s7, s6, s5
	s_add_i32 s8, s6, 1
	s_sub_i32 s7, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s9, s7, s5
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s6, s8, s6
	s_cselect_b32 s7, s9, s7
	s_add_i32 s8, s6, 1
	s_cmp_ge_u32 s7, s5
	s_cselect_b32 s5, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s5, s4
	s_sub_i32 s10, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s10, 0
	s_cbranch_scc1 .LBB0_6
; %bb.1:                                ; %.lr.ph
	s_load_b32 s4, s[0:1], 0x2c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_load_b64 s[8:9], s[0:1], 0x10
	s_add_i32 s1, s10, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 0x3e76c4e1
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[1:2]
	v_add_co_u32 v7, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b32 v0, v[7:8], off
	global_load_b32 v2, v[5:6], off
	s_waitcnt vmcnt(1)
	v_frexp_mant_f32_e64 v5, |v0|
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v6, |v2|
	v_frexp_exp_i32_f32_e32 v20, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v6
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 1, s0
	v_ldexp_f32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v6, v6, v8
	v_dual_add_f32 v7, 1.0, v5 :: v_dual_add_f32 v8, 1.0, v6
	v_dual_add_f32 v11, -1.0, v5 :: v_dual_add_f32 v12, -1.0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v7
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v13, v11, v9 :: v_dual_mul_f32 v14, v12, v10
	v_add_f32_e32 v15, -1.0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v17, -1.0, v8 :: v_dual_mul_f32 v16, v7, v13
	v_dual_mul_f32 v18, v8, v14 :: v_dual_sub_f32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v6, v6, v17
	v_fma_f32 v7, v13, v7, -v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v14, v8, -v18
	v_dual_fmac_f32 v7, v13, v5 :: v_dual_fmac_f32 v8, v14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v5, v16, v7 :: v_dual_add_f32 v6, v18, v8
	v_dual_sub_f32 v15, v11, v5 :: v_dual_sub_f32 v16, v5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v6, v18
	v_sub_f32_e32 v17, v12, v6
	v_dual_sub_f32 v11, v11, v15 :: v_dual_sub_f32 v8, v18, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v16, v7
	v_sub_f32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v7, v5
	v_add_f32_e32 v5, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v9, v5
	v_add_f32_e32 v7, v13, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v12, v17 :: v_dual_mul_f32 v11, v7, v7
	v_sub_f32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v6
	v_add_f32_e32 v6, v17, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v10, v6
	v_add_f32_e32 v8, v14, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v8, v14 :: v_dual_sub_f32 v9, v7, v13
	v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v5, v5, v9
	v_fma_f32 v10, v7, v7, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v14, v6, v6 :: v_dual_mul_f32 v9, v8, v8
	v_add_f32_e32 v12, v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, v8, v8, -v9
	v_dual_fmac_f32 v10, v7, v12 :: v_dual_fmac_f32 v13, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v9, v13
	v_dual_add_f32 v12, v11, v10 :: v_dual_sub_f32 v9, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, s4, v12, 0x3e91f4c4 :: v_dual_fmaak_f32 v16, s4, v14, 0x3e91f4c4
	v_sub_f32_e32 v11, v12, v11
	v_sub_f32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, v12, v15, 0x3ecccdef :: v_dual_fmaak_f32 v16, v14, v16, 0x3ecccdef
	v_sub_f32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v17, v12, v15 :: v_dual_mul_f32 v18, v14, v16
	v_fma_f32 v11, v12, v15, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, v14, v16, -v18
	v_fmac_f32_e32 v11, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v13, v9, v16
	v_mul_f32_e32 v16, v7, v12
	v_frexp_exp_i32_f32_e32 v15, v0
	v_add_f32_e32 v19, v17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v23, v12, v7, -v16
	v_add_f32_e32 v24, 0x3f2aaaaa, v19
	v_add_f32_e32 v22, v18, v13
	v_sub_f32_e32 v17, v19, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v23, v12, v5
	v_ldexp_f32 v5, v5, 1
	v_sub_f32_e32 v18, v22, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v26, 0x3f2aaaaa, v22 :: v_dual_sub_f32 v11, v11, v17
	v_add_f32_e32 v17, 0xbf2aaaaa, v24
	v_dual_fmac_f32 v23, v10, v7 :: v_dual_sub_f32 v12, v13, v18
	v_mul_f32_e32 v21, v8, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f32_e32 v13, 0xbf2aaaaa, v26
	v_add_f32_e32 v11, 0x31739010, v11
	v_dual_sub_f32 v17, v19, v17 :: v_dual_add_f32 v10, 0x31739010, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v25, v14, v8, -v21
	v_sub_f32_e32 v12, v22, v13
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v15, vcc_lo
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v25, v14, v6
	v_subrev_co_ci_u32_e64 v14, vcc_lo, 0, v20, s0
	v_ldexp_f32 v6, v6, 1
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v0|
	v_fmac_f32_e32 v25, v9, v8
	v_add_f32_e32 v9, v10, v12
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v26, v9
	v_dual_add_f32 v11, v11, v17 :: v_dual_sub_f32 v20, v26, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v12, v24, v11 :: v_dual_add_f32 v17, v21, v25
	v_sub_f32_e32 v18, v24, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v22, v17, v15
	v_add_f32_e32 v9, v9, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v11, v18
	v_fma_f32 v20, v17, v15, -v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v20, v17, v9
	v_add_f32_e32 v10, v16, v23
	v_cvt_f32_i32_e32 v9, v14
	v_mul_f32_e32 v19, v10, v12
	v_sub_f32_e32 v16, v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, v10, v12, -v19
	v_sub_f32_e32 v16, v23, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v10, v11
	v_cvt_f32_i32_e32 v10, v13
	v_fmac_f32_e32 v18, v16, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v12, 0x3f317218, v10 :: v_dual_sub_f32 v21, v17, v21
	v_sub_f32_e32 v11, v25, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v20, v11, v15
	v_fma_f32 v15, 0x3f317218, v10, -v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v22, v20 :: v_dual_fmac_f32 v15, 0xb102e308, v10
	v_sub_f32_e32 v21, v14, v22
	v_add_f32_e32 v11, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v11, v19
	v_sub_f32_e32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v18, v20, v21
	v_dual_add_f32 v16, v7, v11 :: v_dual_add_f32 v5, v5, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v6, v18
	v_add_f32_e32 v19, v8, v14
	v_dual_sub_f32 v8, v19, v8 :: v_dual_mul_f32 v13, 0x3f317218, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v14, v8
	v_dual_add_f32 v6, v6, v8 :: v_dual_sub_f32 v7, v16, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v19, v6
	v_sub_f32_e32 v7, v11, v7
	v_fma_f32 v11, 0x3f317218, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v7, v12, v15
	v_add_f32_e32 v8, v16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v7, v12
	v_add_f32_e32 v14, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v18, v14, v7 :: v_dual_fmac_f32 v11, 0xb102e308, v9
	v_dual_sub_f32 v12, v15, v12 :: v_dual_sub_f32 v19, v10, v19
	v_sub_f32_e32 v15, v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v8, v18
	v_sub_f32_e32 v6, v6, v19
	v_add_f32_e32 v9, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v9, v10
	v_sub_f32_e32 v13, v9, v13
	v_sub_f32_e32 v16, v17, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v13
	v_sub_f32_e32 v13, v14, v18
	v_sub_f32_e32 v5, v5, v15
	v_sub_f32_e32 v15, v17, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v16 :: v_dual_sub_f32 v7, v7, v13
	v_dual_add_f32 v7, v8, v7 :: v_dual_add_f32 v8, v11, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v9, v9, v15
	v_add_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v9, v8, v9
	v_add_f32_e32 v13, v12, v5
	v_dual_sub_f32 v10, v13, v12 :: v_dual_sub_f32 v15, v8, v11
	v_add_f32_e32 v7, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v13, v10 :: v_dual_sub_f32 v8, v8, v15
	v_add_f32_e32 v16, v14, v7
	v_sub_f32_e32 v6, v6, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v12, v13
	v_dual_sub_f32 v8, v11, v8 :: v_dual_sub_f32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v10, v17, v9 :: v_dual_sub_f32 v13, v16, v14
	v_add_f32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v5, v12
	v_sub_f32_e32 v11, v10, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v9, v11
	v_add_f32_e32 v6, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v10, v6
	v_sub_f32_e32 v10, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v7, v7, v13
	v_mul_f32_e32 v13, 0, v8
	v_add_f32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, 2.0, v6
	v_add_f32_e32 v7, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v7, v16 :: v_dual_mul_f32 v12, 0, v7
	v_sub_f32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v8, v8 :: v_dual_fmac_f32 v12, 2.0, v5
	v_fma_f32 v5, v8, 2.0, -v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v13
	v_dual_add_f32 v8, v9, v5 :: v_dual_add_f32 v11, v7, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, v7, 2.0, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	v_add_f32_e32 v6, v7, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v11, v6
	v_cndmask_b32_e32 v10, v7, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_cndmask_b32_e32 v12, v8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_dual_sub_f32 v8, v8, v9 :: v_dual_sub_f32 v7, v7, v11
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
	v_dual_sub_f32 v6, v6, v7 :: v_dual_sub_f32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v10, v13
	v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_dual_mul_f32 v17, 0x3fb8aa3b, v15 :: v_dual_sub_f32 v16, v12, v14
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v19, 0x3fb8aa3b, v15, -v17
	v_mul_f32_e32 v18, 0x3fb8aa3b, v16
	v_rndne_f32_e32 v20, v17
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	v_fmac_f32_e32 v19, 0x32a5705f, v15
	v_fma_f32 v21, 0x3fb8aa3b, v16, -v18
	v_rndne_f32_e32 v22, v18
	v_sub_f32_e32 v17, v17, v20
	v_cvt_i32_f32_e32 v7, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v6, v13, v6 :: v_dual_fmac_f32 v21, 0x32a5705f, v16
	v_dual_sub_f32 v18, v18, v22 :: v_dual_add_f32 v17, v17, v19
	v_cvt_i32_f32_e32 v8, v22
	v_add_f32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v18, v18, v21
	v_exp_f32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v9, v18
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v11, v7
	v_ldexp_f32 v8, v9, v8
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v6, v7, v6, v7
	v_cndmask_b32_e32 v8, 0x7f800000, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	v_fma_f32 v5, v8, v5, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v6, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v8
	v_cndmask_b32_e64 v6, 0x7f800000, |v6|, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	v_cndmask_b32_e32 v0, 0, v6, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v5, vcc_lo
	v_add_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, 1.0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 1, v0
	global_store_b32 v[3:4], v0, off
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v1, s2, v1
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc0 .LBB0_2
.LBB0_6:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5montePiPfS0_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5montePiPfS0_ii, .Lfunc_end0-_Z5montePiPfS0_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2184
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5montePiPfS0_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z5montePiPfS0_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
