 
#include <time.h>
#include <stdlib.h>
#include <stdio.h>

#define NUMTHREADS 32
#define N 129

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

void dyadic(int* res, int* a, int* b, int n) {
	for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			res[i+N*j] = a[j]*b[i];
		}
	}
}

__global__ void dyadic_gpu(int* res, int* a, int* b, int n) {
    int x = threadIdx.x + blockDim.x*blockIdx.x;
    int y = threadIdx.y + blockDim.y*blockIdx.y;

    if(x < n && y < n)
        res[x+n*y] = a[y]*b[x];
}

int main() {
	srand(time(NULL));
	int* a = (int*)malloc(N*sizeof(int));
 	int* b = (int*)malloc(N*sizeof(int));

 	for(int i=0; i<N; i++) {
 		a[i] = rand()%100;
 		b[i] = rand()%100;
 	}

 	int* res = (int*)malloc(N*N*sizeof(int));
 	dyadic(res, a, b, N);
	
	// CUDA stuff
        int* d_a, *d_b, *d_res;
        gpuErrchk(cudaMalloc((void**)&d_a, N*sizeof(int)));
        gpuErrchk(cudaMalloc((void**)&d_b, N*sizeof(int)));
        gpuErrchk(cudaMalloc((void**)&d_res, N*N*sizeof(int)));
        gpuErrchk(cudaMemcpy(d_a, a, N*sizeof(int), cudaMemcpyHostToDevice));
        gpuErrchk(cudaMemcpy(d_b, b, N*sizeof(int), cudaMemcpyHostToDevice));
        
        dim3 threads(16, 16, 1);
        dim3 grid(ceil((float)N/(float)16), ceil((float)N/(float)16), 1);
//     (N+threads.x-1)/threads.x    
        cudaMemset(d_res, 0,N*N*sizeof(int)); 
        dyadic_gpu<<<grid,threads>>>(d_res, d_a, d_b, N);
        gpuErrchk(cudaGetLastError());
        int* resgpu = (int*)malloc(N*N*sizeof(int));
        gpuErrchk(cudaMemcpy(resgpu, d_res, N*N*sizeof(int), cudaMemcpyDeviceToHost));

 	for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			printf("%d ", res[i+N*j]);
		}
		printf("\n");
	}
	printf("-----\n");
        for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			printf("%d ", resgpu[i+N*j]);
		}
		printf("\n");
	}
	printf("\ngrid size: %d, %d\n", grid.x, grid.y);
}

	.file	"tmpxft_003b1a61_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z6dyadicPiS_S_i
	.type	_Z6dyadicPiS_S_i, @function
_Z6dyadicPiS_S_i:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L13:
	leaq	(%rdi,%rax,4), %r8
	xorl	%ecx, %ecx
.L14:
	movl	(%rsi,%rcx,4), %r9d
	imull	(%rdx,%rax,4), %r9d
	incq	%rcx
	addq	$516, %r8
	movl	%r9d, -516(%r8)
	cmpq	$129, %rcx
	jne	.L14
	incq	%rax
	cmpq	$129, %rax
	jne	.L13
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6dyadicPiS_S_i, .-_Z6dyadicPiS_S_i
	.globl	_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i
	.type	_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10dyadic_gpuPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L17:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i
	.globl	_Z10dyadic_gpuPiS_S_i
	.type	_Z10dyadic_gpuPiS_S_i, @function
_Z10dyadic_gpuPiS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z10dyadic_gpuPiS_S_i, .-_Z10dyadic_gpuPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/blacksph3re/hops/master/lab4/main.cu"
.LC2:
	.string	"%d "
.LC3:
	.string	"\n"
.LC4:
	.string	"-----\n"
.LC5:
	.string	"\ngrid size: %d, %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$100, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movl	$516, %edi
	call	malloc@PLT
	movl	$516, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rax, %rbp
.L23:
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, (%r12,%rbx)
	call	rand@PLT
	cltd
	idivl	%r13d
	movl	%edx, 0(%rbp,%rbx)
	addq	$4, %rbx
	cmpq	$516, %rbx
	jne	.L23
	movl	$66564, %edi
	leaq	.LC1(%rip), %rbx
	call	malloc@PLT
	movl	$129, %ecx
	movq	%rbp, %rdx
	movq	%r12, %rsi
	movq	%rax, %rdi
	movq	%rax, %r13
	call	_Z6dyadicPiS_S_i
	leaq	8(%rsp), %rdi
	movl	$516, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$50, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	16(%rsp), %rdi
	movl	$516, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$51, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	24(%rsp), %rdi
	movl	$66564, %esi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$52, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$516, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$53, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$516, %edx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$54, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$68719476752, %rax
	movl	$66564, %edx
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	call	cudaMemset@PLT
	movl	40(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdx
	movl	$1, %esi
	movabsq	$38654705673, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$129, %ecx
	movq	24(%rsp), %rdi
	call	_Z35__device_stub__Z10dyadic_gpuPiS_S_iPiS_S_i
.L24:
	call	cudaGetLastError@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$61, %edx
	movl	%eax, %edi
	leaq	.LC2(%rip), %r12
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	$66564, %edi
	call	malloc@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$66564, %edx
	movq	%rax, %rdi
	movq	%rax, %rbp
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	xorl	%ebx, %ebx
	movl	%eax, %edi
	movl	$63, %edx
	call	_Z9gpuAssert9cudaErrorPKcib
.L25:
	leaq	0(%r13,%rbx,4), %r15
	movl	$129, %r14d
.L26:
	movl	(%r15), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$516, %r15
	call	__printf_chk@PLT
	decl	%r14d
	jne	.L26
	leaq	.LC3(%rip), %r14
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	movq	%r14, %rsi
	call	__printf_chk@PLT
	cmpq	$129, %rbx
	jne	.L25
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
.L28:
	leaq	0(%rbp,%rbx,4), %r15
	movl	$129, %r13d
.L29:
	movl	(%r15), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$516, %r15
	call	__printf_chk@PLT
	decl	%r13d
	jne	.L29
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$129, %rbx
	jne	.L28
	xorl	%eax, %eax
	movl	$9, %ecx
	movl	$9, %edx
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z10dyadic_gpuPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10dyadic_gpuPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

 

#include <hip/hip_runtime.h>
#include <time.h>
#include <stdlib.h>
#include <stdio.h>

#define NUMTHREADS 32
#define N 129

#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

void dyadic(int* res, int* a, int* b, int n) {
	for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			res[i+N*j] = a[j]*b[i];
		}
	}
}

__global__ void dyadic_gpu(int* res, int* a, int* b, int n) {
    int x = threadIdx.x + blockDim.x*blockIdx.x;
    int y = threadIdx.y + blockDim.y*blockIdx.y;

    if(x < n && y < n)
        res[x+n*y] = a[y]*b[x];
}

int main() {
	srand(time(NULL));
	int* a = (int*)malloc(N*sizeof(int));
 	int* b = (int*)malloc(N*sizeof(int));

 	for(int i=0; i<N; i++) {
 		a[i] = rand()%100;
 		b[i] = rand()%100;
 	}

 	int* res = (int*)malloc(N*N*sizeof(int));
 	dyadic(res, a, b, N);
	
	// CUDA stuff
        int* d_a, *d_b, *d_res;
        gpuErrchk(hipMalloc((void**)&d_a, N*sizeof(int)));
        gpuErrchk(hipMalloc((void**)&d_b, N*sizeof(int)));
        gpuErrchk(hipMalloc((void**)&d_res, N*N*sizeof(int)));
        gpuErrchk(hipMemcpy(d_a, a, N*sizeof(int), hipMemcpyHostToDevice));
        gpuErrchk(hipMemcpy(d_b, b, N*sizeof(int), hipMemcpyHostToDevice));
        
        dim3 threads(16, 16, 1);
        dim3 grid(ceil((float)N/(float)16), ceil((float)N/(float)16), 1);
//     (N+threads.x-1)/threads.x    
        hipMemset(d_res, 0,N*N*sizeof(int)); 
        dyadic_gpu<<<grid,threads>>>(d_res, d_a, d_b, N);
        gpuErrchk(hipGetLastError());
        int* resgpu = (int*)malloc(N*N*sizeof(int));
        gpuErrchk(hipMemcpy(resgpu, d_res, N*N*sizeof(int), hipMemcpyDeviceToHost));

 	for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			printf("%d ", res[i+N*j]);
		}
		printf("\n");
	}
	printf("-----\n");
        for(int i=0; i<N; i++) {
		for(int j=0; j<N; j++) {
			printf("%d ", resgpu[i+N*j]);
		}
		printf("\n");
	}
	printf("\ngrid size: %d, %d\n", grid.x, grid.y);
}

	.text
	.file	"main.hip"
	.globl	_Z6dyadicPiS_S_i                # -- Begin function _Z6dyadicPiS_S_i
	.type	_Z6dyadicPiS_S_i,@function
_Z6dyadicPiS_S_i:                       # @_Z6dyadicPiS_S_i
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
.LBB0_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	movq	%rdi, %rcx
	xorl	%r8d, %r8d
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rdx,%rax,4), %r9d
	imull	(%rsi,%r8,4), %r9d
	movl	%r9d, (%rcx)
	incq	%r8
	addq	$516, %rcx                      # imm = 0x204
	cmpq	$129, %r8
	jne	.LBB0_2
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rax
	addq	$4, %rdi
	cmpq	$129, %rax
	jne	.LBB0_1
# %bb.4:
	retq
.Lfunc_end0:
	.size	_Z6dyadicPiS_S_i, .Lfunc_end0-_Z6dyadicPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__dyadic_gpuPiS_S_i # -- Begin function _Z25__device_stub__dyadic_gpuPiS_S_i
	.type	_Z25__device_stub__dyadic_gpuPiS_S_i,@function
_Z25__device_stub__dyadic_gpuPiS_S_i:   # @_Z25__device_stub__dyadic_gpuPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10dyadic_gpuPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__dyadic_gpuPiS_S_i, .Lfunc_end1-_Z25__device_stub__dyadic_gpuPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$516, %edi                      # imm = 0x204
	callq	malloc
	movq	%rax, %r15
	movl	$516, %edi                      # imm = 0x204
	callq	malloc
	movq	%rax, %r14
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r15,%rbx,4)
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%rbx,4)
	incq	%rbx
	cmpq	$129, %rbx
	jne	.LBB2_1
# %bb.2:
	movl	$66564, %edi                    # imm = 0x10404
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
	movq	%rbx, %rcx
.LBB2_3:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	movl	(%r14,%rax,4), %edx
	movq	%rcx, %rsi
	xorl	%edi, %edi
.LBB2_4:                                #   Parent Loop BB2_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r15,%rdi,4), %r8d
	imull	%edx, %r8d
	movl	%r8d, (%rsi)
	incq	%rdi
	addq	$516, %rsi                      # imm = 0x204
	cmpq	$129, %rdi
	jne	.LBB2_4
# %bb.5:                                #   in Loop: Header=BB2_3 Depth=1
	incq	%rax
	addq	$4, %rcx
	cmpq	$129, %rax
	jne	.LBB2_3
# %bb.6:                                # %_Z6dyadicPiS_S_i.exit
	leaq	24(%rsp), %rdi
	movl	$516, %esi                      # imm = 0x204
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	leaq	16(%rsp), %rdi
	movl	$516, %esi                      # imm = 0x204
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit38
	leaq	8(%rsp), %rdi
	movl	$66564, %esi                    # imm = 0x10404
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit40
	movq	24(%rsp), %rdi
	movl	$516, %edx                      # imm = 0x204
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_14
# %bb.15:                               # %_Z9gpuAssert10hipError_tPKcib.exit42
	movq	16(%rsp), %rdi
	movl	$516, %edx                      # imm = 0x204
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_16
# %bb.17:                               # %_Z9gpuAssert10hipError_tPKcib.exit44
	movq	8(%rsp), %rdi
	movl	$66564, %edx                    # imm = 0x10404
	xorl	%esi, %esi
	callq	hipMemset
	movabsq	$38654705673, %rdi              # imm = 0x900000009
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_19
# %bb.18:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$129, %ecx
	callq	_Z25__device_stub__dyadic_gpuPiS_S_i
.LBB2_19:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB2_20
# %bb.21:                               # %_Z9gpuAssert10hipError_tPKcib.exit46
	movl	$66564, %edi                    # imm = 0x10404
	callq	malloc
	movq	%rax, %r14
	movq	8(%rsp), %rsi
	movl	$66564, %edx                    # imm = 0x10404
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_31
# %bb.22:                               # %.preheader51.preheader
	xorl	%r15d, %r15d
.LBB2_23:                               # %.preheader51
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_24 Depth 2
	movq	$-66564, %r12                   # imm = 0xFFFEFBFC
.LBB2_24:                               #   Parent Loop BB2_23 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	66564(%rbx,%r12), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$516, %r12                      # imm = 0x204
	jne	.LBB2_24
# %bb.25:                               # %_Z9gpuAssert10hipError_tPKcib.exit48
                                        #   in Loop: Header=BB2_23 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	addq	$4, %rbx
	cmpq	$129, %r15
	jne	.LBB2_23
# %bb.26:
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
.LBB2_27:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_28 Depth 2
	movq	$-66564, %r15                   # imm = 0xFFFEFBFC
.LBB2_28:                               #   Parent Loop BB2_27 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	66564(%r14,%r15), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	addq	$516, %r15                      # imm = 0x204
	jne	.LBB2_28
# %bb.29:                               #   in Loop: Header=BB2_27 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%rbx
	addq	$4, %r14
	cmpq	$129, %rbx
	jne	.LBB2_27
# %bb.30:
	movl	$.L.str.4, %edi
	movl	$9, %esi
	movl	$9, %edx
	xorl	%eax, %eax
	callq	printf
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_7:
	.cfi_def_cfa_offset 80
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$52, %r8d
	jmp	.LBB2_8
.LBB2_10:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$53, %r8d
	jmp	.LBB2_8
.LBB2_12:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$54, %r8d
	jmp	.LBB2_8
.LBB2_14:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$55, %r8d
	jmp	.LBB2_8
.LBB2_16:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$56, %r8d
	jmp	.LBB2_8
.LBB2_20:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$63, %r8d
	jmp	.LBB2_8
.LBB2_31:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$65, %r8d
.LBB2_8:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10dyadic_gpuPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10dyadic_gpuPiS_S_i,@object   # @_Z10dyadic_gpuPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z10dyadic_gpuPiS_S_i
	.p2align	3, 0x0
_Z10dyadic_gpuPiS_S_i:
	.quad	_Z25__device_stub__dyadic_gpuPiS_S_i
	.size	_Z10dyadic_gpuPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/blacksph3re/hops/master/lab4/main.hip"
	.size	.L.str, 100

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\ngrid size: %d, %d\n"
	.size	.L.str.4, 20

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.5, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10dyadic_gpuPiS_S_i"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"-----"
	.size	.Lstr, 6

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__dyadic_gpuPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10dyadic_gpuPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10dyadic_gpuPiS_S_i   ; -- Begin function _Z10dyadic_gpuPiS_S_i
	.globl	_Z10dyadic_gpuPiS_S_i
	.p2align	8
	.type	_Z10dyadic_gpuPiS_S_i,@function
_Z10dyadic_gpuPiS_S_i:                  ; @_Z10dyadic_gpuPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s4, v[4:5]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v1, v0, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v7, v[3:4], off
	global_load_b32 v5, v[5:6], off
	v_mad_u64_u32 v[3:4], null, v2, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v2, v5, v7
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10dyadic_gpuPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10dyadic_gpuPiS_S_i, .Lfunc_end0-_Z10dyadic_gpuPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10dyadic_gpuPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10dyadic_gpuPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
