#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <time.h>


#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)


__global__ void mergeSort(int *d1, int *d2, int width, int n){

	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int n_threads = gridDim.x * blockDim.x;

	int start = tid * width;
	int middle = min(start + (width >> 1), n);
	int end = min(start + width, n);


	// each thread may sort more than one tile (or zero tiles if start >= n)
	while(start < n){
		int a = start;
	    int b = middle;

	    //printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);

	    // merge
	    for (int k = start; k < end; k++) {
	        if (a < middle && (b >= end || d1[a] < d1[b])) {
	            d2[k] = d1[a];
	            a += 1;
	        } else {
	            d2[k] = d1[b];
	            b += 1;
	        }
	    }

	    start += n_threads * width;
	    middle = min(start + (width >> 1), n);
		end = min(start + width, n);
	}

}

int main(){
	
	int n;
	n = 100000;
	int size = n * sizeof(int);

	int *h_in = (int *)malloc(size);
	int *h_out = (int *)malloc(size);

	int *d_in, *d_out;

	for (int i=0; i<n; i++){
		h_in[i] = 100000 - i;
	}

	cudaMalloc((void **)&d_in, size);
	cudaMalloc((void **)&d_out, size);

	cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);

	int *d1 = d_in;
	int *d2 = d_out;

	clock_t start_time = clock();
	for (int width = 2; width < (n << 1); width <<= 1){
		mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
		cudaThreadSynchronize();

		d1 = d1 == d_in ? d_out : d_in;
        d2 = d2 == d_in ? d_out : d_in;

	}
	clock_t end_time = clock();

	cudaMemcpy(h_out, d1, size, cudaMemcpyDeviceToHost);

	for(int i=0; i<n; i++)
		printf("%d\n", h_out[i]);

	printf("\n");

	double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
	printf("total time: %f\n", total_time);

	return 0;
}
	.file	"tmpxft_0023fd18_00000000-6_merge_sort.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
	.type	_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, @function
_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9mergeSortPiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii, .-_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
	.globl	_Z9mergeSortPiS_ii
	.type	_Z9mergeSortPiS_ii, @function
_Z9mergeSortPiS_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
	.cfi_endproc
.LFE2053:
	.size	_Z9mergeSortPiS_ii, .-_Z9mergeSortPiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d\n"
.LC1:
	.string	"\n"
.LC3:
	.string	"total time: %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$400000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$400000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movl	$100000, %ecx
	movq	%rax, %rbp
	xorl	%eax, %eax
.L9:
	movl	%ecx, %edx
	subl	%eax, %edx
	movl	%edx, (%rbx,%rax,4)
	incq	%rax
	cmpq	$100000, %rax
	jne	.L9
	movq	%rsp, %rdi
	movl	$400000, %esi
	movl	$17, %r14d
	movl	$2, %r15d
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$400000, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$400000, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rbx
	movq	8(%rsp), %r12
	call	clock@PLT
	movq	%rax, %r13
.L13:
	movl	$134217729, %edx
	movl	$536870913, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$5, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movl	$100000, %ecx
	movl	%r15d, %edx
	movq	%r12, %rsi
	movq	%rbx, %rdi
	call	_Z32__device_stub__Z9mergeSortPiS_iiPiS_ii
.L10:
	call	cudaThreadSynchronize@PLT
	movq	(%rsp), %rax
	cmpq	%rbx, %rax
	jne	.L16
	movq	8(%rsp), %rbx
	jmp	.L11
.L16:
	movq	%rax, %rbx
.L11:
	cmpq	%r12, %rax
	jne	.L17
	movq	8(%rsp), %r12
	jmp	.L12
.L17:
	movq	%rax, %r12
.L12:
	addl	%r15d, %r15d
	decl	%r14d
	jne	.L13
	call	clock@PLT
	movq	%rbx, %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$400000, %edx
	movq	%rax, %r12
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %r14
.L14:
	movl	0(%rbp,%rbx,4), %edx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$100000, %rbx
	jne	.L14
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	subq	%r13, %r12
	call	__printf_chk@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtsi2sdq	%r12, %xmm0
	divsd	.LC2(%rip), %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z9mergeSortPiS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9mergeSortPiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>

#include <time.h>


#define GRID_SIZE 8
#define BLOCK_SIZE 32
#define min(a, b) (a < b ? a : b)


__global__ void mergeSort(int *d1, int *d2, int width, int n){

	int tid = blockIdx.x * blockDim.x + threadIdx.x;
	int n_threads = gridDim.x * blockDim.x;

	int start = tid * width;
	int middle = min(start + (width >> 1), n);
	int end = min(start + width, n);


	// each thread may sort more than one tile (or zero tiles if start >= n)
	while(start < n){
		int a = start;
	    int b = middle;

	    //printf("thread id %d start %d end %d middle %d width %d\n", tid, start, end, middle, width);

	    // merge
	    for (int k = start; k < end; k++) {
	        if (a < middle && (b >= end || d1[a] < d1[b])) {
	            d2[k] = d1[a];
	            a += 1;
	        } else {
	            d2[k] = d1[b];
	            b += 1;
	        }
	    }

	    start += n_threads * width;
	    middle = min(start + (width >> 1), n);
		end = min(start + width, n);
	}

}

int main(){
	
	int n;
	n = 100000;
	int size = n * sizeof(int);

	int *h_in = (int *)malloc(size);
	int *h_out = (int *)malloc(size);

	int *d_in, *d_out;

	for (int i=0; i<n; i++){
		h_in[i] = 100000 - i;
	}

	hipMalloc((void **)&d_in, size);
	hipMalloc((void **)&d_out, size);

	hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);

	int *d1 = d_in;
	int *d2 = d_out;

	clock_t start_time = clock();
	for (int width = 2; width < (n << 1); width <<= 1){
		mergeSort <<<GRID_SIZE, BLOCK_SIZE>>>(d1, d2, width, n);
		hipDeviceSynchronize();

		d1 = d1 == d_in ? d_out : d_in;
        d2 = d2 == d_in ? d_out : d_in;

	}
	clock_t end_time = clock();

	hipMemcpy(h_out, d1, size, hipMemcpyDeviceToHost);

	for(int i=0; i<n; i++)
		printf("%d\n", h_out[i]);

	printf("\n");

	double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
	printf("total time: %f\n", total_time);

	return 0;
}
	.text
	.file	"merge_sort.hip"
	.globl	_Z24__device_stub__mergeSortPiS_ii # -- Begin function _Z24__device_stub__mergeSortPiS_ii
	.type	_Z24__device_stub__mergeSortPiS_ii,@function
_Z24__device_stub__mergeSortPiS_ii:     # @_Z24__device_stub__mergeSortPiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9mergeSortPiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__mergeSortPiS_ii, .Lfunc_end0-_Z24__device_stub__mergeSortPiS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, %r14
	movl	$400000, %edi                   # imm = 0x61A80
	callq	malloc
	movq	%rax, %rbx
	movl	$100000, %eax                   # imm = 0x186A0
	movq	%r14, %rcx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rcx)
	addq	$4, %rcx
	decq	%rax
	jne	.LBB1_1
# %bb.2:
	movabsq	$4294967304, %r15               # imm = 0x100000008
	leaq	16(%rsp), %r12
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$400000, %esi                   # imm = 0x61A80
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %r12
	movq	(%r13), %r14
	movl	$2, %ebp
	callq	clock
	movq	%rax, (%rsp)                    # 8-byte Spill
	leaq	24(%r15), %r13
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movl	$100000, %ecx                   # imm = 0x186A0
	callq	_Z24__device_stub__mergeSortPiS_ii
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rax
	cmpq	%rax, %r12
	movq	8(%rsp), %rcx
	movq	%rax, %r12
	cmoveq	%rcx, %r12
	cmpq	%rax, %r14
	cmoveq	%rcx, %rax
	addl	%ebp, %ebp
	movq	%rax, %r14
	cmpl	$200000, %ebp                   # imm = 0x30D40
	jl	.LBB1_3
# %bb.6:
	callq	clock
	movq	%rax, %r14
	movl	$400000, %edx                   # imm = 0x61A80
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$100000, %r15                   # imm = 0x186A0
	jne	.LBB1_7
# %bb.8:
	movl	$10, %edi
	callq	putchar@PLT
	subq	(%rsp), %r14                    # 8-byte Folded Reload
	cvtsi2sd	%r14, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9mergeSortPiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9mergeSortPiS_ii,@object      # @_Z9mergeSortPiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9mergeSortPiS_ii
	.p2align	3, 0x0
_Z9mergeSortPiS_ii:
	.quad	_Z24__device_stub__mergeSortPiS_ii
	.size	_Z9mergeSortPiS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d\n"
	.size	.L.str, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"total time: %f\n"
	.size	.L.str.2, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9mergeSortPiS_ii"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__mergeSortPiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9mergeSortPiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9mergeSortPiS_ii      ; -- Begin function _Z9mergeSortPiS_ii
	.globl	_Z9mergeSortPiS_ii
	.p2align	8
	.type	_Z9mergeSortPiS_ii,@function
_Z9mergeSortPiS_ii:                     ; @_Z9mergeSortPiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_add_u32 s4, s0, 24
	s_addc_u32 s5, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s6, 0xffff
	s_mov_b32 s6, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v1, s2
	v_cmpx_gt_i32_e64 s3, v0
	s_cbranch_execz .LBB0_17
; %bb.1:                                ; %.preheader.lr.ph
	s_load_b32 s9, s[4:5], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s1, s2, 1
	v_add_nc_u32_e32 v3, s2, v0
	v_add_nc_u32_e32 v4, s1, v0
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_min_i32_e32 v9, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_min_i32_e32 v10, s3, v4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s9, s2
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_mul_i32 s8, s0, s8
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[6:7], s[8:9], 2
	s_mov_b32 s9, 0
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i32_e64 v0, v9
	s_cbranch_execz .LBB0_16
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v11, v0
	v_mov_b32_e32 v7, v10
	v_mov_b32_e32 v5, v0
	s_mov_b32 s11, 0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_i32_e64 v5, v10
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ; %.lr.ph._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v8, v[12:13], off
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_saveexec_b32 s13, s0
	s_mov_b32 s0, 0
	s_xor_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	s_mov_b32 s0, -1
	s_mov_b32 s15, s12
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[5:6]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v6, v[12:13], off
	v_cmpx_lt_i32_e64 v7, v9
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_waitcnt vmcnt(1)
	v_ashrrev_i32_e32 v8, 31, v7
	s_and_not1_b32 s15, s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], 2, v[7:8]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	global_load_b32 v8, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, v6, v8
	v_cmp_lt_i32_e64 s0, v6, v8
	s_and_b32 s16, vcc_lo, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	s_or_not1_b32 s0, s0, exec_lo
	s_or_b32 s15, s15, s16
.LBB0_9:                                ; %Flow96
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s12, s12, exec_lo
	s_and_b32 s14, s15, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s12, s12, s14
.LBB0_10:                               ; %Flow95
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
                                        ; implicit-def: $vgpr12
	s_and_saveexec_b32 s13, s12
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v12, 1, v7
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v8, off
.LBB0_12:                               ; %Flow97
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_14
; %bb.13:                               ; %._crit_edge75
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v12, v7 :: v_dual_add_nc_u32 v5, 1, v5
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v6, off
.LBB0_14:                               ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v11, 1, v11
	v_add_co_u32 v3, s0, v3, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
	v_cmp_ge_i32_e32 vcc_lo, v11, v9
	v_mov_b32_e32 v7, v12
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_4
; %bb.15:                               ; %Flow98
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_16:                               ; %Flow99
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, s8, v0
	v_add_co_u32 v1, s0, v1, s6
	v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, s1, v0
	v_add_nc_u32_e32 v4, s2, v0
	v_cmp_le_i32_e32 vcc_lo, s3, v0
	v_min_i32_e32 v10, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_min_i32_e32 v9, s3, v4
	s_or_b32 s9, vcc_lo, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB0_2
.LBB0_17:                               ; %._crit_edge73
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9mergeSortPiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9mergeSortPiS_ii, .Lfunc_end0-_Z9mergeSortPiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 672
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9mergeSortPiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z9mergeSortPiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
