
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define NPB_VERSION "3.3.1"

using namespace std;

#define min(x,y) (x) <= (y) ? (x) : (y)
#define max(x,y) (x) >= (y) ? (x) : (y)

// block sizes for CUDA kernels
#define NORM_BLOCK 32
#define SOLVE_BLOCK 32
#define ERHS_BLOCK 32

// timer constants
#define t_total 0
#define t_rhsx 1
#define t_rhsy 2
#define t_rhsz 3
#define t_rhs 4
#define t_xsolve 5
#define t_ysolve 6
#define t_zsolve 7
#define t_rdis1 8
#define t_rdis2 9
#define t_txinvr 10
#define t_pinvr 11
#define t_ninvr 12
#define t_tzetar 13
#define t_add 14
#define t_last 15


//---------------------------------------------------------------------
// diffusion coefficients
//---------------------------------------------------------------------
#define dx1 0.75
#define dx2 0.75
#define dx3 0.75
#define dx4 0.75
#define dx5 0.75
#define dy1 0.75
#define dy2 0.75
#define dy3 0.75
#define	dy4 0.75
#define dy5 0.75
#define dz1 1.0
#define dz2 1.0
#define dz3 1.0
#define dz4 1.0
#define dz5 1.0
//#define dxmax max(dx3,dx4)
//#define dymax max(dy2,dy4)
//#define dzmax max(dz2,dz3)
#define dxmax dx3
#define dymax dy2
#define dzmax dz2
//---------------------------------------------------------------------
//   fourth difference dissipation
//---------------------------------------------------------------------
#define dssp (max(max(dx1,dy1),dz1)*.25)
#define c4dssp (4.0*dssp)
#define c5dssp (5.0*dssp)

#define c1 1.4
#define c2 0.4
#define	c3 0.1
#define c4 1.0
#define c5 1.4
#define c1c2 (c1*c2)
#define c1c5 (c1*c5)
#define c3c4 (c3*c4)
#define c1345 (c1c5*c3c4)
#define conz1 (1.0-c1c5)
#define c2iv 2.5
#define con43 (4.0/3.0)
#define con16 (1.0/6.0)

// macros to linearize multidimensional array accesses 
#define fu(m,i,j,k) fu[(i)+nx*((j)+ny*((k)+nz*(m)))]
#define forcing(m,i,j,k) forcing[(i)+nx*((j)+ny*((k)+nz*(m)))]
#define rhs(m,i,j,k) rhs[m+(i)*5+(j)*5*nx+(k)*5*nx*ny]
#define rho_i(i,j,k) rho_i[i+(j)*nx+(k)*nx*ny]
#define us(i,j,k) us[i+(j)*nx+(k)*nx*ny]
#define vs(i,j,k) vs[i+(j)*nx+(k)*nx*ny]
#define ws(i,j,k) ws[i+(j)*nx+(k)*nx*ny]
#define square(i,j,k) square[i+(j)*nx+(k)*nx*ny]
#define qs(i,j,k) qs[i+(j)*nx+(k)*nx*ny]
#define speed(i,j,k) speed[i+(j)*nx+(k)*nx*ny]

static void inline HandleError( cudaError_t err, const char *file, int line ) {
	if (err != cudaSuccess) {
		printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
		exit( EXIT_FAILURE );
	}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

__constant__ double tx1, tx2, tx3, ty1, ty2, ty3, tz1, tz2, tz3;
__constant__ double bt, dt, dtdssp;
__constant__ double dnxm1, dnym1, dnzm1;
__constant__ double dtx1, dttx2, dty1, dtty2, dtz1, dttz2, c2dttx1, c2dtty1, c2dttz1;
__constant__ double comz1, comz4, comz5, comz6, c3c4tx3, c3c4ty3, c3c4tz3;
__constant__ double xxcon1, xxcon2, xxcon3, xxcon4, xxcon5, dx1tx1, dx2tx1, dx3tx1, dx4tx1, dx5tx1;
__constant__ double yycon1, yycon2, yycon3, yycon4, yycon5, dy1ty1, dy2ty1, dy3ty1, dy4ty1, dy5ty1;
__constant__ double zzcon1, zzcon2, zzcon3, zzcon4, zzcon5, dz1tz1, dz2tz1, dz3tz1, dz4tz1, dz5tz1;
__constant__ double ce[13][5];


//---------------------------------------------------------------------
// exact_rhs computation
//---------------------------------------------------------------------
__device__ static void exact_solution_kernel (const double xi, const double eta, const double zta, double *dtemp) {
	for (int m = 0; m < 5; m++)
		dtemp[m] = ce[0][m] + xi*(ce[1][m] + xi*(ce[4][m] + xi*(ce[7][m] + xi*ce[10][m]))) +
				eta*(ce[2][m] + eta*(ce[5][m] + eta*(ce[8][m] + eta*ce[11][m])))+
				zta*(ce[3][m] + zta*(ce[6][m] + zta*(ce[9][m] + zta*ce[12][m])));
}

__global__ static void exact_rhs_kernel_init (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	for (m = 0; m < 5; m++) forcing(m,i,j,k) = (double)0.0;
}

__global__ static void exact_rhs_kernel_x (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtemp[5], dtpp;
	double ue[5][5], buf[3][5], cuf[3], q[3];

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	j = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || j >= ny-1) return;

	zta = (double)k * dnzm1;
	eta = (double)j * dnym1;
	//---------------------------------------------------------------------
	//      xi-direction flux differences                      
	//---------------------------------------------------------------------
	for (i = 0; i < 3; i++) {
		xi = (double)i * dnxm1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[i+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[i][m] = dtpp*dtemp[m];
		cuf[i] = buf[i][1] * buf[i][1];
		buf[i][0] = cuf[i] + buf[i][2] * buf[i][2] + buf[i][3] * buf[i][3];
		q[i] = 0.5 * (buf[i][1]*ue[i+1][1] + buf[i][2]*ue[i+1][2] + buf[i][3]*ue[i+1][3]);
	}
	for (i = 1; i < nx-1; i++) {
		if (i+2 < nx) {
			xi = (double)(i+2) * dnxm1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}
		
		dtemp[0] = 0.0 - tx2*(ue[3][1]-ue[1][1])+ dx1tx1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = 0.0 - tx2*((ue[3][1]*buf[2][1]+c2*(ue[3][4]-q[2]))-(ue[1][1]*buf[0][1]+c2*(ue[1][4]-q[0])))+xxcon1*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dx2tx1*(ue[3][1]-2.0*ue[2][1]+ue[1][1]);
		dtemp[2] = 0.0 - tx2*(ue[3][2]*buf[2][1]-ue[1][2]*buf[0][1])+xxcon2*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dx3tx1*(ue[3][2]-2.0*ue[2][2]+ue[1][2]);
		dtemp[3] = 0.0 - tx2*(ue[3][3]*buf[2][1]-ue[1][3]*buf[0][1])+xxcon2*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dx4tx1*(ue[3][3]-2.0*ue[2][3]+ue[1][3]);
		dtemp[4] = 0.0 - tx2*(buf[2][1]*(c1*ue[3][4]-c2*q[2])-buf[0][1]*(c1*ue[1][4]-c2*q[0]))+0.5*xxcon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+xxcon4*(cuf[2]-2.0*cuf[1]+cuf[0])+
					xxcon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dx5tx1*(ue[3][4]-2.0*ue[2][4]+ ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation                         
		//---------------------------------------------------------------------
		if (i == 1) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(5.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i == 2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i >= 3 && i < nx-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m]+6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i == nx-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] +6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (i == nx-2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] + 5.0*ue[2][m]);
		}

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (i < nx-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp*ue[3][m];
			cuf[2] = buf[2][1] * buf[2][1];
			buf[2][0] = cuf[2] + buf[2][2] * buf[2][2] + buf[2][3] * buf[2][3];
			q[2] = 0.5 * (buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

__global__ static void exact_rhs_kernel_y (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtemp[5], dtpp;
	double ue[5][5], buf[3][5], cuf[3], q[3];

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || i >= nx-1) return;

	zta = (double)k * dnzm1;
	xi = (double)i * dnxm1;
	//---------------------------------------------------------------------
	//  eta-direction flux differences             
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) {
		eta = (double)j * dnym1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[j+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[j][m] = dtpp * dtemp[m];
		cuf[j] = buf[j][2] * buf[j][2];
		buf[j][0] = cuf[j] + buf[j][1] * buf[j][1] + buf[j][3] * buf[j][3];
		q[j] = 0.5*(buf[j][1]*ue[j+1][1] + buf[j][2]*ue[j+1][2] + buf[j][3]*ue[j+1][3]);
	}

	for (j = 1; j < ny-1; j++) {
		if (j+2 < ny) {
			eta = (double)(j+2) * dnym1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}

		dtemp[0] = forcing(0,i,j,k) - ty2*(ue[3][2]-ue[1][2])+ dy1ty1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = forcing(1,i,j,k) - ty2*(ue[3][1]*buf[2][2]-ue[1][1]*buf[0][2])+yycon2*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dy2ty1*(ue[3][1]-2.0*ue[2][1]+ ue[1][1]);
		dtemp[2] = forcing(2,i,j,k) - ty2*((ue[3][2]*buf[2][2]+c2*(ue[3][4]-q[2]))-(ue[1][2]*buf[0][2]+c2*(ue[1][4]-q[0])))+yycon1*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dy3ty1*( ue[3][2]-2.0*ue[2][2] +ue[1][2]);
		dtemp[3] = forcing(3,i,j,k) - ty2*(ue[3][3]*buf[2][2]-ue[1][3]*buf[0][2])+yycon2*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dy4ty1*( ue[3][3]-2.0*ue[2][3]+ ue[1][3]);
		dtemp[4] = forcing(4,i,j,k) - ty2*(buf[2][2]*(c1*ue[3][4]-c2*q[2])-buf[0][2]*(c1*ue[1][4]-c2*q[0]))+0.5*yycon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+yycon4*(cuf[2]-2.0*cuf[1]+cuf[0])+
					yycon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dy5ty1*(ue[3][4]-2.0*ue[2][4]+ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation                      
		//---------------------------------------------------------------------
		if (j == 1) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (5.0*ue[2][m] - 4.0*ue[3][m] +ue[4][m]);
		} else if (j == 2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] +       ue[4][m]);
		} else if (j >= 3 && j < ny-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (j == ny-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (ue[0][m] - 4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (j == ny-2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (ue[0][m] - 4.0*ue[1][m] + 5.0*ue[2][m]);
		}

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (j < ny-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp * ue[3][m];
			cuf[2] = buf[2][2] * buf[2][2];
			buf[2][0] = cuf[2] + buf[2][1] * buf[2][1] + buf[2][3] * buf[2][3];
			q[2] = 0.5*(buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

__global__ static void exact_rhs_kernel_z (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtpp, dtemp[5];
	double ue[5][5], buf[3][5], cuf[3], q[3];

	j = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (j >= ny-1 || i >= nx-1) return;

	eta = (double)j * dnym1;
	xi = (double)i * dnxm1;
	//---------------------------------------------------------------------
	//      zeta-direction flux differences                      
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) {
		zta = (double)k * dnzm1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[k+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[k][m] = dtpp * dtemp[m];
		cuf[k] = buf[k][3] * buf[k][3];
		buf[k][0] = cuf[k] + buf[k][1] * buf[k][1] + buf[k][2] * buf[k][2];
		q[k] = 0.5*(buf[k][1]*ue[k+1][1] + buf[k][2]*ue[k+1][2] + buf[k][3]*ue[k+1][3]);
	}

	for (k = 1; k < nz-1; k++) {
		if (k+2 < nz) {
			zta = (double)(k+2) * dnzm1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}

		dtemp[0] = forcing(0,i,j,k) - tz2*(ue[3][3]-ue[1][3])+dz1tz1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = forcing(1,i,j,k) - tz2*(ue[3][1]*buf[2][3]-ue[1][1]*buf[0][3])+zzcon2*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dz2tz1*(ue[3][1]-2.0*ue[2][1]+ue[1][1]);
		dtemp[2] = forcing(2,i,j,k) - tz2*(ue[3][2]*buf[2][3]-ue[1][2]*buf[0][3])+zzcon2*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dz3tz1*(ue[3][2]-2.0*ue[2][2]+ue[1][2]);
		dtemp[3] = forcing(3,i,j,k) - tz2*((ue[3][3]*buf[2][3]+c2*(ue[3][4]-q[2]))-(ue[1][3]*buf[0][3]+c2*(ue[1][4]-q[0])))+zzcon1*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dz4tz1*(ue[3][3]-2.0*ue[2][3] +ue[1][3]);
		dtemp[4] = forcing(4,i,j,k) - tz2*(buf[2][3]*(c1*ue[3][4]-c2*q[2])-buf[0][3]*(c1*ue[1][4]-c2*q[0]))+0.5*zzcon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+
					zzcon4*(cuf[2]-2.0*cuf[1]+cuf[0])+zzcon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dz5tz1*(ue[3][4]-2.0*ue[2][4]+ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation
		//---------------------------------------------------------------------
		if (k == 1) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(5.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k == 2) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(-4.0*ue[1][m]+6.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k >= 3 && k < nz-3) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m]+6.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k == nz-3) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (k == nz-2) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m]+5.0*ue[2][m]);
		}
		//---------------------------------------------------------------------
		// now change the sign of the forcing function, 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) forcing(m,i,j,k) = -1.0 * dtemp[m];

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (k < nz-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp * ue[3][m];
			cuf[2] = buf[2][3] * buf[2][3];
			buf[2][0] = cuf[2] + buf[2][1] * buf[2][1] + buf[2][2] * buf[2][2];
			q[2] = 0.5*(buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

void exact_rhs (double* forcing, int nx, int ny, int nz) {
	dim3 gridinit(ny,nz);
	exact_rhs_kernel_init<<<gridinit,nx>>>(forcing, nx, ny, nz);

	int yblock = min(ERHS_BLOCK,ny);
	int ygrid = (ny+yblock-1)/yblock;
	int zblock_y = min(ERHS_BLOCK/yblock,nz);
	int zgrid_y = (nz+zblock_y-1)/zblock_y;
	dim3 grid_x(zgrid_y,ygrid), block_x(zblock_y,yblock);
	exact_rhs_kernel_x<<<grid_x,block_x>>>(forcing, nx, ny, nz);

	int xblock = min(ERHS_BLOCK,nx);
	int xgrid = (nx+xblock-1)/xblock;
	int zblock_x = min(ERHS_BLOCK/xblock,nz);
	int zgrid_x = (nz+zblock_x-1)/zblock_x;
	dim3 grid_y(zgrid_x,xgrid), block_y(zblock_x,xblock);
	exact_rhs_kernel_y<<<grid_y,block_y>>>(forcing, nx, ny, nz);

	int yblock_x = min(ERHS_BLOCK/xblock,ny);
	int ygrid_x = (ny+yblock_x-1)/yblock_x;
	dim3 grid_z(ygrid_x,xgrid), block_z(yblock_x,xblock);
	exact_rhs_kernel_z<<<grid_z,block_z>>>(forcing, nx, ny, nz);
}


//---------------------------------------------------------------------
// initialize_kernel
//---------------------------------------------------------------------
__global__ static void initialize_kernel (double *fu, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, temp[5];
	double Pface11[5], Pface12[5], Pface21[5], Pface22[5], Pface31[5], Pface32[5];
  double zero, one;

	k = blockIdx.x;
	j = blockIdx.y;
	i = threadIdx.x;

	//---------------------------------------------------------------------
	//  to compute the whole thing with a simple loop. Make sure those 
	//  values are nonzero by initializing the whole thing here. 
	//---------------------------------------------------------------------
	fu(0,i,j,k) = (double)1.0;
	fu(1,i,j,k) = (double)0.0;
	fu(2,i,j,k) = (double)0.0;
	fu(3,i,j,k) = (double)0.0;
	fu(4,i,j,k) = (double)1.0;
  zero = (double)0.0;
  one = (double)1.0;

	//---------------------------------------------------------------------
	// first store the "interpolated" values everywhere on the zone    
	//---------------------------------------------------------------------
	zta = (double)k * dnzm1;
	eta = (double)j * dnym1;
	xi = (double)i * dnxm1;
	exact_solution_kernel (zero, eta, zta, Pface11);
	exact_solution_kernel (one, eta, zta, Pface12);
	exact_solution_kernel (xi, zero, zta, Pface21);
	exact_solution_kernel (xi, one, zta, Pface22);
	exact_solution_kernel (xi, eta, zero, Pface31);
	exact_solution_kernel (xi, eta, one, Pface32);
	for (m = 0; m < 5; m++) {
		double Pxi = xi * Pface12[m] + (1.0-xi)*Pface11[m];
		double Peta = eta * Pface22[m] + (1.0-eta)*Pface21[m];
		double Pzeta = zta * Pface32[m] + (1.0-zta)*Pface31[m];
		fu(m,i,j,k) = Pxi + Peta + Pzeta - Pxi*Peta - Pxi*Pzeta - Peta*Pzeta + Pxi*Peta*Pzeta;
	}

	//---------------------------------------------------------------------
	// now store the exact values on the boundaries        
	//---------------------------------------------------------------------

	//---------------------------------------------------------------------
	// west face                                                  
	//---------------------------------------------------------------------
	xi = (double)0.0;
	if (i == 0) {
		zta = (double)k * dnzm1;
		eta = (double)j * dnym1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// east face                                                      
	//---------------------------------------------------------------------
	xi = (double)1.0;
	if (i == nx-1) {
		zta = (double)k * dnzm1;
		eta = (double)j * dnym1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// south face                                                 
	//---------------------------------------------------------------------
	eta = (double)0.0;
	if (j == 0) {
		zta = (double)k * dnzm1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi,eta,zta,temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// north face                                    
	//---------------------------------------------------------------------
	eta = (double)1.0;
	if (j == ny-1) {
		zta = (double)k * dnzm1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi,eta,zta,temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// bottom face                                       
	//---------------------------------------------------------------------
	zta = (double)0.0;
	if (k == 0) {
		eta = (double)j * dnym1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// top face     
	//---------------------------------------------------------------------
	zta = (double)1.0;
	if (k == nz-1) {
		eta = (double)j * dnym1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
}

//---------------------------------------------------------------------
// adi: compute_rhs
//---------------------------------------------------------------------
__global__ static void compute_rhs_kernel_1 (double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *square, double *fu, const int nx, const int ny, const int nz) {
	int i, j, k;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	//---------------------------------------------------------------------
	//      compute the reciprocal of density, and the kinetic energy, 
	//      and the speed of sound. 
	//---------------------------------------------------------------------
	double rho_nv = 1.0/fu(0,i,j,k);
	double square_ijk;
	rho_i(i,j,k) = rho_nv;
	us(i,j,k) = fu(1,i,j,k) * rho_nv;
	vs(i,j,k) = fu(2,i,j,k) * rho_nv;
	ws(i,j,k) = fu(3,i,j,k) * rho_nv;
	square_ijk = 0.5*(fu(1,i,j,k)*fu(1,i,j,k) + fu(2,i,j,k)*fu(2,i,j,k) + fu(3,i,j,k)*fu(3,i,j,k)) * rho_nv;
	square(i,j,k) = 0.5*(fu(1,i,j,k)*fu(1,i,j,k) + fu(2,i,j,k)*fu(2,i,j,k) + fu(3,i,j,k)*fu(3,i,j,k)) * rho_nv;
	qs(i,j,k) = square_ijk * rho_nv;
	//---------------------------------------------------------------------
	//               (don't need speed and ainx until the lhs computation)
	//---------------------------------------------------------------------
	speed(i,j,k) = sqrt(c1c2*rho_nv*(fu(4,i,j,k) - square_ijk));
}

__global__ static void compute_rhs_kernel_2 (double *rho_i, double *us, double *vs, double *ws, double *qs, double *square, double *rhs,  double *forcing, double *fu,  int nx, const int ny, const int nz) {
	int i, j, k, m;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	double rtmp[5];

	//---------------------------------------------------------------------
	// copy the exact forcing term to the right hand side;  because 
	// this forcing term is known, we can store it on the whole zone
	// including the boundary                   
	//---------------------------------------------------------------------
	for (m = 0; m < 5; m++) rtmp[m] = forcing(m,i,j,k);
	
	//---------------------------------------------------------------------
	//      compute xi-direction fluxes 
	//---------------------------------------------------------------------
	if (k >= 1 && k < nz-1 && j >= 1 && j < ny-1 && i >= 1 && i < nx-1) {
		double uijk = us(i,j,k);
		double up1 = us(i+1,j,k);
		double um1 = us(i-1,j,k);
				
		rtmp[0] = rtmp[0] + dx1tx1*(fu(0,i+1,j,k) - 2.0*fu(0,i,j,k) + fu(0,i-1,j,k)) - tx2*(fu(1,i+1,j,k)-fu(1,i-1,j,k));
		rtmp[1] = rtmp[1] + dx2tx1*(fu(1,i+1,j,k) - 2.0*fu(1,i,j,k) + fu(1,i-1,j,k)) + xxcon2*con43*(up1-2.0*uijk+um1) - tx2*(fu(1,i+1,j,k)*up1 - fu(1,i-1,j,k)*um1 + (fu(4,i+1,j,k)-square(i+1,j,k)-fu(4,i-1,j,k)+square(i-1,j,k))*c2);
		rtmp[2] = rtmp[2] + dx3tx1*(fu(2,i+1,j,k) - 2.0*fu(2,i,j,k) + fu(2,i-1,j,k)) + xxcon2*(vs(i+1,j,k)-2.0*vs(i,j,k)+vs(i-1,j,k)) - tx2*(fu(2,i+1,j,k)*up1 - fu(2,i-1,j,k)*um1);
		rtmp[3] = rtmp[3] + dx4tx1*(fu(3,i+1,j,k) - 2.0*fu(3,i,j,k) + fu(3,i-1,j,k)) + xxcon2*(ws(i+1,j,k)-2.0*ws(i,j,k)+ws(i-1,j,k)) - tx2*(fu(3,i+1,j,k)*up1 - fu(3,i-1,j,k)*um1);
		rtmp[4] = rtmp[4] + dx5tx1*(fu(4,i+1,j,k) - 2.0*fu(4,i,j,k) + fu(4,i-1,j,k)) + xxcon3*(qs(i+1,j,k)-2.0*qs(i,j,k)+qs(i-1,j,k))+ xxcon4*(up1*up1-2.0*uijk*uijk+um1*um1) +
				xxcon5*(fu(4,i+1,j,k)*rho_i(i+1,j,k) - 2.0*fu(4,i,j,k)*rho_i(i,j,k) + fu(4,i-1,j,k)*rho_i(i-1,j,k)) - tx2*((c1*fu(4,i+1,j,k) - c2*square(i+1,j,k))*up1 - (c1*fu(4,i-1,j,k) - c2*square(i-1,j,k))*um1 );
		//---------------------------------------------------------------------
		//      add fourth order xi-direction dissipation               
		//---------------------------------------------------------------------
		if (i == 1) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (5.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i >= 3 && i < nx-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * ( fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i == nx-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k) );
		} else if (i == nx-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k) + 5.0*fu(m,i,j,k));
		}
		//---------------------------------------------------------------------
		//      compute eta-direction fluxes 
		//---------------------------------------------------------------------
		double vijk = vs(i,j,k);
		double vp1 = vs(i,j+1,k);
		double vm1 = vs(i,j-1,k);
		rtmp[0] = rtmp[0] + dy1ty1*(fu(0,i,j+1,k) - 2.0*fu(0,i,j,k) + fu(0,i,j-1,k)) - ty2*(fu(2,i,j+1,k)-fu(2,i,j-1,k));
		rtmp[1] = rtmp[1] + dy2ty1*(fu(1,i,j+1,k) - 2.0*fu(1,i,j,k) + fu(1,i,j-1,k)) + yycon2*(us(i,j+1,k)-2.0*us(i,j,k)+us(i,j-1,k)) - ty2*(fu(1,i,j+1,k)*vp1-fu(1,i,j-1,k)*vm1);
		rtmp[2] = rtmp[2] + dy3ty1*(fu(2,i,j+1,k) - 2.0*fu(2,i,j,k) + fu(2,i,j-1,k)) + yycon2*con43*(vp1-2.0*vijk+vm1) - ty2*(fu(2,i,j+1,k)*vp1-fu(2,i,j-1,k)*vm1+(fu(4,i,j+1,k)-square(i,j+1,k)-fu(4,i,j-1,k)+square(i,j-1,k))*c2);
		rtmp[3] = rtmp[3] + dy4ty1*(fu(3,i,j+1,k) - 2.0*fu(3,i,j,k) + fu(3,i,j-1,k)) + yycon2*(ws(i,j+1,k)-2.0*ws(i,j,k)+ws(i,j-1,k))-ty2*(fu(3,i,j+1,k)*vp1-fu(3,i,j-1,k)*vm1);
		rtmp[4] = rtmp[4] + dy5ty1*(fu(4,i,j+1,k) - 2.0*fu(4,i,j,k) + fu(4,i,j-1,k)) + yycon3*(qs(i,j+1,k)-2.0*qs(i,j,k)+qs(i,j-1,k)) + yycon4*(vp1*vp1-2.0*vijk*vijk+vm1*vm1) +
				yycon5*(fu(4,i,j+1,k)*rho_i(i,j+1,k)-2.0*fu(4,i,j,k)*rho_i(i,j,k)+fu(4,i,j-1,k)*rho_i(i,j-1,k)) - ty2*((c1*fu(4,i,j+1,k)-c2*square(i,j+1,k))*vp1 - (c1*fu(4,i,j-1,k)-c2*square(i,j-1,k))*vm1);
		//---------------------------------------------------------------------
		//      add fourth order eta-direction dissipation         
		//---------------------------------------------------------------------
		if (j == 1) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(5.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j >= 3 && j < ny-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j == ny-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k));
		} else if (j == ny-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+5.0*fu(m,i,j,k));
		}
		//---------------------------------------------------------------------
		//      compute zeta-direction fluxes 
		//---------------------------------------------------------------------
		double wijk = ws(i,j,k);
		double wp1 = ws(i,j,k+1);
		double wm1 = ws(i,j,k-1);

		rtmp[0] = rtmp[0] + dz1tz1*(fu(0,i,j,k+1)-2.0*fu(0,i,j,k)+fu(0,i,j,k-1)) - tz2*(fu(3,i,j,k+1)-fu(3,i,j,k-1));
		rtmp[1] = rtmp[1] + dz2tz1*(fu(1,i,j,k+1)-2.0*fu(1,i,j,k)+fu(1,i,j,k-1)) + zzcon2*(us(i,j,k+1)-2.0*us(i,j,k)+us(i,j,k-1)) - tz2*(fu(1,i,j,k+1)*wp1-fu(1,i,j,k-1)*wm1);
		rtmp[2] = rtmp[2] + dz3tz1*(fu(2,i,j,k+1)-2.0*fu(2,i,j,k)+fu(2,i,j,k-1)) + zzcon2*(vs(i,j,k+1)-2.0*vs(i,j,k)+vs(i,j,k-1)) - tz2*(fu(2,i,j,k+1)*wp1-fu(2,i,j,k-1)*wm1);
		rtmp[3] = rtmp[3] + dz4tz1*(fu(3,i,j,k+1)-2.0*fu(3,i,j,k)+fu(3,i,j,k-1)) + zzcon2*con43*(wp1-2.0*wijk+wm1) - tz2*(fu(3,i,j,k+1)*wp1-fu(3,i,j,k-1)*wm1+(fu(4,i,j,k+1)-square(i,j,k+1)-fu(4,i,j,k-1)+square(i,j,k-1))*c2);
		rtmp[4] = rtmp[4] + dz5tz1*(fu(4,i,j,k+1)-2.0*fu(4,i,j,k)+fu(4,i,j,k-1)) + zzcon3*(qs(i,j,k+1)-2.0*qs(i,j,k)+qs(i,j,k-1)) + zzcon4*(wp1*wp1-2.0*wijk*wijk+wm1*wm1) +
			zzcon5*(fu(4,i,j,k+1)*rho_i(i,j,k+1)-2.0*fu(4,i,j,k)*rho_i(i,j,k)+fu(4,i,j,k-1)*rho_i(i,j,k-1)) - tz2*((c1*fu(4,i,j,k+1)-c2*square(i,j,k+1))*wp1-(c1*fu(4,i,j,k-1)-c2*square(i,j,k-1))*wm1);
		//---------------------------------------------------------------------
		//      add fourth order zeta-direction dissipation                
		//---------------------------------------------------------------------
		if (k == 1) {
			for (m = 0; m < 5; m++)	rtmp[m] = rtmp[m] - dssp*(5.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k >= 3 && k < nz-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k == nz-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1));
		} else if (k == nz-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+5.0*fu(m,i,j,k));
		}

		for (m = 0; m < 5; m++) rtmp[m] *= dt;
	}

	for (m = 0; m < 5; m++) rhs(m,i,j,k) = rtmp[m];
}

//---------------------------------------------------------------------
// adi: txinvr
//---------------------------------------------------------------------
__global__ static void txinvr_kernel ( double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *rhs, const int nx, const int ny, const int nz) {
	int i, j, k;

	k = blockIdx.y+1;
	j = blockIdx.x+1;
	i = threadIdx.x+1;

	double ru1 = rho_i(i,j,k);
	double uu = us(i,j,k);
	double vv = vs(i,j,k);
	double ww = ws(i,j,k);
	double ap = speed(i,j,k);
	double ac2inv = 1.0/( ap*ap );

	double r1 = rhs(0,i,j,k);
	double r2 = rhs(1,i,j,k);
	double r3 = rhs(2,i,j,k);
	double r4 = rhs(3,i,j,k);
	double r5 = rhs(4,i,j,k);

	double t1 = c2*ac2inv*(qs(i,j,k)*r1 - uu*r2  - vv*r3 - ww*r4 + r5);
	double t2 = bt * ru1 * ( uu * r1 - r2 );
	double t3 = ( bt * ru1 * ap ) * t1;

	rhs(0,i,j,k) = r1 - t1;
	rhs(1,i,j,k) = -ru1*(ww*r1-r4);
	rhs(2,i,j,k) = ru1*(vv*r1-r3);
	rhs(3,i,j,k) = -t2+t3;
	rhs(4,i,j,k) = t2+t3;
}

//---------------------------------------------------------------------
// adi: x_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m-3)))]
#define lhsp(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m+4)))]
#define lhsm(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(j)+ny*((k)+nz*((i)+nx*(m)))]
__global__ static void x_solve_kernel (double *rho_i, double *us, double *speed, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhon[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	j = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || j >= ny-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three x-factors  
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,0,j,k) = (double)0.0;
  lhsp(1,0,j,k) = (double)0.0;
  lhsp(2,0,j,k) = (double)1.0;
  lhsp(3,0,j,k) = (double)0.0;
  lhsp(4,0,j,k) = (double)0.0;
  zero = (double)0.0;

	//---------------------------------------------------------------------
	// first fill the lhs for the u-eigenvalue                          
	//--------------------------------------------------------------------
	for (i = 0; i < 3; i++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhon[i] = max(max(max(dx2+con43*fac1, dx5+c1c5*fac1), dxmax+fac1), zero+dx1);
    if (dx2+con43*fac1>dx5+c1c5*fac1)
      rhon[i] = dx2+con43*fac1;
    else
      rhon[i] = dx5+c1c5*fac1;
    if (rhon[i]<dxmax+fac1)
      rhon[i] = dxmax+fac1;
    if (rhon[i]<zero+dx1)
      rhon[i] = zero+dx1;


		cv[i] = us(i,j,k);
	}
	_ls[1][0] = (double)0.0;
	_ls[1][1] = - dttx2 * cv[0] - dtx1 * rhon[0];
	_ls[1][2] = 1.0 + c2dttx1 * rhon[1];
	_ls[1][3] = dttx2 * cv[2] - dtx1 * rhon[2];
	_ls[1][4] = (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,1,j,k) = _ls[1][m];
	rhon[0] = rhon[1]; rhon[1] = rhon[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,0,j,k);
		_rs[1][m] = rhs(m,1,j,k);
	}

	//---------------------------------------------------------------------
	//      perform the Thomas algorithm; first, FORWARD ELIMINATION     
	//---------------------------------------------------------------------
	for (i = 0; i < nx-2; i++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (i+2 == nx-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i+2,j,k) = (double)0.0;
      lhsp(1,i+2,j,k) = (double)0.0;
      lhsp(2,i+2,j,k) = (double)1.0;
      lhsp(3,i+2,j,k) = (double)0.0;
      lhsp(4,i+2,j,k) = (double)0.0;

		} else {
			fac1 = c3c4*rho_i(i+3,j,k);
			//rhon[2] = max(max(max(dx2+con43*fac1, dx5+c1c5*fac1), dxmax+fac1), zero+dx1);
      if (dx2+con43*fac1>dx5+c1c5*fac1)
        rhon[2] = dx2+con43*fac1;
      else
        rhon[2] = dx5+c1c5*fac1;
      if (rhon[2]<dxmax+fac1)
        rhon[2] = dxmax+fac1;
      if (rhon[2]<zero+dx1)
        rhon[2] = zero+dx1;

			cv[2] = us(i+3,j,k);
			_ls[2][0] = (double)0.0;
			_ls[2][1] = - dttx2 * cv[0] - dtx1 * rhon[0];
			_ls[2][2] = 1.0 + c2dttx1 * rhon[1];
			_ls[2][3] = dttx2 * cv[2] - dtx1 * rhon[2];
			_ls[2][4] = (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                                  
			//---------------------------------------------------------------------
			if (i+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (i+2 >= 3 && i+2 < nx-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (i+2 == nx-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (i+2 == nx-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i+2,j,k) = _ls[2][m];
			rhon[0] = rhon[1]; rhon[1] = rhon[2];
			cv[0] = cv[1]; cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i+2,j,k);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}

	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	i = nx-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//            scale the last row immediately 
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,nx-2,j,k) = _ls[0][3];
	lhs(4,nx-2,j,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      subsequently, fill the other factors u+c, u-c 
	//---------------------------------------------------------------------
	for (i = 0; i < 3; i++) cv[i] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,0,j,k);
		_lp[0][m] = lhsp(m,0,j,k);
		_ls[1][m] = lhsp(m,1,j,k);
		_lp[1][m] = lhsp(m,1,j,k);
	}
	_lp[1][1] -= dttx2 * cv[0];
	_lp[1][3] += dttx2 * cv[2];
	_ls[1][1] += dttx2 * cv[0];
	_ls[1][3] -= dttx2 * cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,0,j,k);
	_rs[0][4] = rhs(4,0,j,k);
	_rs[1][3] = rhs(3,1,j,k);
	_rs[1][4] = rhs(4,1,j,k);
	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors               
	//---------------------------------------------------------------------
	for (i = 0; i < nx-2; i++) {
		//---------------------------------------------------------------------
		//      first, fill the other factors u+c, u-c 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i+2,j,k);
			_lp[2][m] = lhsp(m,i+2,j,k);
		}
		_rs[2][3] = rhs(3,i+2,j,k);
		_rs[2][4] = rhs(4,i+2,j,k);

		if (i+2 < nx-1) {
			cv[2] = speed(i+3,j,k);
			_lp[2][1] -= dttx2 * cv[0];
			_lp[2][3] += dttx2 * cv[2];
			_ls[2][1] += dttx2 * cv[0];
			_ls[2][3] -= dttx2 * cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		m = 3;
		fac1 = 1.0/_lp[0][2];
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1]*_lp[0][3];
		_lp[1][3] -= _lp[1][1]*_lp[0][4];
		_rs[1][m] -= _lp[1][1]*_rs[0][m];
		_lp[2][1] -= _lp[2][0]*_lp[0][3];
		_lp[2][2] -= _lp[2][0]*_lp[0][4];
		_rs[2][m] -= _lp[2][0]*_rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1]*_ls[0][3];
		_ls[1][3] -= _ls[1][1]*_ls[0][4];
		_rs[1][m] -= _ls[1][1]*_rs[0][m];
		_ls[2][1] -= _ls[2][0]*_ls[0][3];
		_ls[2][2] -= _ls[2][0]*_ls[0][4];
		_rs[2][m] -= _ls[2][0]*_rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	i = nx-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1]*_lp[0][3];
	_lp[1][3] -= _lp[1][1]*_lp[0][4];
	_rs[1][m] -= _lp[1][1]*_rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1]*_ls[0][3];
	_ls[1][3] -= _ls[1][1]*_ls[0][4];
	_rs[1][m] -= _ls[1][1]*_rs[0][m];

	//---------------------------------------------------------------------
	//               Scale the last row immediately
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];

	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,nx-2,j,k)*_rs[1][m];
	_rs[0][3] -= _lp[0][3]*_rs[1][3];
	_rs[0][4] -= _ls[0][3]*_rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}

	for (i = nx-3; i >= 0; i--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];

		if (i+2 < nx-1) {
			//---------------------------------------------------------------------
			//      Do the block-diagonal inversion          
			//---------------------------------------------------------------------
				double r1 = _rs[2][0];
				double r2 = _rs[2][1];
				double r3 = _rs[2][2];
				double r4 = _rs[2][3];
				double r5 = _rs[2][4];
				double t1 = bt * r3;
				double t2 = 0.5 * (r4+r5);

				_rs[2][0] = -r2;
				_rs[2][1] =  r1;
				_rs[2][2] = bt * ( r4 - r5 );
				_rs[2][3] = -t1 + t2;
				_rs[2][4] =  t1 + t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i+2,j,k) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//      Do the block-diagonal inversion          
	//---------------------------------------------------------------------
	double tf1 = bt * _rs[2][2];
	double tf2 = 0.5 * (_rs[2][3]+_rs[2][4]);
	rhs(0,1,j,k) = -_rs[2][1];
	rhs(1,1,j,k) =  _rs[2][0];
	rhs(2,1,j,k) = bt * ( _rs[2][3] - _rs[2][4] );
	rhs(3,1,j,k) = -tf1 + tf2;
	rhs(4,1,j,k) =  tf1 + tf2;

	for (m = 0; m < 5; m++) rhs(m,0,j,k) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp

//---------------------------------------------------------------------
// adi: y_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m-3)))]
#define lhsp(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m+4)))]
#define lhsm(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(i)+nx*((k)+nz*((j)+ny*(m)))]
__global__ static void y_solve_kernel (double *rho_i, double *vs, double *speed, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhoq[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || i >= nx-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three y-factors   
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,i,0,k) = (double)0.0;
  lhsp(1,i,0,k) = (double)0.0;
  lhsp(2,i,0,k) = (double)1.0;
  lhsp(3,i,0,k) = (double)0.0;
  lhsp(4,i,0,k) = (double)0.0;
  zero = (double)0.0;


	//---------------------------------------------------------------------
	//      first fill the lhs for the u-eigenvalue         
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhoq[j] = max(max(max(dy3+con43*fac1, dy5+c1c5*fac1), dymax+fac1), zero+dy1);
   if (dy3+con43*fac1>dy5+c1c5*fac1)
     rhoq[j] = dy3+con43*fac1;
   else
     rhoq[j] = dy5+c1c5*fac1;
   if (rhoq[j]<dymax+fac1)
     rhoq[j] = dymax+fac1;
   if (rhoq[j]<zero+dy1)
     rhoq[j] = zero+dy1;
		cv[j] = vs(i,j,k);
	}
	_ls[1][0] =  (double)0.0;
	_ls[1][1] = -dtty2*cv[0]-dty1 * rhoq[0];
	_ls[1][2] =  1.0 + c2dtty1 * rhoq[1];
	_ls[1][3] =  dtty2*cv[2]-dty1 * rhoq[2];
	_ls[1][4] =  (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,i,1,k) = _ls[1][m];
	rhoq[0] = rhoq[1]; 
  rhoq[1] = rhoq[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,i,0,k);
		_rs[1][m] = rhs(m,i,1,k);
	}

	//---------------------------------------------------------------------
	//                          FORWARD ELIMINATION  
	//---------------------------------------------------------------------
	for (j = 0; j < ny-2; j++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (j+2 == ny-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i,j+2,k) = (double)0.0;
      lhsp(1,i,j+2,k) = (double)0.0;
      lhsp(2,i,j+2,k) = (double)1.0;
      lhsp(3,i,j+2,k) = (double)0.0;
      lhsp(4,i,j+2,k) = (double)0.0;
		} else {
			fac1 = c3c4*rho_i(i,j+3,k);
			//rhoq[2] = max(max(max(dy3+con43*fac1, dy5+c1c5*fac1), dymax+fac1), zero+dy1);
      if (dy3+con43*fac1>dy5+c1c5*fac1)
        rhoq[2] = dy3+con43*fac1;
      else
        rhoq[2] = dy5+c1c5*fac1;
      if (rhoq[2]<dymax+fac1)
        rhoq[2] = dymax+fac1;
      if (rhoq[2]<zero+dy1)
        rhoq[2] = zero+dy1;
			cv[2] = vs(i,j+3,k);
			_ls[2][0] =  (double)0.0;
			_ls[2][1] = -dtty2*cv[0]-dty1 * rhoq[0];
			_ls[2][2] =  1.0 + c2dtty1 * rhoq[1];
			_ls[2][3] =  dtty2*cv[2]-dty1 * rhoq[2];
			_ls[2][4] =  (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                             
			//---------------------------------------------------------------------
			if (j+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (j+2 >= 3 && j+2 < ny-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (j+2 == ny-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (j+2 == ny-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i,j+2,k) = _ls[2][m];
			rhoq[0] = rhoq[1]; rhoq[1] = rhoq[2];
			cv[0] = cv[1]; cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i,j+2,k);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}
	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	j = ny-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//            scale the last row immediately 
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,i,ny-2,k) = _ls[0][3];
	lhs(4,i,ny-2,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors                 
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) cv[j] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,i,0,k);
		_lp[0][m] = lhsp(m,i,0,k);
		_ls[1][m] = lhsp(m,i,1,k);
		_lp[1][m] = lhsp(m,i,1,k);
	}
	_lp[1][1] -= dtty2*cv[0];
	_lp[1][3] += dtty2*cv[2];
	_ls[1][1] += dtty2*cv[0];
	_ls[1][3] -= dtty2*cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,i,0,k);
	_rs[0][4] = rhs(4,i,0,k);
	_rs[1][3] = rhs(3,i,1,k);
	_rs[1][4] = rhs(4,i,1,k);
	for (j = 0; j < ny-2; j++) {
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i,j+2,k);
			_lp[2][m] = lhsp(m,i,j+2,k);
		}
		_rs[2][3] = rhs(3,i,j+2,k);
		_rs[2][4] = rhs(4,i,j+2,k);
		if (j+2 < ny-1) {
			cv[2] = speed(i,j+3,k);
			_lp[2][1] -= dtty2*cv[0];
			_lp[2][3] += dtty2*cv[2];
			_ls[2][1] += dtty2*cv[0];
			_ls[2][3] -= dtty2*cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		fac1 = 1.0/_lp[0][2];
		m = 3;
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1] * _lp[0][3];
		_lp[1][3] -= _lp[1][1] * _lp[0][4];
		_rs[1][m] -= _lp[1][1] * _rs[0][m];
		_lp[2][1] -= _lp[2][0] * _lp[0][3];
		_lp[2][2] -= _lp[2][0] * _lp[0][4];
		_rs[2][m] -= _lp[2][0] * _rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		_rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		_rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	j = ny-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1] * _lp[0][3];
	_lp[1][3] -= _lp[1][1] * _lp[0][4];
	_rs[1][m] -= _lp[1][1] * _rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	_rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               Scale the last row immediately 
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];

	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,i,ny-2,k) * _rs[1][m];
	_rs[0][3] -= _lp[0][3] * _rs[1][3];
	_rs[0][4] -= _ls[0][3] * _rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}
	for (j = ny-3; j >= 0; j--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];
	
		if (j+2 < ny-1) {
			//---------------------------------------------------------------------
			//   block-diagonal matrix-vector multiplication                       
			//---------------------------------------------------------------------
			double r1 = _rs[2][0];
			double r2 = _rs[2][1];
			double r3 = _rs[2][2];
			double r4 = _rs[2][3];
			double r5 = _rs[2][4];

			double t1 = bt * r1;
			double t2 = 0.5 * ( r4 + r5 );

			_rs[2][0] =  bt * ( r4 - r5 );
			_rs[2][1] = -r3;
			_rs[2][2] =  r2;
			_rs[2][3] = -t1 + t2;
			_rs[2][4] =  t1 + t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i,j+2,k) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//   block-diagonal matrix-vector multiplication                       
	//---------------------------------------------------------------------
	double tf1 = bt * _rs[2][0];
	double tf2 = 0.5 * ( _rs[2][3] + _rs[2][4] );
	rhs(0,i,1,k) =  bt * ( _rs[2][3] - _rs[2][4] );
	rhs(1,i,1,k) = -_rs[2][2];
	rhs(2,i,1,k) =  _rs[2][1];
	rhs(3,i,1,k) = -tf1 + tf2;
	rhs(4,i,1,k) =  tf1 + tf2;

	for (m = 0; m < 5; m++) rhs(m,i,0,k) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp

//---------------------------------------------------------------------
// adi: z_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m-3)))]
#define lhsp(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m+4)))]
#define lhsm(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(i)+nx*((j)+ny*((k)+nz*(m)))]
__global__ static void z_solve_kernel (double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *fu, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhos[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	j = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (j >= ny-1 || i >= nx-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three z-factors   
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,i,j,0) = (double)0.0;
  lhsp(1,i,j,0) = (double)0.0;
  lhsp(2,i,j,0) = (double)1.0;
  lhsp(3,i,j,0) = (double)0.0;
  lhsp(4,i,j,0) = (double)0.0;
  zero = (double)0.0;

	//---------------------------------------------------------------------
	// first fill the lhs for the u-eigenvalue                          
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhos[k] = max(max(max(dz4+con43*fac1, dz5+c1c5*fac1), dzmax+fac1), zero+dz1);
    if (dz4+con43*fac1>dz5+c1c5*fac1)
      rhos[k] = dz4+con43*fac1;
    else
      rhos[k] = dz5+c1c5*fac1;
    if (rhos[k]<dzmax+fac1)
      rhos[k] = dzmax+fac1;
    if (rhos[k]<zero+dz1)
      rhos[k] = zero+dz1;
		cv[k] = ws(i,j,k);
	}
	_ls[1][0] =  (double)0.0;
	_ls[1][1] = -dttz2*cv[0] - dtz1*rhos[0];
	_ls[1][2] =  1.0 + c2dttz1 * rhos[1];
	_ls[1][3] =  dttz2*cv[2] - dtz1*rhos[2];
	_ls[1][4]=  (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,i,j,1) = _ls[1][m];
	rhos[0] = rhos[1]; rhos[1] = rhos[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,i,j,0);
		_rs[1][m] = rhs(m,i,j,1);
	}

	//---------------------------------------------------------------------
	//                          FORWARD ELIMINATION  
	//---------------------------------------------------------------------
	for (k = 0; k < nz-2; k++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (k+2 == nz-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i,j,k+2) = (double)0.0;
      lhsp(1,i,j,k+2) = (double)0.0;
      lhsp(2,i,j,k+2) = (double)1.0;
      lhsp(3,i,j,k+2) = (double)0.0;
      lhsp(4,i,j,k+2) = (double)0.0;
		} else {
			fac1 = c3c4*rho_i(i,j,k+3);
			//rhos[2] = max(max(max(dz4+con43*fac1, dz5+c1c5*fac1), dzmax+fac1), zero+dz1);
      if (dz4+con43*fac1>dz5+c1c5*fac1)
        rhos[2] = dz4+con43*fac1;
      else
        rhos[2] = dz5+c1c5*fac1;
      if (rhos[2]<dzmax+fac1)
        rhos[2] = dzmax+fac1;
      if (rhos[2]<zero+dz1)
        rhos[2] = zero+dz1;
			cv[2] = ws(i,j,k+3);
			_ls[2][0] =  (double)0.0;
			_ls[2][1] = -dttz2*cv[0] - dtz1*rhos[0];
			_ls[2][2] =  1.0 + c2dttz1 * rhos[1];
			_ls[2][3] =  dttz2*cv[2] - dtz1*rhos[2];
			_ls[2][4] =  (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                                  
			//---------------------------------------------------------------------
			if (k+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (k+2 >= 3 && k+2 < nz-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (k+2 == nz-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (k+2 == nz-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i,j,k+2) = _ls[2][m];
			rhos[0] = rhos[1]; rhos[1] = rhos[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i,j,k+2);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}
	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	k = nz-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               scale the last row immediately
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,i,j,k) = _ls[0][3];
	lhs(4,i,j,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      subsequently, fill the other factors u+c, u-c 
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) cv[k] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,i,j,0);
		_lp[0][m] = lhsp(m,i,j,0);
		_ls[1][m] = lhsp(m,i,j,1);
		_lp[1][m] = lhsp(m,i,j,1);
	}
	_lp[1][1] -= dttz2*cv[0];
	_lp[1][3] += dttz2*cv[2];
	_ls[1][1] += dttz2*cv[0];
	_ls[1][3] -= dttz2*cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,i,j,0);
	_rs[0][4] = rhs(4,i,j,0);
	_rs[1][3] = rhs(3,i,j,1);
	_rs[1][4] = rhs(4,i,j,1);
	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors               
	//---------------------------------------------------------------------
	for (k = 0; k < nz-2; k++) {
		//---------------------------------------------------------------------
		//      first, fill the other factors u+c, u-c 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i,j,k+2);
			_lp[2][m] = lhsp(m,i,j,k+2);
		}
		_rs[2][3] = rhs(3,i,j,k+2);
		_rs[2][4] = rhs(4,i,j,k+2);
		if (k+2 < nz-1) {
			cv[2] = speed(i,j,k+3);
			_lp[2][1] -= dttz2*cv[0];
			_lp[2][3] += dttz2*cv[2];
			_ls[2][1] += dttz2*cv[0];
			_ls[2][3] -= dttz2*cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		m = 3;
		fac1 = 1.0/_lp[0][2];
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1] * _lp[0][3];
		_lp[1][3] -= _lp[1][1] * _lp[0][4];
		_rs[1][m] -= _lp[1][1] * _rs[0][m];
		_lp[2][1] -= _lp[2][0] * _lp[0][3];
		_lp[2][2] -= _lp[2][0] * _lp[0][4];
		_rs[2][m] -= _lp[2][0] * _rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		_rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		_rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	k = nz-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1] * _lp[0][3];
	_lp[1][3] -= _lp[1][1] * _lp[0][4];
	_rs[1][m] -= _lp[1][1] * _rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	_rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               Scale the last row immediately some of this is overkill
	//               if this is the last cell
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];
		
	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,i,j,nz-2) * _rs[1][m];
	_rs[0][3] -= _lp[0][3] * _rs[1][3];
	_rs[0][4] -= _ls[0][3] * _rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}
	
	for (k = nz-3; k >= 0; k--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];

		if (k+2 < nz-1) {
			//---------------------------------------------------------------------
			//   block-diagonal matrix-vector multiplication tzetar
			//---------------------------------------------------------------------
			double xvel = us(i,j,k+2);
			double yvel = vs(i,j,k+2);
			double zvel = ws(i,j,k+2);
			double ac = speed(i,j,k+2);
			double uzik1 = fu(0,i,j,k+2);
			double t1 = (bt*uzik1)/ac * (_rs[2][3] + _rs[2][4]);
			double t2 = _rs[2][2] + t1;
			double t3 = bt*uzik1 * (_rs[2][3] - _rs[2][4]);

			_rs[2][4] =  uzik1*(-xvel*_rs[2][1] + yvel*_rs[2][0]) + qs(i,j,k+2)*t2 + c2iv*(ac*ac)*t1 + zvel*t3;
			_rs[2][3] =  zvel*t2  + t3;
			_rs[2][2] =  uzik1*_rs[2][0] + yvel*t2;
			_rs[2][1] = -uzik1*_rs[2][1] + xvel*t2;
			_rs[2][0] = t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i,j,k+2) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//   block-diagonal matrix-vector multiplication tzetar
	//---------------------------------------------------------------------
	double xfvel = us(i,j,1);
	double yfvel = vs(i,j,1);
	double zfvel = ws(i,j,1);
	double afc = speed(i,j,1);
	double ufzik1 = fu(0,i,j,1);
	double tf1 = (bt*ufzik1)/afc * (_rs[2][3] + _rs[2][4]);
	double tf2 = _rs[2][2] + tf1;
	double tf3 = bt*ufzik1 * (_rs[2][3] - _rs[2][4]);

	rhs(4,i,j,1) =  ufzik1*(-xfvel*_rs[2][1] + yfvel*_rs[2][0]) + qs(i,j,1)*tf2 + c2iv*(afc*afc)*tf1 + zfvel*tf3;
	rhs(3,i,j,1) =  zfvel*tf2  + tf3;
	rhs(2,i,j,1) =  ufzik1*_rs[2][0] + yfvel*tf2;
	rhs(1,i,j,1) = -ufzik1*_rs[2][1] + xfvel*tf2;
	rhs(0,i,j,1) = tf2;

	for (m = 0; m < 5; m++) rhs(m,i,j,0) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp
//---------------------------------------------------------------------
// 	addition of update to the vector u
//---------------------------------------------------------------------
__global__ static void add_kernel (double *fu, double *rhs, const int nx, const int ny, const int nz) {
	int i, j, k, m;

	k = blockIdx.y+1;
	j = blockIdx.x+1;
	i = threadIdx.x+1;
	m = threadIdx.y;

	fu(m,i,j,k) += rhs(m,i,j,k);
}

//---------------------------------------------------------------------
// adi
//---------------------------------------------------------------------
void adi(bool singlestep, int nx, int ny, int nz, int niter, double* rho_i, double* us, double* vs, double* ws, 
         double* speed, double* qs, double* square, double* rhs, double* lhs, double* forcing, double* fu, double* rstmp) {

	HANDLE_ERROR(cudaDeviceSynchronize());

	int itmax = singlestep ? 1 : niter;
  int xblock, xgrid, yblock, ygrid, zblock, zgrid;
	for (int step = 1; step <= itmax; step++) {
		if (step % 20 == 0 || step == 1 && !singlestep)
			printf(" Time step %4d\n", step);

		//compute_rhs();
	  dim3 grid1(ny,nz);
	  compute_rhs_kernel_1<<<grid1,nx>>>(rho_i, us, vs, ws, speed, qs, square, fu, nx, ny, nz);

	  compute_rhs_kernel_2<<<grid1,nx>>>(rho_i, us, vs, ws, qs, square, rhs, forcing, fu, nx, ny, nz);

		//txinvr();
	  dim3 grid2(ny-2,nz-2);
	  txinvr_kernel<<<grid2,nx-2>>> (rho_i, us, vs, ws, speed, qs, rhs, nx, ny, nz);

		//x_solve();
	  yblock = min(SOLVE_BLOCK,ny);
	  ygrid = (ny+yblock-1)/yblock;
	  zblock = min(SOLVE_BLOCK/yblock,nz);
	  zgrid = (nz+zblock-1)/zblock;
	  dim3 grid3(zgrid,ygrid), block3(zblock,yblock);
	  x_solve_kernel<<<grid3,block3>>>(rho_i, us, speed, rhs, lhs, rstmp, nx, ny, nz);

		//y_solve();
	  xblock = min(SOLVE_BLOCK,nx);
	  xgrid = (nx+xblock-1)/xblock;
	  zblock = min(SOLVE_BLOCK/xblock,nz);
	  zgrid = (nz+zblock-1)/zblock;
	  dim3 grid4(zgrid,xgrid), block4(zblock,xblock);
	  y_solve_kernel<<<grid4,block4>>>(rho_i, vs, speed, rhs, lhs, rstmp, nx, ny, nz);

		//z_solve();
	  xblock = min(SOLVE_BLOCK,nx);
	  xgrid = (nx+xblock-1)/xblock;
	  yblock = min(SOLVE_BLOCK/xblock,ny);
	  ygrid = (ny+yblock-1)/yblock;
	  dim3 grid5(ygrid,xgrid), block5(yblock,xblock);
	  z_solve_kernel<<<grid5,block5>>>(rho_i, us, vs, ws, speed, qs, fu, rhs, lhs, rstmp, nx, ny, nz);

		//add();
	  dim3 grid6(ny-2,nz-2);
	  dim3 block6(nx-2,5);
	  add_kernel<<<grid6,block6>>>(fu, rhs, nx, ny, nz);
	}

	HANDLE_ERROR(cudaDeviceSynchronize());
}
//---------------------------------------------------------------------
//      defaults from parameters
//---------------------------------------------------------------------
void read_input(char benchclass, double* dd_td, int* nx, int* ny, int* nz, int* niter) {
	FILE *file;

	if ((file = fopen("inputsp.data", "rt")) != NULL) {
		char line[1024];
		printf(" Reading from input file inputsp.data\n");
		
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%i", niter);
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%lf", dd_td);
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%i %i %i", nx, ny, nz);
		fclose(file);
	} else {
//		printf(" No input file inputsp.data. Using compiled defaults\n");
		int problem_size;
		switch (benchclass) {
			case 's':
			case 'S': problem_size = 12; *dd_td = 0.015; *niter = 100; break;
			case 'w':
			case 'W': problem_size = 36; *dd_td = 0.0015; *niter = 400; break;
			case 'a':
			case 'A': problem_size = 64; *dd_td = 0.0015; *niter = 400; break;
			case 'b':
			case 'B': problem_size = 102; *dd_td = 0.001; *niter = 400; break;
			case 'c':
			case 'C': problem_size = 162; *dd_td = 0.00067; *niter = 400; break;
			case 'd':
			case 'D': problem_size = 408; *dd_td = 0.00030; *niter = 500; break;
			case 'e':
			case 'E': problem_size = 1020; *dd_td = 0.0001; *niter = 500; break;
			default: printf("setparams: Internal error: invalid class %c\n", benchclass); exit(EXIT_FAILURE);
		}
		*nx = *ny = *nz = problem_size;
	}

	printf("\n\n NAS Parallel Benchmarks (NPB3.3-CUDA) - SP Benchmark\n\n");
	printf(" Size: %4dx%4dx%4d\n", *nx, *ny, *nz);
	printf(" Iterations: %4d    dt_d: %10.6F\n", *niter, *dd_td);
	printf("\n");
}




int main(int argc, char **argv) {
	char benchclass = argc > 1 ? argv[1][0] : 'S';

  struct timeval start_t;
  struct timeval end_t;
  struct timeval skt_t;
  struct timeval ske_t;

	int niter;
	int nx, ny, nz;
  double hdd;
  double dd_d;
	
	double *fu, *forcing, *rhs, *rho_i, *us, *vs, *ws, *qs, *speed, *square, *lhs, *rstmp;
  //double* rmsbuf;
	//double xce[5], xcr[5];

	char CUDAname[256];
	int CUDAmp, CUDAclock, CUDAmemclock, CUDAl2cache;
	size_t CUDAmem;

	//---------------------------------------------------------------------
	//   read input data
	//---------------------------------------------------------------------
	read_input(benchclass, &hdd, &nx, &ny, &nz, &niter);
	dd_d = hdd;

	//---------------------------------------------------------------------
	//   allocate CUDA device memory
	//---------------------------------------------------------------------
	int gridsize = nx*ny*nz;
	int facesize = max(max(nx*ny, nx*nz), ny*nz);

  gettimeofday(&start_t, NULL);

	HANDLE_ERROR(cudaMalloc((void **)&fu, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&forcing, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&rhs, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&rho_i, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&us, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&vs, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&ws, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&qs, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&speed, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&square, gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&lhs, 9*gridsize*sizeof(double)));
	HANDLE_ERROR(cudaMalloc((void **)&rstmp, 5*gridsize*sizeof(double)));
	//HANDLE_ERROR(cudaMalloc((void **)&rmsbuf, 5*facesize*sizeof(double)));

	  double ce_d[13][5];
	  ce_d[0][0] = (double)2.0;
	  ce_d[1][0] = (double)0.0;
	  ce_d[2][0] = (double)0.0;
	  ce_d[3][0] = (double)4.0;
	  ce_d[4][0] = (double)5.0;
	  ce_d[5][0] = (double)3.0;
	  ce_d[6][0] = (double)0.5;
	  ce_d[7][0] = (double)0.02;
	  ce_d[8][0] = (double)0.01;
	  ce_d[9][0] = (double)0.03;
	  ce_d[10][0] = (double)0.5;
	  ce_d[11][0] = (double)0.4;
	  ce_d[12][0] = (double)0.3;

	  ce_d[0][1] = (double)1.0;
	  ce_d[1][1] = (double)0.0;
	  ce_d[2][1] = (double)0.0;
	  ce_d[3][1] = (double)0.0;
	  ce_d[4][1] = (double)1.0;
	  ce_d[5][1] = (double)2.0;
	  ce_d[6][1] = (double)3.0;
	  ce_d[7][1] = (double)0.01;
	  ce_d[8][1] = (double)0.03;
	  ce_d[9][1] = (double)0.02;
	  ce_d[10][1] = (double)0.4;
	  ce_d[11][1] = (double)0.3;
	  ce_d[12][1] = (double)0.5;

	  ce_d[0][2] = (double)2.0;
	  ce_d[1][2] = (double)2.0;
	  ce_d[2][2] = (double)0.0;
	  ce_d[3][2] = (double)0.0;
	  ce_d[4][2] = (double)0.0;
	  ce_d[5][2] = (double)2.0;
	  ce_d[6][2] = (double)3.0;
	  ce_d[7][2] = (double)0.04;
	  ce_d[8][2] = (double)0.03;
	  ce_d[9][2] = (double)0.05;
	  ce_d[10][2] = (double)0.3;
	  ce_d[11][2] = (double)0.5;
	  ce_d[12][2] = (double)0.4;

	  ce_d[0][3] = (double)2.0;
	  ce_d[1][3] = (double)2.0;
	  ce_d[2][3] = (double)0.0;
	  ce_d[3][3] = (double)0.0;
	  ce_d[4][3] = (double)0.0;
	  ce_d[5][3] = (double)2.0;
	  ce_d[6][3] = (double)3.0;
	  ce_d[7][3] = (double)0.03;
	  ce_d[8][3] = (double)0.05;
	  ce_d[9][3] = (double)0.04;
	  ce_d[10][3] = (double)0.2;
	  ce_d[11][3] = (double)0.1;
	  ce_d[12][3] = (double)0.3;

	  ce_d[0][4] = (double)5.0;
	  ce_d[1][4] = (double)4.0;
	  ce_d[2][4] = (double)3.0;
	  ce_d[3][4] = (double)2.0;
	  ce_d[4][4] = (double)0.1;
	  ce_d[5][4] = (double)0.4;
	  ce_d[6][4] = (double)0.3;
	  ce_d[7][4] = (double)0.05;
	  ce_d[8][4] = (double)0.04;
	  ce_d[9][4] = (double)0.03;
	  ce_d[10][4] = (double)0.1;
	  ce_d[11][4] = (double)0.3;
	  ce_d[12][4] = (double)0.2;

	  double bt_d = sqrt(0.5);

	  double dnxm1_d = 1.0/((double)nx-1.0);
	  double dnym1_d = 1.0/((double)ny-1.0);
	  double dnzm1_d = 1.0/((double)nz-1.0);

	  double tx1_d = 1.0 / (dnxm1_d * dnxm1_d);
	  double tx2_d = 1.0 / (2.0 * dnxm1_d);
	  double tx3_d = 1.0 / dnxm1_d;

	  double ty1_d = 1.0 / (dnym1_d * dnym1_d);
	  double ty2_d = 1.0 / (2.0 * dnym1_d);
	  double ty3_d = 1.0 / dnym1_d;
 
	  double tz1_d = 1.0 / (dnzm1_d * dnzm1_d);
	  double tz2_d = 1.0 / (2.0 * dnzm1_d);
	  double tz3_d = 1.0 / dnzm1_d;

	  double dtx1_d = dd_d*tx1_d;
	  double dttx2_d = dd_d*tx2_d;
	  double dty1_d = dd_d*ty1_d;
	  double dtty2_d = dd_d*ty2_d;
	  double dtz1_d = dd_d*tz1_d;
	  double dttz2_d = dd_d*tz2_d;

	  double c2dttx1_d = 2.0*dtx1_d;
	  double c2dtty1_d = 2.0*dty1_d;
	  double c2dttz1_d = 2.0*dtz1_d;

	  double dtdssp_d = dd_d*dssp;

	  double comz1_d  = dtdssp_d;
	  double comz4_d  = 4.0*dtdssp_d;
	  double comz5_d  = 5.0*dtdssp_d;
	  double comz6_d  = 6.0*dtdssp_d;

	  double c3c4tx3_d = c3c4*tx3_d;
	  double c3c4ty3_d = c3c4*ty3_d;
	  double c3c4tz3_d = c3c4*tz3_d;

	  double dx1tx1_d = dx1*tx1_d;
	  double dx2tx1_d = dx2*tx1_d;
	  double dx3tx1_d = dx3*tx1_d;
	  double dx4tx1_d = dx4*tx1_d;
	  double dx5tx1_d = dx5*tx1_d;

	  double dy1ty1_d = dy1*ty1_d;
	  double dy2ty1_d = dy2*ty1_d;
	  double dy3ty1_d = dy3*ty1_d;
	  double dy4ty1_d = dy4*ty1_d;
	  double dy5ty1_d = dy5*ty1_d;

	  double dz1tz1_d = dz1*tz1_d;
	  double dz2tz1_d = dz2*tz1_d;
	  double dz3tz1_d = dz3*tz1_d;
	  double dz4tz1_d = dz4*tz1_d;
	  double dz5tz1_d = dz5*tz1_d;

	  double xxcon1_d = c3c4tx3_d*con43*tx3_d;
	  double xxcon2_d = c3c4tx3_d*tx3_d;
	  double xxcon3_d = c3c4tx3_d*conz1*tx3_d;
	  double xxcon4_d = c3c4tx3_d*con16*tx3_d;
	  double xxcon5_d = c3c4tx3_d*c1c5*tx3_d;

	  double yycon1_d = c3c4ty3_d*con43*ty3_d;
	  double yycon2_d = c3c4ty3_d*ty3_d;
	  double yycon3_d = c3c4ty3_d*conz1*ty3_d;
	  double yycon4_d = c3c4ty3_d*con16*ty3_d;
	  double yycon5_d = c3c4ty3_d*c1c5*ty3_d;

	  double zzcon1_d = c3c4tz3_d*con43*tz3_d;
	  double zzcon2_d = c3c4tz3_d*tz3_d;
	  double zzcon3_d = c3c4tz3_d*conz1*tz3_d;
	  double zzcon4_d = c3c4tz3_d*con16*tz3_d;
	  double zzcon5_d = c3c4tz3_d*c1c5*tz3_d;

	  HANDLE_ERROR (cudaMemcpyToSymbol (&ce, &ce_d, 13*5*sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&bt, &bt_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dnxm1, &dnxm1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dnym1, &dnym1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dnzm1, &dnzm1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tx1, &tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tx2, &tx2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tx3, &tx3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&ty1, &ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&ty2, &ty2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&ty3, &ty3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tz1, &tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tz2, &tz2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&tz3, &tz3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dtx1, &dtx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dttx2, &dttx2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dty1, &dty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dtty2, &dtty2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dtz1, &dtz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dttz2, &dttz2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c2dttx1, &c2dttx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c2dtty1, &c2dtty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c2dttz1, &c2dttz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dt, &dd_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dtdssp, &dtdssp_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&comz1, &comz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&comz4, &comz4_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&comz5, &comz5_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&comz6, &comz6_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c3c4tx3, &c3c4tx3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c3c4ty3, &c3c4ty3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&c3c4tz3, &c3c4tz3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dx1tx1, &dx1tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dx2tx1, &dx2tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dx3tx1, &dx3tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dx4tx1, &dx4tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dx5tx1, &dx5tx1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dy1ty1, &dy1ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dy2ty1, &dy2ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dy3ty1, &dy3ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dy4ty1, &dy4ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dy5ty1, &dy5ty1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dz1tz1, &dz1tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dz2tz1, &dz2tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dz3tz1, &dz3tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dz4tz1, &dz4tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&dz5tz1, &dz5tz1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&xxcon1, &xxcon1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&xxcon2, &xxcon2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&xxcon3, &xxcon3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&xxcon4, &xxcon4_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&xxcon5, &xxcon5_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&yycon1, &yycon1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&yycon2, &yycon2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&yycon3, &yycon3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&yycon4, &yycon4_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&yycon5, &yycon5_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&zzcon1, &zzcon1_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&zzcon2, &zzcon2_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&zzcon3, &zzcon3_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&zzcon4, &zzcon4_d, sizeof(double)));
	  HANDLE_ERROR (cudaMemcpyToSymbol (&zzcon5, &zzcon5_d, sizeof(double)));

  gettimeofday(&skt_t, NULL);
	exact_rhs(forcing, nx, ny, nz);

	//sp->initialize();
  dim3 grid(nz,ny);
	initialize_kernel<<<grid,nx>>> (fu, nx, ny, nz);

	//---------------------------------------------------------------------
	//      do one time step to touch all code, and reinitialize
	//---------------------------------------------------------------------
	adi(true,  nx,  ny,  nz,  niter,  rho_i,  us,  vs,  ws, 
       speed,  qs,  square,  rhs,  lhs,  forcing,  fu,  rstmp);
	//sp->initialize();
	initialize_kernel<<<grid,nx>>> (fu, nx, ny, nz);

	//---------------------------------------------------------------------
	//   main time stepping loop
	//---------------------------------------------------------------------
	//sp->adi(false);
	adi(false,  nx,  ny,  nz,  niter,  rho_i,  us,  vs,  ws, 
       speed,  qs,  square,  rhs,  lhs,  forcing,  fu,  rstmp);

  gettimeofday(&ske_t, NULL);
  gettimeofday(&end_t, NULL);


	std::cout  << "time: "<<((end_t.tv_sec-start_t.tv_sec)+(end_t.tv_usec-start_t.tv_usec)*1e-6) << std::endl;
	std::cout  << "kernel: "<<((ske_t.tv_sec-skt_t.tv_sec)+(ske_t.tv_usec-skt_t.tv_usec)*1e-6) << std::endl;
	//std::cout  << (sdkGetAverageTimerValue(&timer)/1000.0)  / iterations << " seconds per iteration" << std::endl;
	//---------------------------------------------------------------------
	//   verification test
	//---------------------------------------------------------------------
	//char verifyclass;
  //bool verified;

	//---------------------------------------------------------------------
	//      More timers
	//---------------------------------------------------------------------
	//sp->print_timers();

	//delete sp;
	return EXIT_SUCCESS;
}

	.file	"tmpxft_00216792_00000000-6_sp_double.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3643:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3643:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/raydongpub/GPU-FPtuner/master/orig_application/sp_double.cu"
.LC1:
	.string	"%s in %s at line %d\n"
	.text
	.type	_ZL11HandleError9cudaErrorPKci.constprop.0, @function
_ZL11HandleError9cudaErrorPKci.constprop.0:
.LFB4323:
	.cfi_startproc
	testl	%edi, %edi
	je	.L2
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%esi, 12(%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r8d
	movl	$2, %edi
	leaq	.LC0(%rip), %rcx
	movq	%rax, %rdx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4323:
	.size	_ZL11HandleError9cudaErrorPKci.constprop.0, .-_ZL11HandleError9cudaErrorPKci.constprop.0
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB4325:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE4325:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.type	_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii, @function
_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii:
.LFB3673:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL17initialize_kernelPdiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3673:
	.size	_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii, .-_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii
	.type	_ZL17initialize_kernelPdiii, @function
_ZL17initialize_kernelPdiii:
.LFB3674:
	.cfi_startproc
	endbr64
	jmp	_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii
	.cfi_endproc
.LFE3674:
	.size	_ZL17initialize_kernelPdiii, .-_ZL17initialize_kernelPdiii
	.type	_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii, @function
_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii:
.LFB3687:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_ZL10add_kernelPdS_iii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L14:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3687:
	.size	_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii, .-_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii
	.type	_ZL10add_kernelPdS_iii, @function
_ZL10add_kernelPdS_iii:
.LFB3688:
	.cfi_startproc
	endbr64
	jmp	_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii
	.cfi_endproc
.LFE3688:
	.size	_ZL10add_kernelPdS_iii, .-_ZL10add_kernelPdS_iii
	.type	_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii, @function
_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii:
.LFB3685:
	.cfi_startproc
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 8(%rsp)
	movq	280(%rsp), %rax
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	%rsp, %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	296(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	96(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 272
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	144(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L19:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3685:
	.size	_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii, .-_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii
	.type	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, @function
_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii:
.LFB3686:
	.cfi_startproc
	endbr64
	jmp	_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii
	.cfi_endproc
.LFE3686:
	.size	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, .-_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.type	_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii, @function
_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii:
.LFB3683:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZL14y_solve_kernelPdS_S_S_S_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3683:
	.size	_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii, .-_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	.type	_ZL14y_solve_kernelPdS_S_S_S_S_iii, @function
_ZL14y_solve_kernelPdS_S_S_S_S_iii:
.LFB3684:
	.cfi_startproc
	endbr64
	jmp	_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	.cfi_endproc
.LFE3684:
	.size	_ZL14y_solve_kernelPdS_S_S_S_S_iii, .-_ZL14y_solve_kernelPdS_S_S_S_S_iii
	.type	_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii, @function
_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii:
.LFB3681:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZL14x_solve_kernelPdS_S_S_S_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3681:
	.size	_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii, .-_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	.type	_ZL14x_solve_kernelPdS_S_S_S_S_iii, @function
_ZL14x_solve_kernelPdS_S_S_S_S_iii:
.LFB3682:
	.cfi_startproc
	endbr64
	jmp	_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	.cfi_endproc
.LFE3682:
	.size	_ZL14x_solve_kernelPdS_S_S_S_S_iii, .-_ZL14x_solve_kernelPdS_S_S_S_S_iii
	.type	_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, @function
_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii:
.LFB3679:
	.cfi_startproc
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 104(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	72(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 224
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	120(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L34:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3679:
	.size	_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii, .-_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii
	.type	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, @function
_ZL13txinvr_kernelPdS_S_S_S_S_S_iii:
.LFB3680:
	.cfi_startproc
	endbr64
	jmp	_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii
	.cfi_endproc
.LFE3680:
	.size	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, .-_ZL13txinvr_kernelPdS_S_S_S_S_S_iii
	.type	_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii, @function
_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii:
.LFB3677:
	.cfi_startproc
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	256(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 120(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	88(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 256
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	136(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L39:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii, .-_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii
	.type	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, @function
_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii:
.LFB3678:
	.cfi_startproc
	endbr64
	jmp	_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii
	.cfi_endproc
.LFE3678:
	.size	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, .-_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.type	_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, @function
_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii:
.LFB3675:
	.cfi_startproc
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	232(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	%rsp, %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L44:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii, .-_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii
	.type	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, @function
_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii:
.LFB3676:
	.cfi_startproc
	endbr64
	jmp	_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii
	.cfi_endproc
.LFE3676:
	.size	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, .-_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.type	_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii, @function
_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii:
.LFB3671:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL18exact_rhs_kernel_zPdiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L49:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3671:
	.size	_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii, .-_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii
	.type	_ZL18exact_rhs_kernel_zPdiii, @function
_ZL18exact_rhs_kernel_zPdiii:
.LFB3672:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii
	.cfi_endproc
.LFE3672:
	.size	_ZL18exact_rhs_kernel_zPdiii, .-_ZL18exact_rhs_kernel_zPdiii
	.type	_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii, @function
_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii:
.LFB3669:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL18exact_rhs_kernel_yPdiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L54:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3669:
	.size	_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii, .-_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii
	.type	_ZL18exact_rhs_kernel_yPdiii, @function
_ZL18exact_rhs_kernel_yPdiii:
.LFB3670:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii
	.cfi_endproc
.LFE3670:
	.size	_ZL18exact_rhs_kernel_yPdiii, .-_ZL18exact_rhs_kernel_yPdiii
	.type	_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii, @function
_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii:
.LFB3667:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL18exact_rhs_kernel_xPdiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii, .-_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii
	.type	_ZL18exact_rhs_kernel_xPdiii, @function
_ZL18exact_rhs_kernel_xPdiii:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii
	.cfi_endproc
.LFE3668:
	.size	_ZL18exact_rhs_kernel_xPdiii, .-_ZL18exact_rhs_kernel_xPdiii
	.type	_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii, @function
_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii:
.LFB3665:
	.cfi_startproc
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_ZL21exact_rhs_kernel_initPdiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii, .-_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii
	.type	_ZL21exact_rhs_kernel_initPdiii, @function
_ZL21exact_rhs_kernel_initPdiii:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii
	.cfi_endproc
.LFE3666:
	.size	_ZL21exact_rhs_kernel_initPdiii, .-_ZL21exact_rhs_kernel_initPdiii
	.globl	_Z9exact_rhsPdiii
	.type	_Z9exact_rhsPdiii, @function
_Z9exact_rhsPdiii:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movl	%edx, 28(%rsp)
	movl	%ecx, 32(%rsp)
	movl	%esi, 100(%rsp)
	movl	$1, %esi
	movq	%rax, 104(%rsp)
	movl	108(%rsp), %ecx
	movq	%rdi, 8(%rsp)
	movq	100(%rsp), %rdx
	movq	28(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L70
	movq	8(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r13d, %esi
	call	_ZL44__device_stub__Z21exact_rhs_kernel_initPdiiiPdiii
.L70:
	movl	$32, %esi
	movl	$32, %eax
	cmpl	%esi, %ebx
	cmovle	%ebx, %esi
	cltd
	idivl	%esi
	movl	%esi, 56(%rsp)
	cmpl	%ebp, %eax
	cmovg	%ebp, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, %ecx
	leal	-1(%rax,%rbp), %eax
	cltd
	movl	%ecx, 52(%rsp)
	idivl	%ecx
	movl	$1, %ecx
	movl	%eax, 40(%rsp)
	leal	-1(%rsi,%rbx), %eax
	cltd
	idivl	%esi
	movq	52(%rsp), %rdx
	movl	$1, %esi
	movl	%eax, 44(%rsp)
	movq	40(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	movq	8(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r13d, %esi
	call	_ZL41__device_stub__Z18exact_rhs_kernel_xPdiiiPdiii
.L71:
	movl	$32, %r10d
	movl	$32, %eax
	movl	%ebp, %ecx
	movl	$1, %esi
	cmpl	%r10d, %r13d
	cmovle	%r13d, %r10d
	cltd
	idivl	%r10d
	movl	%r10d, 80(%rsp)
	movl	%r10d, %r14d
	cmpl	%ebp, %eax
	movl	%eax, %r12d
	cmovle	%eax, %ecx
	leal	-1(%r10,%r13), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	idivl	%r10d
	movl	%ecx, 76(%rsp)
	movl	%eax, %r15d
	leal	-1(%rcx,%rbp), %eax
	cltd
	movl	%r15d, 68(%rsp)
	idivl	%ecx
	movq	76(%rsp), %rdx
	movl	$1, %ecx
	movl	%eax, 64(%rsp)
	movq	64(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L72
	movq	8(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r13d, %esi
	call	_ZL41__device_stub__Z18exact_rhs_kernel_yPdiiiPdiii
.L72:
	cmpl	%ebx, %r12d
	movl	%r15d, 92(%rsp)
	movl	$1, %ecx
	movl	$1, %esi
	cmovg	%ebx, %r12d
	movl	%r14d, 104(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, 108(%rsp)
	leal	-1(%r12,%rbx), %eax
	movl	%r12d, 100(%rsp)
	cltd
	idivl	%r12d
	movq	100(%rsp), %rdx
	movl	%eax, 88(%rsp)
	movq	88(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	movq	8(%rsp), %rdi
	addq	$120, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movl	%ebp, %ecx
	movl	%ebx, %edx
	movl	%r13d, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL41__device_stub__Z18exact_rhs_kernel_zPdiiiPdiii
.L69:
	.cfi_restore_state
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3637:
	.size	_Z9exact_rhsPdiii, .-_Z9exact_rhsPdiii
	.section	.rodata.str1.1
.LC2:
	.string	" Time step %4d\n"
	.text
	.globl	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	.type	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_, @function
_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%esi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movl	%r8d, 52(%rsp)
	movq	%r9, (%rsp)
	movq	352(%rsp), %r15
	movq	%rax, 8(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	328(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	336(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	344(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	360(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	368(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	384(%rsp), %rax
	movb	%dil, 107(%rsp)
	movq	376(%rsp), %r14
	movq	%rax, 64(%rsp)
	call	cudaDeviceSynchronize@PLT
	movl	$1793, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	testb	%r13b, %r13b
	movl	$1, %eax
	cmove	52(%rsp), %eax
	movl	$1, 48(%rsp)
	movl	%eax, 52(%rsp)
.L77:
	movl	52(%rsp), %edi
	cmpl	%edi, 48(%rsp)
	jg	.L98
	movl	48(%rsp), %eax
	movl	$20, %ecx
	cltd
	idivl	%ecx
	testl	%edx, %edx
	je	.L78
	cmpl	$1, 48(%rsp)
	jne	.L79
	cmpb	$1, 107(%rsp)
	je	.L79
.L78:
	movl	48(%rsp), %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L79:
	movl	%ebx, 120(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movabsq	$4294967297, %rax
	movl	%ebp, 124(%rsp)
	movq	120(%rsp), %rdi
	movq	%rax, 232(%rsp)
	movl	236(%rsp), %ecx
	movl	%r12d, 228(%rsp)
	movq	228(%rsp), %rdx
	movl	$1, 128(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L80
	pushq	%rsi
	.cfi_def_cfa_offset 312
	pushq	%rbp
	.cfi_def_cfa_offset 320
	pushq	%rbx
	.cfi_def_cfa_offset 328
	pushq	%r12
	.cfi_def_cfa_offset 336
	pushq	%r14
	.cfi_def_cfa_offset 344
	pushq	112(%rsp)
	.cfi_def_cfa_offset 352
	movq	88(%rsp), %r9
	movq	72(%rsp), %r8
	movq	80(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_ZL57__device_stub__Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_iii
	addq	$48, %rsp
	.cfi_def_cfa_offset 304
.L80:
	movabsq	$4294967297, %rax
	movq	120(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rax, 232(%rsp)
	movl	128(%rsp), %esi
	movl	%r12d, 228(%rsp)
	movl	236(%rsp), %ecx
	movq	228(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L81
	pushq	%rbp
	.cfi_def_cfa_offset 312
	pushq	%rbx
	.cfi_def_cfa_offset 320
	pushq	%r12
	.cfi_def_cfa_offset 328
	pushq	%r14
	.cfi_def_cfa_offset 336
	pushq	128(%rsp)
	.cfi_def_cfa_offset 344
	pushq	%r15
	.cfi_def_cfa_offset 352
	movq	120(%rsp), %r9
	movq	88(%rsp), %r8
	movq	80(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_ZL59__device_stub__Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_iii
	addq	$48, %rsp
	.cfi_def_cfa_offset 304
.L81:
	leal	-2(%rbp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	%eax, 80(%rsp)
	leal	-2(%rbx), %eax
	movl	%eax, 132(%rsp)
	movl	%eax, 88(%rsp)
	movl	80(%rsp), %eax
	movl	%eax, 136(%rsp)
	leal	-2(%r12), %eax
	movq	132(%rsp), %rdi
	movl	%eax, 228(%rsp)
	movl	%eax, 92(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 232(%rsp)
	movl	236(%rsp), %ecx
	movq	228(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L82
	pushq	%rbp
	.cfi_def_cfa_offset 312
	pushq	%rbx
	.cfi_def_cfa_offset 320
	pushq	%r12
	.cfi_def_cfa_offset 328
	pushq	%r15
	.cfi_def_cfa_offset 336
	movq	72(%rsp), %r9
	movq	56(%rsp), %r8
	movq	64(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_ZL48__device_stub__Z13txinvr_kernelPdS_S_S_S_S_S_iiiPdS_S_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_def_cfa_offset 304
.L82:
	movl	$32, %esi
	movl	$32, %eax
	cmpl	%esi, %ebx
	cmovle	%ebx, %esi
	cltd
	idivl	%esi
	movl	%esi, 160(%rsp)
	cmpl	%ebp, %eax
	cmovg	%ebp, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, %ecx
	leal	-1(%rax,%rbp), %eax
	cltd
	movl	%ecx, 156(%rsp)
	idivl	%ecx
	movl	$1, %ecx
	movl	%eax, 144(%rsp)
	leal	-1(%rsi,%rbx), %eax
	cltd
	idivl	%esi
	movq	156(%rsp), %rdx
	movl	$1, %esi
	movl	%eax, 148(%rsp)
	movq	144(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L83
	pushq	%rcx
	.cfi_def_cfa_offset 312
	movq	%r15, %rcx
	pushq	%rbp
	.cfi_def_cfa_offset 320
	pushq	%rbx
	.cfi_def_cfa_offset 328
	pushq	%r12
	.cfi_def_cfa_offset 336
	movq	96(%rsp), %r9
	movq	88(%rsp), %r8
	movq	56(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_ZL47__device_stub__Z14x_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_def_cfa_offset 304
.L83:
	movl	$32, %r10d
	movl	$32, %eax
	movl	%ebp, %ecx
	movl	$1, %esi
	cmpl	%r10d, %r12d
	cmovle	%r12d, %r10d
	cltd
	idivl	%r10d
	movl	%r10d, 184(%rsp)
	movl	%r10d, 108(%rsp)
	cmpl	%ebp, %eax
	movl	%eax, %r13d
	cmovle	%eax, %ecx
	leal	-1(%r10,%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	idivl	%r10d
	movl	%ecx, 180(%rsp)
	movl	%eax, 84(%rsp)
	leal	-1(%rcx,%rbp), %eax
	cltd
	idivl	%ecx
	movq	180(%rsp), %rdx
	movl	$1, %ecx
	movl	%eax, 168(%rsp)
	movl	84(%rsp), %eax
	movl	%eax, 172(%rsp)
	movq	168(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movl	108(%rsp), %r10d
	testl	%eax, %eax
	jne	.L84
	pushq	%rdx
	.cfi_def_cfa_offset 312
	movq	%r15, %rcx
	pushq	%rbp
	.cfi_def_cfa_offset 320
	pushq	%rbx
	.cfi_def_cfa_offset 328
	pushq	%r12
	.cfi_def_cfa_offset 336
	movq	96(%rsp), %r9
	movq	88(%rsp), %r8
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_ZL47__device_stub__Z14y_solve_kernelPdS_S_S_S_S_iiiPdS_S_S_S_S_iii
	movl	140(%rsp), %r10d
	addq	$32, %rsp
	.cfi_def_cfa_offset 304
.L84:
	cmpl	%ebx, %r13d
	movl	$1, %ecx
	movl	$1, %esi
	movl	%r10d, 208(%rsp)
	cmovg	%ebx, %r13d
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	-1(%r13,%rbx), %eax
	movl	%r13d, 204(%rsp)
	cltd
	idivl	%r13d
	movq	204(%rsp), %rdx
	movl	%eax, 192(%rsp)
	movl	84(%rsp), %eax
	movl	%eax, 196(%rsp)
	movq	192(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	pushq	%rax
	.cfi_def_cfa_offset 312
	pushq	%rbp
	.cfi_def_cfa_offset 320
	pushq	%rbx
	.cfi_def_cfa_offset 328
	pushq	%r12
	.cfi_def_cfa_offset 336
	pushq	96(%rsp)
	.cfi_def_cfa_offset 344
	pushq	96(%rsp)
	.cfi_def_cfa_offset 352
	pushq	%r15
	.cfi_def_cfa_offset 360
	pushq	%r14
	.cfi_def_cfa_offset 368
	movq	104(%rsp), %r9
	movq	88(%rsp), %r8
	movq	96(%rsp), %rcx
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_ZL55__device_stub__Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iiiPdS_S_S_S_S_S_S_S_S_iii
	addq	$64, %rsp
	.cfi_def_cfa_offset 304
.L85:
	movl	88(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	%eax, 216(%rsp)
	movl	80(%rsp), %eax
	movl	%eax, 220(%rsp)
	movl	92(%rsp), %eax
	movq	216(%rsp), %rdi
	movl	%eax, 228(%rsp)
	movabsq	$4294967301, %rax
	movq	%rax, 232(%rsp)
	movl	236(%rsp), %ecx
	movq	228(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L86
	movl	%ebp, %r8d
	movl	%ebx, %ecx
	movl	%r12d, %edx
	movq	%r15, %rsi
	movq	%r14, %rdi
	call	_ZL35__device_stub__Z10add_kernelPdS_iiiPdS_iii
.L86:
	incl	48(%rsp)
	jmp	.L77
.L98:
	call	cudaDeviceSynchronize@PLT
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	movl	$1841, %esi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	%eax, %edi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZL11HandleError9cudaErrorPKci.constprop.0
	.cfi_endproc
.LFE3638:
	.size	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_, .-_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	.section	.rodata.str1.1
.LC9:
	.string	"rt"
.LC10:
	.string	"inputsp.data"
.LC11:
	.string	" Reading from input file inputsp.data\n"
.LC12:
	.string	"%i"
.LC13:
	.string	"%lf"
.LC14:
	.string	"%i %i %i"
.LC15:
	.string	"setparams: Internal error: invalid class %c\n"
.LC16:
	.string	"\n\n NAS Parallel Benchmarks (NPB3.3-CUDA) - SP Benchmark\n\n"
.LC17:
	.string	" Size: %4dx%4dx%4d\n"
.LC18:
	.string	" Iterations: %4d    dt_d: %10.6F\n"
.LC19:
	.string	"\n"
	.text
	.globl	_Z10read_inputcPdPiS0_S0_S0_
	.type	_Z10read_inputcPdPiS0_S0_S0_, @function
_Z10read_inputcPdPiS0_S0_S0_:
.LFB3639:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r8, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	leaq	.LC9(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r9, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$1064, %rsp
	.cfi_def_cfa_offset 1120
	movl	%edi, 8(%rsp)
	leaq	.LC10(%rip), %rdi
	movq	%fs:40, %rax
	movq	%rax, 1048(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movl	8(%rsp), %r10d
	testq	%rax, %rax
	je	.L100
	movq	%rax, %rbx
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	24(%rsp), %rax
	movq	%rbx, %rcx
	movl	$1023, %edx
	movl	$1024, %esi
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	__fgets_chk@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	xorl	%eax, %eax
	leaq	.LC12(%rip), %rsi
	call	__isoc23_sscanf@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rcx
	movl	$1023, %edx
	movl	$1024, %esi
	call	__fgets_chk@PLT
	movq	8(%rsp), %rdi
	movq	%r12, %rdx
	xorl	%eax, %eax
	leaq	.LC13(%rip), %rsi
	call	__isoc23_sscanf@PLT
	movq	8(%rsp), %rdi
	movq	%rbx, %rcx
	movl	$1023, %edx
	movl	$1024, %esi
	call	__fgets_chk@PLT
	movq	8(%rsp), %rdi
	movq	%r15, %r8
	movq	%r14, %rcx
	movq	%r13, %rdx
	leaq	.LC14(%rip), %rsi
	xorl	%eax, %eax
	call	__isoc23_sscanf@PLT
	movq	%rbx, %rdi
	call	fclose@PLT
	jmp	.L101
.L100:
	cmpb	$101, %r10b
	jg	.L102
	cmpb	$82, %r10b
	jg	.L103
	leal	-65(%r10), %eax
	cmpb	$4, %al
	jbe	.L125
	jmp	.L104
.L103:
	leal	-83(%r10), %eax
	cmpb	$18, %al
	ja	.L104
	leaq	.L107(%rip), %rdx
	movzbl	%al, %eax
	movslq	(%rdx,%rax,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata
	.align 4
	.align 4
.L107:
	.long	.L123-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L124-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L104-.L107
	.long	.L111-.L107
	.long	.L110-.L107
	.long	.L109-.L107
	.long	.L108-.L107
	.long	.L122-.L107
	.text
.L125:
	subl	$66, %r10d
	cmpb	$3, %r10b
	ja	.L111
	leaq	.L115(%rip), %rdx
	movzbl	%r10b, %r10d
	movslq	(%rdx,%r10,4), %rax
	addq	%rdx, %rax
	notrack jmp	*%rax
	.section	.rodata
	.align 4
	.align 4
.L115:
	.long	.L110-.L115
	.long	.L109-.L115
	.long	.L108-.L115
	.long	.L122-.L115
	.text
.L102:
	cmpb	$115, %r10b
	je	.L123
	cmpb	$119, %r10b
	je	.L124
	jmp	.L104
.L111:
	movsd	.LC4(%rip), %xmm0
	movl	$400, %edx
	movl	$64, %eax
	jmp	.L113
.L110:
	movsd	.LC5(%rip), %xmm0
	movl	$400, %edx
	movl	$102, %eax
	jmp	.L113
.L109:
	movsd	.LC6(%rip), %xmm0
	movl	$400, %edx
	movl	$162, %eax
	jmp	.L113
.L108:
	movsd	.LC7(%rip), %xmm0
	movl	$500, %edx
	movl	$408, %eax
	jmp	.L113
.L104:
	movl	$2, %edi
	movsbl	%r10b, %edx
	leaq	.LC15(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L122:
	movsd	.LC8(%rip), %xmm0
	movl	$500, %edx
	movl	$1020, %eax
	jmp	.L113
.L123:
	movsd	.LC3(%rip), %xmm0
	movl	$100, %edx
	movl	$12, %eax
	jmp	.L113
.L124:
	movsd	.LC4(%rip), %xmm0
	movl	$400, %edx
	movl	$36, %eax
.L113:
	movsd	%xmm0, (%r12)
	movl	%edx, 0(%rbp)
	movl	%eax, (%r15)
	movl	%eax, (%r14)
	movl	%eax, 0(%r13)
.L101:
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	0(%r13), %edx
	movl	(%r15), %r8d
	xorl	%eax, %eax
	movl	(%r14), %ecx
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	(%r12), %xmm0
	movl	0(%rbp), %edx
	movb	$1, %al
	leaq	.LC18(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	1048(%rsp), %rax
	subq	%fs:40, %rax
	je	.L119
	call	__stack_chk_fail@PLT
.L119:
	addq	$1064, %rsp
	.cfi_def_cfa_offset 56
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3639:
	.size	_Z10read_inputcPdPiS0_S0_S0_, .-_Z10read_inputcPdPiS0_S0_S0_
	.section	.rodata.str1.1
.LC44:
	.string	"time: "
.LC46:
	.string	"kernel: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%edi, %eax
	movl	$83, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$1216, %rsp
	.cfi_def_cfa_offset 1248
	movq	%fs:40, %rdx
	movq	%rdx, 1208(%rsp)
	xorl	%edx, %edx
	decl	%eax
	jle	.L128
	movq	8(%rsi), %rax
	movsbl	(%rax), %edi
.L128:
	movq	%rsp, %r9
	leaq	8(%rsp), %rcx
	leaq	4(%rsp), %rdx
	leaq	12(%rsp), %r8
	leaq	16(%rsp), %rsi
	call	_Z10read_inputcPdPiS0_S0_S0_
	movl	4(%rsp), %ebx
	xorl	%esi, %esi
	imull	8(%rsp), %ebx
	imull	12(%rsp), %ebx
	movsd	16(%rsp), %xmm0
	leaq	624(%rsp), %rdi
	movsd	%xmm0, 24(%rsp)
	call	gettimeofday@PLT
	leal	(%rbx,%rbx,4), %r12d
	leaq	32(%rsp), %rdi
	movslq	%ebx, %rbp
	movslq	%r12d, %r12
	salq	$3, %rbp
	salq	$3, %r12
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$1927, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	40(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$1928, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	48(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$1929, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	56(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1930, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	64(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1931, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	72(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1932, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	80(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1933, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	88(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1934, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	96(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1935, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	104(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$1936, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leal	(%rbx,%rbx,8), %esi
	leaq	112(%rsp), %rdi
	movslq	%esi, %rsi
	leaq	672(%rsp), %rbx
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	$1937, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	leaq	120(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$1938, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movsd	.LC31(%rip), %xmm1
	xorl	%ecx, %ecx
	movsd	.LC20(%rip), %xmm2
	movsd	.LC30(%rip), %xmm3
	movsd	.LC24(%rip), %xmm5
	movq	$0x000000000, 728(%rsp)
	movl	$1, %r8d
	movsd	.LC25(%rip), %xmm0
	movaps	%xmm1, %xmm14
	movaps	%xmm1, %xmm13
	movsd	.LC28(%rip), %xmm4
	movsd	.LC29(%rip), %xmm6
	movl	$520, %edx
	movq	%rbx, %rdi
	movsd	.LC22(%rip), %xmm10
	movsd	.LC26(%rip), %xmm7
	movsd	.LC23(%rip), %xmm9
	movsd	%xmm2, 688(%rsp)
	leaq	688(%rsp), %rsi
	movsd	.LC27(%rip), %xmm8
	movsd	%xmm10, 808(%rsp)
	movsd	%xmm9, 848(%rsp)
	movsd	%xmm5, 888(%rsp)
	movsd	%xmm0, 928(%rsp)
	movsd	%xmm7, 968(%rsp)
	movsd	%xmm8, 1008(%rsp)
	movsd	%xmm4, 1048(%rsp)
	movsd	%xmm0, 1088(%rsp)
	movsd	%xmm6, 1128(%rsp)
	movsd	%xmm3, 1168(%rsp)
	movsd	%xmm1, 696(%rsp)
	movsd	%xmm1, 856(%rsp)
	movsd	%xmm2, 896(%rsp)
	movsd	%xmm5, 936(%rsp)
	movsd	%xmm8, 976(%rsp)
	movq	$0x000000000, 768(%rsp)
	movq	$0x000000000, 736(%rsp)
	movq	$0x000000000, 776(%rsp)
	movq	$0x000000000, 816(%rsp)
	movsd	%xmm4, 1016(%rsp)
	movsd	.LC33(%rip), %xmm8
	movsd	.LC34(%rip), %xmm11
	movsd	%xmm7, 1056(%rsp)
	movsd	.LC32(%rip), %xmm7
	movsd	%xmm0, 1176(%rsp)
	movsd	%xmm0, 1144(%rsp)
	movsd	.LC35(%rip), %xmm0
	movsd	%xmm6, 1096(%rsp)
	movsd	%xmm3, 1136(%rsp)
	movsd	%xmm2, 704(%rsp)
	movsd	%xmm2, 744(%rsp)
	movsd	%xmm2, 904(%rsp)
	movsd	%xmm5, 944(%rsp)
	movsd	%xmm7, 984(%rsp)
	movsd	%xmm4, 1024(%rsp)
	movsd	%xmm8, 1064(%rsp)
	movsd	%xmm3, 1104(%rsp)
	movsd	%xmm6, 1184(%rsp)
	movsd	%xmm2, 712(%rsp)
	movsd	%xmm2, 752(%rsp)
	movsd	%xmm2, 912(%rsp)
	movsd	%xmm5, 952(%rsp)
	movsd	%xmm4, 992(%rsp)
	movsd	%xmm8, 1032(%rsp)
	movsd	%xmm7, 1072(%rsp)
	movsd	%xmm11, 1112(%rsp)
	movq	$0x000000000, 784(%rsp)
	movq	$0x000000000, 824(%rsp)
	movq	$0x000000000, 864(%rsp)
	movq	$0x000000000, 792(%rsp)
	movq	$0x000000000, 832(%rsp)
	movq	$0x000000000, 872(%rsp)
	movsd	%xmm0, 1152(%rsp)
	movq	.LC36(%rip), %rax
	movsd	%xmm2, 840(%rsp)
	cvtsi2sdl	4(%rsp), %xmm2
	movsd	%xmm4, 1080(%rsp)
	movaps	%xmm1, %xmm4
	movsd	%xmm3, 1192(%rsp)
	movsd	%xmm3, 960(%rsp)
	subsd	%xmm1, %xmm2
	movsd	%xmm3, 1160(%rsp)
	movaps	%xmm1, %xmm3
	movsd	%xmm5, 800(%rsp)
	cvtsi2sdl	12(%rsp), %xmm5
	movsd	%xmm6, 920(%rsp)
	divsd	%xmm2, %xmm4
	cvtsi2sdl	8(%rsp), %xmm2
	movsd	%xmm11, 1200(%rsp)
	movaps	%xmm1, %xmm11
	movsd	%xmm7, 1040(%rsp)
	movaps	%xmm1, %xmm7
	subsd	%xmm1, %xmm5
	movsd	%xmm8, 1000(%rsp)
	movaps	%xmm1, %xmm8
	movq	%rax, 128(%rsp)
	leaq	_ZL2ce(%rip), %rax
	movsd	%xmm9, 720(%rsp)
	subsd	%xmm1, %xmm2
	movsd	%xmm10, 760(%rsp)
	movsd	%xmm0, 880(%rsp)
	movsd	%xmm0, 1120(%rsp)
	divsd	%xmm2, %xmm3
	movaps	%xmm1, %xmm2
	movsd	%xmm4, 136(%rsp)
	movaps	%xmm4, %xmm6
	mulsd	%xmm4, %xmm6
	divsd	%xmm5, %xmm2
	movaps	%xmm1, %xmm5
	movsd	%xmm3, 144(%rsp)
	divsd	%xmm6, %xmm5
	movaps	%xmm4, %xmm6
	addsd	%xmm4, %xmm6
	movsd	%xmm2, 152(%rsp)
	divsd	%xmm6, %xmm11
	movaps	%xmm3, %xmm6
	mulsd	%xmm3, %xmm6
	movsd	%xmm5, 160(%rsp)
	movaps	%xmm5, %xmm12
	divsd	%xmm4, %xmm7
	movaps	%xmm1, %xmm4
	movsd	%xmm11, 168(%rsp)
	divsd	%xmm6, %xmm4
	movaps	%xmm3, %xmm6
	addsd	%xmm3, %xmm6
	movsd	%xmm7, 176(%rsp)
	divsd	%xmm6, %xmm14
	movaps	%xmm1, %xmm6
	movsd	%xmm4, 184(%rsp)
	divsd	%xmm3, %xmm6
	movaps	%xmm2, %xmm3
	mulsd	%xmm2, %xmm3
	movsd	%xmm14, 192(%rsp)
	divsd	%xmm3, %xmm8
	movaps	%xmm2, %xmm3
	addsd	%xmm2, %xmm3
	movsd	%xmm6, 200(%rsp)
	divsd	%xmm2, %xmm1
	movsd	24(%rsp), %xmm2
	mulsd	%xmm2, %xmm12
	mulsd	%xmm2, %xmm11
	mulsd	%xmm2, %xmm14
	movsd	%xmm8, 208(%rsp)
	divsd	%xmm3, %xmm13
	movaps	%xmm8, %xmm3
	mulsd	%xmm2, %xmm3
	movsd	%xmm1, 224(%rsp)
	movsd	%xmm13, 216(%rsp)
	mulsd	%xmm2, %xmm13
	movsd	%xmm12, 232(%rsp)
	addsd	%xmm12, %xmm12
	movsd	%xmm11, 240(%rsp)
	movaps	%xmm4, %xmm11
	movsd	%xmm3, 264(%rsp)
	mulsd	%xmm2, %xmm11
	addsd	%xmm3, %xmm3
	mulsd	.LC37(%rip), %xmm2
	movsd	%xmm14, 256(%rsp)
	movsd	%xmm13, 272(%rsp)
	movsd	%xmm3, 296(%rsp)
	movaps	%xmm7, %xmm3
	movsd	%xmm12, 280(%rsp)
	mulsd	%xmm0, %xmm3
	movsd	%xmm11, 248(%rsp)
	addsd	%xmm11, %xmm11
	movsd	%xmm2, 304(%rsp)
	mulsd	%xmm2, %xmm9
	movsd	%xmm2, 312(%rsp)
	mulsd	%xmm2, %xmm10
	mulsd	.LC38(%rip), %xmm2
	movsd	%xmm11, 288(%rsp)
	movsd	%xmm3, 344(%rsp)
	movsd	%xmm8, 448(%rsp)
	movsd	%xmm9, 328(%rsp)
	movsd	.LC39(%rip), %xmm9
	movsd	%xmm10, 320(%rsp)
	movsd	%xmm2, 336(%rsp)
	movaps	%xmm6, %xmm2
	movsd	%xmm8, 456(%rsp)
	mulsd	%xmm0, %xmm2
	movsd	%xmm8, 464(%rsp)
	mulsd	%xmm1, %xmm0
	mulsd	%xmm9, %xmm5
	mulsd	%xmm9, %xmm4
	movsd	%xmm2, 352(%rsp)
	movsd	%xmm0, 360(%rsp)
	movsd	%xmm5, 368(%rsp)
	movsd	%xmm5, 376(%rsp)
	movsd	%xmm5, 384(%rsp)
	movsd	%xmm5, 392(%rsp)
	movsd	%xmm5, 400(%rsp)
	movsd	%xmm4, 408(%rsp)
	movsd	%xmm4, 416(%rsp)
	movsd	%xmm4, 424(%rsp)
	movsd	%xmm4, 432(%rsp)
	movsd	%xmm4, 440(%rsp)
	movaps	%xmm3, %xmm4
	movsd	%xmm8, 472(%rsp)
	movsd	.LC40(%rip), %xmm9
	movsd	.LC41(%rip), %xmm5
	movsd	%xmm8, 480(%rsp)
	movaps	%xmm3, %xmm8
	mulsd	%xmm9, %xmm4
	movq	%rax, 672(%rsp)
	mulsd	%xmm7, %xmm4
	movsd	%xmm4, 488(%rsp)
	movaps	%xmm7, %xmm4
	mulsd	%xmm3, %xmm4
	movsd	%xmm4, 496(%rsp)
	movaps	%xmm3, %xmm4
	mulsd	%xmm5, %xmm4
	mulsd	%xmm7, %xmm4
	movsd	%xmm4, 504(%rsp)
	movsd	.LC42(%rip), %xmm4
	mulsd	%xmm4, %xmm8
	mulsd	%xmm7, %xmm8
	movsd	%xmm8, 512(%rsp)
	movsd	.LC43(%rip), %xmm8
	mulsd	%xmm8, %xmm3
	mulsd	%xmm7, %xmm3
	movsd	%xmm3, 520(%rsp)
	movaps	%xmm2, %xmm3
	mulsd	%xmm9, %xmm3
	mulsd	%xmm0, %xmm9
	mulsd	%xmm6, %xmm3
	mulsd	%xmm1, %xmm9
	movsd	%xmm3, 528(%rsp)
	movaps	%xmm6, %xmm3
	movsd	%xmm9, 568(%rsp)
	mulsd	%xmm2, %xmm3
	movsd	%xmm3, 536(%rsp)
	movaps	%xmm2, %xmm3
	mulsd	%xmm5, %xmm3
	mulsd	%xmm0, %xmm5
	mulsd	%xmm6, %xmm3
	mulsd	%xmm1, %xmm5
	movsd	%xmm3, 544(%rsp)
	movaps	%xmm2, %xmm3
	movsd	%xmm5, 584(%rsp)
	mulsd	%xmm8, %xmm2
	mulsd	%xmm4, %xmm3
	mulsd	%xmm0, %xmm4
	mulsd	%xmm6, %xmm2
	mulsd	%xmm6, %xmm3
	mulsd	%xmm1, %xmm4
	movsd	%xmm2, 560(%rsp)
	movaps	%xmm1, %xmm2
	movsd	%xmm3, 552(%rsp)
	mulsd	%xmm0, %xmm2
	movsd	%xmm4, 592(%rsp)
	mulsd	%xmm8, %xmm0
	movsd	%xmm2, 576(%rsp)
	mulsd	%xmm1, %xmm0
	movsd	%xmm0, 600(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2088, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL2bt(%rip), %rax
	leaq	128(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2089, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dnxm1(%rip), %rax
	leaq	136(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2090, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dnym1(%rip), %rax
	leaq	144(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2091, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dnzm1(%rip), %rax
	leaq	152(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2092, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tx1(%rip), %rax
	leaq	160(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2093, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tx2(%rip), %rax
	leaq	168(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2094, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tx3(%rip), %rax
	leaq	176(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2095, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3ty1(%rip), %rax
	leaq	184(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2096, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3ty2(%rip), %rax
	leaq	192(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2097, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3ty3(%rip), %rax
	leaq	200(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2098, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tz1(%rip), %rax
	leaq	208(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2099, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tz2(%rip), %rax
	leaq	216(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2100, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL3tz3(%rip), %rax
	leaq	224(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2101, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL4dtx1(%rip), %rax
	leaq	232(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2102, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dttx2(%rip), %rax
	leaq	240(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2103, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL4dty1(%rip), %rax
	leaq	248(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2104, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dtty2(%rip), %rax
	leaq	256(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2105, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL4dtz1(%rip), %rax
	leaq	264(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2106, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5dttz2(%rip), %rax
	leaq	272(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2107, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c2dttx1(%rip), %rax
	leaq	280(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2108, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c2dtty1(%rip), %rax
	leaq	288(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2109, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c2dttz1(%rip), %rax
	leaq	296(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2110, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL2dt(%rip), %rax
	leaq	24(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2111, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dtdssp(%rip), %rax
	leaq	304(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2112, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5comz1(%rip), %rax
	leaq	312(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2113, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5comz4(%rip), %rax
	leaq	320(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2114, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5comz5(%rip), %rax
	leaq	328(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2115, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL5comz6(%rip), %rax
	leaq	336(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2116, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c3c4tx3(%rip), %rax
	leaq	344(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2117, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c3c4ty3(%rip), %rax
	leaq	352(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2118, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL7c3c4tz3(%rip), %rax
	leaq	360(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2119, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dx1tx1(%rip), %rax
	leaq	368(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2120, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dx2tx1(%rip), %rax
	leaq	376(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2121, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dx3tx1(%rip), %rax
	leaq	384(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2122, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dx4tx1(%rip), %rax
	leaq	392(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2123, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dx5tx1(%rip), %rax
	leaq	400(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2124, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dy1ty1(%rip), %rax
	leaq	408(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2125, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dy2ty1(%rip), %rax
	leaq	416(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2126, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dy3ty1(%rip), %rax
	leaq	424(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2127, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dy4ty1(%rip), %rax
	leaq	432(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2128, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dy5ty1(%rip), %rax
	leaq	440(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2129, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dz1tz1(%rip), %rax
	leaq	448(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2130, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dz2tz1(%rip), %rax
	leaq	456(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2131, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dz3tz1(%rip), %rax
	leaq	464(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2132, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dz4tz1(%rip), %rax
	leaq	472(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2133, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6dz5tz1(%rip), %rax
	leaq	480(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2134, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6xxcon1(%rip), %rax
	leaq	488(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2135, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6xxcon2(%rip), %rax
	leaq	496(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2136, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6xxcon3(%rip), %rax
	leaq	504(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2137, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6xxcon4(%rip), %rax
	leaq	512(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2138, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6xxcon5(%rip), %rax
	leaq	520(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2139, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6yycon1(%rip), %rax
	leaq	528(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2140, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6yycon2(%rip), %rax
	leaq	536(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2141, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6yycon3(%rip), %rax
	leaq	544(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2142, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6yycon4(%rip), %rax
	leaq	552(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2143, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6yycon5(%rip), %rax
	leaq	560(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2144, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6zzcon1(%rip), %rax
	leaq	568(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2145, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6zzcon2(%rip), %rax
	leaq	576(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2146, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6zzcon3(%rip), %rax
	leaq	584(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2147, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%ecx, %ecx
	movl	$1, %r8d
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6zzcon4(%rip), %rax
	leaq	592(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2148, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%rbx, %rdi
	movl	$8, %edx
	leaq	_ZL6zzcon5(%rip), %rax
	leaq	600(%rsp), %rsi
	movq	%rax, 672(%rsp)
	call	cudaMemcpyToSymbol@PLT
	movl	$2149, %esi
	movl	%eax, %edi
	call	_ZL11HandleError9cudaErrorPKci.constprop.0
	xorl	%esi, %esi
	leaq	656(%rsp), %rdi
	call	gettimeofday@PLT
	movl	12(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	movq	40(%rsp), %rdi
	call	_Z9exact_rhsPdiii
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, 620(%rsp)
	movl	$1, %esi
	movl	%eax, 612(%rsp)
	movl	8(%rsp), %eax
	movl	%eax, 616(%rsp)
	movl	4(%rsp), %eax
	movq	612(%rsp), %rdi
	movl	%eax, 672(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 676(%rsp)
	movl	680(%rsp), %ecx
	movq	672(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L129
	movl	12(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	movq	32(%rsp), %rdi
	call	_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii
.L129:
	pushq	%rdx
	.cfi_def_cfa_offset 1256
	movl	$1, %edi
	pushq	128(%rsp)
	.cfi_def_cfa_offset 1264
	pushq	48(%rsp)
	.cfi_def_cfa_offset 1272
	pushq	64(%rsp)
	.cfi_def_cfa_offset 1280
	pushq	144(%rsp)
	.cfi_def_cfa_offset 1288
	pushq	88(%rsp)
	.cfi_def_cfa_offset 1296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1304
	pushq	144(%rsp)
	.cfi_def_cfa_offset 1312
	pushq	160(%rsp)
	.cfi_def_cfa_offset 1320
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1328
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1336
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1344
	movq	152(%rsp), %r9
	movl	96(%rsp), %r8d
	movl	108(%rsp), %ecx
	movl	104(%rsp), %edx
	movl	100(%rsp), %esi
	call	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	movl	100(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 768(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 772(%rsp)
	movl	776(%rsp), %ecx
	addq	$96, %rsp
	.cfi_def_cfa_offset 1248
	movq	672(%rsp), %rdx
	movq	612(%rsp), %rdi
	movl	620(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L130
	movl	12(%rsp), %ecx
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	movq	32(%rsp), %rdi
	call	_ZL40__device_stub__Z17initialize_kernelPdiiiPdiii
.L130:
	pushq	%rax
	.cfi_def_cfa_offset 1256
	xorl	%edi, %edi
	leaq	_ZSt4cout(%rip), %rbx
	pushq	128(%rsp)
	.cfi_def_cfa_offset 1264
	pushq	48(%rsp)
	.cfi_def_cfa_offset 1272
	pushq	64(%rsp)
	.cfi_def_cfa_offset 1280
	pushq	144(%rsp)
	.cfi_def_cfa_offset 1288
	pushq	88(%rsp)
	.cfi_def_cfa_offset 1296
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1304
	pushq	144(%rsp)
	.cfi_def_cfa_offset 1312
	pushq	160(%rsp)
	.cfi_def_cfa_offset 1320
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1328
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1336
	pushq	152(%rsp)
	.cfi_def_cfa_offset 1344
	movq	152(%rsp), %r9
	movl	96(%rsp), %r8d
	movl	108(%rsp), %ecx
	movl	104(%rsp), %edx
	movl	100(%rsp), %esi
	call	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	addq	$96, %rsp
	.cfi_def_cfa_offset 1248
	xorl	%esi, %esi
	leaq	672(%rsp), %rdi
	call	gettimeofday@PLT
	xorl	%esi, %esi
	leaq	640(%rsp), %rdi
	call	gettimeofday@PLT
	leaq	.LC44(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	648(%rsp), %rax
	subq	632(%rsp), %rax
	cvtsi2sdq	%rax, %xmm0
	movq	640(%rsp), %rax
	mulsd	.LC45(%rip), %xmm0
	subq	624(%rsp), %rax
	cvtsi2sdq	%rax, %xmm1
	addsd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC46(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	680(%rsp), %rax
	subq	664(%rsp), %rax
	cvtsi2sdq	%rax, %xmm0
	movq	672(%rsp), %rax
	mulsd	.LC45(%rip), %xmm0
	subq	656(%rsp), %rax
	cvtsi2sdq	%rax, %xmm1
	addsd	%xmm1, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	1208(%rsp), %rax
	subq	%fs:40, %rax
	je	.L131
	call	__stack_chk_fail@PLT
.L131:
	addq	$1216, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3640:
	.size	main, .-main
	.section	.rodata.str1.1
.LC47:
	.string	"_Z10add_kernelPdS_iii"
.LC48:
	.string	"_Z14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii"
.LC49:
	.string	"_Z14y_solve_kernelPdS_S_S_S_S_iii"
.LC50:
	.string	"_Z14x_solve_kernelPdS_S_S_S_S_iii"
.LC51:
	.string	"_Z13txinvr_kernelPdS_S_S_S_S_S_iii"
.LC52:
	.string	"_Z20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii"
.LC53:
	.string	"_Z20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii"
.LC54:
	.string	"_Z17initialize_kernelPdiii"
.LC55:
	.string	"_Z18exact_rhs_kernel_zPdiii"
.LC56:
	.string	"_Z18exact_rhs_kernel_yPdiii"
.LC57:
	.string	"_Z18exact_rhs_kernel_xPdiii"
.LC58:
	.string	"_Z21exact_rhs_kernel_initPdiii"
.LC59:
	.string	"tx1"
.LC60:
	.string	"tx2"
.LC61:
	.string	"tx3"
.LC62:
	.string	"ty1"
.LC63:
	.string	"ty2"
.LC64:
	.string	"ty3"
.LC65:
	.string	"tz1"
.LC66:
	.string	"tz2"
.LC67:
	.string	"tz3"
.LC68:
	.string	"bt"
.LC69:
	.string	"dt"
.LC70:
	.string	"dtdssp"
.LC71:
	.string	"dnxm1"
.LC72:
	.string	"dnym1"
.LC73:
	.string	"dnzm1"
.LC74:
	.string	"dtx1"
.LC75:
	.string	"dttx2"
.LC76:
	.string	"dty1"
.LC77:
	.string	"dtty2"
.LC78:
	.string	"dtz1"
.LC79:
	.string	"dttz2"
.LC80:
	.string	"c2dttx1"
.LC81:
	.string	"c2dtty1"
.LC82:
	.string	"c2dttz1"
.LC83:
	.string	"comz1"
.LC84:
	.string	"comz4"
.LC85:
	.string	"comz5"
.LC86:
	.string	"comz6"
.LC87:
	.string	"c3c4tx3"
.LC88:
	.string	"c3c4ty3"
.LC89:
	.string	"c3c4tz3"
.LC90:
	.string	"xxcon1"
.LC91:
	.string	"xxcon2"
.LC92:
	.string	"xxcon3"
.LC93:
	.string	"xxcon4"
.LC94:
	.string	"xxcon5"
.LC95:
	.string	"dx1tx1"
.LC96:
	.string	"dx2tx1"
.LC97:
	.string	"dx3tx1"
.LC98:
	.string	"dx4tx1"
.LC99:
	.string	"dx5tx1"
.LC100:
	.string	"yycon1"
.LC101:
	.string	"yycon2"
.LC102:
	.string	"yycon3"
.LC103:
	.string	"yycon4"
.LC104:
	.string	"yycon5"
.LC105:
	.string	"dy1ty1"
.LC106:
	.string	"dy2ty1"
.LC107:
	.string	"dy3ty1"
.LC108:
	.string	"dy4ty1"
.LC109:
	.string	"dy5ty1"
.LC110:
	.string	"zzcon1"
.LC111:
	.string	"zzcon2"
.LC112:
	.string	"zzcon3"
.LC113:
	.string	"zzcon4"
.LC114:
	.string	"zzcon5"
.LC115:
	.string	"dz1tz1"
.LC116:
	.string	"dz2tz1"
.LC117:
	.string	"dz3tz1"
.LC118:
	.string	"dz4tz1"
.LC119:
	.string	"dz5tz1"
.LC120:
	.string	"ce"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3690:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZL10add_kernelPdS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC48(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC49(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL14y_solve_kernelPdS_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC50(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL14x_solve_kernelPdS_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC51(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC52(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC53(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC54(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL17initialize_kernelPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC55(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_ZL18exact_rhs_kernel_zPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC56(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL18exact_rhs_kernel_yPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC57(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL18exact_rhs_kernel_xPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC58(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_ZL21exact_rhs_kernel_initPdiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC59(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL3tx1(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC60(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3tx2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC61(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3tx3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC62(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC63(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3ty2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC64(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3ty3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC65(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC66(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3tz2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC67(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL3tz3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC68(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL2bt(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC69(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL2dt(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC70(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dtdssp(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC71(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dnxm1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC72(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dnym1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC73(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dnzm1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC74(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4dtx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC75(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dttx2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC76(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4dty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC77(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dtty2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC78(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL4dtz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC79(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5dttz2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC80(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c2dttx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC81(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c2dtty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC82(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c2dttz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC83(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5comz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC84(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5comz4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC85(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5comz5(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC86(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5comz6(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC87(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c3c4tx3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC88(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c3c4ty3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC89(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL7c3c4tz3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC90(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6xxcon1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC91(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6xxcon2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC92(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6xxcon3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC93(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6xxcon4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC94(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6xxcon5(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC95(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dx1tx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC96(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dx2tx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC97(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dx3tx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC98(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dx4tx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC99(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dx5tx1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC100(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6yycon1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC101(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6yycon2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC102(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6yycon3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC103(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6yycon4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC104(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6yycon5(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC105(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dy1ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC106(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dy2ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC107(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dy3ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC108(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dy4ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC109(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dy5ty1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC110(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6zzcon1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC111(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6zzcon2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC112(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6zzcon3(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC113(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6zzcon4(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC114(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6zzcon5(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC115(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dz1tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC116(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dz2tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC117(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dz3tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC118(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dz4tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC119(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL6dz5tz1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC120(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$520, %r9d
	leaq	_ZL2ce(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3690:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL2ce
	.comm	_ZL2ce,520,32
	.local	_ZL6dz5tz1
	.comm	_ZL6dz5tz1,8,8
	.local	_ZL6dz4tz1
	.comm	_ZL6dz4tz1,8,8
	.local	_ZL6dz3tz1
	.comm	_ZL6dz3tz1,8,8
	.local	_ZL6dz2tz1
	.comm	_ZL6dz2tz1,8,8
	.local	_ZL6dz1tz1
	.comm	_ZL6dz1tz1,8,8
	.local	_ZL6zzcon5
	.comm	_ZL6zzcon5,8,8
	.local	_ZL6zzcon4
	.comm	_ZL6zzcon4,8,8
	.local	_ZL6zzcon3
	.comm	_ZL6zzcon3,8,8
	.local	_ZL6zzcon2
	.comm	_ZL6zzcon2,8,8
	.local	_ZL6zzcon1
	.comm	_ZL6zzcon1,8,8
	.local	_ZL6dy5ty1
	.comm	_ZL6dy5ty1,8,8
	.local	_ZL6dy4ty1
	.comm	_ZL6dy4ty1,8,8
	.local	_ZL6dy3ty1
	.comm	_ZL6dy3ty1,8,8
	.local	_ZL6dy2ty1
	.comm	_ZL6dy2ty1,8,8
	.local	_ZL6dy1ty1
	.comm	_ZL6dy1ty1,8,8
	.local	_ZL6yycon5
	.comm	_ZL6yycon5,8,8
	.local	_ZL6yycon4
	.comm	_ZL6yycon4,8,8
	.local	_ZL6yycon3
	.comm	_ZL6yycon3,8,8
	.local	_ZL6yycon2
	.comm	_ZL6yycon2,8,8
	.local	_ZL6yycon1
	.comm	_ZL6yycon1,8,8
	.local	_ZL6dx5tx1
	.comm	_ZL6dx5tx1,8,8
	.local	_ZL6dx4tx1
	.comm	_ZL6dx4tx1,8,8
	.local	_ZL6dx3tx1
	.comm	_ZL6dx3tx1,8,8
	.local	_ZL6dx2tx1
	.comm	_ZL6dx2tx1,8,8
	.local	_ZL6dx1tx1
	.comm	_ZL6dx1tx1,8,8
	.local	_ZL6xxcon5
	.comm	_ZL6xxcon5,8,8
	.local	_ZL6xxcon4
	.comm	_ZL6xxcon4,8,8
	.local	_ZL6xxcon3
	.comm	_ZL6xxcon3,8,8
	.local	_ZL6xxcon2
	.comm	_ZL6xxcon2,8,8
	.local	_ZL6xxcon1
	.comm	_ZL6xxcon1,8,8
	.local	_ZL7c3c4tz3
	.comm	_ZL7c3c4tz3,8,8
	.local	_ZL7c3c4ty3
	.comm	_ZL7c3c4ty3,8,8
	.local	_ZL7c3c4tx3
	.comm	_ZL7c3c4tx3,8,8
	.local	_ZL5comz6
	.comm	_ZL5comz6,8,8
	.local	_ZL5comz5
	.comm	_ZL5comz5,8,8
	.local	_ZL5comz4
	.comm	_ZL5comz4,8,8
	.local	_ZL5comz1
	.comm	_ZL5comz1,8,8
	.local	_ZL7c2dttz1
	.comm	_ZL7c2dttz1,8,8
	.local	_ZL7c2dtty1
	.comm	_ZL7c2dtty1,8,8
	.local	_ZL7c2dttx1
	.comm	_ZL7c2dttx1,8,8
	.local	_ZL5dttz2
	.comm	_ZL5dttz2,8,8
	.local	_ZL4dtz1
	.comm	_ZL4dtz1,8,8
	.local	_ZL5dtty2
	.comm	_ZL5dtty2,8,8
	.local	_ZL4dty1
	.comm	_ZL4dty1,8,8
	.local	_ZL5dttx2
	.comm	_ZL5dttx2,8,8
	.local	_ZL4dtx1
	.comm	_ZL4dtx1,8,8
	.local	_ZL5dnzm1
	.comm	_ZL5dnzm1,8,8
	.local	_ZL5dnym1
	.comm	_ZL5dnym1,8,8
	.local	_ZL5dnxm1
	.comm	_ZL5dnxm1,8,8
	.local	_ZL6dtdssp
	.comm	_ZL6dtdssp,8,8
	.local	_ZL2dt
	.comm	_ZL2dt,8,8
	.local	_ZL2bt
	.comm	_ZL2bt,8,8
	.local	_ZL3tz3
	.comm	_ZL3tz3,8,8
	.local	_ZL3tz2
	.comm	_ZL3tz2,8,8
	.local	_ZL3tz1
	.comm	_ZL3tz1,8,8
	.local	_ZL3ty3
	.comm	_ZL3ty3,8,8
	.local	_ZL3ty2
	.comm	_ZL3ty2,8,8
	.local	_ZL3ty1
	.comm	_ZL3ty1,8,8
	.local	_ZL3tx3
	.comm	_ZL3tx3,8,8
	.local	_ZL3tx2
	.comm	_ZL3tx2,8,8
	.local	_ZL3tx1
	.comm	_ZL3tx1,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	-343597384
	.long	1066317905
	.align 8
.LC4:
	.long	-1133871366
	.long	1062769524
	.align 8
.LC5:
	.long	-755914244
	.long	1062232653
	.align 8
.LC6:
	.long	189665756
	.long	1061549150
	.align 8
.LC7:
	.long	810889825
	.long	1060350250
	.align 8
.LC8:
	.long	-350469331
	.long	1058682594
	.align 8
.LC20:
	.long	0
	.long	1073741824
	.align 8
.LC22:
	.long	0
	.long	1074790400
	.align 8
.LC23:
	.long	0
	.long	1075052544
	.align 8
.LC24:
	.long	0
	.long	1074266112
	.align 8
.LC25:
	.long	0
	.long	1071644672
	.align 8
.LC26:
	.long	1202590843
	.long	1066695393
	.align 8
.LC27:
	.long	1202590843
	.long	1065646817
	.align 8
.LC28:
	.long	-343597384
	.long	1067366481
	.align 8
.LC29:
	.long	-1717986918
	.long	1071225241
	.align 8
.LC30:
	.long	858993459
	.long	1070805811
	.align 8
.LC31:
	.long	0
	.long	1072693248
	.align 8
.LC32:
	.long	1202590843
	.long	1067743969
	.align 8
.LC33:
	.long	-1717986918
	.long	1068079513
	.align 8
.LC34:
	.long	-1717986918
	.long	1070176665
	.align 8
.LC35:
	.long	-1717986918
	.long	1069128089
	.align 8
.LC36:
	.long	1719614413
	.long	1072079006
	.align 8
.LC37:
	.long	0
	.long	1070596096
	.align 8
.LC38:
	.long	0
	.long	1075314688
	.align 8
.LC39:
	.long	0
	.long	1072168960
	.align 8
.LC40:
	.long	1431655765
	.long	1073042773
	.align 8
.LC41:
	.long	-343597386
	.long	-1074874287
	.align 8
.LC42:
	.long	1431655765
	.long	1069897045
	.align 8
.LC43:
	.long	-171798693
	.long	1073699880
	.align 8
.LC45:
	.long	-1598689907
	.long	1051772663
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
#include <hip/hip_runtime.h>

#include <sys/time.h>
#define NPB_VERSION "3.3.1"

using namespace std;

#define min(x,y) (x) <= (y) ? (x) : (y)
#define max(x,y) (x) >= (y) ? (x) : (y)

// block sizes for CUDA kernels
#define NORM_BLOCK 32
#define SOLVE_BLOCK 32
#define ERHS_BLOCK 32

// timer constants
#define t_total 0
#define t_rhsx 1
#define t_rhsy 2
#define t_rhsz 3
#define t_rhs 4
#define t_xsolve 5
#define t_ysolve 6
#define t_zsolve 7
#define t_rdis1 8
#define t_rdis2 9
#define t_txinvr 10
#define t_pinvr 11
#define t_ninvr 12
#define t_tzetar 13
#define t_add 14
#define t_last 15


//---------------------------------------------------------------------
// diffusion coefficients
//---------------------------------------------------------------------
#define dx1 0.75
#define dx2 0.75
#define dx3 0.75
#define dx4 0.75
#define dx5 0.75
#define dy1 0.75
#define dy2 0.75
#define dy3 0.75
#define	dy4 0.75
#define dy5 0.75
#define dz1 1.0
#define dz2 1.0
#define dz3 1.0
#define dz4 1.0
#define dz5 1.0
//#define dxmax max(dx3,dx4)
//#define dymax max(dy2,dy4)
//#define dzmax max(dz2,dz3)
#define dxmax dx3
#define dymax dy2
#define dzmax dz2
//---------------------------------------------------------------------
//   fourth difference dissipation
//---------------------------------------------------------------------
#define dssp (max(max(dx1,dy1),dz1)*.25)
#define c4dssp (4.0*dssp)
#define c5dssp (5.0*dssp)

#define c1 1.4
#define c2 0.4
#define	c3 0.1
#define c4 1.0
#define c5 1.4
#define c1c2 (c1*c2)
#define c1c5 (c1*c5)
#define c3c4 (c3*c4)
#define c1345 (c1c5*c3c4)
#define conz1 (1.0-c1c5)
#define c2iv 2.5
#define con43 (4.0/3.0)
#define con16 (1.0/6.0)

// macros to linearize multidimensional array accesses 
#define fu(m,i,j,k) fu[(i)+nx*((j)+ny*((k)+nz*(m)))]
#define forcing(m,i,j,k) forcing[(i)+nx*((j)+ny*((k)+nz*(m)))]
#define rhs(m,i,j,k) rhs[m+(i)*5+(j)*5*nx+(k)*5*nx*ny]
#define rho_i(i,j,k) rho_i[i+(j)*nx+(k)*nx*ny]
#define us(i,j,k) us[i+(j)*nx+(k)*nx*ny]
#define vs(i,j,k) vs[i+(j)*nx+(k)*nx*ny]
#define ws(i,j,k) ws[i+(j)*nx+(k)*nx*ny]
#define square(i,j,k) square[i+(j)*nx+(k)*nx*ny]
#define qs(i,j,k) qs[i+(j)*nx+(k)*nx*ny]
#define speed(i,j,k) speed[i+(j)*nx+(k)*nx*ny]

static void inline HandleError( hipError_t err, const char *file, int line ) {
	if (err != hipSuccess) {
		printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
		exit( EXIT_FAILURE );
	}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))

__constant__ double tx1, tx2, tx3, ty1, ty2, ty3, tz1, tz2, tz3;
__constant__ double bt, dt, dtdssp;
__constant__ double dnxm1, dnym1, dnzm1;
__constant__ double dtx1, dttx2, dty1, dtty2, dtz1, dttz2, c2dttx1, c2dtty1, c2dttz1;
__constant__ double comz1, comz4, comz5, comz6, c3c4tx3, c3c4ty3, c3c4tz3;
__constant__ double xxcon1, xxcon2, xxcon3, xxcon4, xxcon5, dx1tx1, dx2tx1, dx3tx1, dx4tx1, dx5tx1;
__constant__ double yycon1, yycon2, yycon3, yycon4, yycon5, dy1ty1, dy2ty1, dy3ty1, dy4ty1, dy5ty1;
__constant__ double zzcon1, zzcon2, zzcon3, zzcon4, zzcon5, dz1tz1, dz2tz1, dz3tz1, dz4tz1, dz5tz1;
__constant__ double ce[13][5];


//---------------------------------------------------------------------
// exact_rhs computation
//---------------------------------------------------------------------
__device__ static void exact_solution_kernel (const double xi, const double eta, const double zta, double *dtemp) {
	for (int m = 0; m < 5; m++)
		dtemp[m] = ce[0][m] + xi*(ce[1][m] + xi*(ce[4][m] + xi*(ce[7][m] + xi*ce[10][m]))) +
				eta*(ce[2][m] + eta*(ce[5][m] + eta*(ce[8][m] + eta*ce[11][m])))+
				zta*(ce[3][m] + zta*(ce[6][m] + zta*(ce[9][m] + zta*ce[12][m])));
}

__global__ static void exact_rhs_kernel_init (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	for (m = 0; m < 5; m++) forcing(m,i,j,k) = (double)0.0;
}

__global__ static void exact_rhs_kernel_x (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtemp[5], dtpp;
	double ue[5][5], buf[3][5], cuf[3], q[3];

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	j = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || j >= ny-1) return;

	zta = (double)k * dnzm1;
	eta = (double)j * dnym1;
	//---------------------------------------------------------------------
	//      xi-direction flux differences                      
	//---------------------------------------------------------------------
	for (i = 0; i < 3; i++) {
		xi = (double)i * dnxm1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[i+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[i][m] = dtpp*dtemp[m];
		cuf[i] = buf[i][1] * buf[i][1];
		buf[i][0] = cuf[i] + buf[i][2] * buf[i][2] + buf[i][3] * buf[i][3];
		q[i] = 0.5 * (buf[i][1]*ue[i+1][1] + buf[i][2]*ue[i+1][2] + buf[i][3]*ue[i+1][3]);
	}
	for (i = 1; i < nx-1; i++) {
		if (i+2 < nx) {
			xi = (double)(i+2) * dnxm1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}
		
		dtemp[0] = 0.0 - tx2*(ue[3][1]-ue[1][1])+ dx1tx1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = 0.0 - tx2*((ue[3][1]*buf[2][1]+c2*(ue[3][4]-q[2]))-(ue[1][1]*buf[0][1]+c2*(ue[1][4]-q[0])))+xxcon1*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dx2tx1*(ue[3][1]-2.0*ue[2][1]+ue[1][1]);
		dtemp[2] = 0.0 - tx2*(ue[3][2]*buf[2][1]-ue[1][2]*buf[0][1])+xxcon2*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dx3tx1*(ue[3][2]-2.0*ue[2][2]+ue[1][2]);
		dtemp[3] = 0.0 - tx2*(ue[3][3]*buf[2][1]-ue[1][3]*buf[0][1])+xxcon2*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dx4tx1*(ue[3][3]-2.0*ue[2][3]+ue[1][3]);
		dtemp[4] = 0.0 - tx2*(buf[2][1]*(c1*ue[3][4]-c2*q[2])-buf[0][1]*(c1*ue[1][4]-c2*q[0]))+0.5*xxcon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+xxcon4*(cuf[2]-2.0*cuf[1]+cuf[0])+
					xxcon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dx5tx1*(ue[3][4]-2.0*ue[2][4]+ ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation                         
		//---------------------------------------------------------------------
		if (i == 1) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(5.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i == 2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i >= 3 && i < nx-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m]+6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (i == nx-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] +6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (i == nx-2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] + 5.0*ue[2][m]);
		}

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (i < nx-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp*ue[3][m];
			cuf[2] = buf[2][1] * buf[2][1];
			buf[2][0] = cuf[2] + buf[2][2] * buf[2][2] + buf[2][3] * buf[2][3];
			q[2] = 0.5 * (buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

__global__ static void exact_rhs_kernel_y (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtemp[5], dtpp;
	double ue[5][5], buf[3][5], cuf[3], q[3];

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || i >= nx-1) return;

	zta = (double)k * dnzm1;
	xi = (double)i * dnxm1;
	//---------------------------------------------------------------------
	//  eta-direction flux differences             
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) {
		eta = (double)j * dnym1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[j+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[j][m] = dtpp * dtemp[m];
		cuf[j] = buf[j][2] * buf[j][2];
		buf[j][0] = cuf[j] + buf[j][1] * buf[j][1] + buf[j][3] * buf[j][3];
		q[j] = 0.5*(buf[j][1]*ue[j+1][1] + buf[j][2]*ue[j+1][2] + buf[j][3]*ue[j+1][3]);
	}

	for (j = 1; j < ny-1; j++) {
		if (j+2 < ny) {
			eta = (double)(j+2) * dnym1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}

		dtemp[0] = forcing(0,i,j,k) - ty2*(ue[3][2]-ue[1][2])+ dy1ty1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = forcing(1,i,j,k) - ty2*(ue[3][1]*buf[2][2]-ue[1][1]*buf[0][2])+yycon2*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dy2ty1*(ue[3][1]-2.0*ue[2][1]+ ue[1][1]);
		dtemp[2] = forcing(2,i,j,k) - ty2*((ue[3][2]*buf[2][2]+c2*(ue[3][4]-q[2]))-(ue[1][2]*buf[0][2]+c2*(ue[1][4]-q[0])))+yycon1*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dy3ty1*( ue[3][2]-2.0*ue[2][2] +ue[1][2]);
		dtemp[3] = forcing(3,i,j,k) - ty2*(ue[3][3]*buf[2][2]-ue[1][3]*buf[0][2])+yycon2*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dy4ty1*( ue[3][3]-2.0*ue[2][3]+ ue[1][3]);
		dtemp[4] = forcing(4,i,j,k) - ty2*(buf[2][2]*(c1*ue[3][4]-c2*q[2])-buf[0][2]*(c1*ue[1][4]-c2*q[0]))+0.5*yycon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+yycon4*(cuf[2]-2.0*cuf[1]+cuf[0])+
					yycon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dy5ty1*(ue[3][4]-2.0*ue[2][4]+ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation                      
		//---------------------------------------------------------------------
		if (j == 1) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (5.0*ue[2][m] - 4.0*ue[3][m] +ue[4][m]);
		} else if (j == 2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] +       ue[4][m]);
		} else if (j >= 3 && j < ny-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp*(ue[0][m] - 4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m] + ue[4][m]);
		} else if (j == ny-3) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (ue[0][m] - 4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (j == ny-2) {
			for (m = 0; m < 5; m++) forcing(m,i,j,k) = dtemp[m] - dssp * (ue[0][m] - 4.0*ue[1][m] + 5.0*ue[2][m]);
		}

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (j < ny-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp * ue[3][m];
			cuf[2] = buf[2][2] * buf[2][2];
			buf[2][0] = cuf[2] + buf[2][1] * buf[2][1] + buf[2][3] * buf[2][3];
			q[2] = 0.5*(buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

__global__ static void exact_rhs_kernel_z (double *forcing, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, dtpp, dtemp[5];
	double ue[5][5], buf[3][5], cuf[3], q[3];

	j = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (j >= ny-1 || i >= nx-1) return;

	eta = (double)j * dnym1;
	xi = (double)i * dnxm1;
	//---------------------------------------------------------------------
	//      zeta-direction flux differences                      
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) {
		zta = (double)k * dnzm1;
		exact_solution_kernel(xi, eta, zta, dtemp);
		for (m = 0; m < 5; m++) ue[k+1][m] = dtemp[m];
		dtpp = 1.0/dtemp[0];
		for (m = 1; m < 5; m++) buf[k][m] = dtpp * dtemp[m];
		cuf[k] = buf[k][3] * buf[k][3];
		buf[k][0] = cuf[k] + buf[k][1] * buf[k][1] + buf[k][2] * buf[k][2];
		q[k] = 0.5*(buf[k][1]*ue[k+1][1] + buf[k][2]*ue[k+1][2] + buf[k][3]*ue[k+1][3]);
	}

	for (k = 1; k < nz-1; k++) {
		if (k+2 < nz) {
			zta = (double)(k+2) * dnzm1;
			exact_solution_kernel(xi, eta, zta, dtemp);
			for (m = 0; m < 5; m++) ue[4][m] = dtemp[m];
		}

		dtemp[0] = forcing(0,i,j,k) - tz2*(ue[3][3]-ue[1][3])+dz1tz1*(ue[3][0]-2.0*ue[2][0]+ue[1][0]);
		dtemp[1] = forcing(1,i,j,k) - tz2*(ue[3][1]*buf[2][3]-ue[1][1]*buf[0][3])+zzcon2*(buf[2][1]-2.0*buf[1][1]+buf[0][1])+dz2tz1*(ue[3][1]-2.0*ue[2][1]+ue[1][1]);
		dtemp[2] = forcing(2,i,j,k) - tz2*(ue[3][2]*buf[2][3]-ue[1][2]*buf[0][3])+zzcon2*(buf[2][2]-2.0*buf[1][2]+buf[0][2])+dz3tz1*(ue[3][2]-2.0*ue[2][2]+ue[1][2]);
		dtemp[3] = forcing(3,i,j,k) - tz2*((ue[3][3]*buf[2][3]+c2*(ue[3][4]-q[2]))-(ue[1][3]*buf[0][3]+c2*(ue[1][4]-q[0])))+zzcon1*(buf[2][3]-2.0*buf[1][3]+buf[0][3])+dz4tz1*(ue[3][3]-2.0*ue[2][3] +ue[1][3]);
		dtemp[4] = forcing(4,i,j,k) - tz2*(buf[2][3]*(c1*ue[3][4]-c2*q[2])-buf[0][3]*(c1*ue[1][4]-c2*q[0]))+0.5*zzcon3*(buf[2][0]-2.0*buf[1][0]+buf[0][0])+
					zzcon4*(cuf[2]-2.0*cuf[1]+cuf[0])+zzcon5*(buf[2][4]-2.0*buf[1][4]+buf[0][4])+dz5tz1*(ue[3][4]-2.0*ue[2][4]+ue[1][4]);
		//---------------------------------------------------------------------
		//            Fourth-order dissipation
		//---------------------------------------------------------------------
		if (k == 1) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(5.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k == 2) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(-4.0*ue[1][m]+6.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k >= 3 && k < nz-3) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m]+6.0*ue[2][m]-4.0*ue[3][m]+ue[4][m]);
		} else if (k == nz-3) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m] + 6.0*ue[2][m] - 4.0*ue[3][m]);
		} else if (k == nz-2) {
			for (m = 0; m < 5; m++) dtemp[m] = dtemp[m] - dssp*(ue[0][m]-4.0*ue[1][m]+5.0*ue[2][m]);
		}
		//---------------------------------------------------------------------
		// now change the sign of the forcing function, 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) forcing(m,i,j,k) = -1.0 * dtemp[m];

		for (m = 0; m < 5; m++) {
			ue[0][m] = ue[1][m]; 
			ue[1][m] = ue[2][m];
			ue[2][m] = ue[3][m];
			ue[3][m] = ue[4][m];
			buf[0][m] = buf[1][m];
			buf[1][m] = buf[2][m];
		}
		cuf[0] = cuf[1]; cuf[1] = cuf[2];
		q[0] = q[1]; q[1] = q[2];

		if (k < nz-2) {
			dtpp = 1.0/ue[3][0];
			for (m = 1; m < 5; m++) buf[2][m] = dtpp * ue[3][m];
			cuf[2] = buf[2][3] * buf[2][3];
			buf[2][0] = cuf[2] + buf[2][1] * buf[2][1] + buf[2][2] * buf[2][2];
			q[2] = 0.5*(buf[2][1]*ue[3][1] + buf[2][2]*ue[3][2] + buf[2][3]*ue[3][3]);
		}
	}
}

void exact_rhs (double* forcing, int nx, int ny, int nz) {
	dim3 gridinit(ny,nz);
	exact_rhs_kernel_init<<<gridinit,nx>>>(forcing, nx, ny, nz);

	int yblock = min(ERHS_BLOCK,ny);
	int ygrid = (ny+yblock-1)/yblock;
	int zblock_y = min(ERHS_BLOCK/yblock,nz);
	int zgrid_y = (nz+zblock_y-1)/zblock_y;
	dim3 grid_x(zgrid_y,ygrid), block_x(zblock_y,yblock);
	exact_rhs_kernel_x<<<grid_x,block_x>>>(forcing, nx, ny, nz);

	int xblock = min(ERHS_BLOCK,nx);
	int xgrid = (nx+xblock-1)/xblock;
	int zblock_x = min(ERHS_BLOCK/xblock,nz);
	int zgrid_x = (nz+zblock_x-1)/zblock_x;
	dim3 grid_y(zgrid_x,xgrid), block_y(zblock_x,xblock);
	exact_rhs_kernel_y<<<grid_y,block_y>>>(forcing, nx, ny, nz);

	int yblock_x = min(ERHS_BLOCK/xblock,ny);
	int ygrid_x = (ny+yblock_x-1)/yblock_x;
	dim3 grid_z(ygrid_x,xgrid), block_z(yblock_x,xblock);
	exact_rhs_kernel_z<<<grid_z,block_z>>>(forcing, nx, ny, nz);
}


//---------------------------------------------------------------------
// initialize_kernel
//---------------------------------------------------------------------
__global__ static void initialize_kernel (double *fu, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double xi, eta, zta, temp[5];
	double Pface11[5], Pface12[5], Pface21[5], Pface22[5], Pface31[5], Pface32[5];
  double zero, one;

	k = blockIdx.x;
	j = blockIdx.y;
	i = threadIdx.x;

	//---------------------------------------------------------------------
	//  to compute the whole thing with a simple loop. Make sure those 
	//  values are nonzero by initializing the whole thing here. 
	//---------------------------------------------------------------------
	fu(0,i,j,k) = (double)1.0;
	fu(1,i,j,k) = (double)0.0;
	fu(2,i,j,k) = (double)0.0;
	fu(3,i,j,k) = (double)0.0;
	fu(4,i,j,k) = (double)1.0;
  zero = (double)0.0;
  one = (double)1.0;

	//---------------------------------------------------------------------
	// first store the "interpolated" values everywhere on the zone    
	//---------------------------------------------------------------------
	zta = (double)k * dnzm1;
	eta = (double)j * dnym1;
	xi = (double)i * dnxm1;
	exact_solution_kernel (zero, eta, zta, Pface11);
	exact_solution_kernel (one, eta, zta, Pface12);
	exact_solution_kernel (xi, zero, zta, Pface21);
	exact_solution_kernel (xi, one, zta, Pface22);
	exact_solution_kernel (xi, eta, zero, Pface31);
	exact_solution_kernel (xi, eta, one, Pface32);
	for (m = 0; m < 5; m++) {
		double Pxi = xi * Pface12[m] + (1.0-xi)*Pface11[m];
		double Peta = eta * Pface22[m] + (1.0-eta)*Pface21[m];
		double Pzeta = zta * Pface32[m] + (1.0-zta)*Pface31[m];
		fu(m,i,j,k) = Pxi + Peta + Pzeta - Pxi*Peta - Pxi*Pzeta - Peta*Pzeta + Pxi*Peta*Pzeta;
	}

	//---------------------------------------------------------------------
	// now store the exact values on the boundaries        
	//---------------------------------------------------------------------

	//---------------------------------------------------------------------
	// west face                                                  
	//---------------------------------------------------------------------
	xi = (double)0.0;
	if (i == 0) {
		zta = (double)k * dnzm1;
		eta = (double)j * dnym1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// east face                                                      
	//---------------------------------------------------------------------
	xi = (double)1.0;
	if (i == nx-1) {
		zta = (double)k * dnzm1;
		eta = (double)j * dnym1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// south face                                                 
	//---------------------------------------------------------------------
	eta = (double)0.0;
	if (j == 0) {
		zta = (double)k * dnzm1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi,eta,zta,temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// north face                                    
	//---------------------------------------------------------------------
	eta = (double)1.0;
	if (j == ny-1) {
		zta = (double)k * dnzm1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi,eta,zta,temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// bottom face                                       
	//---------------------------------------------------------------------
	zta = (double)0.0;
	if (k == 0) {
		eta = (double)j * dnym1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
	//---------------------------------------------------------------------
	// top face     
	//---------------------------------------------------------------------
	zta = (double)1.0;
	if (k == nz-1) {
		eta = (double)j * dnym1;
		xi = (double)i * dnxm1;
		exact_solution_kernel (xi, eta, zta, temp);
		for (m = 0; m < 5; m++) fu(m,i,j,k) = temp[m];
	}
}

//---------------------------------------------------------------------
// adi: compute_rhs
//---------------------------------------------------------------------
__global__ static void compute_rhs_kernel_1 (double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *square, double *fu, const int nx, const int ny, const int nz) {
	int i, j, k;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	//---------------------------------------------------------------------
	//      compute the reciprocal of density, and the kinetic energy, 
	//      and the speed of sound. 
	//---------------------------------------------------------------------
	double rho_nv = 1.0/fu(0,i,j,k);
	double square_ijk;
	rho_i(i,j,k) = rho_nv;
	us(i,j,k) = fu(1,i,j,k) * rho_nv;
	vs(i,j,k) = fu(2,i,j,k) * rho_nv;
	ws(i,j,k) = fu(3,i,j,k) * rho_nv;
	square_ijk = 0.5*(fu(1,i,j,k)*fu(1,i,j,k) + fu(2,i,j,k)*fu(2,i,j,k) + fu(3,i,j,k)*fu(3,i,j,k)) * rho_nv;
	square(i,j,k) = 0.5*(fu(1,i,j,k)*fu(1,i,j,k) + fu(2,i,j,k)*fu(2,i,j,k) + fu(3,i,j,k)*fu(3,i,j,k)) * rho_nv;
	qs(i,j,k) = square_ijk * rho_nv;
	//---------------------------------------------------------------------
	//               (don't need speed and ainx until the lhs computation)
	//---------------------------------------------------------------------
	speed(i,j,k) = sqrt(c1c2*rho_nv*(fu(4,i,j,k) - square_ijk));
}

__global__ static void compute_rhs_kernel_2 (double *rho_i, double *us, double *vs, double *ws, double *qs, double *square, double *rhs,  double *forcing, double *fu,  int nx, const int ny, const int nz) {
	int i, j, k, m;
	k = blockIdx.y;
	j = blockIdx.x;
	i = threadIdx.x;
	double rtmp[5];

	//---------------------------------------------------------------------
	// copy the exact forcing term to the right hand side;  because 
	// this forcing term is known, we can store it on the whole zone
	// including the boundary                   
	//---------------------------------------------------------------------
	for (m = 0; m < 5; m++) rtmp[m] = forcing(m,i,j,k);
	
	//---------------------------------------------------------------------
	//      compute xi-direction fluxes 
	//---------------------------------------------------------------------
	if (k >= 1 && k < nz-1 && j >= 1 && j < ny-1 && i >= 1 && i < nx-1) {
		double uijk = us(i,j,k);
		double up1 = us(i+1,j,k);
		double um1 = us(i-1,j,k);
				
		rtmp[0] = rtmp[0] + dx1tx1*(fu(0,i+1,j,k) - 2.0*fu(0,i,j,k) + fu(0,i-1,j,k)) - tx2*(fu(1,i+1,j,k)-fu(1,i-1,j,k));
		rtmp[1] = rtmp[1] + dx2tx1*(fu(1,i+1,j,k) - 2.0*fu(1,i,j,k) + fu(1,i-1,j,k)) + xxcon2*con43*(up1-2.0*uijk+um1) - tx2*(fu(1,i+1,j,k)*up1 - fu(1,i-1,j,k)*um1 + (fu(4,i+1,j,k)-square(i+1,j,k)-fu(4,i-1,j,k)+square(i-1,j,k))*c2);
		rtmp[2] = rtmp[2] + dx3tx1*(fu(2,i+1,j,k) - 2.0*fu(2,i,j,k) + fu(2,i-1,j,k)) + xxcon2*(vs(i+1,j,k)-2.0*vs(i,j,k)+vs(i-1,j,k)) - tx2*(fu(2,i+1,j,k)*up1 - fu(2,i-1,j,k)*um1);
		rtmp[3] = rtmp[3] + dx4tx1*(fu(3,i+1,j,k) - 2.0*fu(3,i,j,k) + fu(3,i-1,j,k)) + xxcon2*(ws(i+1,j,k)-2.0*ws(i,j,k)+ws(i-1,j,k)) - tx2*(fu(3,i+1,j,k)*up1 - fu(3,i-1,j,k)*um1);
		rtmp[4] = rtmp[4] + dx5tx1*(fu(4,i+1,j,k) - 2.0*fu(4,i,j,k) + fu(4,i-1,j,k)) + xxcon3*(qs(i+1,j,k)-2.0*qs(i,j,k)+qs(i-1,j,k))+ xxcon4*(up1*up1-2.0*uijk*uijk+um1*um1) +
				xxcon5*(fu(4,i+1,j,k)*rho_i(i+1,j,k) - 2.0*fu(4,i,j,k)*rho_i(i,j,k) + fu(4,i-1,j,k)*rho_i(i-1,j,k)) - tx2*((c1*fu(4,i+1,j,k) - c2*square(i+1,j,k))*up1 - (c1*fu(4,i-1,j,k) - c2*square(i-1,j,k))*um1 );
		//---------------------------------------------------------------------
		//      add fourth order xi-direction dissipation               
		//---------------------------------------------------------------------
		if (i == 1) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (5.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i >= 3 && i < nx-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * ( fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k)+fu(m,i+2,j,k));
		} else if (i == nx-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i+1,j,k) );
		} else if (i == nx-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp * (fu(m,i-2,j,k)-4.0*fu(m,i-1,j,k) + 5.0*fu(m,i,j,k));
		}
		//---------------------------------------------------------------------
		//      compute eta-direction fluxes 
		//---------------------------------------------------------------------
		double vijk = vs(i,j,k);
		double vp1 = vs(i,j+1,k);
		double vm1 = vs(i,j-1,k);
		rtmp[0] = rtmp[0] + dy1ty1*(fu(0,i,j+1,k) - 2.0*fu(0,i,j,k) + fu(0,i,j-1,k)) - ty2*(fu(2,i,j+1,k)-fu(2,i,j-1,k));
		rtmp[1] = rtmp[1] + dy2ty1*(fu(1,i,j+1,k) - 2.0*fu(1,i,j,k) + fu(1,i,j-1,k)) + yycon2*(us(i,j+1,k)-2.0*us(i,j,k)+us(i,j-1,k)) - ty2*(fu(1,i,j+1,k)*vp1-fu(1,i,j-1,k)*vm1);
		rtmp[2] = rtmp[2] + dy3ty1*(fu(2,i,j+1,k) - 2.0*fu(2,i,j,k) + fu(2,i,j-1,k)) + yycon2*con43*(vp1-2.0*vijk+vm1) - ty2*(fu(2,i,j+1,k)*vp1-fu(2,i,j-1,k)*vm1+(fu(4,i,j+1,k)-square(i,j+1,k)-fu(4,i,j-1,k)+square(i,j-1,k))*c2);
		rtmp[3] = rtmp[3] + dy4ty1*(fu(3,i,j+1,k) - 2.0*fu(3,i,j,k) + fu(3,i,j-1,k)) + yycon2*(ws(i,j+1,k)-2.0*ws(i,j,k)+ws(i,j-1,k))-ty2*(fu(3,i,j+1,k)*vp1-fu(3,i,j-1,k)*vm1);
		rtmp[4] = rtmp[4] + dy5ty1*(fu(4,i,j+1,k) - 2.0*fu(4,i,j,k) + fu(4,i,j-1,k)) + yycon3*(qs(i,j+1,k)-2.0*qs(i,j,k)+qs(i,j-1,k)) + yycon4*(vp1*vp1-2.0*vijk*vijk+vm1*vm1) +
				yycon5*(fu(4,i,j+1,k)*rho_i(i,j+1,k)-2.0*fu(4,i,j,k)*rho_i(i,j,k)+fu(4,i,j-1,k)*rho_i(i,j-1,k)) - ty2*((c1*fu(4,i,j+1,k)-c2*square(i,j+1,k))*vp1 - (c1*fu(4,i,j-1,k)-c2*square(i,j-1,k))*vm1);
		//---------------------------------------------------------------------
		//      add fourth order eta-direction dissipation         
		//---------------------------------------------------------------------
		if (j == 1) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(5.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j >= 3 && j < ny-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k)+fu(m,i,j+2,k));
		} else if (j == ny-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j+1,k));
		} else if (j == ny-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j-2,k)-4.0*fu(m,i,j-1,k)+5.0*fu(m,i,j,k));
		}
		//---------------------------------------------------------------------
		//      compute zeta-direction fluxes 
		//---------------------------------------------------------------------
		double wijk = ws(i,j,k);
		double wp1 = ws(i,j,k+1);
		double wm1 = ws(i,j,k-1);

		rtmp[0] = rtmp[0] + dz1tz1*(fu(0,i,j,k+1)-2.0*fu(0,i,j,k)+fu(0,i,j,k-1)) - tz2*(fu(3,i,j,k+1)-fu(3,i,j,k-1));
		rtmp[1] = rtmp[1] + dz2tz1*(fu(1,i,j,k+1)-2.0*fu(1,i,j,k)+fu(1,i,j,k-1)) + zzcon2*(us(i,j,k+1)-2.0*us(i,j,k)+us(i,j,k-1)) - tz2*(fu(1,i,j,k+1)*wp1-fu(1,i,j,k-1)*wm1);
		rtmp[2] = rtmp[2] + dz3tz1*(fu(2,i,j,k+1)-2.0*fu(2,i,j,k)+fu(2,i,j,k-1)) + zzcon2*(vs(i,j,k+1)-2.0*vs(i,j,k)+vs(i,j,k-1)) - tz2*(fu(2,i,j,k+1)*wp1-fu(2,i,j,k-1)*wm1);
		rtmp[3] = rtmp[3] + dz4tz1*(fu(3,i,j,k+1)-2.0*fu(3,i,j,k)+fu(3,i,j,k-1)) + zzcon2*con43*(wp1-2.0*wijk+wm1) - tz2*(fu(3,i,j,k+1)*wp1-fu(3,i,j,k-1)*wm1+(fu(4,i,j,k+1)-square(i,j,k+1)-fu(4,i,j,k-1)+square(i,j,k-1))*c2);
		rtmp[4] = rtmp[4] + dz5tz1*(fu(4,i,j,k+1)-2.0*fu(4,i,j,k)+fu(4,i,j,k-1)) + zzcon3*(qs(i,j,k+1)-2.0*qs(i,j,k)+qs(i,j,k-1)) + zzcon4*(wp1*wp1-2.0*wijk*wijk+wm1*wm1) +
			zzcon5*(fu(4,i,j,k+1)*rho_i(i,j,k+1)-2.0*fu(4,i,j,k)*rho_i(i,j,k)+fu(4,i,j,k-1)*rho_i(i,j,k-1)) - tz2*((c1*fu(4,i,j,k+1)-c2*square(i,j,k+1))*wp1-(c1*fu(4,i,j,k-1)-c2*square(i,j,k-1))*wm1);
		//---------------------------------------------------------------------
		//      add fourth order zeta-direction dissipation                
		//---------------------------------------------------------------------
		if (k == 1) {
			for (m = 0; m < 5; m++)	rtmp[m] = rtmp[m] - dssp*(5.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k == 2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k >= 3 && k < nz-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1)+fu(m,i,j,k+2));
		} else if (k == nz-3) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+6.0*fu(m,i,j,k)-4.0*fu(m,i,j,k+1));
		} else if (k == nz-2) {
			for (m = 0; m < 5; m++) rtmp[m] = rtmp[m] - dssp*(fu(m,i,j,k-2)-4.0*fu(m,i,j,k-1)+5.0*fu(m,i,j,k));
		}

		for (m = 0; m < 5; m++) rtmp[m] *= dt;
	}

	for (m = 0; m < 5; m++) rhs(m,i,j,k) = rtmp[m];
}

//---------------------------------------------------------------------
// adi: txinvr
//---------------------------------------------------------------------
__global__ static void txinvr_kernel ( double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *rhs, const int nx, const int ny, const int nz) {
	int i, j, k;

	k = blockIdx.y+1;
	j = blockIdx.x+1;
	i = threadIdx.x+1;

	double ru1 = rho_i(i,j,k);
	double uu = us(i,j,k);
	double vv = vs(i,j,k);
	double ww = ws(i,j,k);
	double ap = speed(i,j,k);
	double ac2inv = 1.0/( ap*ap );

	double r1 = rhs(0,i,j,k);
	double r2 = rhs(1,i,j,k);
	double r3 = rhs(2,i,j,k);
	double r4 = rhs(3,i,j,k);
	double r5 = rhs(4,i,j,k);

	double t1 = c2*ac2inv*(qs(i,j,k)*r1 - uu*r2  - vv*r3 - ww*r4 + r5);
	double t2 = bt * ru1 * ( uu * r1 - r2 );
	double t3 = ( bt * ru1 * ap ) * t1;

	rhs(0,i,j,k) = r1 - t1;
	rhs(1,i,j,k) = -ru1*(ww*r1-r4);
	rhs(2,i,j,k) = ru1*(vv*r1-r3);
	rhs(3,i,j,k) = -t2+t3;
	rhs(4,i,j,k) = t2+t3;
}

//---------------------------------------------------------------------
// adi: x_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m-3)))]
#define lhsp(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m+4)))]
#define lhsm(m,i,j,k) lhs[(j-1)+(ny-2)*((k-1)+(nz-2)*((i)+nx*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(j)+ny*((k)+nz*((i)+nx*(m)))]
__global__ static void x_solve_kernel (double *rho_i, double *us, double *speed, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhon[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	j = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || j >= ny-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three x-factors  
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,0,j,k) = (double)0.0;
  lhsp(1,0,j,k) = (double)0.0;
  lhsp(2,0,j,k) = (double)1.0;
  lhsp(3,0,j,k) = (double)0.0;
  lhsp(4,0,j,k) = (double)0.0;
  zero = (double)0.0;

	//---------------------------------------------------------------------
	// first fill the lhs for the u-eigenvalue                          
	//--------------------------------------------------------------------
	for (i = 0; i < 3; i++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhon[i] = max(max(max(dx2+con43*fac1, dx5+c1c5*fac1), dxmax+fac1), zero+dx1);
    if (dx2+con43*fac1>dx5+c1c5*fac1)
      rhon[i] = dx2+con43*fac1;
    else
      rhon[i] = dx5+c1c5*fac1;
    if (rhon[i]<dxmax+fac1)
      rhon[i] = dxmax+fac1;
    if (rhon[i]<zero+dx1)
      rhon[i] = zero+dx1;


		cv[i] = us(i,j,k);
	}
	_ls[1][0] = (double)0.0;
	_ls[1][1] = - dttx2 * cv[0] - dtx1 * rhon[0];
	_ls[1][2] = 1.0 + c2dttx1 * rhon[1];
	_ls[1][3] = dttx2 * cv[2] - dtx1 * rhon[2];
	_ls[1][4] = (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,1,j,k) = _ls[1][m];
	rhon[0] = rhon[1]; rhon[1] = rhon[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,0,j,k);
		_rs[1][m] = rhs(m,1,j,k);
	}

	//---------------------------------------------------------------------
	//      perform the Thomas algorithm; first, FORWARD ELIMINATION     
	//---------------------------------------------------------------------
	for (i = 0; i < nx-2; i++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (i+2 == nx-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i+2,j,k) = (double)0.0;
      lhsp(1,i+2,j,k) = (double)0.0;
      lhsp(2,i+2,j,k) = (double)1.0;
      lhsp(3,i+2,j,k) = (double)0.0;
      lhsp(4,i+2,j,k) = (double)0.0;

		} else {
			fac1 = c3c4*rho_i(i+3,j,k);
			//rhon[2] = max(max(max(dx2+con43*fac1, dx5+c1c5*fac1), dxmax+fac1), zero+dx1);
      if (dx2+con43*fac1>dx5+c1c5*fac1)
        rhon[2] = dx2+con43*fac1;
      else
        rhon[2] = dx5+c1c5*fac1;
      if (rhon[2]<dxmax+fac1)
        rhon[2] = dxmax+fac1;
      if (rhon[2]<zero+dx1)
        rhon[2] = zero+dx1;

			cv[2] = us(i+3,j,k);
			_ls[2][0] = (double)0.0;
			_ls[2][1] = - dttx2 * cv[0] - dtx1 * rhon[0];
			_ls[2][2] = 1.0 + c2dttx1 * rhon[1];
			_ls[2][3] = dttx2 * cv[2] - dtx1 * rhon[2];
			_ls[2][4] = (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                                  
			//---------------------------------------------------------------------
			if (i+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (i+2 >= 3 && i+2 < nx-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (i+2 == nx-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (i+2 == nx-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i+2,j,k) = _ls[2][m];
			rhon[0] = rhon[1]; rhon[1] = rhon[2];
			cv[0] = cv[1]; cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i+2,j,k);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}

	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	i = nx-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//            scale the last row immediately 
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,nx-2,j,k) = _ls[0][3];
	lhs(4,nx-2,j,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      subsequently, fill the other factors u+c, u-c 
	//---------------------------------------------------------------------
	for (i = 0; i < 3; i++) cv[i] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,0,j,k);
		_lp[0][m] = lhsp(m,0,j,k);
		_ls[1][m] = lhsp(m,1,j,k);
		_lp[1][m] = lhsp(m,1,j,k);
	}
	_lp[1][1] -= dttx2 * cv[0];
	_lp[1][3] += dttx2 * cv[2];
	_ls[1][1] += dttx2 * cv[0];
	_ls[1][3] -= dttx2 * cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,0,j,k);
	_rs[0][4] = rhs(4,0,j,k);
	_rs[1][3] = rhs(3,1,j,k);
	_rs[1][4] = rhs(4,1,j,k);
	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors               
	//---------------------------------------------------------------------
	for (i = 0; i < nx-2; i++) {
		//---------------------------------------------------------------------
		//      first, fill the other factors u+c, u-c 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i+2,j,k);
			_lp[2][m] = lhsp(m,i+2,j,k);
		}
		_rs[2][3] = rhs(3,i+2,j,k);
		_rs[2][4] = rhs(4,i+2,j,k);

		if (i+2 < nx-1) {
			cv[2] = speed(i+3,j,k);
			_lp[2][1] -= dttx2 * cv[0];
			_lp[2][3] += dttx2 * cv[2];
			_ls[2][1] += dttx2 * cv[0];
			_ls[2][3] -= dttx2 * cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		m = 3;
		fac1 = 1.0/_lp[0][2];
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1]*_lp[0][3];
		_lp[1][3] -= _lp[1][1]*_lp[0][4];
		_rs[1][m] -= _lp[1][1]*_rs[0][m];
		_lp[2][1] -= _lp[2][0]*_lp[0][3];
		_lp[2][2] -= _lp[2][0]*_lp[0][4];
		_rs[2][m] -= _lp[2][0]*_rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1]*_ls[0][3];
		_ls[1][3] -= _ls[1][1]*_ls[0][4];
		_rs[1][m] -= _ls[1][1]*_rs[0][m];
		_ls[2][1] -= _ls[2][0]*_ls[0][3];
		_ls[2][2] -= _ls[2][0]*_ls[0][4];
		_rs[2][m] -= _ls[2][0]*_rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	i = nx-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1]*_lp[0][3];
	_lp[1][3] -= _lp[1][1]*_lp[0][4];
	_rs[1][m] -= _lp[1][1]*_rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1]*_ls[0][3];
	_ls[1][3] -= _ls[1][1]*_ls[0][4];
	_rs[1][m] -= _ls[1][1]*_rs[0][m];

	//---------------------------------------------------------------------
	//               Scale the last row immediately
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];

	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,nx-2,j,k)*_rs[1][m];
	_rs[0][3] -= _lp[0][3]*_rs[1][3];
	_rs[0][4] -= _ls[0][3]*_rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}

	for (i = nx-3; i >= 0; i--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];

		if (i+2 < nx-1) {
			//---------------------------------------------------------------------
			//      Do the block-diagonal inversion          
			//---------------------------------------------------------------------
				double r1 = _rs[2][0];
				double r2 = _rs[2][1];
				double r3 = _rs[2][2];
				double r4 = _rs[2][3];
				double r5 = _rs[2][4];
				double t1 = bt * r3;
				double t2 = 0.5 * (r4+r5);

				_rs[2][0] = -r2;
				_rs[2][1] =  r1;
				_rs[2][2] = bt * ( r4 - r5 );
				_rs[2][3] = -t1 + t2;
				_rs[2][4] =  t1 + t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i+2,j,k) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//      Do the block-diagonal inversion          
	//---------------------------------------------------------------------
	double tf1 = bt * _rs[2][2];
	double tf2 = 0.5 * (_rs[2][3]+_rs[2][4]);
	rhs(0,1,j,k) = -_rs[2][1];
	rhs(1,1,j,k) =  _rs[2][0];
	rhs(2,1,j,k) = bt * ( _rs[2][3] - _rs[2][4] );
	rhs(3,1,j,k) = -tf1 + tf2;
	rhs(4,1,j,k) =  tf1 + tf2;

	for (m = 0; m < 5; m++) rhs(m,0,j,k) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp

//---------------------------------------------------------------------
// adi: y_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m-3)))]
#define lhsp(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m+4)))]
#define lhsm(m,i,j,k) lhs[(i-1)+(nx-2)*((k-1)+(nz-2)*((j)+ny*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(i)+nx*((k)+nz*((j)+ny*(m)))]
__global__ static void y_solve_kernel (double *rho_i, double *vs, double *speed, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhoq[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	k = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (k >= nz-1 || i >= nx-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three y-factors   
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,i,0,k) = (double)0.0;
  lhsp(1,i,0,k) = (double)0.0;
  lhsp(2,i,0,k) = (double)1.0;
  lhsp(3,i,0,k) = (double)0.0;
  lhsp(4,i,0,k) = (double)0.0;
  zero = (double)0.0;


	//---------------------------------------------------------------------
	//      first fill the lhs for the u-eigenvalue         
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhoq[j] = max(max(max(dy3+con43*fac1, dy5+c1c5*fac1), dymax+fac1), zero+dy1);
   if (dy3+con43*fac1>dy5+c1c5*fac1)
     rhoq[j] = dy3+con43*fac1;
   else
     rhoq[j] = dy5+c1c5*fac1;
   if (rhoq[j]<dymax+fac1)
     rhoq[j] = dymax+fac1;
   if (rhoq[j]<zero+dy1)
     rhoq[j] = zero+dy1;
		cv[j] = vs(i,j,k);
	}
	_ls[1][0] =  (double)0.0;
	_ls[1][1] = -dtty2*cv[0]-dty1 * rhoq[0];
	_ls[1][2] =  1.0 + c2dtty1 * rhoq[1];
	_ls[1][3] =  dtty2*cv[2]-dty1 * rhoq[2];
	_ls[1][4] =  (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,i,1,k) = _ls[1][m];
	rhoq[0] = rhoq[1]; 
  rhoq[1] = rhoq[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,i,0,k);
		_rs[1][m] = rhs(m,i,1,k);
	}

	//---------------------------------------------------------------------
	//                          FORWARD ELIMINATION  
	//---------------------------------------------------------------------
	for (j = 0; j < ny-2; j++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (j+2 == ny-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i,j+2,k) = (double)0.0;
      lhsp(1,i,j+2,k) = (double)0.0;
      lhsp(2,i,j+2,k) = (double)1.0;
      lhsp(3,i,j+2,k) = (double)0.0;
      lhsp(4,i,j+2,k) = (double)0.0;
		} else {
			fac1 = c3c4*rho_i(i,j+3,k);
			//rhoq[2] = max(max(max(dy3+con43*fac1, dy5+c1c5*fac1), dymax+fac1), zero+dy1);
      if (dy3+con43*fac1>dy5+c1c5*fac1)
        rhoq[2] = dy3+con43*fac1;
      else
        rhoq[2] = dy5+c1c5*fac1;
      if (rhoq[2]<dymax+fac1)
        rhoq[2] = dymax+fac1;
      if (rhoq[2]<zero+dy1)
        rhoq[2] = zero+dy1;
			cv[2] = vs(i,j+3,k);
			_ls[2][0] =  (double)0.0;
			_ls[2][1] = -dtty2*cv[0]-dty1 * rhoq[0];
			_ls[2][2] =  1.0 + c2dtty1 * rhoq[1];
			_ls[2][3] =  dtty2*cv[2]-dty1 * rhoq[2];
			_ls[2][4] =  (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                             
			//---------------------------------------------------------------------
			if (j+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (j+2 >= 3 && j+2 < ny-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (j+2 == ny-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (j+2 == ny-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i,j+2,k) = _ls[2][m];
			rhoq[0] = rhoq[1]; rhoq[1] = rhoq[2];
			cv[0] = cv[1]; cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i,j+2,k);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}
	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	j = ny-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//            scale the last row immediately 
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,i,ny-2,k) = _ls[0][3];
	lhs(4,i,ny-2,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors                 
	//---------------------------------------------------------------------
	for (j = 0; j < 3; j++) cv[j] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,i,0,k);
		_lp[0][m] = lhsp(m,i,0,k);
		_ls[1][m] = lhsp(m,i,1,k);
		_lp[1][m] = lhsp(m,i,1,k);
	}
	_lp[1][1] -= dtty2*cv[0];
	_lp[1][3] += dtty2*cv[2];
	_ls[1][1] += dtty2*cv[0];
	_ls[1][3] -= dtty2*cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,i,0,k);
	_rs[0][4] = rhs(4,i,0,k);
	_rs[1][3] = rhs(3,i,1,k);
	_rs[1][4] = rhs(4,i,1,k);
	for (j = 0; j < ny-2; j++) {
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i,j+2,k);
			_lp[2][m] = lhsp(m,i,j+2,k);
		}
		_rs[2][3] = rhs(3,i,j+2,k);
		_rs[2][4] = rhs(4,i,j+2,k);
		if (j+2 < ny-1) {
			cv[2] = speed(i,j+3,k);
			_lp[2][1] -= dtty2*cv[0];
			_lp[2][3] += dtty2*cv[2];
			_ls[2][1] += dtty2*cv[0];
			_ls[2][3] -= dtty2*cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		fac1 = 1.0/_lp[0][2];
		m = 3;
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1] * _lp[0][3];
		_lp[1][3] -= _lp[1][1] * _lp[0][4];
		_rs[1][m] -= _lp[1][1] * _rs[0][m];
		_lp[2][1] -= _lp[2][0] * _lp[0][3];
		_lp[2][2] -= _lp[2][0] * _lp[0][4];
		_rs[2][m] -= _lp[2][0] * _rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		_rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		_rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	j = ny-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1] * _lp[0][3];
	_lp[1][3] -= _lp[1][1] * _lp[0][4];
	_rs[1][m] -= _lp[1][1] * _rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	_rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               Scale the last row immediately 
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];

	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,i,ny-2,k) * _rs[1][m];
	_rs[0][3] -= _lp[0][3] * _rs[1][3];
	_rs[0][4] -= _ls[0][3] * _rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}
	for (j = ny-3; j >= 0; j--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];
	
		if (j+2 < ny-1) {
			//---------------------------------------------------------------------
			//   block-diagonal matrix-vector multiplication                       
			//---------------------------------------------------------------------
			double r1 = _rs[2][0];
			double r2 = _rs[2][1];
			double r3 = _rs[2][2];
			double r4 = _rs[2][3];
			double r5 = _rs[2][4];

			double t1 = bt * r1;
			double t2 = 0.5 * ( r4 + r5 );

			_rs[2][0] =  bt * ( r4 - r5 );
			_rs[2][1] = -r3;
			_rs[2][2] =  r2;
			_rs[2][3] = -t1 + t2;
			_rs[2][4] =  t1 + t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i,j+2,k) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//   block-diagonal matrix-vector multiplication                       
	//---------------------------------------------------------------------
	double tf1 = bt * _rs[2][0];
	double tf2 = 0.5 * ( _rs[2][3] + _rs[2][4] );
	rhs(0,i,1,k) =  bt * ( _rs[2][3] - _rs[2][4] );
	rhs(1,i,1,k) = -_rs[2][2];
	rhs(2,i,1,k) =  _rs[2][1];
	rhs(3,i,1,k) = -tf1 + tf2;
	rhs(4,i,1,k) =  tf1 + tf2;

	for (m = 0; m < 5; m++) rhs(m,i,0,k) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp

//---------------------------------------------------------------------
// adi: z_solve
//---------------------------------------------------------------------
#define lhs(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m-3)))]
#define lhsp(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m+4)))]
#define lhsm(m,i,j,k) lhs[(i-1)+(nx-2)*((j-1)+(ny-2)*((k)+nz*(m-3+2)))]
#define rtmp(m,i,j,k) rstmp[(i)+nx*((j)+ny*((k)+nz*(m)))]
__global__ static void z_solve_kernel (double *rho_i, double *us, double *vs, double *ws, double *speed, double *qs, double *fu, double *rhs, double *lhs, double *rstmp, const int nx, const int ny, const int nz) {
	int i, j, k, m;
	double rhos[3], cv[3], _ls[3][5], _lp[3][5], _rs[3][5], fac1;
  double zero;

	j = blockIdx.x*blockDim.x+threadIdx.x+1;
	i = blockIdx.y*blockDim.y+threadIdx.y+1;
	if (j >= ny-1 || i >= nx-1) return;

	//---------------------------------------------------------------------
	// Computes the left hand side for the three z-factors   
	//---------------------------------------------------------------------
	//---------------------------------------------------------------------
	//     zap the whole left hand side for starters
	//---------------------------------------------------------------------
	_ls[0][0] = (double)0.0;
	_ls[0][1] = (double)0.0;
	_ls[0][2] = (double)1.0;
	_ls[0][3] = (double)0.0;
	_ls[0][4] = (double)0.0;
  lhsp(0,i,j,0) = (double)0.0;
  lhsp(1,i,j,0) = (double)0.0;
  lhsp(2,i,j,0) = (double)1.0;
  lhsp(3,i,j,0) = (double)0.0;
  lhsp(4,i,j,0) = (double)0.0;
  zero = (double)0.0;

	//---------------------------------------------------------------------
	// first fill the lhs for the u-eigenvalue                          
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) {
		fac1 = c3c4*rho_i(i,j,k);
		//rhos[k] = max(max(max(dz4+con43*fac1, dz5+c1c5*fac1), dzmax+fac1), zero+dz1);
    if (dz4+con43*fac1>dz5+c1c5*fac1)
      rhos[k] = dz4+con43*fac1;
    else
      rhos[k] = dz5+c1c5*fac1;
    if (rhos[k]<dzmax+fac1)
      rhos[k] = dzmax+fac1;
    if (rhos[k]<zero+dz1)
      rhos[k] = zero+dz1;
		cv[k] = ws(i,j,k);
	}
	_ls[1][0] =  (double)0.0;
	_ls[1][1] = -dttz2*cv[0] - dtz1*rhos[0];
	_ls[1][2] =  1.0 + c2dttz1 * rhos[1];
	_ls[1][3] =  dttz2*cv[2] - dtz1*rhos[2];
	_ls[1][4]=  (double)0.0;
	_ls[1][2] += comz5;
	_ls[1][3] -= comz4;
	_ls[1][4] += comz1;
	for (m = 0; m < 5; m++) lhsp(m,i,j,1) = _ls[1][m];
	rhos[0] = rhos[1]; rhos[1] = rhos[2];
	cv[0] = cv[1]; cv[1] = cv[2];
	for (m = 0; m < 3; m++) {
		_rs[0][m] = rhs(m,i,j,0);
		_rs[1][m] = rhs(m,i,j,1);
	}

	//---------------------------------------------------------------------
	//                          FORWARD ELIMINATION  
	//---------------------------------------------------------------------
	for (k = 0; k < nz-2; k++) {
		//---------------------------------------------------------------------
		// first fill the lhs for the u-eigenvalue                          
		//---------------------------------------------------------------------
		if (k+2 == nz-1) {
			_ls[2][0] = (double)0.0;
			_ls[2][1] = (double)0.0;
			_ls[2][2] = (double)1.0;
			_ls[2][3] = (double)0.0;
			_ls[2][4] = (double)0.0;
      lhsp(0,i,j,k+2) = (double)0.0;
      lhsp(1,i,j,k+2) = (double)0.0;
      lhsp(2,i,j,k+2) = (double)1.0;
      lhsp(3,i,j,k+2) = (double)0.0;
      lhsp(4,i,j,k+2) = (double)0.0;
		} else {
			fac1 = c3c4*rho_i(i,j,k+3);
			//rhos[2] = max(max(max(dz4+con43*fac1, dz5+c1c5*fac1), dzmax+fac1), zero+dz1);
      if (dz4+con43*fac1>dz5+c1c5*fac1)
        rhos[2] = dz4+con43*fac1;
      else
        rhos[2] = dz5+c1c5*fac1;
      if (rhos[2]<dzmax+fac1)
        rhos[2] = dzmax+fac1;
      if (rhos[2]<zero+dz1)
        rhos[2] = zero+dz1;
			cv[2] = ws(i,j,k+3);
			_ls[2][0] =  (double)0.0;
			_ls[2][1] = -dttz2*cv[0] - dtz1*rhos[0];
			_ls[2][2] =  1.0 + c2dttz1 * rhos[1];
			_ls[2][3] =  dttz2*cv[2] - dtz1*rhos[2];
			_ls[2][4] =  (double)0.0;
			//---------------------------------------------------------------------
			//      add fourth order dissipation                                  
			//---------------------------------------------------------------------
			if (k+2 == 2) {
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (k+2 >= 3 && k+2 < nz-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
				_ls[2][4] += comz1;
			} else if (k+2 == nz-3) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz6;
				_ls[2][3] -= comz4;
			} else if (k+2 == nz-2) {
				_ls[2][0] += comz1;
				_ls[2][1] -= comz4;
				_ls[2][2] += comz5;
			}

			//---------------------------------------------------------------------
			//      store computed lhs for later reuse
			//---------------------------------------------------------------------
			for (m = 0; m < 5; m++) lhsp(m,i,j,k+2) = _ls[2][m];
			rhos[0] = rhos[1]; rhos[1] = rhos[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		//---------------------------------------------------------------------
		//      load rhs values for current iteration
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[2][m] = rhs(m,i,j,k+2);

		//---------------------------------------------------------------------
		//      perform current iteration
		//---------------------------------------------------------------------
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		for (m = 0; m < 3; m++) _rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		lhs(3,i,j,k) = _ls[0][3];
		lhs(4,i,j,k) = _ls[0][4];
		for (m = 0; m < 5; m++) {
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
		for (m = 0; m < 3; m++) {
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
	}
	//---------------------------------------------------------------------
	//      The last two rows in this zone are a bit different, 
	//      since they do not have two more rows available for the
	//      elimination of off-diagonal entries
	//---------------------------------------------------------------------
	k = nz-2;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	for (m = 0; m < 3; m++) _rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	for (m = 0; m < 3; m++) _rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               scale the last row immediately
	//---------------------------------------------------------------------
	fac1 = 1.0/_ls[1][2];
	for (m = 0; m < 3; m++) _rs[1][m] *= fac1;
	lhs(3,i,j,k) = _ls[0][3];
	lhs(4,i,j,k) = _ls[0][4];

	//---------------------------------------------------------------------
	//      subsequently, fill the other factors u+c, u-c 
	//---------------------------------------------------------------------
	for (k = 0; k < 3; k++) cv[k] = speed(i,j,k);
	for (m = 0; m < 5; m++) {
		_ls[0][m] = lhsp(m,i,j,0);
		_lp[0][m] = lhsp(m,i,j,0);
		_ls[1][m] = lhsp(m,i,j,1);
		_lp[1][m] = lhsp(m,i,j,1);
	}
	_lp[1][1] -= dttz2*cv[0];
	_lp[1][3] += dttz2*cv[2];
	_ls[1][1] += dttz2*cv[0];
	_ls[1][3] -= dttz2*cv[2];
	cv[0] = cv[1]; 
  cv[1] = cv[2];
	_rs[0][3] = rhs(3,i,j,0);
	_rs[0][4] = rhs(4,i,j,0);
	_rs[1][3] = rhs(3,i,j,1);
	_rs[1][4] = rhs(4,i,j,1);
	//---------------------------------------------------------------------
	//      do the u+c and the u-c factors               
	//---------------------------------------------------------------------
	for (k = 0; k < nz-2; k++) {
		//---------------------------------------------------------------------
		//      first, fill the other factors u+c, u-c 
		//---------------------------------------------------------------------
		for (m = 0; m < 5; m++) {
			_ls[2][m] = lhsp(m,i,j,k+2);
			_lp[2][m] = lhsp(m,i,j,k+2);
		}
		_rs[2][3] = rhs(3,i,j,k+2);
		_rs[2][4] = rhs(4,i,j,k+2);
		if (k+2 < nz-1) {
			cv[2] = speed(i,j,k+3);
			_lp[2][1] -= dttz2*cv[0];
			_lp[2][3] += dttz2*cv[2];
			_ls[2][1] += dttz2*cv[0];
			_ls[2][3] -= dttz2*cv[2];
			cv[0] = cv[1]; 
      cv[1] = cv[2];
		}

		m = 3;
		fac1 = 1.0/_lp[0][2];
		_lp[0][3] *= fac1;
		_lp[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_lp[1][2] -= _lp[1][1] * _lp[0][3];
		_lp[1][3] -= _lp[1][1] * _lp[0][4];
		_rs[1][m] -= _lp[1][1] * _rs[0][m];
		_lp[2][1] -= _lp[2][0] * _lp[0][3];
		_lp[2][2] -= _lp[2][0] * _lp[0][4];
		_rs[2][m] -= _lp[2][0] * _rs[0][m];

		m = 4;
		fac1 = 1.0/_ls[0][2];
		_ls[0][3] *= fac1;
		_ls[0][4] *= fac1;
		_rs[0][m] *= fac1;
		_ls[1][2] -= _ls[1][1] * _ls[0][3];
		_ls[1][3] -= _ls[1][1] * _ls[0][4];
		_rs[1][m] -= _ls[1][1] * _rs[0][m];
		_ls[2][1] -= _ls[2][0] * _ls[0][3];
		_ls[2][2] -= _ls[2][0] * _ls[0][4];
		_rs[2][m] -= _ls[2][0] * _rs[0][m];

		//---------------------------------------------------------------------
		//      store computed lhs and prepare data for next iteration
		//	rhs is stored in a temp array such that write accesses are coalesced
		//---------------------------------------------------------------------
		for (m = 3; m < 5; m++) {
			lhsp(m,i,j,k) = _lp[0][m];
			lhsm(m,i,j,k) = _ls[0][m];
			rtmp(m,i,j,k) = _rs[0][m];
			_rs[0][m] = _rs[1][m];
			_rs[1][m] = _rs[2][m];
		}
		for (m = 0; m < 5; m++) {
			_lp[0][m] = _lp[1][m];
			_lp[1][m] = _lp[2][m];
			_ls[0][m] = _ls[1][m];
			_ls[1][m] = _ls[2][m];
		}
	}
	//---------------------------------------------------------------------
	//         And again the last two rows separately
	//---------------------------------------------------------------------
	k = nz-2;
	m = 3;
	fac1 = 1.0/_lp[0][2];
	_lp[0][3] *= fac1;
	_lp[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_lp[1][2] -= _lp[1][1] * _lp[0][3];
	_lp[1][3] -= _lp[1][1] * _lp[0][4];
	_rs[1][m] -= _lp[1][1] * _rs[0][m];

	m = 4;
	fac1 = 1.0/_ls[0][2];
	_ls[0][3] *= fac1;
	_ls[0][4] *= fac1;
	_rs[0][m] *= fac1;
	_ls[1][2] -= _ls[1][1] * _ls[0][3];
	_ls[1][3] -= _ls[1][1] * _ls[0][4];
	_rs[1][m] -= _ls[1][1] * _rs[0][m];
	//---------------------------------------------------------------------
	//               Scale the last row immediately some of this is overkill
	//               if this is the last cell
	//---------------------------------------------------------------------
	_rs[1][3] /= _lp[1][2];
	_rs[1][4] /= _ls[1][2];
		
	//---------------------------------------------------------------------
	//                         BACKSUBSTITUTION 
	//---------------------------------------------------------------------
	for (m = 0; m < 3; m++) _rs[0][m] -= lhs(3,i,j,nz-2) * _rs[1][m];
	_rs[0][3] -= _lp[0][3] * _rs[1][3];
	_rs[0][4] -= _ls[0][3] * _rs[1][4];
	for (m = 0; m < 5; m++) {
		_rs[2][m] = _rs[1][m];
		_rs[1][m] = _rs[0][m];
	}
	
	for (k = nz-3; k >= 0; k--) {
		//---------------------------------------------------------------------
		//      The first three factors
		//---------------------------------------------------------------------
		for (m = 0; m < 3; m++) _rs[0][m] = rtmp(m,i,j,k) - lhs(3,i,j,k)*_rs[1][m] - lhs(4,i,j,k)*_rs[2][m];
		//---------------------------------------------------------------------
		//      And the remaining two
		//---------------------------------------------------------------------
		_rs[0][3] = rtmp(3,i,j,k) - lhsp(3,i,j,k)*_rs[1][3] - lhsp(4,i,j,k)*_rs[2][3];
		_rs[0][4] = rtmp(4,i,j,k) - lhsm(3,i,j,k)*_rs[1][4] - lhsm(4,i,j,k)*_rs[2][4];

		if (k+2 < nz-1) {
			//---------------------------------------------------------------------
			//   block-diagonal matrix-vector multiplication tzetar
			//---------------------------------------------------------------------
			double xvel = us(i,j,k+2);
			double yvel = vs(i,j,k+2);
			double zvel = ws(i,j,k+2);
			double ac = speed(i,j,k+2);
			double uzik1 = fu(0,i,j,k+2);
			double t1 = (bt*uzik1)/ac * (_rs[2][3] + _rs[2][4]);
			double t2 = _rs[2][2] + t1;
			double t3 = bt*uzik1 * (_rs[2][3] - _rs[2][4]);

			_rs[2][4] =  uzik1*(-xvel*_rs[2][1] + yvel*_rs[2][0]) + qs(i,j,k+2)*t2 + c2iv*(ac*ac)*t1 + zvel*t3;
			_rs[2][3] =  zvel*t2  + t3;
			_rs[2][2] =  uzik1*_rs[2][0] + yvel*t2;
			_rs[2][1] = -uzik1*_rs[2][1] + xvel*t2;
			_rs[2][0] = t2;
		}

		for (m = 0; m < 5; m++) {
			rhs(m,i,j,k+2) = _rs[2][m];
			_rs[2][m] = _rs[1][m];
			_rs[1][m] = _rs[0][m];
		}
	}

	//---------------------------------------------------------------------
	//   block-diagonal matrix-vector multiplication tzetar
	//---------------------------------------------------------------------
	double xfvel = us(i,j,1);
	double yfvel = vs(i,j,1);
	double zfvel = ws(i,j,1);
	double afc = speed(i,j,1);
	double ufzik1 = fu(0,i,j,1);
	double tf1 = (bt*ufzik1)/afc * (_rs[2][3] + _rs[2][4]);
	double tf2 = _rs[2][2] + tf1;
	double tf3 = bt*ufzik1 * (_rs[2][3] - _rs[2][4]);

	rhs(4,i,j,1) =  ufzik1*(-xfvel*_rs[2][1] + yfvel*_rs[2][0]) + qs(i,j,1)*tf2 + c2iv*(afc*afc)*tf1 + zfvel*tf3;
	rhs(3,i,j,1) =  zfvel*tf2  + tf3;
	rhs(2,i,j,1) =  ufzik1*_rs[2][0] + yfvel*tf2;
	rhs(1,i,j,1) = -ufzik1*_rs[2][1] + xfvel*tf2;
	rhs(0,i,j,1) = tf2;

	for (m = 0; m < 5; m++) rhs(m,i,j,0) = _rs[1][m];
}
#undef lhs
#undef lhsp
#undef lhsm
#undef rtmp
//---------------------------------------------------------------------
// 	addition of update to the vector u
//---------------------------------------------------------------------
__global__ static void add_kernel (double *fu, double *rhs, const int nx, const int ny, const int nz) {
	int i, j, k, m;

	k = blockIdx.y+1;
	j = blockIdx.x+1;
	i = threadIdx.x+1;
	m = threadIdx.y;

	fu(m,i,j,k) += rhs(m,i,j,k);
}

//---------------------------------------------------------------------
// adi
//---------------------------------------------------------------------
void adi(bool singlestep, int nx, int ny, int nz, int niter, double* rho_i, double* us, double* vs, double* ws, 
         double* speed, double* qs, double* square, double* rhs, double* lhs, double* forcing, double* fu, double* rstmp) {

	HANDLE_ERROR(hipDeviceSynchronize());

	int itmax = singlestep ? 1 : niter;
  int xblock, xgrid, yblock, ygrid, zblock, zgrid;
	for (int step = 1; step <= itmax; step++) {
		if (step % 20 == 0 || step == 1 && !singlestep)
			printf(" Time step %4d\n", step);

		//compute_rhs();
	  dim3 grid1(ny,nz);
	  compute_rhs_kernel_1<<<grid1,nx>>>(rho_i, us, vs, ws, speed, qs, square, fu, nx, ny, nz);

	  compute_rhs_kernel_2<<<grid1,nx>>>(rho_i, us, vs, ws, qs, square, rhs, forcing, fu, nx, ny, nz);

		//txinvr();
	  dim3 grid2(ny-2,nz-2);
	  txinvr_kernel<<<grid2,nx-2>>> (rho_i, us, vs, ws, speed, qs, rhs, nx, ny, nz);

		//x_solve();
	  yblock = min(SOLVE_BLOCK,ny);
	  ygrid = (ny+yblock-1)/yblock;
	  zblock = min(SOLVE_BLOCK/yblock,nz);
	  zgrid = (nz+zblock-1)/zblock;
	  dim3 grid3(zgrid,ygrid), block3(zblock,yblock);
	  x_solve_kernel<<<grid3,block3>>>(rho_i, us, speed, rhs, lhs, rstmp, nx, ny, nz);

		//y_solve();
	  xblock = min(SOLVE_BLOCK,nx);
	  xgrid = (nx+xblock-1)/xblock;
	  zblock = min(SOLVE_BLOCK/xblock,nz);
	  zgrid = (nz+zblock-1)/zblock;
	  dim3 grid4(zgrid,xgrid), block4(zblock,xblock);
	  y_solve_kernel<<<grid4,block4>>>(rho_i, vs, speed, rhs, lhs, rstmp, nx, ny, nz);

		//z_solve();
	  xblock = min(SOLVE_BLOCK,nx);
	  xgrid = (nx+xblock-1)/xblock;
	  yblock = min(SOLVE_BLOCK/xblock,ny);
	  ygrid = (ny+yblock-1)/yblock;
	  dim3 grid5(ygrid,xgrid), block5(yblock,xblock);
	  z_solve_kernel<<<grid5,block5>>>(rho_i, us, vs, ws, speed, qs, fu, rhs, lhs, rstmp, nx, ny, nz);

		//add();
	  dim3 grid6(ny-2,nz-2);
	  dim3 block6(nx-2,5);
	  add_kernel<<<grid6,block6>>>(fu, rhs, nx, ny, nz);
	}

	HANDLE_ERROR(hipDeviceSynchronize());
}
//---------------------------------------------------------------------
//      defaults from parameters
//---------------------------------------------------------------------
void read_input(char benchclass, double* dd_td, int* nx, int* ny, int* nz, int* niter) {
	FILE *file;

	if ((file = fopen("inputsp.data", "rt")) != NULL) {
		char line[1024];
		printf(" Reading from input file inputsp.data\n");
		
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%i", niter);
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%lf", dd_td);
		fgets(line, sizeof(line)-1, file);
		sscanf(line, "%i %i %i", nx, ny, nz);
		fclose(file);
	} else {
//		printf(" No input file inputsp.data. Using compiled defaults\n");
		int problem_size;
		switch (benchclass) {
			case 's':
			case 'S': problem_size = 12; *dd_td = 0.015; *niter = 100; break;
			case 'w':
			case 'W': problem_size = 36; *dd_td = 0.0015; *niter = 400; break;
			case 'a':
			case 'A': problem_size = 64; *dd_td = 0.0015; *niter = 400; break;
			case 'b':
			case 'B': problem_size = 102; *dd_td = 0.001; *niter = 400; break;
			case 'c':
			case 'C': problem_size = 162; *dd_td = 0.00067; *niter = 400; break;
			case 'd':
			case 'D': problem_size = 408; *dd_td = 0.00030; *niter = 500; break;
			case 'e':
			case 'E': problem_size = 1020; *dd_td = 0.0001; *niter = 500; break;
			default: printf("setparams: Internal error: invalid class %c\n", benchclass); exit(EXIT_FAILURE);
		}
		*nx = *ny = *nz = problem_size;
	}

	printf("\n\n NAS Parallel Benchmarks (NPB3.3-CUDA) - SP Benchmark\n\n");
	printf(" Size: %4dx%4dx%4d\n", *nx, *ny, *nz);
	printf(" Iterations: %4d    dt_d: %10.6F\n", *niter, *dd_td);
	printf("\n");
}




int main(int argc, char **argv) {
	char benchclass = argc > 1 ? argv[1][0] : 'S';

  struct timeval start_t;
  struct timeval end_t;
  struct timeval skt_t;
  struct timeval ske_t;

	int niter;
	int nx, ny, nz;
  double hdd;
  double dd_d;
	
	double *fu, *forcing, *rhs, *rho_i, *us, *vs, *ws, *qs, *speed, *square, *lhs, *rstmp;
  //double* rmsbuf;
	//double xce[5], xcr[5];

	char CUDAname[256];
	int CUDAmp, CUDAclock, CUDAmemclock, CUDAl2cache;
	size_t CUDAmem;

	//---------------------------------------------------------------------
	//   read input data
	//---------------------------------------------------------------------
	read_input(benchclass, &hdd, &nx, &ny, &nz, &niter);
	dd_d = hdd;

	//---------------------------------------------------------------------
	//   allocate CUDA device memory
	//---------------------------------------------------------------------
	int gridsize = nx*ny*nz;
	int facesize = max(max(nx*ny, nx*nz), ny*nz);

  gettimeofday(&start_t, NULL);

	HANDLE_ERROR(hipMalloc((void **)&fu, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&forcing, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&rhs, 5*gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&rho_i, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&us, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&vs, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&ws, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&qs, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&speed, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&square, gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&lhs, 9*gridsize*sizeof(double)));
	HANDLE_ERROR(hipMalloc((void **)&rstmp, 5*gridsize*sizeof(double)));
	//HANDLE_ERROR(cudaMalloc((void **)&rmsbuf, 5*facesize*sizeof(double)));

	  double ce_d[13][5];
	  ce_d[0][0] = (double)2.0;
	  ce_d[1][0] = (double)0.0;
	  ce_d[2][0] = (double)0.0;
	  ce_d[3][0] = (double)4.0;
	  ce_d[4][0] = (double)5.0;
	  ce_d[5][0] = (double)3.0;
	  ce_d[6][0] = (double)0.5;
	  ce_d[7][0] = (double)0.02;
	  ce_d[8][0] = (double)0.01;
	  ce_d[9][0] = (double)0.03;
	  ce_d[10][0] = (double)0.5;
	  ce_d[11][0] = (double)0.4;
	  ce_d[12][0] = (double)0.3;

	  ce_d[0][1] = (double)1.0;
	  ce_d[1][1] = (double)0.0;
	  ce_d[2][1] = (double)0.0;
	  ce_d[3][1] = (double)0.0;
	  ce_d[4][1] = (double)1.0;
	  ce_d[5][1] = (double)2.0;
	  ce_d[6][1] = (double)3.0;
	  ce_d[7][1] = (double)0.01;
	  ce_d[8][1] = (double)0.03;
	  ce_d[9][1] = (double)0.02;
	  ce_d[10][1] = (double)0.4;
	  ce_d[11][1] = (double)0.3;
	  ce_d[12][1] = (double)0.5;

	  ce_d[0][2] = (double)2.0;
	  ce_d[1][2] = (double)2.0;
	  ce_d[2][2] = (double)0.0;
	  ce_d[3][2] = (double)0.0;
	  ce_d[4][2] = (double)0.0;
	  ce_d[5][2] = (double)2.0;
	  ce_d[6][2] = (double)3.0;
	  ce_d[7][2] = (double)0.04;
	  ce_d[8][2] = (double)0.03;
	  ce_d[9][2] = (double)0.05;
	  ce_d[10][2] = (double)0.3;
	  ce_d[11][2] = (double)0.5;
	  ce_d[12][2] = (double)0.4;

	  ce_d[0][3] = (double)2.0;
	  ce_d[1][3] = (double)2.0;
	  ce_d[2][3] = (double)0.0;
	  ce_d[3][3] = (double)0.0;
	  ce_d[4][3] = (double)0.0;
	  ce_d[5][3] = (double)2.0;
	  ce_d[6][3] = (double)3.0;
	  ce_d[7][3] = (double)0.03;
	  ce_d[8][3] = (double)0.05;
	  ce_d[9][3] = (double)0.04;
	  ce_d[10][3] = (double)0.2;
	  ce_d[11][3] = (double)0.1;
	  ce_d[12][3] = (double)0.3;

	  ce_d[0][4] = (double)5.0;
	  ce_d[1][4] = (double)4.0;
	  ce_d[2][4] = (double)3.0;
	  ce_d[3][4] = (double)2.0;
	  ce_d[4][4] = (double)0.1;
	  ce_d[5][4] = (double)0.4;
	  ce_d[6][4] = (double)0.3;
	  ce_d[7][4] = (double)0.05;
	  ce_d[8][4] = (double)0.04;
	  ce_d[9][4] = (double)0.03;
	  ce_d[10][4] = (double)0.1;
	  ce_d[11][4] = (double)0.3;
	  ce_d[12][4] = (double)0.2;

	  double bt_d = sqrt(0.5);

	  double dnxm1_d = 1.0/((double)nx-1.0);
	  double dnym1_d = 1.0/((double)ny-1.0);
	  double dnzm1_d = 1.0/((double)nz-1.0);

	  double tx1_d = 1.0 / (dnxm1_d * dnxm1_d);
	  double tx2_d = 1.0 / (2.0 * dnxm1_d);
	  double tx3_d = 1.0 / dnxm1_d;

	  double ty1_d = 1.0 / (dnym1_d * dnym1_d);
	  double ty2_d = 1.0 / (2.0 * dnym1_d);
	  double ty3_d = 1.0 / dnym1_d;
 
	  double tz1_d = 1.0 / (dnzm1_d * dnzm1_d);
	  double tz2_d = 1.0 / (2.0 * dnzm1_d);
	  double tz3_d = 1.0 / dnzm1_d;

	  double dtx1_d = dd_d*tx1_d;
	  double dttx2_d = dd_d*tx2_d;
	  double dty1_d = dd_d*ty1_d;
	  double dtty2_d = dd_d*ty2_d;
	  double dtz1_d = dd_d*tz1_d;
	  double dttz2_d = dd_d*tz2_d;

	  double c2dttx1_d = 2.0*dtx1_d;
	  double c2dtty1_d = 2.0*dty1_d;
	  double c2dttz1_d = 2.0*dtz1_d;

	  double dtdssp_d = dd_d*dssp;

	  double comz1_d  = dtdssp_d;
	  double comz4_d  = 4.0*dtdssp_d;
	  double comz5_d  = 5.0*dtdssp_d;
	  double comz6_d  = 6.0*dtdssp_d;

	  double c3c4tx3_d = c3c4*tx3_d;
	  double c3c4ty3_d = c3c4*ty3_d;
	  double c3c4tz3_d = c3c4*tz3_d;

	  double dx1tx1_d = dx1*tx1_d;
	  double dx2tx1_d = dx2*tx1_d;
	  double dx3tx1_d = dx3*tx1_d;
	  double dx4tx1_d = dx4*tx1_d;
	  double dx5tx1_d = dx5*tx1_d;

	  double dy1ty1_d = dy1*ty1_d;
	  double dy2ty1_d = dy2*ty1_d;
	  double dy3ty1_d = dy3*ty1_d;
	  double dy4ty1_d = dy4*ty1_d;
	  double dy5ty1_d = dy5*ty1_d;

	  double dz1tz1_d = dz1*tz1_d;
	  double dz2tz1_d = dz2*tz1_d;
	  double dz3tz1_d = dz3*tz1_d;
	  double dz4tz1_d = dz4*tz1_d;
	  double dz5tz1_d = dz5*tz1_d;

	  double xxcon1_d = c3c4tx3_d*con43*tx3_d;
	  double xxcon2_d = c3c4tx3_d*tx3_d;
	  double xxcon3_d = c3c4tx3_d*conz1*tx3_d;
	  double xxcon4_d = c3c4tx3_d*con16*tx3_d;
	  double xxcon5_d = c3c4tx3_d*c1c5*tx3_d;

	  double yycon1_d = c3c4ty3_d*con43*ty3_d;
	  double yycon2_d = c3c4ty3_d*ty3_d;
	  double yycon3_d = c3c4ty3_d*conz1*ty3_d;
	  double yycon4_d = c3c4ty3_d*con16*ty3_d;
	  double yycon5_d = c3c4ty3_d*c1c5*ty3_d;

	  double zzcon1_d = c3c4tz3_d*con43*tz3_d;
	  double zzcon2_d = c3c4tz3_d*tz3_d;
	  double zzcon3_d = c3c4tz3_d*conz1*tz3_d;
	  double zzcon4_d = c3c4tz3_d*con16*tz3_d;
	  double zzcon5_d = c3c4tz3_d*c1c5*tz3_d;

	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&ce), &ce_d, 13*5*sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&bt), &bt_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dnxm1), &dnxm1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dnym1), &dnym1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dnzm1), &dnzm1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tx1), &tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tx2), &tx2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tx3), &tx3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&ty1), &ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&ty2), &ty2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&ty3), &ty3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tz1), &tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tz2), &tz2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&tz3), &tz3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dtx1), &dtx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dttx2), &dttx2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dty1), &dty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dtty2), &dtty2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dtz1), &dtz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dttz2), &dttz2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c2dttx1), &c2dttx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c2dtty1), &c2dtty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c2dttz1), &c2dttz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dt), &dd_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dtdssp), &dtdssp_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&comz1), &comz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&comz4), &comz4_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&comz5), &comz5_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&comz6), &comz6_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c3c4tx3), &c3c4tx3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c3c4ty3), &c3c4ty3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&c3c4tz3), &c3c4tz3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dx1tx1), &dx1tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dx2tx1), &dx2tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dx3tx1), &dx3tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dx4tx1), &dx4tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dx5tx1), &dx5tx1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dy1ty1), &dy1ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dy2ty1), &dy2ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dy3ty1), &dy3ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dy4ty1), &dy4ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dy5ty1), &dy5ty1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dz1tz1), &dz1tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dz2tz1), &dz2tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dz3tz1), &dz3tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dz4tz1), &dz4tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&dz5tz1), &dz5tz1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&xxcon1), &xxcon1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&xxcon2), &xxcon2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&xxcon3), &xxcon3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&xxcon4), &xxcon4_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&xxcon5), &xxcon5_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&yycon1), &yycon1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&yycon2), &yycon2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&yycon3), &yycon3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&yycon4), &yycon4_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&yycon5), &yycon5_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&zzcon1), &zzcon1_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&zzcon2), &zzcon2_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&zzcon3), &zzcon3_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&zzcon4), &zzcon4_d, sizeof(double)));
	  HANDLE_ERROR (hipMemcpyToSymbol (HIP_SYMBOL(&zzcon5), &zzcon5_d, sizeof(double)));

  gettimeofday(&skt_t, NULL);
	exact_rhs(forcing, nx, ny, nz);

	//sp->initialize();
  dim3 grid(nz,ny);
	initialize_kernel<<<grid,nx>>> (fu, nx, ny, nz);

	//---------------------------------------------------------------------
	//      do one time step to touch all code, and reinitialize
	//---------------------------------------------------------------------
	adi(true,  nx,  ny,  nz,  niter,  rho_i,  us,  vs,  ws, 
       speed,  qs,  square,  rhs,  lhs,  forcing,  fu,  rstmp);
	//sp->initialize();
	initialize_kernel<<<grid,nx>>> (fu, nx, ny, nz);

	//---------------------------------------------------------------------
	//   main time stepping loop
	//---------------------------------------------------------------------
	//sp->adi(false);
	adi(false,  nx,  ny,  nz,  niter,  rho_i,  us,  vs,  ws, 
       speed,  qs,  square,  rhs,  lhs,  forcing,  fu,  rstmp);

  gettimeofday(&ske_t, NULL);
  gettimeofday(&end_t, NULL);


	std::cout  << "time: "<<((end_t.tv_sec-start_t.tv_sec)+(end_t.tv_usec-start_t.tv_usec)*1e-6) << std::endl;
	std::cout  << "kernel: "<<((ske_t.tv_sec-skt_t.tv_sec)+(ske_t.tv_usec-skt_t.tv_usec)*1e-6) << std::endl;
	//std::cout  << (sdkGetAverageTimerValue(&timer)/1000.0)  / iterations << " seconds per iteration" << std::endl;
	//---------------------------------------------------------------------
	//   verification test
	//---------------------------------------------------------------------
	//char verifyclass;
  //bool verified;

	//---------------------------------------------------------------------
	//      More timers
	//---------------------------------------------------------------------
	//sp->print_timers();

	//delete sp;
	return EXIT_SUCCESS;
}

	.text
	.file	"sp_double.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z9exact_rhsPdiii               # -- Begin function _Z9exact_rhsPdiii
	.type	_Z9exact_rhsPdiii,@function
_Z9exact_rhsPdiii:                      # @_Z9exact_rhsPdiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movl	%edx, %r14d
	movl	%esi, %ebp
	movq	%rdi, %r15
	movl	%edx, %eax
	movq	%rbx, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movl	%esi, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	movq	%r15, %rdi
	movl	%ebp, %esi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_ZL36__device_stub__exact_rhs_kernel_initPdiii
.LBB0_2:
	cmpl	$32, %r14d
	movl	$32, %r13d
	movl	$32, %ecx
	cmovll	%r14d, %ecx
	leal	(%r14,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
	movl	%eax, %edi
	movl	$32, %eax
	xorl	%edx, %edx
	idivl	%ecx
	movl	%eax, %esi
	cmpl	%ebx, %eax
	cmovgel	%ebx, %esi
	leal	-1(%rbx), %r12d
	leal	(%rbx,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rdi
	orq	%rax, %rdi
	shlq	$32, %rcx
	orq	%rsi, %rcx
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:
	movq	%r15, %rdi
	movl	%ebp, %esi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	callq	_ZL33__device_stub__exact_rhs_kernel_xPdiii
.LBB0_4:
	movq	%r15, (%rsp)                    # 8-byte Spill
	leal	-1(%r14), %r15d
	cmpl	$32, %ebp
	cmovll	%ebp, %r13d
	movq	%rbp, 8(%rsp)                   # 8-byte Spill
	leal	-1(%rbp,%r13), %eax
	cltd
	idivl	%r13d
	movl	%eax, %ebp
	movl	$32, %eax
	xorl	%edx, %edx
	idivl	%r13d
	movq	%rbx, %rcx
	movl	%eax, %ebx
	cmpl	%ecx, %eax
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
                                        # kill: def $ecx killed $ecx killed $rcx def $rcx
	cmovll	%eax, %ecx
	addl	%ecx, %r12d
	movl	%r12d, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rbp
	leaq	(%rax,%rbp), %rdi
	shlq	$32, %r13
	orq	%r13, %rcx
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:
	movq	(%rsp), %rdi                    # 8-byte Reload
	movq	8(%rsp), %rsi                   # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r14d, %edx
	movq	16(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	callq	_ZL33__device_stub__exact_rhs_kernel_yPdiii
.LBB0_6:
	cmpl	%r14d, %ebx
	cmovgel	%r14d, %ebx
	addl	%ebx, %r15d
	movl	%r15d, %eax
	cltd
	idivl	%ebx
                                        # kill: def $eax killed $eax def $rax
	orq	%rax, %rbp
	orq	%rbx, %r13
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_8
# %bb.7:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_8:
	.cfi_def_cfa_offset 80
	movq	(%rsp), %rdi                    # 8-byte Reload
	movq	8(%rsp), %rsi                   # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	movl	%r14d, %edx
	movq	16(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZL33__device_stub__exact_rhs_kernel_zPdiii # TAILCALL
.Lfunc_end0:
	.size	_Z9exact_rhsPdiii, .Lfunc_end0-_Z9exact_rhsPdiii
	.cfi_endproc
                                        # -- End function
	.type	_ZL36__device_stub__exact_rhs_kernel_initPdiii,@function # -- Begin function _ZL36__device_stub__exact_rhs_kernel_initPdiii
_ZL36__device_stub__exact_rhs_kernel_initPdiii: # @_ZL36__device_stub__exact_rhs_kernel_initPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL21exact_rhs_kernel_initPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZL36__device_stub__exact_rhs_kernel_initPdiii, .Lfunc_end1-_ZL36__device_stub__exact_rhs_kernel_initPdiii
	.cfi_endproc
                                        # -- End function
	.type	_ZL33__device_stub__exact_rhs_kernel_xPdiii,@function # -- Begin function _ZL33__device_stub__exact_rhs_kernel_xPdiii
_ZL33__device_stub__exact_rhs_kernel_xPdiii: # @_ZL33__device_stub__exact_rhs_kernel_xPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL18exact_rhs_kernel_xPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZL33__device_stub__exact_rhs_kernel_xPdiii, .Lfunc_end2-_ZL33__device_stub__exact_rhs_kernel_xPdiii
	.cfi_endproc
                                        # -- End function
	.type	_ZL33__device_stub__exact_rhs_kernel_yPdiii,@function # -- Begin function _ZL33__device_stub__exact_rhs_kernel_yPdiii
_ZL33__device_stub__exact_rhs_kernel_yPdiii: # @_ZL33__device_stub__exact_rhs_kernel_yPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL18exact_rhs_kernel_yPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZL33__device_stub__exact_rhs_kernel_yPdiii, .Lfunc_end3-_ZL33__device_stub__exact_rhs_kernel_yPdiii
	.cfi_endproc
                                        # -- End function
	.type	_ZL33__device_stub__exact_rhs_kernel_zPdiii,@function # -- Begin function _ZL33__device_stub__exact_rhs_kernel_zPdiii
_ZL33__device_stub__exact_rhs_kernel_zPdiii: # @_ZL33__device_stub__exact_rhs_kernel_zPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL18exact_rhs_kernel_zPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_ZL33__device_stub__exact_rhs_kernel_zPdiii, .Lfunc_end4-_ZL33__device_stub__exact_rhs_kernel_zPdiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_ # -- Begin function _Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	.type	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_,@function
_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_:    # @_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 16(%rsp)                   # 8-byte Spill
	movl	%r8d, %ebx
	movl	%ecx, %r15d
	movl	%edx, %r12d
                                        # kill: def $esi killed $esi def $rsi
	movq	%rsi, 8(%rsp)                   # 8-byte Spill
	movl	%edi, %ebp
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_1
# %bb.3:                                # %_ZL11HandleError10hipError_tPKci.exit
	movl	%ebp, 28(%rsp)                  # 4-byte Spill
	testb	%bpl, %bpl
	movl	$1, %ebp
	cmovnel	%ebp, %ebx
	testl	%ebx, %ebx
	jle	.LBB5_23
# %bb.4:                                # %.lr.ph
	movl	%r12d, %eax
	movq	%r15, %r14
	shlq	$32, %r14
	orq	%rax, %r14
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movl	%ecx, %r13d
	btsq	$32, %r13
	leal	-2(%r12), %eax
	leal	-2(%r15), %edx
	shlq	$32, %rdx
	orq	%rax, %rdx
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	leal	-2(%rcx), %eax
	movq	%rax, %rdx
	btsq	$32, %rdx
	movq	%rdx, 112(%rsp)                 # 8-byte Spill
	movl	$32, %edx
	cmpl	%edx, %r12d
	movl	$32, %esi
	cmovll	%r12d, %esi
	movq	%rsi, %rdi
	shlq	$32, %rdi
	movq	%rdi, 88(%rsp)                  # 8-byte Spill
	cmpl	%edx, %ecx
	cmovll	%ecx, %edx
	movabsq	$21474836480, %rdi              # imm = 0x500000000
	orq	%rax, %rdi
	movq	%rdi, 80(%rsp)                  # 8-byte Spill
	movq	%rdx, %rax
	shlq	$32, %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	negl	%ebx
	leal	-1(%r12), %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	%rsi, 96(%rsp)                  # 8-byte Spill
	leal	(%r12,%rsi), %eax
	decl	%eax
	movl	%eax, 36(%rsp)                  # 4-byte Spill
	leal	-1(%r15), %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	%rdx, 104(%rsp)                 # 8-byte Spill
	leal	-1(%rcx,%rdx), %eax
	movl	%eax, 32(%rsp)                  # 4-byte Spill
	movq	%r14, 128(%rsp)                 # 8-byte Spill
	movq	%r13, 120(%rsp)                 # 8-byte Spill
	movq	%rbx, 64(%rsp)                  # 8-byte Spill
.LBB5_5:                                # =>This Inner Loop Header: Depth=1
	movl	%ebp, %eax
	movl	$3435973837, %ecx               # imm = 0xCCCCCCCD
	imulq	%rcx, %rax
	shrq	$36, %rax
	shll	$2, %eax
	leal	(%rax,%rax,4), %ecx
	cmpl	$1, %ebp
	setne	%al
	cmpl	%ecx, %ebp
	je	.LBB5_7
# %bb.6:                                #   in Loop: Header=BB5_5 Depth=1
	orb	28(%rsp), %al                   # 1-byte Folded Reload
	jne	.LBB5_8
.LBB5_7:                                #   in Loop: Header=BB5_5 Depth=1
	movl	$.L.str.1, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
.LBB5_8:                                #   in Loop: Header=BB5_5 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:                                #   in Loop: Header=BB5_5 Depth=1
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	200(%rsp), %rsi
	movq	208(%rsp), %rdx
	movq	216(%rsp), %rcx
	movq	224(%rsp), %r8
	movq	232(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	296(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	272(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB5_10:                               #   in Loop: Header=BB5_5 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_12
# %bb.11:                               #   in Loop: Header=BB5_5 Depth=1
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	192(%rsp), %rsi
	movq	200(%rsp), %rdx
	movq	208(%rsp), %rcx
	movq	224(%rsp), %r8
	movq	232(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	280(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	addq	$48, %rsp
	.cfi_adjust_cfa_offset -48
.LBB5_12:                               #   in Loop: Header=BB5_5 Depth=1
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	112(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_14
# %bb.13:                               #   in Loop: Header=BB5_5 Depth=1
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	192(%rsp), %rsi
	movq	200(%rsp), %rdx
	movq	208(%rsp), %rcx
	movq	216(%rsp), %r8
	movq	224(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	264(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB5_14:                               #   in Loop: Header=BB5_5 Depth=1
	movl	36(%rsp), %eax                  # 4-byte Reload
	cltd
	movq	96(%rsp), %rcx                  # 8-byte Reload
	idivl	%ecx
	movl	%eax, %edi
	movl	$32, %eax
	xorl	%edx, %edx
	idivl	%ecx
	movl	%eax, %ecx
	cmpl	%r15d, %eax
	cmovgel	%r15d, %ecx
	movq	48(%rsp), %r13                  # 8-byte Reload
	leal	(%rcx,%r13), %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rdi
	orq	%rax, %rdi
	orq	88(%rsp), %rcx                  # 8-byte Folded Reload
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.15:                               #   in Loop: Header=BB5_5 Depth=1
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	200(%rsp), %rsi
	movq	224(%rsp), %rdx
	movq	248(%rsp), %rcx
	movq	256(%rsp), %r8
	movq	280(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB5_16:                               #   in Loop: Header=BB5_5 Depth=1
	movl	32(%rsp), %eax                  # 4-byte Reload
	cltd
	movq	104(%rsp), %rcx                 # 8-byte Reload
	idivl	%ecx
	movl	%eax, %r14d
	movl	$32, %eax
	xorl	%edx, %edx
	idivl	%ecx
	movl	%eax, %ebx
	cmpl	%r15d, %eax
	movl	%r15d, %ecx
	cmovll	%eax, %ecx
	leal	(%rcx,%r13), %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %r14
	leaq	(%rax,%r14), %rdi
	movq	72(%rsp), %r13                  # 8-byte Reload
	orq	%r13, %rcx
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_18
# %bb.17:                               #   in Loop: Header=BB5_5 Depth=1
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	208(%rsp), %rsi
	movq	224(%rsp), %rdx
	movq	248(%rsp), %rcx
	movq	256(%rsp), %r8
	movq	280(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB5_18:                               #   in Loop: Header=BB5_5 Depth=1
	cmpl	%r12d, %ebx
	cmovgel	%r12d, %ebx
	movq	56(%rsp), %rax                  # 8-byte Reload
	addl	%ebx, %eax
	cltd
	idivl	%ebx
                                        # kill: def $eax killed $eax def $rax
	orq	%rax, %r14
	orq	%r13, %rbx
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_20
# %bb.19:                               #   in Loop: Header=BB5_5 Depth=1
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	200(%rsp), %rsi
	movq	208(%rsp), %rdx
	movq	216(%rsp), %rcx
	movq	224(%rsp), %r8
	movq	232(%rsp), %r9
	pushq	%r15
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	304(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	288(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	320(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB5_20:                               #   in Loop: Header=BB5_5 Depth=1
	movq	40(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movq	80(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	64(%rsp), %rbx                  # 8-byte Reload
	movq	128(%rsp), %r14                 # 8-byte Reload
	jne	.LBB5_22
# %bb.21:                               #   in Loop: Header=BB5_5 Depth=1
	movq	264(%rsp), %rdi
	movq	240(%rsp), %rsi
	movq	8(%rsp), %rdx                   # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movl	%r12d, %ecx
	movl	%r15d, %r8d
	callq	_ZL25__device_stub__add_kernelPdS_iii
.LBB5_22:                               #   in Loop: Header=BB5_5 Depth=1
	leal	(%rbx,%rbp), %eax
	incl	%eax
	movl	%ebp, %ecx
	incl	%ecx
	movl	%ecx, %ebp
	cmpl	$1, %eax
	movq	120(%rsp), %r13                 # 8-byte Reload
	jne	.LBB5_5
.LBB5_23:                               # %._crit_edge
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.25:                               # %_ZL11HandleError10hipError_tPKci.exit202
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_1:
	.cfi_def_cfa_offset 192
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1793, %ecx                     # imm = 0x701
	jmp	.LBB5_2
.LBB5_24:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1841, %ecx                     # imm = 0x731
.LBB5_2:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_, .Lfunc_end5-_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.type	_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,@function # -- Begin function _ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii: # @_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, .Lfunc_end6-_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,@function # -- Begin function _ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii: # @_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, .Lfunc_end7-_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii,@function # -- Begin function _ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii: # @_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii, .Lfunc_end8-_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii,@function # -- Begin function _ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii: # @_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL14x_solve_kernelPdS_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii, .Lfunc_end9-_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii,@function # -- Begin function _ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii: # @_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL14y_solve_kernelPdS_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii, .Lfunc_end10-_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,@function # -- Begin function _ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii: # @_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, .Lfunc_end11-_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.cfi_endproc
                                        # -- End function
	.type	_ZL25__device_stub__add_kernelPdS_iii,@function # -- Begin function _ZL25__device_stub__add_kernelPdS_iii
_ZL25__device_stub__add_kernelPdS_iii:  # @_ZL25__device_stub__add_kernelPdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL10add_kernelPdS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_ZL25__device_stub__add_kernelPdS_iii, .Lfunc_end12-_ZL25__device_stub__add_kernelPdS_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z10read_inputcPdPiS0_S0_S0_
.LCPI13_0:
	.quad	0x3f8eb851eb851eb8              # double 0.014999999999999999
.LCPI13_1:
	.quad	0x3f1a36e2eb1c432d              # double 1.0E-4
.LCPI13_2:
	.quad	0x3f33a92a30553261              # double 2.9999999999999997E-4
.LCPI13_3:
	.quad	0x3f45f45e0b4e11dc              # double 6.7000000000000002E-4
.LCPI13_4:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI13_5:
	.quad	0x3f589374bc6a7efa              # double 0.0015
	.text
	.globl	_Z10read_inputcPdPiS0_S0_S0_
	.type	_Z10read_inputcPdPiS0_S0_S0_,@function
_Z10read_inputcPdPiS0_S0_S0_:           # @_Z10read_inputcPdPiS0_S0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1048, %rsp                     # imm = 0x418
	.cfi_def_cfa_offset 1104
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %r14
	movq	%r8, 8(%rsp)                    # 8-byte Spill
	movq	%rcx, %rbp
	movq	%rdx, %r12
	movq	%rsi, %r15
	movl	%edi, %ebx
	movl	$.L.str.2, %edi
	movl	$.L.str.3, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB13_2
# %bb.1:
	movq	%rax, %r13
	movl	$.Lstr, %edi
	callq	puts@PLT
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movl	$1023, %esi                     # imm = 0x3FF
	movq	%r13, %rdx
	callq	fgets
	movl	$.L.str.5, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	%rbx, %rdi
	movl	$1023, %esi                     # imm = 0x3FF
	movq	%r13, %rdx
	callq	fgets
	movl	$.L.str.6, %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	%rbx, %rdi
	movl	$1023, %esi                     # imm = 0x3FF
	movq	%r13, %rdx
	callq	fgets
	movl	$.L.str.7, %esi
	movq	%rbx, %rdi
	movq	%r12, %rdx
	movq	%rbp, %rcx
	movq	%rbp, %rbx
	movq	8(%rsp), %rbp                   # 8-byte Reload
	movq	%rbp, %r8
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	movq	%r13, %rdi
	callq	fclose
	jmp	.LBB13_18
.LBB13_2:
	movq	%r12, %rdi
	movq	%rbp, %r13
	movq	8(%rsp), %rbp                   # 8-byte Reload
	movsbl	%bl, %esi
	movl	$12, %eax
	movl	$100, %ecx
	movsd	.LCPI13_0(%rip), %xmm0          # xmm0 = mem[0],zero
	cmpl	$86, %esi
	jle	.LBB13_3
# %bb.7:
	leal	-87(%rsi), %edx
	cmpl	$14, %edx
	movq	%r13, %rbx
	movq	%rdi, %r12
	ja	.LBB13_8
# %bb.19:
	jmpq	*.LJTI13_1(,%rdx,8)
.LBB13_3:
	leal	-65(%rsi), %edx
	cmpl	$4, %edx
	movq	%r13, %rbx
	movq	%rdi, %r12
	ja	.LBB13_4
# %bb.6:
	jmpq	*.LJTI13_0(,%rdx,8)
.LBB13_12:
	movl	$64, %eax
	jmp	.LBB13_11
.LBB13_8:
	cmpl	$115, %esi
	je	.LBB13_17
# %bb.9:
	cmpl	$119, %esi
	jne	.LBB13_5
.LBB13_10:
	movl	$36, %eax
.LBB13_11:
	movl	$400, %ecx                      # imm = 0x190
	movsd	.LCPI13_5(%rip), %xmm0          # xmm0 = mem[0],zero
	jmp	.LBB13_17
.LBB13_15:
	movl	$1020, %eax                     # imm = 0x3FC
	movl	$500, %ecx                      # imm = 0x1F4
	movsd	.LCPI13_1(%rip), %xmm0          # xmm0 = mem[0],zero
	jmp	.LBB13_17
.LBB13_14:
	movl	$408, %eax                      # imm = 0x198
	movl	$500, %ecx                      # imm = 0x1F4
	movsd	.LCPI13_2(%rip), %xmm0          # xmm0 = mem[0],zero
	jmp	.LBB13_17
.LBB13_13:
	movl	$162, %eax
	movl	$400, %ecx                      # imm = 0x190
	movsd	.LCPI13_3(%rip), %xmm0          # xmm0 = mem[0],zero
	jmp	.LBB13_17
.LBB13_16:
	movl	$102, %eax
	movl	$400, %ecx                      # imm = 0x190
	movsd	.LCPI13_4(%rip), %xmm0          # xmm0 = mem[0],zero
	jmp	.LBB13_17
.LBB13_4:
	cmpl	$83, %esi
	jne	.LBB13_5
.LBB13_17:
	movsd	%xmm0, (%r15)
	movl	%ecx, (%r14)
	movl	%eax, (%rbp)
	movl	%eax, (%rbx)
	movl	%eax, (%r12)
.LBB13_18:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	(%r12), %esi
	movl	(%rbx), %edx
	movl	(%rbp), %ecx
	movl	$.L.str.10, %edi
	xorl	%eax, %eax
	callq	printf
	movl	(%r14), %esi
	movsd	(%r15), %xmm0                   # xmm0 = mem[0],zero
	movl	$.L.str.11, %edi
	movb	$1, %al
	callq	printf
	movl	$10, %edi
	callq	putchar@PLT
	addq	$1048, %rsp                     # imm = 0x418
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB13_5:
	.cfi_def_cfa_offset 1104
	movl	$.L.str.8, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end13:
	.size	_Z10read_inputcPdPiS0_S0_S0_, .Lfunc_end13-_Z10read_inputcPdPiS0_S0_S0_
	.cfi_endproc
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
.LJTI13_0:
	.quad	.LBB13_12
	.quad	.LBB13_16
	.quad	.LBB13_13
	.quad	.LBB13_14
	.quad	.LBB13_15
.LJTI13_1:
	.quad	.LBB13_10
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_5
	.quad	.LBB13_12
	.quad	.LBB13_16
	.quad	.LBB13_13
	.quad	.LBB13_14
	.quad	.LBB13_15
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI14_0:
	.quad	0xbff0000000000000              # double -1
.LCPI14_1:
	.quad	0x3ff0000000000000              # double 1
.LCPI14_2:
	.quad	0x3fd0000000000000              # double 0.25
.LCPI14_3:
	.quad	0x4010000000000000              # double 4
.LCPI14_4:
	.quad	0x4014000000000000              # double 5
.LCPI14_5:
	.quad	0x4018000000000000              # double 6
.LCPI14_6:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
.LCPI14_7:
	.quad	0x3fe8000000000000              # double 0.75
.LCPI14_8:
	.quad	0x3ff5555555555555              # double 1.3333333333333333
.LCPI14_9:
	.quad	0xbfeeb851eb851eb6              # double -0.95999999999999974
.LCPI14_10:
	.quad	0x3fc5555555555555              # double 0.16666666666666666
.LCPI14_11:
	.quad	0x3fff5c28f5c28f5b              # double 1.9599999999999997
.LCPI14_12:
	.quad	0x3eb0c6f7a0b5ed8d              # double 9.9999999999999995E-7
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$1192, %rsp                     # imm = 0x4A8
	.cfi_def_cfa_offset 1232
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movb	$83, %al
	cmpl	$2, %edi
	jl	.LBB14_2
# %bb.1:
	movq	8(%rsi), %rax
	movb	(%rax), %al
.LBB14_2:
	movsbl	%al, %edi
	leaq	648(%rsp), %rbx
	leaq	16(%rsp), %r14
	leaq	24(%rsp), %r15
	leaq	20(%rsp), %r12
	leaq	28(%rsp), %r9
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movq	%r15, %rcx
	movq	%r12, %r8
	callq	_Z10read_inputcPdPiS0_S0_S0_
	movsd	(%rbx), %xmm0                   # xmm0 = mem[0],zero
	movsd	%xmm0, 128(%rsp)
	movslq	(%r14), %rax
	movslq	(%r15), %rcx
	imulq	%rax, %rcx
	movslq	(%r12), %r15
	imulq	%rcx, %r15
	leaq	632(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	leaq	(,%r15,8), %rax
	leaq	(%rax,%rax,4), %rbx
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_3
# %bb.5:                                # %_ZL11HandleError10hipError_tPKci.exit
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_6
# %bb.7:                                # %_ZL11HandleError10hipError_tPKci.exit30
	leaq	120(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_8
# %bb.9:                                # %_ZL11HandleError10hipError_tPKci.exit32
	movslq	%r15d, %r14
	shlq	$3, %r14
	leaq	112(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_10
# %bb.11:                               # %_ZL11HandleError10hipError_tPKci.exit34
	leaq	104(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_12
# %bb.13:                               # %_ZL11HandleError10hipError_tPKci.exit36
	leaq	96(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_14
# %bb.15:                               # %_ZL11HandleError10hipError_tPKci.exit38
	leaq	88(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_16
# %bb.17:                               # %_ZL11HandleError10hipError_tPKci.exit40
	leaq	80(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_18
# %bb.19:                               # %_ZL11HandleError10hipError_tPKci.exit42
	leaq	72(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_20
# %bb.21:                               # %_ZL11HandleError10hipError_tPKci.exit44
	leaq	64(%rsp), %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_22
# %bb.23:                               # %_ZL11HandleError10hipError_tPKci.exit46
	leal	(%r15,%r15,8), %eax
	movslq	%eax, %rsi
	shlq	$3, %rsi
	leaq	56(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_24
# %bb.25:                               # %_ZL11HandleError10hipError_tPKci.exit48
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB14_26
# %bb.27:                               # %_ZL11HandleError10hipError_tPKci.exit50
	movabsq	$4611686018427387904, %rax      # imm = 0x4000000000000000
	leaq	672(%rsp), %rsi
	movq	%rax, (%rsi)
	xorpd	%xmm0, %xmm0
	movupd	%xmm0, 40(%rsi)
	movapd	%xmm0, 80(%rsi)
	movabsq	$4616189618054758400, %rcx      # imm = 0x4010000000000000
	movq	%rcx, 120(%rsi)
	movabsq	$4617315517961601024, %rdx      # imm = 0x4014000000000000
	movq	%rdx, 160(%rsi)
	movabsq	$4613937818241073152, %rdi      # imm = 0x4008000000000000
	movq	%rdi, 200(%rsi)
	movabsq	$4602678819172646912, %r11      # imm = 0x3FE0000000000000
	movq	%r11, 240(%rsi)
	movabsq	$4581421828931458171, %rbx      # imm = 0x3F947AE147AE147B
	movq	%rbx, 280(%rsi)
	movabsq	$4576918229304087675, %r14      # imm = 0x3F847AE147AE147B
	movq	%r14, 320(%rsi)
	movabsq	$4584304132692975288, %r8       # imm = 0x3F9EB851EB851EB8
	movq	%r8, 360(%rsi)
	movq	%r11, 400(%rsi)
	movabsq	$4600877379321698714, %r10      # imm = 0x3FD999999999999A
	movq	%r10, 440(%rsi)
	movabsq	$4599075939470750515, %r9       # imm = 0x3FD3333333333333
	movq	%r9, 480(%rsi)
	movabsq	$4607182418800017408, %r15      # imm = 0x3FF0000000000000
	movq	%r15, 8(%rsi)
	movq	$0, 128(%rsi)
	movq	%r15, 168(%rsi)
	movq	%rax, 208(%rsi)
	movq	%rdi, 248(%rsi)
	movq	%r14, 288(%rsi)
	movq	%r8, 328(%rsi)
	movq	%rbx, 368(%rsi)
	movq	%r10, 408(%rsi)
	movq	%r9, 448(%rsi)
	movq	%r11, 488(%rsi)
	movq	%rax, 16(%rsi)
	movq	%rax, 56(%rsi)
	movapd	%xmm0, 96(%rsi)
	movupd	%xmm0, 136(%rsi)
	movapd	%xmm0, 176(%rsi)
	movq	%rax, 216(%rsi)
	movq	%rdi, 256(%rsi)
	movabsq	$4585925428558828667, %rbx      # imm = 0x3FA47AE147AE147B
	movq	%rbx, 296(%rsi)
	movq	%r8, 336(%rsi)
	movabsq	$4587366580439587226, %r14      # imm = 0x3FA999999999999A
	movq	%r14, 376(%rsi)
	movq	%r9, 416(%rsi)
	movq	%r11, 456(%rsi)
	movq	%r10, 496(%rsi)
	movq	%rax, 24(%rsi)
	movq	%rax, 64(%rsi)
	movq	%rax, 224(%rsi)
	movq	%rdi, 264(%rsi)
	movq	%r8, 304(%rsi)
	movq	%r14, 344(%rsi)
	movq	%rbx, 384(%rsi)
	movabsq	$4596373779694328218, %r11      # imm = 0x3FC999999999999A
	movq	%r11, 424(%rsi)
	movabsq	$4591870180066957722, %r15      # imm = 0x3FB999999999999A
	movq	%r15, 464(%rsi)
	movq	%r9, 504(%rsi)
	movq	%rdx, 32(%rsi)
	movq	%rcx, 72(%rsi)
	movq	%rdi, 112(%rsi)
	movq	%rax, 152(%rsi)
	movq	%r15, 192(%rsi)
	movq	%r10, 232(%rsi)
	movq	%r9, 272(%rsi)
	movq	%r14, 312(%rsi)
	movq	%rbx, 352(%rsi)
	movq	%r8, 392(%rsi)
	movq	%r15, 432(%rsi)
	movq	%r9, 472(%rsi)
	movq	%r11, 512(%rsi)
	movabsq	$4604544271217802189, %rax      # imm = 0x3FE6A09E667F3BCD
	movq	%rax, 608(%rsp)
	cvtsi2sdl	16(%rsp), %xmm1
	movsd	.LCPI14_0(%rip), %xmm2          # xmm2 = mem[0],zero
	addsd	%xmm2, %xmm1
	movsd	.LCPI14_1(%rip), %xmm0          # xmm0 = mem[0],zero
	movapd	%xmm0, %xmm4
	divsd	%xmm1, %xmm4
	movsd	%xmm4, 600(%rsp)
	xorps	%xmm1, %xmm1
	cvtsi2sdl	24(%rsp), %xmm1
	addsd	%xmm2, %xmm1
	movapd	%xmm0, %xmm6
	divsd	%xmm1, %xmm6
	xorps	%xmm1, %xmm1
	cvtsi2sdl	20(%rsp), %xmm1
	movsd	%xmm6, 592(%rsp)
	addsd	%xmm2, %xmm1
	movapd	%xmm0, %xmm5
	divsd	%xmm1, %xmm5
	movsd	%xmm5, 584(%rsp)
	movapd	%xmm4, %xmm1
	mulsd	%xmm4, %xmm1
	movapd	%xmm0, %xmm3
	divsd	%xmm1, %xmm3
	movsd	%xmm3, 576(%rsp)
	movapd	%xmm0, %xmm2
	divsd	%xmm4, %xmm2
	addsd	%xmm4, %xmm4
	movapd	%xmm0, %xmm9
	divsd	%xmm4, %xmm9
	movsd	%xmm9, 568(%rsp)
	movsd	%xmm2, 560(%rsp)
	movapd	%xmm6, %xmm1
	mulsd	%xmm6, %xmm1
	movapd	%xmm0, %xmm4
	divsd	%xmm1, %xmm4
	movsd	%xmm4, 552(%rsp)
	movapd	%xmm0, %xmm1
	divsd	%xmm6, %xmm1
	addsd	%xmm6, %xmm6
	movapd	%xmm0, %xmm10
	divsd	%xmm6, %xmm10
	movsd	%xmm10, 544(%rsp)
	movsd	%xmm1, 536(%rsp)
	movapd	%xmm0, %xmm6
	movapd	%xmm5, %xmm8
	movapd	%xmm0, %xmm7
	divsd	%xmm5, %xmm0
	mulsd	%xmm5, %xmm5
	divsd	%xmm5, %xmm6
	movsd	%xmm6, 528(%rsp)
	addsd	%xmm8, %xmm8
	divsd	%xmm8, %xmm7
	movsd	%xmm7, 520(%rsp)
	movsd	%xmm0, 512(%rsp)
	movsd	128(%rsp), %xmm5                # xmm5 = mem[0],zero
	movapd	%xmm3, %xmm8
	mulsd	%xmm5, %xmm8
	movsd	%xmm8, 504(%rsp)
	mulsd	%xmm5, %xmm9
	movsd	%xmm9, 496(%rsp)
	movapd	%xmm4, %xmm9
	mulsd	%xmm5, %xmm9
	movsd	%xmm9, 488(%rsp)
	mulsd	%xmm5, %xmm10
	movsd	%xmm10, 480(%rsp)
	movsd	%xmm6, 288(%rsp)
	movsd	%xmm6, 280(%rsp)
	movsd	%xmm6, 272(%rsp)
	movsd	%xmm6, 264(%rsp)
	movsd	%xmm6, 256(%rsp)
	mulsd	%xmm5, %xmm6
	movsd	%xmm6, 472(%rsp)
	mulsd	%xmm5, %xmm7
	movsd	%xmm7, 464(%rsp)
	addsd	%xmm8, %xmm8
	movsd	%xmm8, 456(%rsp)
	addsd	%xmm9, %xmm9
	movsd	%xmm9, 448(%rsp)
	addsd	%xmm6, %xmm6
	movsd	%xmm6, 440(%rsp)
	mulsd	.LCPI14_2(%rip), %xmm5
	movsd	%xmm5, 432(%rsp)
	movsd	%xmm5, 424(%rsp)
	movsd	.LCPI14_3(%rip), %xmm6          # xmm6 = mem[0],zero
	mulsd	%xmm5, %xmm6
	movsd	%xmm6, 416(%rsp)
	movsd	.LCPI14_4(%rip), %xmm6          # xmm6 = mem[0],zero
	mulsd	%xmm5, %xmm6
	movsd	%xmm6, 408(%rsp)
	mulsd	.LCPI14_5(%rip), %xmm5
	movsd	%xmm5, 400(%rsp)
	movsd	.LCPI14_6(%rip), %xmm5          # xmm5 = mem[0],zero
	movapd	%xmm2, %xmm9
	mulsd	%xmm5, %xmm9
	movsd	%xmm9, 392(%rsp)
	movapd	%xmm1, %xmm6
	mulsd	%xmm5, %xmm6
	movsd	%xmm6, 384(%rsp)
	mulsd	%xmm0, %xmm5
	movsd	%xmm5, 376(%rsp)
	movsd	.LCPI14_7(%rip), %xmm7          # xmm7 = mem[0],zero
	mulsd	%xmm7, %xmm3
	movsd	%xmm3, 368(%rsp)
	movsd	%xmm3, 360(%rsp)
	movsd	%xmm3, 352(%rsp)
	movsd	%xmm3, 344(%rsp)
	movsd	%xmm3, 336(%rsp)
	mulsd	%xmm7, %xmm4
	movsd	%xmm4, 328(%rsp)
	movsd	%xmm4, 320(%rsp)
	movsd	%xmm4, 312(%rsp)
	movsd	%xmm4, 304(%rsp)
	movsd	%xmm4, 296(%rsp)
	movsd	.LCPI14_8(%rip), %xmm3          # xmm3 = mem[0],zero
	movapd	%xmm9, %xmm4
	mulsd	%xmm3, %xmm4
	mulsd	%xmm2, %xmm4
	movsd	%xmm4, 248(%rsp)
	movapd	%xmm2, %xmm4
	mulsd	%xmm9, %xmm4
	movsd	%xmm4, 240(%rsp)
	movsd	.LCPI14_9(%rip), %xmm4          # xmm4 = mem[0],zero
	movapd	%xmm9, %xmm7
	mulsd	%xmm4, %xmm7
	mulsd	%xmm2, %xmm7
	movsd	%xmm7, 232(%rsp)
	movsd	.LCPI14_10(%rip), %xmm7         # xmm7 = mem[0],zero
	movapd	%xmm9, %xmm8
	mulsd	%xmm7, %xmm8
	mulsd	%xmm2, %xmm8
	movsd	%xmm8, 224(%rsp)
	movsd	.LCPI14_11(%rip), %xmm8         # xmm8 = mem[0],zero
	mulsd	%xmm8, %xmm9
	mulsd	%xmm2, %xmm9
	movsd	%xmm9, 216(%rsp)
	movapd	%xmm6, %xmm2
	mulsd	%xmm3, %xmm2
	mulsd	%xmm1, %xmm2
	movsd	%xmm2, 208(%rsp)
	movapd	%xmm1, %xmm2
	mulsd	%xmm6, %xmm2
	movsd	%xmm2, 200(%rsp)
	movapd	%xmm6, %xmm2
	mulsd	%xmm4, %xmm2
	mulsd	%xmm1, %xmm2
	movsd	%xmm2, 192(%rsp)
	movapd	%xmm6, %xmm2
	mulsd	%xmm7, %xmm2
	mulsd	%xmm1, %xmm2
	movsd	%xmm2, 184(%rsp)
	mulsd	%xmm8, %xmm6
	mulsd	%xmm1, %xmm6
	movsd	%xmm6, 176(%rsp)
	mulsd	%xmm5, %xmm3
	mulsd	%xmm0, %xmm3
	movsd	%xmm3, 168(%rsp)
	movapd	%xmm0, %xmm1
	mulsd	%xmm5, %xmm1
	movsd	%xmm1, 160(%rsp)
	mulsd	%xmm5, %xmm4
	mulsd	%xmm0, %xmm4
	movsd	%xmm4, 152(%rsp)
	mulsd	%xmm5, %xmm7
	mulsd	%xmm0, %xmm7
	movsd	%xmm7, 144(%rsp)
	mulsd	%xmm8, %xmm5
	mulsd	%xmm0, %xmm5
	movsd	%xmm5, 136(%rsp)
	movq	%rsp, %rdi
	movq	$ce, (%rdi)
	movl	$520, %edx                      # imm = 0x208
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_28
# %bb.29:                               # %_ZL11HandleError10hipError_tPKci.exit52
	movq	%rsp, %rdi
	movq	$bt, (%rdi)
	leaq	608(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_30
# %bb.31:                               # %_ZL11HandleError10hipError_tPKci.exit54
	movq	%rsp, %rdi
	movq	$dnxm1, (%rdi)
	leaq	600(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_32
# %bb.33:                               # %_ZL11HandleError10hipError_tPKci.exit56
	movq	%rsp, %rdi
	movq	$dnym1, (%rdi)
	leaq	592(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_34
# %bb.35:                               # %_ZL11HandleError10hipError_tPKci.exit58
	movq	%rsp, %rdi
	movq	$dnzm1, (%rdi)
	leaq	584(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_36
# %bb.37:                               # %_ZL11HandleError10hipError_tPKci.exit60
	movq	%rsp, %rdi
	movq	$tx1, (%rdi)
	leaq	576(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_38
# %bb.39:                               # %_ZL11HandleError10hipError_tPKci.exit62
	movq	%rsp, %rdi
	movq	$tx2, (%rdi)
	leaq	568(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_40
# %bb.41:                               # %_ZL11HandleError10hipError_tPKci.exit64
	movq	%rsp, %rdi
	movq	$tx3, (%rdi)
	leaq	560(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_42
# %bb.43:                               # %_ZL11HandleError10hipError_tPKci.exit66
	movq	%rsp, %rdi
	movq	$ty1, (%rdi)
	leaq	552(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_44
# %bb.45:                               # %_ZL11HandleError10hipError_tPKci.exit68
	movq	%rsp, %rdi
	movq	$ty2, (%rdi)
	leaq	544(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_46
# %bb.47:                               # %_ZL11HandleError10hipError_tPKci.exit70
	movq	%rsp, %rdi
	movq	$ty3, (%rdi)
	leaq	536(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_48
# %bb.49:                               # %_ZL11HandleError10hipError_tPKci.exit72
	movq	%rsp, %rdi
	movq	$tz1, (%rdi)
	leaq	528(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_50
# %bb.51:                               # %_ZL11HandleError10hipError_tPKci.exit74
	movq	%rsp, %rdi
	movq	$tz2, (%rdi)
	leaq	520(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_52
# %bb.53:                               # %_ZL11HandleError10hipError_tPKci.exit76
	movq	%rsp, %rdi
	movq	$tz3, (%rdi)
	leaq	512(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_54
# %bb.55:                               # %_ZL11HandleError10hipError_tPKci.exit78
	movq	%rsp, %rdi
	movq	$dtx1, (%rdi)
	leaq	504(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_56
# %bb.57:                               # %_ZL11HandleError10hipError_tPKci.exit80
	movq	%rsp, %rdi
	movq	$dttx2, (%rdi)
	leaq	496(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_58
# %bb.59:                               # %_ZL11HandleError10hipError_tPKci.exit82
	movq	%rsp, %rdi
	movq	$dty1, (%rdi)
	leaq	488(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_60
# %bb.61:                               # %_ZL11HandleError10hipError_tPKci.exit84
	movq	%rsp, %rdi
	movq	$dtty2, (%rdi)
	leaq	480(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_62
# %bb.63:                               # %_ZL11HandleError10hipError_tPKci.exit86
	movq	%rsp, %rdi
	movq	$dtz1, (%rdi)
	leaq	472(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_64
# %bb.65:                               # %_ZL11HandleError10hipError_tPKci.exit88
	movq	%rsp, %rdi
	movq	$dttz2, (%rdi)
	leaq	464(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_66
# %bb.67:                               # %_ZL11HandleError10hipError_tPKci.exit90
	movq	%rsp, %rdi
	movq	$c2dttx1, (%rdi)
	leaq	456(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_68
# %bb.69:                               # %_ZL11HandleError10hipError_tPKci.exit92
	movq	%rsp, %rdi
	movq	$c2dtty1, (%rdi)
	leaq	448(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_70
# %bb.71:                               # %_ZL11HandleError10hipError_tPKci.exit94
	movq	%rsp, %rdi
	movq	$c2dttz1, (%rdi)
	leaq	440(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_72
# %bb.73:                               # %_ZL11HandleError10hipError_tPKci.exit96
	movq	%rsp, %rdi
	movq	$dt, (%rdi)
	leaq	128(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_74
# %bb.75:                               # %_ZL11HandleError10hipError_tPKci.exit98
	movq	%rsp, %rdi
	movq	$dtdssp, (%rdi)
	leaq	432(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_76
# %bb.77:                               # %_ZL11HandleError10hipError_tPKci.exit100
	movq	%rsp, %rdi
	movq	$comz1, (%rdi)
	leaq	424(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_78
# %bb.79:                               # %_ZL11HandleError10hipError_tPKci.exit102
	movq	%rsp, %rdi
	movq	$comz4, (%rdi)
	leaq	416(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_80
# %bb.81:                               # %_ZL11HandleError10hipError_tPKci.exit104
	movq	%rsp, %rdi
	movq	$comz5, (%rdi)
	leaq	408(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_82
# %bb.83:                               # %_ZL11HandleError10hipError_tPKci.exit106
	movq	%rsp, %rdi
	movq	$comz6, (%rdi)
	leaq	400(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_84
# %bb.85:                               # %_ZL11HandleError10hipError_tPKci.exit108
	movq	%rsp, %rdi
	movq	$c3c4tx3, (%rdi)
	leaq	392(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_86
# %bb.87:                               # %_ZL11HandleError10hipError_tPKci.exit110
	movq	%rsp, %rdi
	movq	$c3c4ty3, (%rdi)
	leaq	384(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_88
# %bb.89:                               # %_ZL11HandleError10hipError_tPKci.exit112
	movq	%rsp, %rdi
	movq	$c3c4tz3, (%rdi)
	leaq	376(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_90
# %bb.91:                               # %_ZL11HandleError10hipError_tPKci.exit114
	movq	%rsp, %rdi
	movq	$dx1tx1, (%rdi)
	leaq	368(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_92
# %bb.93:                               # %_ZL11HandleError10hipError_tPKci.exit116
	movq	%rsp, %rdi
	movq	$dx2tx1, (%rdi)
	leaq	360(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_94
# %bb.95:                               # %_ZL11HandleError10hipError_tPKci.exit118
	movq	%rsp, %rdi
	movq	$dx3tx1, (%rdi)
	leaq	352(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_96
# %bb.97:                               # %_ZL11HandleError10hipError_tPKci.exit120
	movq	%rsp, %rdi
	movq	$dx4tx1, (%rdi)
	leaq	344(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_98
# %bb.99:                               # %_ZL11HandleError10hipError_tPKci.exit122
	movq	%rsp, %rdi
	movq	$dx5tx1, (%rdi)
	leaq	336(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_100
# %bb.101:                              # %_ZL11HandleError10hipError_tPKci.exit124
	movq	%rsp, %rdi
	movq	$dy1ty1, (%rdi)
	leaq	328(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_102
# %bb.103:                              # %_ZL11HandleError10hipError_tPKci.exit126
	movq	%rsp, %rdi
	movq	$dy2ty1, (%rdi)
	leaq	320(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_104
# %bb.105:                              # %_ZL11HandleError10hipError_tPKci.exit128
	movq	%rsp, %rdi
	movq	$dy3ty1, (%rdi)
	leaq	312(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_106
# %bb.107:                              # %_ZL11HandleError10hipError_tPKci.exit130
	movq	%rsp, %rdi
	movq	$dy4ty1, (%rdi)
	leaq	304(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_108
# %bb.109:                              # %_ZL11HandleError10hipError_tPKci.exit132
	movq	%rsp, %rdi
	movq	$dy5ty1, (%rdi)
	leaq	296(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_110
# %bb.111:                              # %_ZL11HandleError10hipError_tPKci.exit134
	movq	%rsp, %rdi
	movq	$dz1tz1, (%rdi)
	leaq	288(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_112
# %bb.113:                              # %_ZL11HandleError10hipError_tPKci.exit136
	movq	%rsp, %rdi
	movq	$dz2tz1, (%rdi)
	leaq	280(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_114
# %bb.115:                              # %_ZL11HandleError10hipError_tPKci.exit138
	movq	%rsp, %rdi
	movq	$dz3tz1, (%rdi)
	leaq	272(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_116
# %bb.117:                              # %_ZL11HandleError10hipError_tPKci.exit140
	movq	%rsp, %rdi
	movq	$dz4tz1, (%rdi)
	leaq	264(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_118
# %bb.119:                              # %_ZL11HandleError10hipError_tPKci.exit142
	movq	%rsp, %rdi
	movq	$dz5tz1, (%rdi)
	leaq	256(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_120
# %bb.121:                              # %_ZL11HandleError10hipError_tPKci.exit144
	movq	%rsp, %rdi
	movq	$xxcon1, (%rdi)
	leaq	248(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_122
# %bb.123:                              # %_ZL11HandleError10hipError_tPKci.exit146
	movq	%rsp, %rdi
	movq	$xxcon2, (%rdi)
	leaq	240(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_124
# %bb.125:                              # %_ZL11HandleError10hipError_tPKci.exit148
	movq	%rsp, %rdi
	movq	$xxcon3, (%rdi)
	leaq	232(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_126
# %bb.127:                              # %_ZL11HandleError10hipError_tPKci.exit150
	movq	%rsp, %rdi
	movq	$xxcon4, (%rdi)
	leaq	224(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_128
# %bb.129:                              # %_ZL11HandleError10hipError_tPKci.exit152
	movq	%rsp, %rdi
	movq	$xxcon5, (%rdi)
	leaq	216(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_130
# %bb.131:                              # %_ZL11HandleError10hipError_tPKci.exit154
	movq	%rsp, %rdi
	movq	$yycon1, (%rdi)
	leaq	208(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_132
# %bb.133:                              # %_ZL11HandleError10hipError_tPKci.exit156
	movq	%rsp, %rdi
	movq	$yycon2, (%rdi)
	leaq	200(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_134
# %bb.135:                              # %_ZL11HandleError10hipError_tPKci.exit158
	movq	%rsp, %rdi
	movq	$yycon3, (%rdi)
	leaq	192(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_136
# %bb.137:                              # %_ZL11HandleError10hipError_tPKci.exit160
	movq	%rsp, %rdi
	movq	$yycon4, (%rdi)
	leaq	184(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_138
# %bb.139:                              # %_ZL11HandleError10hipError_tPKci.exit162
	movq	%rsp, %rdi
	movq	$yycon5, (%rdi)
	leaq	176(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_140
# %bb.141:                              # %_ZL11HandleError10hipError_tPKci.exit164
	movq	%rsp, %rdi
	movq	$zzcon1, (%rdi)
	leaq	168(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_142
# %bb.143:                              # %_ZL11HandleError10hipError_tPKci.exit166
	movq	%rsp, %rdi
	movq	$zzcon2, (%rdi)
	leaq	160(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_144
# %bb.145:                              # %_ZL11HandleError10hipError_tPKci.exit168
	movq	%rsp, %rdi
	movq	$zzcon3, (%rdi)
	leaq	152(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_146
# %bb.147:                              # %_ZL11HandleError10hipError_tPKci.exit170
	movq	%rsp, %rdi
	movq	$zzcon4, (%rdi)
	leaq	144(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_148
# %bb.149:                              # %_ZL11HandleError10hipError_tPKci.exit172
	movq	%rsp, %rdi
	movq	$zzcon5, (%rdi)
	leaq	136(%rsp), %rsi
	movl	$8, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB14_150
# %bb.151:                              # %_ZL11HandleError10hipError_tPKci.exit174
	movabsq	$4294967296, %r14               # imm = 0x100000000
	leaq	616(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	40(%rsp), %rdi
	movl	16(%rsp), %esi
	movl	24(%rsp), %edx
	movl	20(%rsp), %ecx
	callq	_Z9exact_rhsPdiii
	movl	20(%rsp), %eax
	movl	24(%rsp), %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movl	16(%rsp), %edx
	btsq	$32, %rdx
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_153
# %bb.152:
	movq	32(%rsp), %rdi
	movl	16(%rsp), %esi
	movl	24(%rsp), %edx
	movl	20(%rsp), %ecx
	callq	_ZL32__device_stub__initialize_kernelPdiii
.LBB14_153:
	movl	16(%rsp), %esi
	movl	24(%rsp), %edx
	movl	20(%rsp), %ecx
	movl	28(%rsp), %r8d
	movq	112(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$1, %edi
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	movl	16(%rsp), %edx
	orq	%r14, %rdx
	movq	%rbx, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB14_155
# %bb.154:
	movq	32(%rsp), %rdi
	movl	16(%rsp), %esi
	movl	24(%rsp), %edx
	movl	20(%rsp), %ecx
	callq	_ZL32__device_stub__initialize_kernelPdiii
.LBB14_155:
	movl	16(%rsp), %esi
	movl	24(%rsp), %edx
	movl	20(%rsp), %ecx
	movl	28(%rsp), %r8d
	movq	112(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	xorl	%edi, %edi
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	48(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	136(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	176(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	192(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z3adibiiiiPdS_S_S_S_S_S_S_S_S_S_S_
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	leaq	656(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%rsp, %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$6, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r14), %rax
	movq	8(%r14), %rcx
	subq	632(%rsp), %rax
	cvtsi2sd	%rax, %xmm1
	subq	640(%rsp), %rcx
	cvtsi2sd	%rcx, %xmm0
	mulsd	.LCPI14_12(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$8, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	8(%rbx), %rcx
	subq	616(%rsp), %rax
	xorps	%xmm1, %xmm1
	cvtsi2sd	%rax, %xmm1
	subq	624(%rsp), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rcx, %xmm0
	mulsd	.LCPI14_12(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	addq	$1192, %rsp                     # imm = 0x4A8
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB14_3:
	.cfi_def_cfa_offset 1232
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1927, %ecx                     # imm = 0x787
	jmp	.LBB14_4
.LBB14_6:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1928, %ecx                     # imm = 0x788
	jmp	.LBB14_4
.LBB14_8:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1929, %ecx                     # imm = 0x789
	jmp	.LBB14_4
.LBB14_10:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1930, %ecx                     # imm = 0x78A
	jmp	.LBB14_4
.LBB14_12:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1931, %ecx                     # imm = 0x78B
	jmp	.LBB14_4
.LBB14_14:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1932, %ecx                     # imm = 0x78C
	jmp	.LBB14_4
.LBB14_16:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1933, %ecx                     # imm = 0x78D
	jmp	.LBB14_4
.LBB14_18:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1934, %ecx                     # imm = 0x78E
	jmp	.LBB14_4
.LBB14_20:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1935, %ecx                     # imm = 0x78F
	jmp	.LBB14_4
.LBB14_22:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1936, %ecx                     # imm = 0x790
	jmp	.LBB14_4
.LBB14_24:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1937, %ecx                     # imm = 0x791
	jmp	.LBB14_4
.LBB14_26:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$1938, %ecx                     # imm = 0x792
	jmp	.LBB14_4
.LBB14_28:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2088, %ecx                     # imm = 0x828
	jmp	.LBB14_4
.LBB14_30:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2089, %ecx                     # imm = 0x829
	jmp	.LBB14_4
.LBB14_32:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2090, %ecx                     # imm = 0x82A
	jmp	.LBB14_4
.LBB14_34:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2091, %ecx                     # imm = 0x82B
	jmp	.LBB14_4
.LBB14_36:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2092, %ecx                     # imm = 0x82C
	jmp	.LBB14_4
.LBB14_38:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2093, %ecx                     # imm = 0x82D
	jmp	.LBB14_4
.LBB14_40:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2094, %ecx                     # imm = 0x82E
	jmp	.LBB14_4
.LBB14_42:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2095, %ecx                     # imm = 0x82F
	jmp	.LBB14_4
.LBB14_44:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2096, %ecx                     # imm = 0x830
	jmp	.LBB14_4
.LBB14_46:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2097, %ecx                     # imm = 0x831
	jmp	.LBB14_4
.LBB14_48:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2098, %ecx                     # imm = 0x832
	jmp	.LBB14_4
.LBB14_50:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2099, %ecx                     # imm = 0x833
	jmp	.LBB14_4
.LBB14_52:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2100, %ecx                     # imm = 0x834
	jmp	.LBB14_4
.LBB14_54:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2101, %ecx                     # imm = 0x835
	jmp	.LBB14_4
.LBB14_56:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2102, %ecx                     # imm = 0x836
	jmp	.LBB14_4
.LBB14_58:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2103, %ecx                     # imm = 0x837
	jmp	.LBB14_4
.LBB14_60:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2104, %ecx                     # imm = 0x838
	jmp	.LBB14_4
.LBB14_62:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2105, %ecx                     # imm = 0x839
	jmp	.LBB14_4
.LBB14_64:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2106, %ecx                     # imm = 0x83A
	jmp	.LBB14_4
.LBB14_66:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2107, %ecx                     # imm = 0x83B
	jmp	.LBB14_4
.LBB14_68:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2108, %ecx                     # imm = 0x83C
	jmp	.LBB14_4
.LBB14_70:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2109, %ecx                     # imm = 0x83D
	jmp	.LBB14_4
.LBB14_72:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2110, %ecx                     # imm = 0x83E
	jmp	.LBB14_4
.LBB14_74:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2111, %ecx                     # imm = 0x83F
	jmp	.LBB14_4
.LBB14_76:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2112, %ecx                     # imm = 0x840
	jmp	.LBB14_4
.LBB14_78:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2113, %ecx                     # imm = 0x841
	jmp	.LBB14_4
.LBB14_80:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2114, %ecx                     # imm = 0x842
	jmp	.LBB14_4
.LBB14_82:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2115, %ecx                     # imm = 0x843
	jmp	.LBB14_4
.LBB14_84:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2116, %ecx                     # imm = 0x844
	jmp	.LBB14_4
.LBB14_86:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2117, %ecx                     # imm = 0x845
	jmp	.LBB14_4
.LBB14_88:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2118, %ecx                     # imm = 0x846
	jmp	.LBB14_4
.LBB14_90:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2119, %ecx                     # imm = 0x847
	jmp	.LBB14_4
.LBB14_92:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2120, %ecx                     # imm = 0x848
	jmp	.LBB14_4
.LBB14_94:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2121, %ecx                     # imm = 0x849
	jmp	.LBB14_4
.LBB14_96:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2122, %ecx                     # imm = 0x84A
	jmp	.LBB14_4
.LBB14_98:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2123, %ecx                     # imm = 0x84B
	jmp	.LBB14_4
.LBB14_100:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2124, %ecx                     # imm = 0x84C
	jmp	.LBB14_4
.LBB14_102:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2125, %ecx                     # imm = 0x84D
	jmp	.LBB14_4
.LBB14_104:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2126, %ecx                     # imm = 0x84E
	jmp	.LBB14_4
.LBB14_106:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2127, %ecx                     # imm = 0x84F
	jmp	.LBB14_4
.LBB14_108:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2128, %ecx                     # imm = 0x850
	jmp	.LBB14_4
.LBB14_110:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2129, %ecx                     # imm = 0x851
	jmp	.LBB14_4
.LBB14_112:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2130, %ecx                     # imm = 0x852
	jmp	.LBB14_4
.LBB14_114:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2131, %ecx                     # imm = 0x853
	jmp	.LBB14_4
.LBB14_116:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2132, %ecx                     # imm = 0x854
	jmp	.LBB14_4
.LBB14_118:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2133, %ecx                     # imm = 0x855
	jmp	.LBB14_4
.LBB14_120:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2134, %ecx                     # imm = 0x856
	jmp	.LBB14_4
.LBB14_122:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2135, %ecx                     # imm = 0x857
	jmp	.LBB14_4
.LBB14_124:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2136, %ecx                     # imm = 0x858
	jmp	.LBB14_4
.LBB14_126:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2137, %ecx                     # imm = 0x859
	jmp	.LBB14_4
.LBB14_128:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2138, %ecx                     # imm = 0x85A
	jmp	.LBB14_4
.LBB14_130:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2139, %ecx                     # imm = 0x85B
	jmp	.LBB14_4
.LBB14_132:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2140, %ecx                     # imm = 0x85C
	jmp	.LBB14_4
.LBB14_134:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2141, %ecx                     # imm = 0x85D
	jmp	.LBB14_4
.LBB14_136:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2142, %ecx                     # imm = 0x85E
	jmp	.LBB14_4
.LBB14_138:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2143, %ecx                     # imm = 0x85F
	jmp	.LBB14_4
.LBB14_140:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2144, %ecx                     # imm = 0x860
	jmp	.LBB14_4
.LBB14_142:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2145, %ecx                     # imm = 0x861
	jmp	.LBB14_4
.LBB14_144:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2146, %ecx                     # imm = 0x862
	jmp	.LBB14_4
.LBB14_146:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2147, %ecx                     # imm = 0x863
	jmp	.LBB14_4
.LBB14_148:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2148, %ecx                     # imm = 0x864
	jmp	.LBB14_4
.LBB14_150:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.15, %edi
	movl	$.L.str, %edx
	movq	%rax, %rsi
	movl	$2149, %ecx                     # imm = 0x865
.LBB14_4:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end14:
	.size	main, .Lfunc_end14-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL32__device_stub__initialize_kernelPdiii,@function # -- Begin function _ZL32__device_stub__initialize_kernelPdiii
_ZL32__device_stub__initialize_kernelPdiii: # @_ZL32__device_stub__initialize_kernelPdiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL17initialize_kernelPdiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_ZL32__device_stub__initialize_kernelPdiii, .Lfunc_end15-_ZL32__device_stub__initialize_kernelPdiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB16_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB16_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL21exact_rhs_kernel_initPdiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL18exact_rhs_kernel_xPdiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL18exact_rhs_kernel_yPdiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL18exact_rhs_kernel_zPdiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL14x_solve_kernelPdS_S_S_S_S_iii, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL14y_solve_kernelPdS_S_S_S_S_iii, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL10add_kernelPdS_iii, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL17initialize_kernelPdiii, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$tx1, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$tx2, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$tx3, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ty1, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ty2, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ty3, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$tz1, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$tz2, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$tz3, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$bt, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dt, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dtdssp, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dnxm1, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dnym1, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dnzm1, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dtx1, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dttx2, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dty1, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dtty2, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dtz1, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dttz2, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c2dttx1, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c2dtty1, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c2dttz1, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$comz1, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$comz4, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$comz5, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$comz6, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c3c4tx3, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c3c4ty3, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c3c4tz3, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$xxcon1, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$xxcon2, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$xxcon3, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$xxcon4, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$xxcon5, %esi
	movl	$.L__unnamed_48, %edx
	movl	$.L__unnamed_48, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dx1tx1, %esi
	movl	$.L__unnamed_49, %edx
	movl	$.L__unnamed_49, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dx2tx1, %esi
	movl	$.L__unnamed_50, %edx
	movl	$.L__unnamed_50, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dx3tx1, %esi
	movl	$.L__unnamed_51, %edx
	movl	$.L__unnamed_51, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dx4tx1, %esi
	movl	$.L__unnamed_52, %edx
	movl	$.L__unnamed_52, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dx5tx1, %esi
	movl	$.L__unnamed_53, %edx
	movl	$.L__unnamed_53, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yycon1, %esi
	movl	$.L__unnamed_54, %edx
	movl	$.L__unnamed_54, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yycon2, %esi
	movl	$.L__unnamed_55, %edx
	movl	$.L__unnamed_55, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yycon3, %esi
	movl	$.L__unnamed_56, %edx
	movl	$.L__unnamed_56, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yycon4, %esi
	movl	$.L__unnamed_57, %edx
	movl	$.L__unnamed_57, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$yycon5, %esi
	movl	$.L__unnamed_58, %edx
	movl	$.L__unnamed_58, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dy1ty1, %esi
	movl	$.L__unnamed_59, %edx
	movl	$.L__unnamed_59, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dy2ty1, %esi
	movl	$.L__unnamed_60, %edx
	movl	$.L__unnamed_60, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dy3ty1, %esi
	movl	$.L__unnamed_61, %edx
	movl	$.L__unnamed_61, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dy4ty1, %esi
	movl	$.L__unnamed_62, %edx
	movl	$.L__unnamed_62, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dy5ty1, %esi
	movl	$.L__unnamed_63, %edx
	movl	$.L__unnamed_63, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$zzcon1, %esi
	movl	$.L__unnamed_64, %edx
	movl	$.L__unnamed_64, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$zzcon2, %esi
	movl	$.L__unnamed_65, %edx
	movl	$.L__unnamed_65, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$zzcon3, %esi
	movl	$.L__unnamed_66, %edx
	movl	$.L__unnamed_66, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$zzcon4, %esi
	movl	$.L__unnamed_67, %edx
	movl	$.L__unnamed_67, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$zzcon5, %esi
	movl	$.L__unnamed_68, %edx
	movl	$.L__unnamed_68, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dz1tz1, %esi
	movl	$.L__unnamed_69, %edx
	movl	$.L__unnamed_69, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dz2tz1, %esi
	movl	$.L__unnamed_70, %edx
	movl	$.L__unnamed_70, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dz3tz1, %esi
	movl	$.L__unnamed_71, %edx
	movl	$.L__unnamed_71, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dz4tz1, %esi
	movl	$.L__unnamed_72, %edx
	movl	$.L__unnamed_72, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$dz5tz1, %esi
	movl	$.L__unnamed_73, %edx
	movl	$.L__unnamed_73, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$ce, %esi
	movl	$.L__unnamed_74, %edx
	movl	$.L__unnamed_74, %ecx
	movl	$520, %r9d                      # imm = 0x208
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end16:
	.size	__hip_module_ctor, .Lfunc_end16-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB17_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB17_2:
	retq
.Lfunc_end17:
	.size	__hip_module_dtor, .Lfunc_end17-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	tx1,@object                     # @tx1
	.local	tx1
	.comm	tx1,8,8
	.type	tx2,@object                     # @tx2
	.local	tx2
	.comm	tx2,8,8
	.type	tx3,@object                     # @tx3
	.local	tx3
	.comm	tx3,8,8
	.type	ty1,@object                     # @ty1
	.local	ty1
	.comm	ty1,8,8
	.type	ty2,@object                     # @ty2
	.local	ty2
	.comm	ty2,8,8
	.type	ty3,@object                     # @ty3
	.local	ty3
	.comm	ty3,8,8
	.type	tz1,@object                     # @tz1
	.local	tz1
	.comm	tz1,8,8
	.type	tz2,@object                     # @tz2
	.local	tz2
	.comm	tz2,8,8
	.type	tz3,@object                     # @tz3
	.local	tz3
	.comm	tz3,8,8
	.type	bt,@object                      # @bt
	.local	bt
	.comm	bt,8,8
	.type	dt,@object                      # @dt
	.local	dt
	.comm	dt,8,8
	.type	dtdssp,@object                  # @dtdssp
	.local	dtdssp
	.comm	dtdssp,8,8
	.type	dnxm1,@object                   # @dnxm1
	.local	dnxm1
	.comm	dnxm1,8,8
	.type	dnym1,@object                   # @dnym1
	.local	dnym1
	.comm	dnym1,8,8
	.type	dnzm1,@object                   # @dnzm1
	.local	dnzm1
	.comm	dnzm1,8,8
	.type	dtx1,@object                    # @dtx1
	.local	dtx1
	.comm	dtx1,8,8
	.type	dttx2,@object                   # @dttx2
	.local	dttx2
	.comm	dttx2,8,8
	.type	dty1,@object                    # @dty1
	.local	dty1
	.comm	dty1,8,8
	.type	dtty2,@object                   # @dtty2
	.local	dtty2
	.comm	dtty2,8,8
	.type	dtz1,@object                    # @dtz1
	.local	dtz1
	.comm	dtz1,8,8
	.type	dttz2,@object                   # @dttz2
	.local	dttz2
	.comm	dttz2,8,8
	.type	c2dttx1,@object                 # @c2dttx1
	.local	c2dttx1
	.comm	c2dttx1,8,8
	.type	c2dtty1,@object                 # @c2dtty1
	.local	c2dtty1
	.comm	c2dtty1,8,8
	.type	c2dttz1,@object                 # @c2dttz1
	.local	c2dttz1
	.comm	c2dttz1,8,8
	.type	comz1,@object                   # @comz1
	.local	comz1
	.comm	comz1,8,8
	.type	comz4,@object                   # @comz4
	.local	comz4
	.comm	comz4,8,8
	.type	comz5,@object                   # @comz5
	.local	comz5
	.comm	comz5,8,8
	.type	comz6,@object                   # @comz6
	.local	comz6
	.comm	comz6,8,8
	.type	c3c4tx3,@object                 # @c3c4tx3
	.local	c3c4tx3
	.comm	c3c4tx3,8,8
	.type	c3c4ty3,@object                 # @c3c4ty3
	.local	c3c4ty3
	.comm	c3c4ty3,8,8
	.type	c3c4tz3,@object                 # @c3c4tz3
	.local	c3c4tz3
	.comm	c3c4tz3,8,8
	.type	xxcon1,@object                  # @xxcon1
	.local	xxcon1
	.comm	xxcon1,8,8
	.type	xxcon2,@object                  # @xxcon2
	.local	xxcon2
	.comm	xxcon2,8,8
	.type	xxcon3,@object                  # @xxcon3
	.local	xxcon3
	.comm	xxcon3,8,8
	.type	xxcon4,@object                  # @xxcon4
	.local	xxcon4
	.comm	xxcon4,8,8
	.type	xxcon5,@object                  # @xxcon5
	.local	xxcon5
	.comm	xxcon5,8,8
	.type	dx1tx1,@object                  # @dx1tx1
	.local	dx1tx1
	.comm	dx1tx1,8,8
	.type	dx2tx1,@object                  # @dx2tx1
	.local	dx2tx1
	.comm	dx2tx1,8,8
	.type	dx3tx1,@object                  # @dx3tx1
	.local	dx3tx1
	.comm	dx3tx1,8,8
	.type	dx4tx1,@object                  # @dx4tx1
	.local	dx4tx1
	.comm	dx4tx1,8,8
	.type	dx5tx1,@object                  # @dx5tx1
	.local	dx5tx1
	.comm	dx5tx1,8,8
	.type	yycon1,@object                  # @yycon1
	.local	yycon1
	.comm	yycon1,8,8
	.type	yycon2,@object                  # @yycon2
	.local	yycon2
	.comm	yycon2,8,8
	.type	yycon3,@object                  # @yycon3
	.local	yycon3
	.comm	yycon3,8,8
	.type	yycon4,@object                  # @yycon4
	.local	yycon4
	.comm	yycon4,8,8
	.type	yycon5,@object                  # @yycon5
	.local	yycon5
	.comm	yycon5,8,8
	.type	dy1ty1,@object                  # @dy1ty1
	.local	dy1ty1
	.comm	dy1ty1,8,8
	.type	dy2ty1,@object                  # @dy2ty1
	.local	dy2ty1
	.comm	dy2ty1,8,8
	.type	dy3ty1,@object                  # @dy3ty1
	.local	dy3ty1
	.comm	dy3ty1,8,8
	.type	dy4ty1,@object                  # @dy4ty1
	.local	dy4ty1
	.comm	dy4ty1,8,8
	.type	dy5ty1,@object                  # @dy5ty1
	.local	dy5ty1
	.comm	dy5ty1,8,8
	.type	zzcon1,@object                  # @zzcon1
	.local	zzcon1
	.comm	zzcon1,8,8
	.type	zzcon2,@object                  # @zzcon2
	.local	zzcon2
	.comm	zzcon2,8,8
	.type	zzcon3,@object                  # @zzcon3
	.local	zzcon3
	.comm	zzcon3,8,8
	.type	zzcon4,@object                  # @zzcon4
	.local	zzcon4
	.comm	zzcon4,8,8
	.type	zzcon5,@object                  # @zzcon5
	.local	zzcon5
	.comm	zzcon5,8,8
	.type	dz1tz1,@object                  # @dz1tz1
	.local	dz1tz1
	.comm	dz1tz1,8,8
	.type	dz2tz1,@object                  # @dz2tz1
	.local	dz2tz1
	.comm	dz2tz1,8,8
	.type	dz3tz1,@object                  # @dz3tz1
	.local	dz3tz1
	.comm	dz3tz1,8,8
	.type	dz4tz1,@object                  # @dz4tz1
	.local	dz4tz1
	.comm	dz4tz1,8,8
	.type	dz5tz1,@object                  # @dz5tz1
	.local	dz5tz1
	.comm	dz5tz1,8,8
	.type	ce,@object                      # @ce
	.local	ce
	.comm	ce,520,16
	.type	_ZL21exact_rhs_kernel_initPdiii,@object # @_ZL21exact_rhs_kernel_initPdiii
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL21exact_rhs_kernel_initPdiii:
	.quad	_ZL36__device_stub__exact_rhs_kernel_initPdiii
	.size	_ZL21exact_rhs_kernel_initPdiii, 8

	.type	_ZL18exact_rhs_kernel_xPdiii,@object # @_ZL18exact_rhs_kernel_xPdiii
	.p2align	3, 0x0
_ZL18exact_rhs_kernel_xPdiii:
	.quad	_ZL33__device_stub__exact_rhs_kernel_xPdiii
	.size	_ZL18exact_rhs_kernel_xPdiii, 8

	.type	_ZL18exact_rhs_kernel_yPdiii,@object # @_ZL18exact_rhs_kernel_yPdiii
	.p2align	3, 0x0
_ZL18exact_rhs_kernel_yPdiii:
	.quad	_ZL33__device_stub__exact_rhs_kernel_yPdiii
	.size	_ZL18exact_rhs_kernel_yPdiii, 8

	.type	_ZL18exact_rhs_kernel_zPdiii,@object # @_ZL18exact_rhs_kernel_zPdiii
	.p2align	3, 0x0
_ZL18exact_rhs_kernel_zPdiii:
	.quad	_ZL33__device_stub__exact_rhs_kernel_zPdiii
	.size	_ZL18exact_rhs_kernel_zPdiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/raydongpub/GPU-FPtuner/master/orig_application/sp_double.hip"
	.size	.L.str, 123

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" Time step %4d\n"
	.size	.L.str.1, 16

	.type	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,@object # @_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii:
	.quad	_ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.size	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, 8

	.type	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,@object # @_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.p2align	3, 0x0
_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii:
	.quad	_ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.size	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, 8

	.type	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii,@object # @_ZL13txinvr_kernelPdS_S_S_S_S_S_iii
	.p2align	3, 0x0
_ZL13txinvr_kernelPdS_S_S_S_S_S_iii:
	.quad	_ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
	.size	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, 8

	.type	_ZL14x_solve_kernelPdS_S_S_S_S_iii,@object # @_ZL14x_solve_kernelPdS_S_S_S_S_iii
	.p2align	3, 0x0
_ZL14x_solve_kernelPdS_S_S_S_S_iii:
	.quad	_ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
	.size	_ZL14x_solve_kernelPdS_S_S_S_S_iii, 8

	.type	_ZL14y_solve_kernelPdS_S_S_S_S_iii,@object # @_ZL14y_solve_kernelPdS_S_S_S_S_iii
	.p2align	3, 0x0
_ZL14y_solve_kernelPdS_S_S_S_S_iii:
	.quad	_ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
	.size	_ZL14y_solve_kernelPdS_S_S_S_S_iii, 8

	.type	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,@object # @_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.p2align	3, 0x0
_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii:
	.quad	_ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.size	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, 8

	.type	_ZL10add_kernelPdS_iii,@object  # @_ZL10add_kernelPdS_iii
	.p2align	3, 0x0
_ZL10add_kernelPdS_iii:
	.quad	_ZL25__device_stub__add_kernelPdS_iii
	.size	_ZL10add_kernelPdS_iii, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"inputsp.data"
	.size	.L.str.2, 13

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"rt"
	.size	.L.str.3, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%i"
	.size	.L.str.5, 3

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%lf"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%i %i %i"
	.size	.L.str.7, 9

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"setparams: Internal error: invalid class %c\n"
	.size	.L.str.8, 45

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	" Size: %4dx%4dx%4d\n"
	.size	.L.str.10, 20

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	" Iterations: %4d    dt_d: %10.6F\n"
	.size	.L.str.11, 34

	.type	_ZL17initialize_kernelPdiii,@object # @_ZL17initialize_kernelPdiii
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL17initialize_kernelPdiii:
	.quad	_ZL32__device_stub__initialize_kernelPdiii
	.size	_ZL17initialize_kernelPdiii, 8

	.type	.L.str.13,@object               # @.str.13
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.13:
	.asciz	"time: "
	.size	.L.str.13, 7

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"kernel: "
	.size	.L.str.14, 9

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"%s in %s at line %d\n"
	.size	.L.str.15, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZL21exact_rhs_kernel_initPdiii"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZL18exact_rhs_kernel_xPdiii"
	.size	.L__unnamed_2, 29

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZL18exact_rhs_kernel_yPdiii"
	.size	.L__unnamed_3, 29

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZL18exact_rhs_kernel_zPdiii"
	.size	.L__unnamed_4, 29

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii"
	.size	.L__unnamed_5, 45

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii"
	.size	.L__unnamed_6, 47

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_ZL13txinvr_kernelPdS_S_S_S_S_S_iii"
	.size	.L__unnamed_7, 36

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_ZL14x_solve_kernelPdS_S_S_S_S_iii"
	.size	.L__unnamed_8, 35

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_ZL14y_solve_kernelPdS_S_S_S_S_iii"
	.size	.L__unnamed_9, 35

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii"
	.size	.L__unnamed_10, 43

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_ZL10add_kernelPdS_iii"
	.size	.L__unnamed_11, 23

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_ZL17initialize_kernelPdiii"
	.size	.L__unnamed_12, 28

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"tx1"
	.size	.L__unnamed_13, 4

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"tx2"
	.size	.L__unnamed_14, 4

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"tx3"
	.size	.L__unnamed_15, 4

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"ty1"
	.size	.L__unnamed_16, 4

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"ty2"
	.size	.L__unnamed_17, 4

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"ty3"
	.size	.L__unnamed_18, 4

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"tz1"
	.size	.L__unnamed_19, 4

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"tz2"
	.size	.L__unnamed_20, 4

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"tz3"
	.size	.L__unnamed_21, 4

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"bt"
	.size	.L__unnamed_22, 3

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"dt"
	.size	.L__unnamed_23, 3

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"dtdssp"
	.size	.L__unnamed_24, 7

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"dnxm1"
	.size	.L__unnamed_25, 6

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"dnym1"
	.size	.L__unnamed_26, 6

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"dnzm1"
	.size	.L__unnamed_27, 6

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"dtx1"
	.size	.L__unnamed_28, 5

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"dttx2"
	.size	.L__unnamed_29, 6

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"dty1"
	.size	.L__unnamed_30, 5

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"dtty2"
	.size	.L__unnamed_31, 6

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"dtz1"
	.size	.L__unnamed_32, 5

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"dttz2"
	.size	.L__unnamed_33, 6

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"c2dttx1"
	.size	.L__unnamed_34, 8

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"c2dtty1"
	.size	.L__unnamed_35, 8

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"c2dttz1"
	.size	.L__unnamed_36, 8

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"comz1"
	.size	.L__unnamed_37, 6

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"comz4"
	.size	.L__unnamed_38, 6

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"comz5"
	.size	.L__unnamed_39, 6

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"comz6"
	.size	.L__unnamed_40, 6

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"c3c4tx3"
	.size	.L__unnamed_41, 8

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"c3c4ty3"
	.size	.L__unnamed_42, 8

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"c3c4tz3"
	.size	.L__unnamed_43, 8

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"xxcon1"
	.size	.L__unnamed_44, 7

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"xxcon2"
	.size	.L__unnamed_45, 7

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"xxcon3"
	.size	.L__unnamed_46, 7

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"xxcon4"
	.size	.L__unnamed_47, 7

	.type	.L__unnamed_48,@object          # @47
.L__unnamed_48:
	.asciz	"xxcon5"
	.size	.L__unnamed_48, 7

	.type	.L__unnamed_49,@object          # @48
.L__unnamed_49:
	.asciz	"dx1tx1"
	.size	.L__unnamed_49, 7

	.type	.L__unnamed_50,@object          # @49
.L__unnamed_50:
	.asciz	"dx2tx1"
	.size	.L__unnamed_50, 7

	.type	.L__unnamed_51,@object          # @50
.L__unnamed_51:
	.asciz	"dx3tx1"
	.size	.L__unnamed_51, 7

	.type	.L__unnamed_52,@object          # @51
.L__unnamed_52:
	.asciz	"dx4tx1"
	.size	.L__unnamed_52, 7

	.type	.L__unnamed_53,@object          # @52
.L__unnamed_53:
	.asciz	"dx5tx1"
	.size	.L__unnamed_53, 7

	.type	.L__unnamed_54,@object          # @53
.L__unnamed_54:
	.asciz	"yycon1"
	.size	.L__unnamed_54, 7

	.type	.L__unnamed_55,@object          # @54
.L__unnamed_55:
	.asciz	"yycon2"
	.size	.L__unnamed_55, 7

	.type	.L__unnamed_56,@object          # @55
.L__unnamed_56:
	.asciz	"yycon3"
	.size	.L__unnamed_56, 7

	.type	.L__unnamed_57,@object          # @56
.L__unnamed_57:
	.asciz	"yycon4"
	.size	.L__unnamed_57, 7

	.type	.L__unnamed_58,@object          # @57
.L__unnamed_58:
	.asciz	"yycon5"
	.size	.L__unnamed_58, 7

	.type	.L__unnamed_59,@object          # @58
.L__unnamed_59:
	.asciz	"dy1ty1"
	.size	.L__unnamed_59, 7

	.type	.L__unnamed_60,@object          # @59
.L__unnamed_60:
	.asciz	"dy2ty1"
	.size	.L__unnamed_60, 7

	.type	.L__unnamed_61,@object          # @60
.L__unnamed_61:
	.asciz	"dy3ty1"
	.size	.L__unnamed_61, 7

	.type	.L__unnamed_62,@object          # @61
.L__unnamed_62:
	.asciz	"dy4ty1"
	.size	.L__unnamed_62, 7

	.type	.L__unnamed_63,@object          # @62
.L__unnamed_63:
	.asciz	"dy5ty1"
	.size	.L__unnamed_63, 7

	.type	.L__unnamed_64,@object          # @63
.L__unnamed_64:
	.asciz	"zzcon1"
	.size	.L__unnamed_64, 7

	.type	.L__unnamed_65,@object          # @64
.L__unnamed_65:
	.asciz	"zzcon2"
	.size	.L__unnamed_65, 7

	.type	.L__unnamed_66,@object          # @65
.L__unnamed_66:
	.asciz	"zzcon3"
	.size	.L__unnamed_66, 7

	.type	.L__unnamed_67,@object          # @66
.L__unnamed_67:
	.asciz	"zzcon4"
	.size	.L__unnamed_67, 7

	.type	.L__unnamed_68,@object          # @67
.L__unnamed_68:
	.asciz	"zzcon5"
	.size	.L__unnamed_68, 7

	.type	.L__unnamed_69,@object          # @68
.L__unnamed_69:
	.asciz	"dz1tz1"
	.size	.L__unnamed_69, 7

	.type	.L__unnamed_70,@object          # @69
.L__unnamed_70:
	.asciz	"dz2tz1"
	.size	.L__unnamed_70, 7

	.type	.L__unnamed_71,@object          # @70
.L__unnamed_71:
	.asciz	"dz3tz1"
	.size	.L__unnamed_71, 7

	.type	.L__unnamed_72,@object          # @71
.L__unnamed_72:
	.asciz	"dz4tz1"
	.size	.L__unnamed_72, 7

	.type	.L__unnamed_73,@object          # @72
.L__unnamed_73:
	.asciz	"dz5tz1"
	.size	.L__unnamed_73, 7

	.type	.L__unnamed_74,@object          # @73
.L__unnamed_74:
	.asciz	"ce"
	.size	.L__unnamed_74, 3

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	" Reading from input file inputsp.data"
	.size	.Lstr, 38

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\n\n NAS Parallel Benchmarks (NPB3.3-CUDA) - SP Benchmark\n"
	.size	.Lstr.1, 57

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL36__device_stub__exact_rhs_kernel_initPdiii
	.addrsig_sym _ZL33__device_stub__exact_rhs_kernel_xPdiii
	.addrsig_sym _ZL33__device_stub__exact_rhs_kernel_yPdiii
	.addrsig_sym _ZL33__device_stub__exact_rhs_kernel_zPdiii
	.addrsig_sym _ZL35__device_stub__compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.addrsig_sym _ZL35__device_stub__compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.addrsig_sym _ZL28__device_stub__txinvr_kernelPdS_S_S_S_S_S_iii
	.addrsig_sym _ZL29__device_stub__x_solve_kernelPdS_S_S_S_S_iii
	.addrsig_sym _ZL29__device_stub__y_solve_kernelPdS_S_S_S_S_iii
	.addrsig_sym _ZL29__device_stub__z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.addrsig_sym _ZL25__device_stub__add_kernelPdS_iii
	.addrsig_sym _ZL32__device_stub__initialize_kernelPdiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym tx1
	.addrsig_sym tx2
	.addrsig_sym tx3
	.addrsig_sym ty1
	.addrsig_sym ty2
	.addrsig_sym ty3
	.addrsig_sym tz1
	.addrsig_sym tz2
	.addrsig_sym tz3
	.addrsig_sym bt
	.addrsig_sym dt
	.addrsig_sym dtdssp
	.addrsig_sym dnxm1
	.addrsig_sym dnym1
	.addrsig_sym dnzm1
	.addrsig_sym dtx1
	.addrsig_sym dttx2
	.addrsig_sym dty1
	.addrsig_sym dtty2
	.addrsig_sym dtz1
	.addrsig_sym dttz2
	.addrsig_sym c2dttx1
	.addrsig_sym c2dtty1
	.addrsig_sym c2dttz1
	.addrsig_sym comz1
	.addrsig_sym comz4
	.addrsig_sym comz5
	.addrsig_sym comz6
	.addrsig_sym c3c4tx3
	.addrsig_sym c3c4ty3
	.addrsig_sym c3c4tz3
	.addrsig_sym xxcon1
	.addrsig_sym xxcon2
	.addrsig_sym xxcon3
	.addrsig_sym xxcon4
	.addrsig_sym xxcon5
	.addrsig_sym dx1tx1
	.addrsig_sym dx2tx1
	.addrsig_sym dx3tx1
	.addrsig_sym dx4tx1
	.addrsig_sym dx5tx1
	.addrsig_sym yycon1
	.addrsig_sym yycon2
	.addrsig_sym yycon3
	.addrsig_sym yycon4
	.addrsig_sym yycon5
	.addrsig_sym dy1ty1
	.addrsig_sym dy2ty1
	.addrsig_sym dy3ty1
	.addrsig_sym dy4ty1
	.addrsig_sym dy5ty1
	.addrsig_sym zzcon1
	.addrsig_sym zzcon2
	.addrsig_sym zzcon3
	.addrsig_sym zzcon4
	.addrsig_sym zzcon5
	.addrsig_sym dz1tz1
	.addrsig_sym dz2tz1
	.addrsig_sym dz3tz1
	.addrsig_sym dz4tz1
	.addrsig_sym dz5tz1
	.addrsig_sym ce
	.addrsig_sym _ZL21exact_rhs_kernel_initPdiii
	.addrsig_sym _ZL18exact_rhs_kernel_xPdiii
	.addrsig_sym _ZL18exact_rhs_kernel_yPdiii
	.addrsig_sym _ZL18exact_rhs_kernel_zPdiii
	.addrsig_sym _ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.addrsig_sym _ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.addrsig_sym _ZL13txinvr_kernelPdS_S_S_S_S_S_iii
	.addrsig_sym _ZL14x_solve_kernelPdS_S_S_S_S_iii
	.addrsig_sym _ZL14y_solve_kernelPdS_S_S_S_S_iii
	.addrsig_sym _ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.addrsig_sym _ZL10add_kernelPdS_iii
	.addrsig_sym _ZL17initialize_kernelPdiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL21exact_rhs_kernel_initPdiii,"axG",@progbits,_ZL21exact_rhs_kernel_initPdiii,comdat
	.globl	_ZL21exact_rhs_kernel_initPdiii ; -- Begin function _ZL21exact_rhs_kernel_initPdiii
	.p2align	8
	.type	_ZL21exact_rhs_kernel_initPdiii,@function
_ZL21exact_rhs_kernel_initPdiii:        ; @_ZL21exact_rhs_kernel_initPdiii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s3, 5
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s15, s15, s5
	s_mul_i32 s2, s6, s5
	s_add_i32 s14, s14, s15
	s_mul_i32 s2, s2, s4
	v_mad_u64_u32 v[1:2], null, s4, s14, v[0:1]
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, v3
	s_add_i32 s3, s3, -1
	s_cmp_lg_u32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc1 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL21exact_rhs_kernel_initPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL21exact_rhs_kernel_initPdiii,"axG",@progbits,_ZL21exact_rhs_kernel_initPdiii,comdat
.Lfunc_end0:
	.size	_ZL21exact_rhs_kernel_initPdiii, .Lfunc_end0-_ZL21exact_rhs_kernel_initPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL18exact_rhs_kernel_xPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_xPdiii,comdat
	.globl	_ZL18exact_rhs_kernel_xPdiii    ; -- Begin function _ZL18exact_rhs_kernel_xPdiii
	.p2align	8
	.type	_ZL18exact_rhs_kernel_xPdiii,@function
_ZL18exact_rhs_kernel_xPdiii:           ; @_ZL18exact_rhs_kernel_xPdiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[8:11], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v30, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s3
	s_mul_i32 s11, s15, s2
	v_add3_u32 v31, v1, s14, 1
	v_add3_u32 v0, v30, s11, 1
	s_add_i32 s2, s10, -1
	s_add_i32 s3, s9, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v31
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_50
; %bb.1:
	v_cvt_f64_i32_e32 v[1:2], v31
	v_cvt_f64_i32_e32 v[3:4], v0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnzm1@rel32@lo+4
	s_addc_u32 s3, s3, dnzm1@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, dnym1@rel32@lo+4
	s_addc_u32 s5, s5, dnym1@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	v_or_b32_e64 v32, 0xe0, 8
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[18:19], s[2:3], v[1:2]
	v_mul_f64 v[20:21], s[4:5], v[3:4]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnxm1@rel32@lo+4
	s_addc_u32 s3, s3, dnxm1@rel32@hi+12
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_add_i32 s33, 16, 40
	s_load_b64 s[6:7], s[2:3], 0x0
                                        ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13
                                        ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13
	s_mov_b32 s16, s33
                                        ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17
                                        ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
                                        ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_3 Depth 2
                                        ;     Child Loop BB1_5 Depth 2
                                        ;     Child Loop BB1_7 Depth 2
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[24:25], s[6:7], v[22:23]
	s_mov_b64 s[14:15], 0
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, ce@rel32@lo+4
	s_addc_u32 s13, s13, ce@rel32@hi+12
.LBB1_3:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[2:3], s[12:13], 0x118
	s_load_b64 s[4:5], s[12:13], 0x190
	s_load_b64 s[18:19], s[12:13], 0xa0
	s_load_b64 s[20:21], s[12:13], 0xc8
	s_load_b64 s[22:23], s[12:13], 0x140
	s_load_b64 s[24:25], s[12:13], 0x1b8
	s_load_b64 s[26:27], s[12:13], 0xf0
	s_load_b64 s[28:29], s[12:13], 0x168
	s_cmp_eq_u32 s14, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[24:25], s[4:5], s[2:3]
	v_fma_f64 v[35:36], v[20:21], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[33:34], v[24:25], v[33:34], s[18:19]
	s_clause 0x4
	s_load_b64 s[2:3], s[12:13], 0x1e0
	s_load_b64 s[4:5], s[12:13], 0x28
	s_load_b64 s[18:19], s[12:13], 0x0
	s_load_b64 s[22:23], s[12:13], 0x50
	s_load_b64 s[24:25], s[12:13], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[35:36], v[20:21], v[35:36], s[20:21]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[37:38], v[18:19], s[2:3], s[28:29]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s14, 2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s14, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[24:25], v[33:34], s[4:5]
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cselect_b32 s5, -1, 0
	v_fma_f64 v[35:36], v[20:21], v[35:36], s[22:23]
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[37:38], v[18:19], v[37:38], s[26:27]
	v_fma_f64 v[33:34], v[24:25], v[33:34], s[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[37:38], v[18:19], v[37:38], s[24:25]
	v_fma_f64 v[33:34], v[20:21], v[35:36], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[18:19], v[37:38], v[33:34]
	v_dual_cndmask_b32 v9, v9, v34 :: v_dual_cndmask_b32 v8, v8, v33
	v_cndmask_b32_e64 v7, v7, v34, s2
	v_cndmask_b32_e64 v6, v6, v33, s2
	v_cndmask_b32_e64 v5, v5, v34, s3
	v_cndmask_b32_e64 v4, v4, v33, s3
	v_cndmask_b32_e64 v3, v3, v34, s4
	v_cndmask_b32_e64 v2, v2, v33, s4
	v_cndmask_b32_e64 v1, v1, v34, s5
	v_cndmask_b32_e64 v0, v0, v33, s5
	s_cbranch_scc1 .LBB1_3
; %bb.4:                                ; %_ZL21exact_solution_kerneldddPd.exit.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b64 s[2:3], 0
	s_mov_b32 s4, s16
.LBB1_5:                                ; %_ZL21exact_solution_kerneldddPd.exit
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v24, v1, v3 :: v_dual_cndmask_b32 v25, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v24, v24, v5 :: v_dual_cndmask_b32 v25, v25, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_dual_cndmask_b32 v24, v24, v7 :: v_dual_cndmask_b32 v33, v25, v6
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v25, v24, v9 :: v_dual_cndmask_b32 v24, v33, v8
	scratch_store_b64 off, v[24:25], s4
	s_add_i32 s4, s4, 8
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	s_cbranch_scc1 .LBB1_5
; %bb.6:                                ;   in Loop: Header=BB1_2 Depth=1
	v_div_scale_f64 v[24:25], null, v[0:1], v[0:1], 1.0
	s_mov_b64 s[2:3], 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[33:34], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[35:36], -v[24:25], v[33:34], 1.0
	v_fma_f64 v[33:34], v[33:34], v[35:36], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], -v[24:25], v[33:34], 1.0
	v_fma_f64 v[33:34], v[33:34], v[35:36], v[33:34]
	v_div_scale_f64 v[35:36], vcc_lo, 1.0, v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[37:38], v[35:36], v[33:34]
	v_fma_f64 v[24:25], -v[24:25], v[37:38], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[24:25], v[24:25], v[33:34], v[37:38]
	v_mov_b32_e32 v33, v32
	v_div_fixup_f64 v[24:25], v[24:25], v[0:1], 1.0
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v34, v1, v3 :: v_dual_cndmask_b32 v35, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v34, v34, v5 :: v_dual_cndmask_b32 v35, v35, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v34, v34, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v36, v35, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_dual_cndmask_b32 v35, v34, v9 :: v_dual_cndmask_b32 v34, v36, v8
	s_cmp_lg_u32 s2, 5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[34:35], v[24:25], v[34:35]
	scratch_store_b64 v33, v[34:35], off
	v_add_nc_u32_e32 v33, 8, v33
	s_cbranch_scc1 .LBB1_7
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mul_i32 s5, s17, 40
	s_add_i32 s4, s17, 1
	s_add_i32 s12, s5, 0xe0
	s_cmp_eq_u32 s17, 2
	s_clause 0x1
	scratch_load_b128 v[33:36], off, s12 offset:8
	scratch_load_b64 v[24:25], off, s12 offset:24
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s17, 1
	v_add_f64 v[22:23], v[22:23], 1.0
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s17, 0
	v_add_nc_u32_e32 v32, 40, v32
	s_cselect_b32 s3, -1, 0
	s_add_i32 s5, s5, 16
	s_clause 0x1
	scratch_load_b128 v[37:40], off, s5 offset:48
	scratch_load_b64 v[43:44], off, s5 offset:64
	s_add_i32 s16, s16, 40
	s_cmp_eq_u32 s4, 3
	s_waitcnt vmcnt(3)
	v_mul_f64 v[41:42], v[33:34], v[33:34]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[39:40], v[35:36], v[39:40]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[35:36], v[35:36], v[35:36], v[41:42]
	v_dual_cndmask_b32 v15, v15, v42 :: v_dual_cndmask_b32 v14, v14, v41
	v_cndmask_b32_e64 v13, v13, v42, s2
	v_cndmask_b32_e64 v12, v12, v41, s2
	v_cndmask_b32_e64 v27, v27, v42, s3
	v_cndmask_b32_e64 v26, v26, v41, s3
	v_fma_f64 v[33:34], v[33:34], v[37:38], v[39:40]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], v[24:25], v[43:44], v[33:34]
	v_fma_f64 v[24:25], v[24:25], v[24:25], v[35:36]
	v_mul_f64 v[33:34], v[33:34], 0.5
	scratch_store_b64 off, v[24:25], s12
	v_dual_cndmask_b32 v17, v17, v34 :: v_dual_cndmask_b32 v16, v16, v33
	v_cndmask_b32_e64 v11, v11, v34, s2
	v_cndmask_b32_e64 v10, v10, v33, s2
	v_cndmask_b32_e64 v29, v29, v34, s3
	v_cndmask_b32_e64 v28, v28, v33, s3
	s_cbranch_scc1 .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s17, s4
	s_branch .LBB1_2
.LBB1_10:                               ; %.preheader193
	s_cmp_lt_i32 s8, 3
	s_cbranch_scc1 .LBB1_50
; %bb.11:                               ; %.lr.ph
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, xxcon3@rel32@lo+4
	s_addc_u32 s3, s3, xxcon3@rel32@hi+12
	v_mul_lo_u32 v24, s9, v31
	s_load_b64 s[2:3], s[2:3], 0x0
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, tx2@rel32@lo+4
	s_addc_u32 s13, s13, tx2@rel32@hi+12
	s_load_b64 s[4:5], s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dx1tx1@rel32@lo+4
	s_addc_u32 s1, s1, dx1tx1@rel32@hi+12
	s_movk_i32 s14, 0x80
	s_mov_b32 s40, 16
	v_add_nc_u32_e64 v34, s14, 16
	v_add3_u32 v30, v30, v24, s11
	s_load_b64 s[14:15], s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, xxcon1@rel32@lo+4
	s_addc_u32 s1, s1, xxcon1@rel32@hi+12
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, dx2tx1@rel32@lo+4
	s_addc_u32 s19, s19, dx2tx1@rel32@hi+12
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, xxcon2@rel32@lo+4
	s_addc_u32 s21, s21, xxcon2@rel32@hi+12
	v_mad_u64_u32 v[24:25], null, s8, v30, s[8:9]
	v_mov_b32_e32 v22, 0xe0
	s_addk_i32 s40, 0x50
	s_load_b64 s[16:17], s[0:1], 0x0
	s_load_b64 s[18:19], s[18:19], 0x0
	s_load_b64 s[20:21], s[20:21], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dx3tx1@rel32@lo+4
	s_addc_u32 s1, s1, dx3tx1@rel32@hi+12
	s_load_b64 s[12:13], s[12:13], 0x0
	s_mul_i32 s52, s10, s9
	v_dual_mov_b32 v32, 16 :: v_dual_add_nc_u32 v37, 1, v24
	v_add_nc_u32_e32 v35, 0x58, v22
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[22:23], s[2:3], 0.5
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dx4tx1@rel32@lo+4
	s_addc_u32 s3, s3, dx4tx1@rel32@hi+12
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, xxcon4@rel32@lo+4
	s_addc_u32 s27, s27, xxcon4@rel32@hi+12
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, xxcon5@rel32@lo+4
	s_addc_u32 s29, s29, xxcon5@rel32@hi+12
	s_getpc_b64 s[30:31]
	s_add_u32 s30, s30, dx5tx1@rel32@lo+4
	s_addc_u32 s31, s31, dx5tx1@rel32@hi+12
	s_load_b64 s[22:23], s[0:1], 0x0
	s_load_b64 s[24:25], s[2:3], 0x0
	s_load_b64 s[26:27], s[26:27], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	s_load_b64 s[30:31], s[30:31], 0x0
	s_add_i32 s41, s8, -3
	s_add_i32 s42, s8, -2
	s_add_u32 s43, s4, 16
	s_addc_u32 s44, s5, 0
	s_movk_i32 s0, 0xa0
	s_add_u32 s45, s4, 8
	s_addc_u32 s46, s5, 0
	s_ashr_i32 s47, s8, 31
	v_add_nc_u32_e32 v33, 0x78, v32
	v_add_nc_u32_e64 v36, s0, 16
	s_add_u32 s49, s4, -16
	s_addc_u32 s50, s5, -1
	s_add_u32 s51, s4, 0xffffffe8
	s_mov_b32 s10, 0x9999999a
	s_mov_b32 s34, 0x66666666
	s_mov_b32 s48, s8
	s_mov_b32 s11, 0x3fd99999
	s_mov_b32 s35, 0x3ff66666
	s_addc_u32 s9, s5, -1
	s_mul_i32 s52, s52, s8
	s_mov_b32 s53, 1
.LBB1_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_14 Depth 2
                                        ;     Child Loop BB1_16 Depth 2
                                        ;     Child Loop BB1_20 Depth 2
                                        ;     Child Loop BB1_30 Depth 2
                                        ;     Child Loop BB1_34 Depth 2
                                        ;     Child Loop BB1_38 Depth 2
                                        ;     Child Loop BB1_42 Depth 2
                                        ;     Child Loop BB1_44 Depth 2
                                        ;     Child Loop BB1_47 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s53, 2
	s_cmp_ge_i32 s0, s8
	s_cbranch_scc1 .LBB1_17
; %bb.13:                               ;   in Loop: Header=BB1_12 Depth=1
	v_cvt_f64_i32_e32 v[30:31], s0
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[36:37]
	s_add_u32 s36, s36, ce@rel32@lo+4
	s_addc_u32 s37, s37, ce@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[30:31], s[6:7], v[30:31]
.LBB1_14:                               ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[0:1], s[36:37], 0x118
	s_load_b64 s[2:3], s[36:37], 0x190
	s_load_b64 s[54:55], s[36:37], 0xa0
	s_load_b64 s[56:57], s[36:37], 0xc8
	s_load_b64 s[58:59], s[36:37], 0x140
	s_load_b64 s[60:61], s[36:37], 0x1b8
	s_load_b64 s[62:63], s[36:37], 0xf0
	s_load_b64 s[64:65], s[36:37], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[30:31], s[2:3], s[0:1]
	v_fma_f64 v[40:41], v[20:21], s[60:61], s[58:59]
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[54:55]
	s_clause 0x4
	s_load_b64 s[0:1], s[36:37], 0x1e0
	s_load_b64 s[2:3], s[36:37], 0x28
	s_load_b64 s[54:55], s[36:37], 0x0
	s_load_b64 s[58:59], s[36:37], 0x50
	s_load_b64 s[60:61], s[36:37], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[40:41], v[20:21], v[40:41], s[56:57]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[42:43], v[18:19], s[0:1], s[64:65]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[40:41], v[20:21], v[40:41], s[58:59]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s36, s36, 8
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[18:19], v[42:43], s[62:63]
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], v[18:19], v[42:43], s[60:61]
	v_fma_f64 v[38:39], v[20:21], v[40:41], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[18:19], v[42:43], v[38:39]
	v_dual_cndmask_b32 v9, v9, v39 :: v_dual_cndmask_b32 v8, v8, v38
	v_cndmask_b32_e64 v7, v7, v39, s0
	v_cndmask_b32_e64 v6, v6, v38, s0
	v_cndmask_b32_e64 v5, v5, v39, s1
	v_cndmask_b32_e64 v4, v4, v38, s1
	v_cndmask_b32_e64 v3, v3, v39, s2
	v_cndmask_b32_e64 v2, v2, v38, s2
	v_cndmask_b32_e64 v1, v1, v39, s3
	v_cndmask_b32_e64 v0, v0, v38, s3
	s_cbranch_scc1 .LBB1_14
; %bb.15:                               ; %_ZL21exact_solution_kerneldddPd.exit167.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_mov_b32_e32 v25, v36
	s_mov_b64 s[0:1], 0
.LBB1_16:                               ; %_ZL21exact_solution_kerneldddPd.exit167
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_dual_cndmask_b32 v30, v1, v3 :: v_dual_cndmask_b32 v31, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v30, v30, v5 :: v_dual_cndmask_b32 v31, v31, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v30, v30, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v38, v31, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_cndmask_b32_e32 v31, v30, v9, vcc_lo
	v_cndmask_b32_e32 v30, v38, v8, vcc_lo
	s_cmp_lg_u32 s0, 5
	scratch_store_b64 v25, v[30:31], off
	v_add_nc_u32_e32 v25, 8, v25
	s_cbranch_scc1 .LBB1_16
.LBB1_17:                               ; %NodeBlock
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_clause 0xf
	scratch_load_b128 v[0:3], off, off offset:88
	scratch_load_b64 v[8:9], off, off offset:168
	scratch_load_b128 v[4:7], off, off offset:224
	scratch_load_b128 v[38:41], off, off offset:304
	scratch_load_b128 v[42:45], off, off offset:256
	scratch_load_b128 v[46:49], off, off offset:272
	scratch_load_b128 v[50:53], off, off offset:320
	scratch_load_b128 v[54:57], off, off offset:72
	scratch_load_b128 v[58:61], off, off offset:288
	scratch_load_b128 v[62:65], off, off offset:136
	scratch_load_b128 v[66:69], off, off offset:56
	scratch_load_b64 v[30:31], off, off offset:336
	scratch_load_b128 v[70:73], off, off offset:152
	scratch_load_b128 v[74:77], off, off offset:104
	scratch_load_b128 v[78:81], off, off offset:120
	scratch_load_b128 v[82:85], off, off offset:240
	v_mul_f64 v[86:87], v[28:29], s[10:11]
	v_mul_f64 v[88:89], v[16:17], s[10:11]
	v_fma_f64 v[92:93], v[12:13], -2.0, v[14:15]
	s_mov_b32 s1, -1
	s_mov_b32 s3, 0
	s_cmp_lt_i32 s53, 2
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[26:27], v[92:93]
	s_waitcnt vmcnt(15)
	v_fma_f64 v[86:87], v[0:1], s[34:35], -v[86:87]
	s_waitcnt vmcnt(14)
	v_add_f64 v[90:91], v[8:9], -v[16:17]
	v_add_f64 v[28:29], v[0:1], -v[28:29]
	v_fma_f64 v[88:89], v[8:9], s[34:35], -v[88:89]
	s_waitcnt vmcnt(11)
	v_fma_f64 v[38:39], v[44:45], -2.0, v[38:39]
	s_waitcnt vmcnt(10)
	v_fma_f64 v[44:45], v[46:47], -2.0, v[40:41]
	s_waitcnt vmcnt(9)
	v_fma_f64 v[46:47], v[48:49], -2.0, v[50:51]
	s_waitcnt vmcnt(8)
	v_mul_f64 v[48:49], v[6:7], v[54:55]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[50:51], v[58:59], -2.0, v[52:53]
	v_mul_f64 v[52:53], v[6:7], v[56:57]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[2:3], v[2:3], -2.0, v[62:63]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[8:9], v[80:81], -2.0, v[8:9]
	v_mul_f64 v[86:87], v[6:7], v[86:87]
	v_mul_f64 v[90:91], v[90:91], s[10:11]
	v_mul_f64 v[28:29], v[28:29], s[10:11]
	v_add_f64 v[4:5], v[4:5], v[38:39]
	v_fma_f64 v[48:49], v[40:41], v[70:71], -v[48:49]
	v_add_f64 v[2:3], v[66:67], v[2:3]
	v_add_f64 v[8:9], v[0:1], v[8:9]
	v_fma_f64 v[86:87], v[40:41], v[88:89], -v[86:87]
	v_fma_f64 v[58:59], v[64:65], v[40:41], v[90:91]
	v_fma_f64 v[27:28], v[68:69], v[6:7], v[28:29]
	v_fma_f64 v[29:30], v[60:61], -2.0, v[30:31]
	v_fma_f64 v[40:41], v[40:41], v[72:73], -v[52:53]
	v_fma_f64 v[52:53], v[74:75], -2.0, v[64:65]
	v_fma_f64 v[60:61], v[78:79], -2.0, v[72:73]
	v_add_f64 v[6:7], v[6:7], v[44:45]
	s_waitcnt vmcnt(0)
	v_add_f64 v[44:45], v[82:83], v[46:47]
	v_add_f64 v[46:47], v[84:85], v[50:51]
	v_fma_f64 v[38:39], -s[12:13], v[86:87], 0
	v_add_f64 v[27:28], v[58:59], -v[27:28]
	v_fma_f64 v[58:59], v[76:77], -2.0, v[70:71]
	v_add_f64 v[29:30], v[42:43], v[29:30]
	v_fma_f64 v[42:43], -s[12:13], v[48:49], 0
	v_fma_f64 v[40:41], -s[12:13], v[40:41], 0
	v_add_f64 v[50:51], v[56:57], v[60:61]
	v_fma_f64 v[4:5], v[22:23], v[4:5], v[38:39]
	v_add_f64 v[38:39], v[64:65], -v[68:69]
	v_fma_f64 v[27:28], -s[12:13], v[27:28], 0
	v_add_f64 v[48:49], v[54:55], v[58:59]
	v_fma_f64 v[42:43], s[20:21], v[44:45], v[42:43]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[4:5], v[25:26], s[26:27], v[4:5]
	v_fma_f64 v[25:26], -s[12:13], v[38:39], 0
	v_add_f64 v[38:39], v[68:69], v[52:53]
	v_fma_f64 v[6:7], s[16:17], v[6:7], v[27:28]
	v_fma_f64 v[27:28], s[20:21], v[46:47], v[40:41]
	v_fma_f64 v[29:30], s[28:29], v[29:30], v[4:5]
	v_fma_f64 v[0:1], s[14:15], v[2:3], v[25:26]
	v_fma_f64 v[4:5], s[22:23], v[48:49], v[42:43]
	v_fma_f64 v[2:3], s[18:19], v[38:39], v[6:7]
	v_fma_f64 v[6:7], s[24:25], v[50:51], v[27:28]
	v_fma_f64 v[8:9], s[30:31], v[8:9], v[29:30]
	s_cbranch_scc1 .LBB1_23
; %bb.18:                               ; %LeafBlock452
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_eq_u32 s53, 2
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB1_22
; %bb.19:                               ; %.preheader190.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_mov_b32_e32 v25, v24
	s_mov_b64 s[36:37], 0
	s_mov_b32 s38, s40
.LBB1_20:                               ; %.preheader190
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s38 offset:-40
	scratch_load_b64 v[28:29], off, s38
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s36, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s36, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v30, v5, s0
	s_cmp_eq_u32 s36, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s39, s38, 40
	v_cndmask_b32_e64 v40, v30, v7, s1
	scratch_load_b64 v[30:31], off, s39
	s_add_i32 s39, s38, 0x50
	s_add_i32 s38, s38, 8
	scratch_load_b64 v[38:39], off, s39
	s_add_u32 s36, s36, 1
	s_addc_u32 s37, s37, 0
	s_cmp_eq_u32 s36, 5
	s_waitcnt vmcnt(3)
	v_mul_f64 v[26:27], v[26:27], -4.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], 0x40180000, v[28:29], v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v40, v9, s2
	v_cndmask_b32_e64 v28, v28, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v6, s1
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[30:31], -4.0, v[26:27]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[38:39], v[26:27]
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s52, v25
	v_add_co_u32 v29, vcc_lo, s43, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s44, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB1_20
; %bb.21:                               ; %Flow454
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s0, 0
.LBB1_22:                               ; %Flow465
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s1, 0
.LBB1_23:                               ; %Flow464
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB1_25
; %bb.24:                               ; %LeafBlock
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lg_u32 s53, 1
	s_mov_b32 s3, -1
	s_cselect_b32 s0, -1, 0
.LBB1_25:                               ; %Flow466
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_40
; %bb.26:                               ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_gt_u32 s53, 2
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s53, s41
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_cbranch_vccz .LBB1_36
; %bb.27:                               ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lg_u32 s53, s41
	s_cbranch_scc0 .LBB1_32
; %bb.28:                               ;   in Loop: Header=BB1_12 Depth=1
	s_cmp_lg_u32 s53, s42
	s_cbranch_scc1 .LBB1_31
; %bb.29:                               ; %.preheader186.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_mov_b32_e32 v25, v24
	s_mov_b64 s[36:37], 0
	s_mov_b32 s3, s33
.LBB1_30:                               ; %.preheader186
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s3 offset:-40
	scratch_load_b64 v[28:29], off, s3
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s36, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s36, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v30, v5, s0
	s_cmp_eq_u32 s36, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	v_cndmask_b32_e64 v38, v30, v7, s1
	scratch_load_b64 v[30:31], off, s38
	s_add_u32 s36, s36, 1
	s_addc_u32 s37, s37, 0
	s_add_i32 s3, s3, 8
	s_cmp_eq_u32 s36, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[28:29], -4.0, v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v38, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v4, s0
	v_cndmask_b32_e64 v28, v28, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[26:27], 0x40140000, v[30:31], v[26:27]
	v_fma_f64 v[26:27], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v29, 31, v25
	v_add_co_u32 v28, vcc_lo, v25, s48
	v_add_nc_u32_e32 v25, s52, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v29, vcc_lo, s47, v29, vcc_lo
	v_lshlrev_b64 v[28:29], 3, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s49, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s50, v29, vcc_lo
	global_store_b64 v[28:29], v[26:27], off
	s_cbranch_scc0 .LBB1_30
.LBB1_31:                               ; %Flow456
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s0, 0
.LBB1_32:                               ; %Flow458
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_35
; %bb.33:                               ; %.preheader184.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_dual_mov_b32 v25, v33 :: v_dual_mov_b32 v26, v24
	s_mov_b64 s[0:1], 0
.LBB1_34:                               ; %.preheader184
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x3
	scratch_load_b64 v[27:28], v25, off offset:-120
	scratch_load_b64 v[29:30], v25, off offset:-80
	scratch_load_b64 v[38:39], v25, off offset:-40
	scratch_load_b64 v[40:41], v25, off
	s_cmp_eq_u32 s0, 1
	v_add_nc_u32_e32 v25, 8, v25
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[27:28], v[29:30], -4.0, v[27:28]
	v_dual_cndmask_b32 v29, v1, v3 :: v_dual_cndmask_b32 v30, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v29, v29, v5 :: v_dual_cndmask_b32 v30, v30, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v29, v29, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v31, v30, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_dual_cndmask_b32 v30, v29, v9 :: v_dual_cndmask_b32 v29, v31, v8
	s_cmp_eq_u32 s0, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[27:28], 0x40180000, v[38:39], v[27:28]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], v[40:41], -4.0, v[27:28]
	v_fma_f64 v[27:28], 0xbfd00000, v[27:28], v[29:30]
	v_ashrrev_i32_e32 v30, 31, v26
	v_add_co_u32 v29, vcc_lo, v26, s48
	v_add_nc_u32_e32 v26, s52, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v30, vcc_lo, s47, v30, vcc_lo
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s51, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB1_34
.LBB1_35:                               ; %Flow459
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s0, 0
.LBB1_36:                               ; %Flow461
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_39
; %bb.37:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_mov_b32_e32 v25, v37
	s_mov_b64 s[36:37], 0
	s_mov_b32 s3, s40
.LBB1_38:                               ; %.preheader
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x2
	scratch_load_b64 v[26:27], off, s3 offset:-80
	scratch_load_b64 v[28:29], off, s3 offset:-40
	scratch_load_b64 v[30:31], off, s3
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s36, 2
	v_cndmask_b32_e32 v38, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s36, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v38, v38, v5, s0
	s_cmp_eq_u32 s36, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	v_cndmask_b32_e64 v42, v38, v7, s1
	scratch_load_b64 v[38:39], off, s38
	s_add_i32 s38, s3, 0x50
	s_add_u32 s36, s36, 1
	scratch_load_b64 v[40:41], off, s38
	s_addc_u32 s37, s37, 0
	s_add_i32 s3, s3, 8
	s_cmp_eq_u32 s36, 5
	s_waitcnt vmcnt(3)
	v_fma_f64 v[26:27], v[28:29], -4.0, v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v42, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v4, s0
	v_cndmask_b32_e64 v28, v28, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[26:27], 0x40180000, v[30:31], v[26:27]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[38:39], -4.0, v[26:27]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[40:41], v[26:27]
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s52, v25
	v_add_co_u32 v29, vcc_lo, s4, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB1_38
.LBB1_39:                               ; %Flow462
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s3, 0
.LBB1_40:                               ; %Flow467
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB1_43
; %bb.41:                               ; %.preheader188.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	v_mov_b32_e32 v25, v24
	s_mov_b64 s[36:37], 0
	s_mov_b32 s3, s40
.LBB1_42:                               ; %.preheader188
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s36, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v26, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s36, 3
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v26, v26, v5, s0
	s_cmp_eq_u32 s36, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v38, v26, v7, s1
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s38
	scratch_load_b64 v[28:29], off, s3
	s_add_i32 s38, s3, 0x50
	s_add_i32 s3, s3, 8
	scratch_load_b64 v[30:31], off, s38
	s_add_u32 s36, s36, 1
	s_addc_u32 s37, s37, 0
	s_cmp_eq_u32 s36, 5
	s_waitcnt vmcnt(2)
	v_mul_f64 v[26:27], v[26:27], -4.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], 0x40140000, v[28:29], v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v38, v9, s2
	v_cndmask_b32_e64 v28, v28, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v6, s1
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(0)
	v_add_f64 v[26:27], v[30:31], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s52, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v29, vcc_lo, s45, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s46, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB1_42
.LBB1_43:                               ; %.loopexit.preheader
                                        ;   in Loop: Header=BB1_12 Depth=1
	s_mov_b32 s0, 0
.LBB1_44:                               ; %.loopexit
                                        ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s1, v32
	v_add_nc_u32_e64 v25, 0xe0, s0
	s_add_i32 s37, s0, 0xe0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s1, s1, s0
	v_add_nc_u32_e32 v31, 40, v25
	s_add_i32 s2, s1, 40
	v_add_nc_u32_e32 v42, 0x50, v25
	s_add_i32 s3, s1, 0x50
	s_add_i32 s36, s1, 0x78
	s_addk_i32 s1, 0xa0
	s_clause 0x3
	scratch_load_b64 v[25:26], off, s2
	scratch_load_b64 v[27:28], off, s3
	scratch_load_b64 v[29:30], off, s36
	scratch_load_b64 v[38:39], off, s1
	s_clause 0x1
	scratch_load_b64 v[40:41], v31, off
	scratch_load_b64 v[42:43], v42, off
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 8
	s_waitcnt vmcnt(5)
	scratch_store_b64 off, v[25:26], s1
	s_waitcnt vmcnt(4)
	scratch_store_b64 off, v[27:28], s2
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[29:30], s3
	s_waitcnt vmcnt(2)
	scratch_store_b64 off, v[38:39], s36
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[40:41], s37
	s_waitcnt vmcnt(0)
	scratch_store_b64 v31, v[42:43], off
	s_cmp_lg_u32 s0, 40
	s_cbranch_scc1 .LBB1_44
; %bb.45:                               ;   in Loop: Header=BB1_12 Depth=1
	v_dual_mov_b32 v26, v12 :: v_dual_mov_b32 v27, v13
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	v_dual_mov_b32 v28, v10 :: v_dual_mov_b32 v29, v11
	v_dual_mov_b32 v10, v16 :: v_dual_mov_b32 v11, v17
	s_cmp_ge_i32 s53, s42
	s_cbranch_scc1 .LBB1_49
; %bb.46:                               ;   in Loop: Header=BB1_12 Depth=1
	scratch_load_b64 v[14:15], off, off offset:136
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[16:17], null, v[14:15], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[30:31], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[38:39], -v[16:17], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[38:39], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], -v[16:17], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[38:39], v[30:31]
	v_div_scale_f64 v[38:39], vcc_lo, 1.0, v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[40:41], v[38:39], v[30:31]
	v_fma_f64 v[16:17], -v[16:17], v[40:41], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[16:17], v[16:17], v[30:31], v[40:41]
	v_div_fixup_f64 v[14:15], v[16:17], v[14:15], 1.0
.LBB1_47:                               ;   Parent Loop BB1_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v16, s0, v34
	v_add_nc_u32_e32 v25, s0, v35
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 32
	scratch_load_b64 v[16:17], v16, off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[16:17], v[14:15], v[16:17]
	scratch_store_b64 v25, v[16:17], off
	s_cbranch_scc1 .LBB1_47
; %bb.48:                               ;   in Loop: Header=BB1_12 Depth=1
	s_clause 0x3
	scratch_load_b128 v[38:41], off, off offset:144
	scratch_load_b128 v[42:45], off, off offset:312
	scratch_load_b64 v[16:17], off, off offset:328
	scratch_load_b64 v[30:31], off, off offset:160
	s_waitcnt vmcnt(2)
	v_mul_f64 v[40:41], v[44:45], v[40:41]
	v_mul_f64 v[14:15], v[42:43], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[42:43], v[38:39], v[40:41]
	v_fma_f64 v[40:41], v[44:45], v[44:45], v[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[16:17], v[30:31], v[38:39]
	v_fma_f64 v[38:39], v[16:17], v[16:17], v[40:41]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[16:17], v[30:31], 0.5
	scratch_store_b64 off, v[38:39], off offset:304
.LBB1_49:                               ;   in Loop: Header=BB1_12 Depth=1
	v_add_nc_u32_e32 v37, 1, v37
	s_add_i32 s0, s53, 1
	s_cmp_lg_u32 s53, s42
	s_mov_b32 s53, s0
	s_cbranch_scc1 .LBB1_12
.LBB1_50:                               ; %.loopexit194
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL18exact_rhs_kernel_xPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 352
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 94
		.amdhsa_next_free_sgpr 66
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL18exact_rhs_kernel_xPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_xPdiii,comdat
.Lfunc_end1:
	.size	_ZL18exact_rhs_kernel_xPdiii, .Lfunc_end1-_ZL18exact_rhs_kernel_xPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5104
; NumSgprs: 68
; NumVgprs: 94
; ScratchSize: 352
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 68
; NumVGPRsForWavesPerEU: 94
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL18exact_rhs_kernel_yPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_yPdiii,comdat
	.globl	_ZL18exact_rhs_kernel_yPdiii    ; -- Begin function _ZL18exact_rhs_kernel_yPdiii
	.p2align	8
	.type	_ZL18exact_rhs_kernel_yPdiii,@function
_ZL18exact_rhs_kernel_yPdiii:           ; @_ZL18exact_rhs_kernel_yPdiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[8:11], s[0:1], 0x8
	v_and_b32_e32 v39, 0x3ff, v0
	v_bfe_u32 v29, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s26, s14, s3
	s_mul_i32 s11, s15, s2
	v_add3_u32 v34, v39, s26, 1
	v_add3_u32 v18, v29, s11, 1
	s_add_i32 s2, s10, -1
	s_add_i32 s3, s8, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v34
	v_cmp_gt_i32_e64 s2, s3, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_50
; %bb.1:
	v_cvt_f64_i32_e32 v[0:1], v34
	v_cvt_f64_i32_e32 v[2:3], v18
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnzm1@rel32@lo+4
	s_addc_u32 s3, s3, dnzm1@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, dnxm1@rel32@lo+4
	s_addc_u32 s5, s5, dnxm1@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	v_or_b32_e64 v32, 0xe0, 8
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $vgpr27_vgpr28
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[19:20], s[2:3], v[0:1]
	v_mul_f64 v[21:22], s[4:5], v[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnym1@rel32@lo+4
	s_addc_u32 s3, s3, dnym1@rel32@hi+12
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_add_i32 s33, 16, 40
	s_load_b64 s[6:7], s[2:3], 0x0
                                        ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13
                                        ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13
	s_mov_b32 s16, s33
                                        ; implicit-def: $vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17
                                        ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
                                        ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
                                        ;     Child Loop BB2_5 Depth 2
                                        ;     Child Loop BB2_7 Depth 2
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[30:31], s[6:7], v[23:24]
	s_mov_b64 s[14:15], 0
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, ce@rel32@lo+4
	s_addc_u32 s13, s13, ce@rel32@hi+12
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[2:3], s[12:13], 0x118
	s_load_b64 s[4:5], s[12:13], 0x190
	s_load_b64 s[18:19], s[12:13], 0xa0
	s_load_b64 s[20:21], s[12:13], 0xc8
	s_load_b64 s[22:23], s[12:13], 0x140
	s_load_b64 s[24:25], s[12:13], 0x1b8
	s_load_b64 s[28:29], s[12:13], 0xf0
	s_load_b64 s[30:31], s[12:13], 0x168
	s_cmp_eq_u32 s14, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[21:22], s[4:5], s[2:3]
	v_fma_f64 v[37:38], v[30:31], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[35:36], v[21:22], v[35:36], s[18:19]
	s_clause 0x4
	s_load_b64 s[2:3], s[12:13], 0x1e0
	s_load_b64 s[4:5], s[12:13], 0x28
	s_load_b64 s[18:19], s[12:13], 0x0
	s_load_b64 s[22:23], s[12:13], 0x50
	s_load_b64 s[24:25], s[12:13], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[37:38], v[30:31], v[37:38], s[20:21]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[40:41], v[19:20], s[2:3], s[30:31]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s14, 2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s14, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[35:36], v[21:22], v[35:36], s[4:5]
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cselect_b32 s5, -1, 0
	v_fma_f64 v[37:38], v[30:31], v[37:38], s[22:23]
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], v[19:20], v[40:41], s[28:29]
	v_fma_f64 v[35:36], v[21:22], v[35:36], s[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[40:41], v[19:20], v[40:41], s[24:25]
	v_fma_f64 v[35:36], v[30:31], v[37:38], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[19:20], v[40:41], v[35:36]
	v_dual_cndmask_b32 v9, v9, v36 :: v_dual_cndmask_b32 v8, v8, v35
	v_cndmask_b32_e64 v7, v7, v36, s2
	v_cndmask_b32_e64 v6, v6, v35, s2
	v_cndmask_b32_e64 v5, v5, v36, s3
	v_cndmask_b32_e64 v4, v4, v35, s3
	v_cndmask_b32_e64 v3, v3, v36, s4
	v_cndmask_b32_e64 v2, v2, v35, s4
	v_cndmask_b32_e64 v1, v1, v36, s5
	v_cndmask_b32_e64 v0, v0, v35, s5
	s_cbranch_scc1 .LBB2_3
; %bb.4:                                ; %_ZL21exact_solution_kerneldddPd.exit.preheader
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b64 s[2:3], 0
	s_mov_b32 s4, s16
.LBB2_5:                                ; %_ZL21exact_solution_kerneldddPd.exit
                                        ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v30, v1, v3 :: v_dual_cndmask_b32 v31, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v30, v30, v5 :: v_dual_cndmask_b32 v31, v31, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_dual_cndmask_b32 v30, v30, v7 :: v_dual_cndmask_b32 v33, v31, v6
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v31, v30, v9 :: v_dual_cndmask_b32 v30, v33, v8
	scratch_store_b64 off, v[30:31], s4
	s_add_i32 s4, s4, 8
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	s_cbranch_scc1 .LBB2_5
; %bb.6:                                ;   in Loop: Header=BB2_2 Depth=1
	v_div_scale_f64 v[30:31], null, v[0:1], v[0:1], 1.0
	v_mov_b32_e32 v33, v32
	s_mov_b64 s[2:3], 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[35:36], v[30:31]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[37:38], -v[30:31], v[35:36], 1.0
	v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[37:38], -v[30:31], v[35:36], 1.0
	v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36]
	v_div_scale_f64 v[37:38], vcc_lo, 1.0, v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[40:41], v[37:38], v[35:36]
	v_fma_f64 v[30:31], -v[30:31], v[40:41], v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[30:31], v[30:31], v[35:36], v[40:41]
	v_div_fixup_f64 v[30:31], v[30:31], v[0:1], 1.0
.LBB2_7:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v35, v1, v3 :: v_dual_cndmask_b32 v36, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v35, v35, v5 :: v_dual_cndmask_b32 v36, v36, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v35, v35, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v37, v36, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_dual_cndmask_b32 v36, v35, v9 :: v_dual_cndmask_b32 v35, v37, v8
	s_cmp_lg_u32 s2, 5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[35:36], v[30:31], v[35:36]
	scratch_store_b64 v33, v[35:36], off
	v_add_nc_u32_e32 v33, 8, v33
	s_cbranch_scc1 .LBB2_7
; %bb.8:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mul_i32 s5, s17, 40
	s_add_i32 s4, s17, 1
	s_add_i32 s12, s5, 0xe0
	s_cmp_eq_u32 s17, 2
	s_clause 0x1
	scratch_load_b128 v[35:38], off, s12 offset:8
	scratch_load_b64 v[30:31], off, s12 offset:24
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s17, 1
	v_add_f64 v[23:24], v[23:24], 1.0
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s17, 0
	v_add_nc_u32_e32 v32, 40, v32
	s_cselect_b32 s3, -1, 0
	s_add_i32 s5, s5, 16
	s_clause 0x1
	scratch_load_b128 v[40:43], off, s5 offset:48
	scratch_load_b64 v[46:47], off, s5 offset:64
	s_add_i32 s16, s16, 40
	s_cmp_eq_u32 s4, 3
	s_waitcnt vmcnt(3)
	v_mul_f64 v[44:45], v[37:38], v[37:38]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[37:38], v[37:38], v[42:43]
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v15, v15, v45 :: v_dual_cndmask_b32 v14, v14, v44
	v_cndmask_b32_e64 v13, v13, v45, s2
	v_cndmask_b32_e64 v12, v12, v44, s2
	v_cndmask_b32_e64 v26, v26, v45, s3
	v_cndmask_b32_e64 v25, v25, v44, s3
	v_fma_f64 v[37:38], v[35:36], v[40:41], v[37:38]
	v_fma_f64 v[35:36], v[35:36], v[35:36], v[44:45]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[37:38], v[30:31], v[46:47], v[37:38]
	v_fma_f64 v[30:31], v[30:31], v[30:31], v[35:36]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[37:38], v[37:38], 0.5
	scratch_store_b64 off, v[30:31], s12
	v_dual_cndmask_b32 v17, v17, v38 :: v_dual_cndmask_b32 v16, v16, v37
	v_cndmask_b32_e64 v11, v11, v38, s2
	v_cndmask_b32_e64 v10, v10, v37, s2
	v_cndmask_b32_e64 v28, v28, v38, s3
	v_cndmask_b32_e64 v27, v27, v37, s3
	s_cbranch_scc1 .LBB2_10
; %bb.9:                                ;   in Loop: Header=BB2_2 Depth=1
	s_mov_b32 s17, s4
	s_branch .LBB2_2
.LBB2_10:                               ; %.preheader228
	s_cmp_lt_i32 s9, 3
	s_cbranch_scc1 .LBB2_50
; %bb.11:                               ; %.lr.ph
	v_add_nc_u32_e32 v23, s10, v34
	v_mul_lo_u32 v32, v34, s9
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ty2@rel32@lo+4
	s_addc_u32 s3, s3, ty2@rel32@hi+12
	v_add3_u32 v39, v39, s26, 2
	s_load_b64 s[4:5], s[0:1], 0x0
	v_mul_lo_u32 v34, v23, s9
	v_add_nc_u32_e32 v23, s10, v23
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dy1ty1@rel32@lo+4
	s_addc_u32 s1, s1, dy1ty1@rel32@hi+12
	s_load_b64 s[12:13], s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yycon3@rel32@lo+4
	s_addc_u32 s3, s3, yycon3@rel32@hi+12
	s_load_b64 s[14:15], s[0:1], 0x0
	v_add_nc_u32_e32 v30, s10, v23
	s_load_b64 s[0:1], s[2:3], 0x0
	v_mul_lo_u32 v40, s9, v39
	v_mul_lo_u32 v46, s8, v32
	v_dual_mov_b32 v31, 16 :: v_dual_mov_b32 v24, 0xe0
	v_mul_lo_u32 v38, v30, s9
	v_add_nc_u32_e32 v30, s10, v30
	v_mul_lo_u32 v37, v23, s9
	s_mov_b32 s40, 16
	v_add_nc_u32_e32 v45, -2, v40
	v_add_nc_u32_e32 v40, -3, v40
	v_mul_lo_u32 v39, v30, s9
	v_add_nc_u32_e32 v30, 2, v32
	s_addk_i32 s40, 0x50
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yycon2@rel32@lo+4
	s_addc_u32 s3, s3, yycon2@rel32@hi+12
	s_movk_i32 s16, 0x80
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, dy2ty1@rel32@lo+4
	s_addc_u32 s19, s19, dy2ty1@rel32@hi+12
	v_mad_u64_u32 v[43:44], null, s8, v45, v[29:30]
	v_mad_u64_u32 v[41:42], null, s8, v30, v[29:30]
	v_mad_u64_u32 v[44:45], null, s8, v40, v[29:30]
	v_add3_u32 v29, v46, s8, v29
	v_add_nc_u32_e64 v35, s16, 16
	s_load_b64 s[16:17], s[2:3], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yycon1@rel32@lo+4
	s_addc_u32 s3, s3, yycon1@rel32@hi+12
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, dy3ty1@rel32@lo+4
	s_addc_u32 s23, s23, dy3ty1@rel32@hi+12
	v_add3_u32 v42, v29, s11, 1
	v_add_nc_u32_e32 v36, 0x58, v24
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[23:24], s[0:1], 0.5
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, dy4ty1@rel32@lo+4
	s_addc_u32 s25, s25, dy4ty1@rel32@hi+12
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, yycon4@rel32@lo+4
	s_addc_u32 s1, s1, yycon4@rel32@hi+12
	v_mov_b32_e32 v45, v42
	s_load_b64 s[20:21], s[2:3], 0x0
	s_load_b64 s[22:23], s[22:23], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, yycon5@rel32@lo+4
	s_addc_u32 s3, s3, yycon5@rel32@hi+12
	s_getpc_b64 s[30:31]
	s_add_u32 s30, s30, dy5ty1@rel32@lo+4
	s_addc_u32 s31, s31, dy5ty1@rel32@hi+12
	s_load_b64 s[26:27], s[0:1], 0x0
	s_load_b64 s[28:29], s[2:3], 0x0
	s_load_b64 s[30:31], s[30:31], 0x0
	s_load_b64 s[18:19], s[18:19], 0x0
	s_load_b64 s[24:25], s[24:25], 0x0
	s_movk_i32 s0, 0xa0
	v_add_nc_u32_e32 v33, 0x78, v31
	v_add_nc_u32_e64 v40, s0, 16
	v_add3_u32 v41, v41, s11, 1
	v_add3_u32 v43, v43, s11, 1
	v_add3_u32 v44, v44, s11, 1
	s_mul_i32 s43, s10, s9
	s_mov_b32 s34, 0x9999999a
	s_mov_b32 s36, 0x66666666
	s_add_i32 s41, s9, -3
	s_add_i32 s42, s9, -2
	s_mov_b32 s35, 0x3fd99999
	s_mov_b32 s37, 0x3ff66666
	s_mov_b32 s44, 1
	s_mul_i32 s43, s43, s8
.LBB2_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_14 Depth 2
                                        ;     Child Loop BB2_16 Depth 2
                                        ;     Child Loop BB2_20 Depth 2
                                        ;     Child Loop BB2_30 Depth 2
                                        ;     Child Loop BB2_34 Depth 2
                                        ;     Child Loop BB2_38 Depth 2
                                        ;     Child Loop BB2_42 Depth 2
                                        ;     Child Loop BB2_44 Depth 2
                                        ;     Child Loop BB2_47 Depth 2
	s_add_i32 s0, s44, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s0, s9
	s_cbranch_scc1 .LBB2_17
; %bb.13:                               ;   in Loop: Header=BB2_12 Depth=1
	v_cvt_f64_i32_e32 v[29:30], s0
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, ce@rel32@lo+4
	s_addc_u32 s11, s11, ce@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[29:30], s[6:7], v[29:30]
.LBB2_14:                               ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[0:1], s[10:11], 0x118
	s_load_b64 s[2:3], s[10:11], 0x190
	s_load_b64 s[46:47], s[10:11], 0xa0
	s_load_b64 s[48:49], s[10:11], 0xc8
	s_load_b64 s[50:51], s[10:11], 0x140
	s_load_b64 s[52:53], s[10:11], 0x1b8
	s_load_b64 s[54:55], s[10:11], 0xf0
	s_load_b64 s[56:57], s[10:11], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[46:47], v[21:22], s[2:3], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[29:30], s[52:53], s[50:51]
	v_fma_f64 v[46:47], v[21:22], v[46:47], s[46:47]
	s_clause 0x4
	s_load_b64 s[0:1], s[10:11], 0x1e0
	s_load_b64 s[2:3], s[10:11], 0x28
	s_load_b64 s[46:47], s[10:11], 0x0
	s_load_b64 s[50:51], s[10:11], 0x50
	s_load_b64 s[52:53], s[10:11], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[29:30], v[48:49], s[48:49]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[50:51], v[19:20], s[0:1], s[56:57]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[21:22], v[46:47], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[48:49], v[29:30], v[48:49], s[50:51]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[50:51], v[19:20], v[50:51], s[54:55]
	v_fma_f64 v[46:47], v[21:22], v[46:47], s[46:47]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[50:51], v[19:20], v[50:51], s[52:53]
	v_fma_f64 v[46:47], v[29:30], v[48:49], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[46:47], v[19:20], v[50:51], v[46:47]
	v_dual_cndmask_b32 v9, v9, v47 :: v_dual_cndmask_b32 v8, v8, v46
	v_cndmask_b32_e64 v7, v7, v47, s0
	v_cndmask_b32_e64 v6, v6, v46, s0
	v_cndmask_b32_e64 v5, v5, v47, s1
	v_cndmask_b32_e64 v4, v4, v46, s1
	v_cndmask_b32_e64 v3, v3, v47, s2
	v_cndmask_b32_e64 v2, v2, v46, s2
	v_cndmask_b32_e64 v1, v1, v47, s3
	v_cndmask_b32_e64 v0, v0, v46, s3
	s_cbranch_scc1 .LBB2_14
; %bb.15:                               ; %_ZL21exact_solution_kerneldddPd.exit202.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v29, v40
	s_mov_b64 s[0:1], 0
.LBB2_16:                               ; %_ZL21exact_solution_kerneldddPd.exit202
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	v_cndmask_b32_e32 v46, v0, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v30, v5, vcc_lo
	v_cndmask_b32_e32 v46, v46, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v30, v7, vcc_lo
	v_cndmask_b32_e32 v46, v46, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_cndmask_b32_e32 v47, v30, v9, vcc_lo
	v_cndmask_b32_e32 v46, v46, v8, vcc_lo
	s_cmp_lg_u32 s0, 5
	scratch_store_b64 v29, v[46:47], off
	v_add_nc_u32_e32 v29, 8, v29
	s_cbranch_scc1 .LBB2_16
.LBB2_17:                               ; %NodeBlock
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_clause 0xe
	scratch_load_b128 v[0:3], off, off offset:304
	scratch_load_b128 v[4:7], off, off offset:272
	scratch_load_b128 v[46:49], off, off offset:256
	scratch_load_b128 v[50:53], off, off offset:88
	scratch_load_b128 v[54:57], off, off offset:320
	scratch_load_b64 v[8:9], off, off offset:168
	scratch_load_b128 v[58:61], off, off offset:224
	scratch_load_b128 v[62:65], off, off offset:240
	scratch_load_b128 v[66:69], off, off offset:56
	scratch_load_b128 v[70:73], off, off offset:72
	scratch_load_b128 v[74:77], off, off offset:288
	scratch_load_b64 v[29:30], off, off offset:336
	scratch_load_b128 v[78:81], off, off offset:136
	scratch_load_b128 v[82:85], off, off offset:152
	scratch_load_b128 v[86:89], off, off offset:104
	v_mul_f64 v[90:91], v[27:28], s[34:35]
	v_add_nc_u32_e32 v94, s44, v32
	v_add_nc_u32_e32 v96, s44, v38
	v_add_nc_u32_e32 v98, s44, v39
	s_mov_b32 s1, -1
	s_mov_b32 s3, 0
	s_cmp_lt_i32 s44, 2
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(13)
	v_fma_f64 v[2:3], v[4:5], -2.0, v[2:3]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[0:1], v[48:49], -2.0, v[0:1]
	v_mul_f64 v[4:5], v[16:17], s[34:35]
	s_waitcnt vmcnt(11)
	v_fma_f64 v[48:49], v[50:51], s[36:37], -v[90:91]
	s_waitcnt vmcnt(9)
	v_add_f64 v[90:91], v[8:9], -v[16:17]
	v_fma_f64 v[6:7], v[6:7], -2.0, v[54:55]
	v_add_f64 v[27:28], v[50:51], -v[27:28]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[92:93], v[62:63], v[72:73]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[56:57], v[74:75], -2.0, v[56:57]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[29:30], v[76:77], -2.0, v[29:30]
	v_mad_u64_u32 v[76:77], null, v94, s8, v[18:19]
	v_add_nc_u32_e32 v94, s44, v37
	s_waitcnt vmcnt(2)
	v_fma_f64 v[52:53], v[52:53], -2.0, v[78:79]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[78:79], v[86:87], -2.0, v[80:81]
	v_fma_f64 v[86:87], v[88:89], -2.0, v[82:83]
	v_ashrrev_i32_e32 v77, 31, v76
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[76:77], 3, v[76:77]
	v_add_co_u32 v76, vcc_lo, s4, v76
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v77, vcc_lo, s5, v77, vcc_lo
	v_add_f64 v[60:61], v[60:61], v[2:3]
	v_fma_f64 v[4:5], v[8:9], s[36:37], -v[4:5]
	v_mul_f64 v[2:3], v[62:63], v[48:49]
	v_add_f64 v[48:49], v[58:59], v[0:1]
	v_mul_f64 v[58:59], v[68:69], v[62:63]
	v_mul_f64 v[90:91], v[90:91], s[34:35]
	v_mul_f64 v[27:28], v[27:28], s[34:35]
	v_fma_f64 v[74:75], v[54:55], v[84:85], -v[92:93]
	v_add_nc_u32_e32 v92, s44, v34
	v_add_f64 v[6:7], v[62:63], v[6:7]
	v_add_f64 v[56:57], v[64:65], v[56:57]
	v_add_f64 v[29:30], v[46:47], v[29:30]
	v_fma_f64 v[4:5], v[54:55], v[4:5], -v[2:3]
	scratch_load_b128 v[0:3], off, off offset:120
	v_fma_f64 v[58:59], v[80:81], v[54:55], -v[58:59]
	v_fma_f64 v[54:55], v[82:83], v[54:55], v[90:91]
	v_mad_u64_u32 v[90:91], null, v92, s8, v[18:19]
	v_mad_u64_u32 v[92:93], null, v94, s8, v[18:19]
	v_mad_u64_u32 v[94:95], null, v96, s8, v[18:19]
	v_mad_u64_u32 v[96:97], null, v98, s8, v[18:19]
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v91, 31, v90
	v_fma_f64 v[27:28], v[70:71], v[62:63], v[27:28]
	v_ashrrev_i32_e32 v93, 31, v92
	v_fma_f64 v[98:99], v[12:13], -2.0, v[14:15]
	v_ashrrev_i32_e32 v95, 31, v94
	v_lshlrev_b64 v[90:91], 3, v[90:91]
	v_ashrrev_i32_e32 v97, 31, v96
	v_lshlrev_b64 v[92:93], 3, v[92:93]
	v_add_f64 v[82:83], v[82:83], -v[70:71]
	v_lshlrev_b64 v[94:95], 3, v[94:95]
	v_add_co_u32 v90, vcc_lo, s4, v90
	v_add_co_ci_u32_e32 v91, vcc_lo, s5, v91, vcc_lo
	v_add_co_u32 v92, vcc_lo, s4, v92
	v_lshlrev_b64 v[96:97], 3, v[96:97]
	v_add_co_ci_u32_e32 v93, vcc_lo, s5, v93, vcc_lo
	v_add_co_u32 v94, vcc_lo, s4, v94
	v_add_co_ci_u32_e32 v95, vcc_lo, s5, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v96, vcc_lo, s4, v96
	v_add_co_ci_u32_e32 v97, vcc_lo, s5, v97, vcc_lo
	global_load_b64 v[80:81], v[96:97], off
	v_add_f64 v[27:28], v[54:55], -v[27:28]
	v_add_f64 v[25:26], v[25:26], v[98:99]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[0:1], v[0:1], -2.0, v[84:85]
	v_fma_f64 v[2:3], v[2:3], -2.0, v[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], -s[12:13], v[4:5], v[80:81]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[4:5], v[23:24], v[48:49], v[4:5]
	s_clause 0x3
	global_load_b64 v[48:49], v[90:91], off
	global_load_b64 v[54:55], v[94:95], off
	global_load_b64 v[80:81], v[92:93], off
	global_load_b64 v[76:77], v[76:77], off
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[4:5], v[25:26], s[26:27], v[4:5]
	v_add_f64 v[25:26], v[66:67], v[52:53]
	v_add_f64 v[52:53], v[68:69], v[78:79]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[46:47], -s[12:13], v[58:59], v[48:49]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[48:49], -s[12:13], v[74:75], v[54:55]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[27:28], -s[12:13], v[27:28], v[80:81]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[8:9], -s[12:13], v[82:83], v[76:77]
	v_add_f64 v[54:55], v[70:71], v[86:87]
	v_add_f64 v[58:59], v[72:73], v[0:1]
	v_fma_f64 v[46:47], s[16:17], v[60:61], v[46:47]
	v_fma_f64 v[48:49], s[16:17], v[56:57], v[48:49]
	v_fma_f64 v[6:7], s[20:21], v[6:7], v[27:28]
	v_fma_f64 v[27:28], s[28:29], v[29:30], v[4:5]
	v_add_f64 v[29:30], v[50:51], v[2:3]
	v_fma_f64 v[0:1], s[14:15], v[25:26], v[8:9]
	v_fma_f64 v[2:3], s[18:19], v[52:53], v[46:47]
	v_fma_f64 v[4:5], s[22:23], v[54:55], v[6:7]
	v_fma_f64 v[6:7], s[24:25], v[58:59], v[48:49]
	v_fma_f64 v[8:9], s[30:31], v[29:30], v[27:28]
	s_cbranch_scc1 .LBB2_23
; %bb.18:                               ; %LeafBlock477
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_cmp_eq_u32 s44, 2
	s_mov_b32 s0, -1
	s_cbranch_scc0 .LBB2_22
; %bb.19:                               ; %.preheader225.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v25, v41
	s_mov_b64 s[10:11], 0
	s_mov_b32 s38, s40
.LBB2_20:                               ; %.preheader225
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s38 offset:-40
	scratch_load_b64 v[28:29], off, s38
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s10, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s10, 4
	v_cndmask_b32_e64 v30, v30, v5, s0
	s_cselect_b32 s2, -1, 0
	s_add_i32 s39, s38, 40
	scratch_load_b64 v[46:47], off, s39
	s_add_i32 s39, s38, 0x50
	v_cndmask_b32_e64 v30, v30, v7, s1
	scratch_load_b64 v[48:49], off, s39
	s_add_i32 s38, s38, 8
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, 5
	s_waitcnt vmcnt(3)
	v_mul_f64 v[26:27], v[26:27], -4.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], 0x40180000, v[28:29], v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v30, v9, s2
	v_cndmask_b32_e64 v28, v28, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v6, s1
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[46:47], -4.0, v[26:27]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[48:49], v[26:27]
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s43, v25
	v_add_co_u32 v29, vcc_lo, s4, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB2_20
; %bb.21:                               ; %Flow479
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s0, 0
.LBB2_22:                               ; %Flow490
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s1, 0
.LBB2_23:                               ; %Flow489
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB2_25
; %bb.24:                               ; %LeafBlock
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_cmp_lg_u32 s44, 1
	s_mov_b32 s3, -1
	s_cselect_b32 s0, -1, 0
.LBB2_25:                               ; %Flow491
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_40
; %bb.26:                               ;   in Loop: Header=BB2_12 Depth=1
	s_cmp_gt_u32 s44, 2
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s44, s41
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s0, -1
	s_cbranch_vccz .LBB2_36
; %bb.27:                               ;   in Loop: Header=BB2_12 Depth=1
	s_cmp_lg_u32 s44, s41
	s_cbranch_scc0 .LBB2_32
; %bb.28:                               ;   in Loop: Header=BB2_12 Depth=1
	s_cmp_lg_u32 s44, s42
	s_cbranch_scc1 .LBB2_31
; %bb.29:                               ; %.preheader221.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v25, v43
	s_mov_b64 s[10:11], 0
	s_mov_b32 s3, s33
.LBB2_30:                               ; %.preheader221
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s3 offset:-40
	scratch_load_b64 v[28:29], off, s3
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s10, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s10, 4
	v_cndmask_b32_e64 v30, v30, v5, s0
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	s_add_u32 s10, s10, 1
	scratch_load_b64 v[46:47], off, s38
	v_cndmask_b32_e64 v30, v30, v7, s1
	s_addc_u32 s11, s11, 0
	s_add_i32 s3, s3, 8
	s_cmp_eq_u32 s10, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[28:29], -4.0, v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v30, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v4, s0
	v_cndmask_b32_e64 v28, v28, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[26:27], 0x40140000, v[46:47], v[26:27]
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s43, v25
	v_add_co_u32 v29, vcc_lo, s4, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB2_30
.LBB2_31:                               ; %Flow481
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s0, 0
.LBB2_32:                               ; %Flow483
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_35
; %bb.33:                               ; %.preheader219.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v27, v33
	v_mov_b32_e32 v25, v44
	s_mov_b64 s[0:1], 0
.LBB2_34:                               ; %.preheader219
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x3
	scratch_load_b64 v[28:29], v27, off offset:-120
	scratch_load_b64 v[46:47], v27, off offset:-80
	scratch_load_b64 v[48:49], v27, off offset:-40
	scratch_load_b64 v[50:51], v27, off
	s_cmp_eq_u32 s0, 1
	v_add_nc_u32_e32 v27, 8, v27
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v26, v1, v3, vcc_lo
	v_cndmask_b32_e32 v30, v0, v2, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v5, vcc_lo
	v_cndmask_b32_e32 v30, v30, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v7, vcc_lo
	v_cndmask_b32_e32 v30, v30, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 5
	s_waitcnt vmcnt(2)
	v_fma_f64 v[28:29], v[46:47], -4.0, v[28:29]
	v_cndmask_b32_e32 v47, v26, v9, vcc_lo
	v_cndmask_b32_e32 v46, v30, v8, vcc_lo
	v_ashrrev_i32_e32 v26, 31, v25
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], 0x40180000, v[48:49], v[28:29]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[28:29], v[50:51], -4.0, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], 0xbfd00000, v[28:29], v[46:47]
	v_lshlrev_b64 v[46:47], 3, v[25:26]
	v_add_nc_u32_e32 v25, s43, v25
	v_add_co_u32 v46, vcc_lo, s4, v46
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v47, vcc_lo, s5, v47, vcc_lo
	global_store_b64 v[46:47], v[28:29], off
	s_cbranch_scc0 .LBB2_34
.LBB2_35:                               ; %Flow484
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s0, 0
.LBB2_36:                               ; %Flow486
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_39
; %bb.37:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v25, v45
	s_mov_b64 s[10:11], 0
	s_mov_b32 s3, s40
.LBB2_38:                               ; %.preheader
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x2
	scratch_load_b64 v[26:27], off, s3 offset:-80
	scratch_load_b64 v[28:29], off, s3 offset:-40
	scratch_load_b64 v[46:47], off, s3
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s10, 2
	v_cndmask_b32_e32 v30, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s10, 4
	v_cndmask_b32_e64 v30, v30, v5, s0
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	scratch_load_b64 v[48:49], off, s38
	s_add_i32 s38, s3, 0x50
	v_cndmask_b32_e64 v30, v30, v7, s1
	scratch_load_b64 v[50:51], off, s38
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_add_i32 s3, s3, 8
	s_cmp_eq_u32 s10, 5
	s_waitcnt vmcnt(3)
	v_fma_f64 v[26:27], v[28:29], -4.0, v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v30, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v4, s0
	v_cndmask_b32_e64 v28, v28, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[26:27], 0x40180000, v[46:47], v[26:27]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[26:27], v[48:49], -4.0, v[26:27]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[50:51], v[26:27]
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s43, v25
	v_add_co_u32 v29, vcc_lo, s4, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB2_38
.LBB2_39:                               ; %Flow487
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s3, 0
.LBB2_40:                               ; %Flow492
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB2_43
; %bb.41:                               ; %.preheader223.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	v_mov_b32_e32 v25, v42
	s_mov_b64 s[10:11], 0
	s_mov_b32 s3, s40
.LBB2_42:                               ; %.preheader223
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s10, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s10, 2
	v_cndmask_b32_e32 v26, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s10, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v26, v26, v5, s0
	s_cmp_eq_u32 s10, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s38, s3, 40
	v_cndmask_b32_e64 v30, v26, v7, s1
	s_clause 0x1
	scratch_load_b64 v[26:27], off, s38
	scratch_load_b64 v[28:29], off, s3
	s_add_i32 s38, s3, 0x50
	s_add_i32 s3, s3, 8
	scratch_load_b64 v[46:47], off, s38
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s10, 5
	s_waitcnt vmcnt(2)
	v_mul_f64 v[26:27], v[26:27], -4.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], 0x40140000, v[28:29], v[26:27]
	v_cndmask_b32_e32 v28, v0, v2, vcc_lo
	v_cndmask_b32_e64 v29, v30, v9, s2
	v_cndmask_b32_e64 v28, v28, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v6, s1
	v_cndmask_b32_e64 v28, v28, v8, s2
	s_waitcnt vmcnt(0)
	v_add_f64 v[26:27], v[46:47], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], 0xbfd00000, v[26:27], v[28:29]
	v_ashrrev_i32_e32 v26, 31, v25
	v_lshlrev_b64 v[29:30], 3, v[25:26]
	v_add_nc_u32_e32 v25, s43, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v29, vcc_lo, s4, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_store_b64 v[29:30], v[27:28], off
	s_cbranch_scc0 .LBB2_42
.LBB2_43:                               ; %.loopexit.preheader
                                        ;   in Loop: Header=BB2_12 Depth=1
	s_mov_b32 s0, 0
.LBB2_44:                               ; %.loopexit
                                        ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s1, v31
	v_add_nc_u32_e64 v25, 0xe0, s0
	s_add_i32 s11, s0, 0xe0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s1, s1, s0
	v_add_nc_u32_e32 v52, 40, v25
	s_add_i32 s2, s1, 40
	v_add_nc_u32_e32 v50, 0x50, v25
	s_add_i32 s3, s1, 0x50
	s_add_i32 s10, s1, 0x78
	s_addk_i32 s1, 0xa0
	s_clause 0x3
	scratch_load_b64 v[25:26], off, s2
	scratch_load_b64 v[27:28], off, s3
	scratch_load_b64 v[29:30], off, s10
	scratch_load_b64 v[46:47], off, s1
	s_clause 0x1
	scratch_load_b64 v[48:49], v52, off
	scratch_load_b64 v[50:51], v50, off
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 8
	s_waitcnt vmcnt(5)
	scratch_store_b64 off, v[25:26], s1
	s_waitcnt vmcnt(4)
	scratch_store_b64 off, v[27:28], s2
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[29:30], s3
	s_waitcnt vmcnt(2)
	scratch_store_b64 off, v[46:47], s10
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[48:49], s11
	s_waitcnt vmcnt(0)
	scratch_store_b64 v52, v[50:51], off
	s_cmp_lg_u32 s0, 40
	s_cbranch_scc1 .LBB2_44
; %bb.45:                               ;   in Loop: Header=BB2_12 Depth=1
	v_dual_mov_b32 v25, v12 :: v_dual_mov_b32 v26, v13
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	v_dual_mov_b32 v27, v10 :: v_dual_mov_b32 v28, v11
	v_dual_mov_b32 v10, v16 :: v_dual_mov_b32 v11, v17
	s_cmp_ge_i32 s44, s42
	s_cbranch_scc1 .LBB2_49
; %bb.46:                               ;   in Loop: Header=BB2_12 Depth=1
	scratch_load_b64 v[14:15], off, off offset:136
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[16:17], null, v[14:15], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[29:30], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[46:47], -v[16:17], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[46:47], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[46:47], -v[16:17], v[29:30], 1.0
	v_fma_f64 v[29:30], v[29:30], v[46:47], v[29:30]
	v_div_scale_f64 v[46:47], vcc_lo, 1.0, v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[46:47], v[29:30]
	v_fma_f64 v[16:17], -v[16:17], v[48:49], v[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[16:17], v[16:17], v[29:30], v[48:49]
	v_div_fixup_f64 v[14:15], v[16:17], v[14:15], 1.0
.LBB2_47:                               ;   Parent Loop BB2_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v16, s0, v35
	v_add_nc_u32_e32 v29, s0, v36
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 32
	scratch_load_b64 v[16:17], v16, off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[16:17], v[14:15], v[16:17]
	scratch_store_b64 v29, v[16:17], off
	s_cbranch_scc1 .LBB2_47
; %bb.48:                               ;   in Loop: Header=BB2_12 Depth=1
	s_clause 0x3
	scratch_load_b128 v[46:49], off, off offset:144
	scratch_load_b128 v[50:53], off, off offset:312
	scratch_load_b64 v[16:17], off, off offset:328
	scratch_load_b64 v[29:30], off, off offset:160
	s_waitcnt vmcnt(2)
	v_mul_f64 v[48:49], v[52:53], v[48:49]
	v_mul_f64 v[14:15], v[52:53], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[46:47], v[50:51], v[46:47], v[48:49]
	v_fma_f64 v[48:49], v[50:51], v[50:51], v[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[16:17], v[29:30], v[46:47]
	v_fma_f64 v[46:47], v[16:17], v[16:17], v[48:49]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[16:17], v[29:30], 0.5
	scratch_store_b64 off, v[46:47], off offset:304
.LBB2_49:                               ;   in Loop: Header=BB2_12 Depth=1
	v_add_nc_u32_e32 v45, s8, v45
	s_add_i32 s0, s44, 1
	s_cmp_lg_u32 s44, s42
	s_mov_b32 s44, s0
	s_cbranch_scc1 .LBB2_12
.LBB2_50:                               ; %.loopexit229
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL18exact_rhs_kernel_yPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 352
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 100
		.amdhsa_next_free_sgpr 58
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL18exact_rhs_kernel_yPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_yPdiii,comdat
.Lfunc_end2:
	.size	_ZL18exact_rhs_kernel_yPdiii, .Lfunc_end2-_ZL18exact_rhs_kernel_yPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5416
; NumSgprs: 60
; NumVgprs: 100
; ScratchSize: 352
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 12
; NumSGPRsForWavesPerEU: 60
; NumVGPRsForWavesPerEU: 100
; Occupancy: 12
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL18exact_rhs_kernel_zPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_zPdiii,comdat
	.globl	_ZL18exact_rhs_kernel_zPdiii    ; -- Begin function _ZL18exact_rhs_kernel_zPdiii
	.p2align	8
	.type	_ZL18exact_rhs_kernel_zPdiii,@function
_ZL18exact_rhs_kernel_zPdiii:           ; @_ZL18exact_rhs_kernel_zPdiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[8:11], s[0:1], 0x8
	v_and_b32_e32 v19, 0x3ff, v0
	v_bfe_u32 v18, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s26, s14, s3
	s_mul_i32 s38, s15, s2
	v_add3_u32 v34, v19, s26, 1
	v_add3_u32 v35, v18, s38, 1
	s_add_i32 s2, s9, -1
	s_add_i32 s3, s8, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v34
	v_cmp_gt_i32_e64 s2, s3, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_58
; %bb.1:
	v_cvt_f64_i32_e32 v[0:1], v34
	v_cvt_f64_i32_e32 v[2:3], v35
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnym1@rel32@lo+4
	s_addc_u32 s3, s3, dnym1@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, dnxm1@rel32@lo+4
	s_addc_u32 s5, s5, dnxm1@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_load_b64 s[4:5], s[4:5], 0x0
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	v_or_b32_e64 v20, 0xe0, 8
                                        ; implicit-def: $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29
                                        ; implicit-def: $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
                                        ; implicit-def: $vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[36:37], s[2:3], v[0:1]
	v_mul_f64 v[38:39], s[4:5], v[2:3]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dnzm1@rel32@lo+4
	s_addc_u32 s3, s3, dnzm1@rel32@hi+12
	s_add_i32 s11, 16, 40
	s_load_b64 s[6:7], s[2:3], 0x0
	s_mov_b32 s16, s11
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr10_vgpr11
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_3 Depth 2
                                        ;     Child Loop BB3_5 Depth 2
                                        ;     Child Loop BB3_7 Depth 2
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[14:15], s[6:7], v[16:17]
	s_mov_b64 s[14:15], 0
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, ce@rel32@lo+4
	s_addc_u32 s13, s13, ce@rel32@hi+12
.LBB3_3:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[2:3], s[12:13], 0x118
	s_load_b64 s[4:5], s[12:13], 0x190
	s_load_b64 s[18:19], s[12:13], 0xa0
	s_load_b64 s[20:21], s[12:13], 0xc8
	s_load_b64 s[22:23], s[12:13], 0x140
	s_load_b64 s[24:25], s[12:13], 0x1b8
	s_load_b64 s[28:29], s[12:13], 0xf0
	s_load_b64 s[30:31], s[12:13], 0x168
	s_cmp_eq_u32 s14, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[21:22], v[38:39], s[4:5], s[2:3]
	v_fma_f64 v[23:24], v[36:37], s[24:25], s[22:23]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[21:22], v[38:39], v[21:22], s[18:19]
	s_clause 0x4
	s_load_b64 s[2:3], s[12:13], 0x1e0
	s_load_b64 s[4:5], s[12:13], 0x28
	s_load_b64 s[18:19], s[12:13], 0x0
	s_load_b64 s[22:23], s[12:13], 0x50
	s_load_b64 s[24:25], s[12:13], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[23:24], v[36:37], v[23:24], s[20:21]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[40:41], v[14:15], s[2:3], s[30:31]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s14, 2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s14, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[38:39], v[21:22], s[4:5]
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cselect_b32 s5, -1, 0
	v_fma_f64 v[23:24], v[36:37], v[23:24], s[22:23]
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], v[14:15], v[40:41], s[28:29]
	v_fma_f64 v[21:22], v[38:39], v[21:22], s[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[40:41], v[14:15], v[40:41], s[24:25]
	v_fma_f64 v[21:22], v[36:37], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[14:15], v[40:41], v[21:22]
	v_dual_cndmask_b32 v9, v9, v22 :: v_dual_cndmask_b32 v8, v8, v21
	v_cndmask_b32_e64 v7, v7, v22, s2
	v_cndmask_b32_e64 v6, v6, v21, s2
	v_cndmask_b32_e64 v5, v5, v22, s3
	v_cndmask_b32_e64 v4, v4, v21, s3
	v_cndmask_b32_e64 v3, v3, v22, s4
	v_cndmask_b32_e64 v2, v2, v21, s4
	v_cndmask_b32_e64 v1, v1, v22, s5
	v_cndmask_b32_e64 v0, v0, v21, s5
	s_cbranch_scc1 .LBB3_3
; %bb.4:                                ; %_ZL21exact_solution_kerneldddPd.exit.preheader
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b64 s[2:3], 0
	s_mov_b32 s4, s16
.LBB3_5:                                ; %_ZL21exact_solution_kerneldddPd.exit
                                        ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v14, v1, v3 :: v_dual_cndmask_b32 v15, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v14, v14, v5 :: v_dual_cndmask_b32 v15, v15, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_dual_cndmask_b32 v14, v14, v7 :: v_dual_cndmask_b32 v21, v15, v6
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v15, v14, v9 :: v_dual_cndmask_b32 v14, v21, v8
	scratch_store_b64 off, v[14:15], s4
	s_add_i32 s4, s4, 8
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	s_cbranch_scc1 .LBB3_5
; %bb.6:                                ;   in Loop: Header=BB3_2 Depth=1
	v_div_scale_f64 v[14:15], null, v[0:1], v[0:1], 1.0
	s_mov_b64 s[2:3], 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[21:22], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[14:15], v[21:22], 1.0
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], -v[14:15], v[21:22], 1.0
	v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
	v_div_scale_f64 v[23:24], vcc_lo, 1.0, v[0:1], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[40:41], v[23:24], v[21:22]
	v_fma_f64 v[14:15], -v[14:15], v[40:41], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[14:15], v[14:15], v[21:22], v[40:41]
	v_mov_b32_e32 v21, v20
	v_div_fixup_f64 v[14:15], v[14:15], v[0:1], 1.0
.LBB3_7:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v22, v1, v3 :: v_dual_cndmask_b32 v23, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v22, v22, v5 :: v_dual_cndmask_b32 v23, v23, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v22, v22, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v24, v23, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	v_dual_cndmask_b32 v23, v22, v9 :: v_dual_cndmask_b32 v22, v24, v8
	s_cmp_lg_u32 s2, 5
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[22:23], v[14:15], v[22:23]
	scratch_store_b64 v21, v[22:23], off
	v_add_nc_u32_e32 v21, 8, v21
	s_cbranch_scc1 .LBB3_7
; %bb.8:                                ;   in Loop: Header=BB3_2 Depth=1
	s_mul_i32 s5, s17, 40
	s_add_i32 s4, s17, 1
	s_add_i32 s12, s5, 0xe0
	s_cmp_eq_u32 s17, 2
	s_clause 0x1
	scratch_load_b64 v[14:15], off, s12 offset:24
	scratch_load_b128 v[21:24], off, s12 offset:8
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s17, 1
	v_add_f64 v[16:17], v[16:17], 1.0
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s17, 0
	v_add_nc_u32_e32 v20, 40, v20
	s_cselect_b32 s3, -1, 0
	s_add_i32 s5, s5, 16
	s_clause 0x1
	scratch_load_b128 v[40:43], off, s5 offset:48
	scratch_load_b64 v[46:47], off, s5 offset:64
	s_add_i32 s16, s16, 40
	s_cmp_eq_u32 s4, 3
	s_waitcnt vmcnt(3)
	v_mul_f64 v[44:45], v[14:15], v[14:15]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[42:43], v[23:24], v[42:43]
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v31, v31, v45 :: v_dual_cndmask_b32 v30, v30, v44
	v_cndmask_b32_e64 v29, v29, v45, s2
	v_cndmask_b32_e64 v28, v28, v44, s2
	v_cndmask_b32_e64 v13, v13, v45, s3
	v_cndmask_b32_e64 v12, v12, v44, s3
	v_fma_f64 v[40:41], v[21:22], v[40:41], v[42:43]
	v_fma_f64 v[21:22], v[21:22], v[21:22], v[44:45]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[14:15], v[46:47], v[40:41]
	v_fma_f64 v[21:22], v[23:24], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[14:15], v[14:15], 0.5
	scratch_store_b64 off, v[21:22], s12
	v_dual_cndmask_b32 v33, v33, v15 :: v_dual_cndmask_b32 v32, v32, v14
	v_cndmask_b32_e64 v27, v27, v15, s2
	v_cndmask_b32_e64 v26, v26, v14, s2
	v_cndmask_b32_e64 v11, v11, v15, s3
	v_cndmask_b32_e64 v10, v10, v14, s3
	s_cbranch_scc1 .LBB3_10
; %bb.9:                                ;   in Loop: Header=BB3_2 Depth=1
	s_mov_b32 s17, s4
	s_branch .LBB3_2
.LBB3_10:                               ; %.preheader216
	s_cmp_lt_i32 s10, 3
	s_cbranch_scc1 .LBB3_58
; %bb.11:                               ; %.lr.ph
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, zzcon3@rel32@lo+4
	s_addc_u32 s3, s3, zzcon3@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, tz2@rel32@lo+4
	s_addc_u32 s13, s13, tz2@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_getpc_b64 s[14:15]
	s_add_u32 s14, s14, dz1tz1@rel32@lo+4
	s_addc_u32 s15, s15, dz1tz1@rel32@hi+12
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, zzcon2@rel32@lo+4
	s_addc_u32 s1, s1, zzcon2@rel32@hi+12
	v_add3_u32 v15, s26, s9, v19
	s_load_b64 s[16:17], s[0:1], 0x0
	s_load_b64 s[14:15], s[14:15], 0x0
	v_mov_b32_e32 v14, 0xe0
	v_mov_b32_e32 v42, 16
	v_mul_lo_u32 v15, s8, v15
	s_mov_b32 s33, 16
	s_mul_i32 s44, s9, s8
	v_add_nc_u32_e32 v45, 0x58, v14
	v_add_nc_u32_e32 v43, 0x78, v42
	s_mov_b32 s34, 0x9999999a
	s_mov_b32 s36, 0x66666666
	s_mov_b32 s35, 0x3fd99999
	v_add3_u32 v14, v15, s8, v18
	s_mov_b32 s37, 0x3ff66666
	s_mov_b32 s46, 1
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[40:41], s[2:3], 0.5
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dz2tz1@rel32@lo+4
	s_addc_u32 s3, s3, dz2tz1@rel32@hi+12
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, dz3tz1@rel32@lo+4
	s_addc_u32 s21, s21, dz3tz1@rel32@hi+12
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, zzcon1@rel32@lo+4
	s_addc_u32 s1, s1, zzcon1@rel32@hi+12
	s_load_b64 s[18:19], s[2:3], 0x0
	s_load_b64 s[20:21], s[20:21], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dz4tz1@rel32@lo+4
	s_addc_u32 s3, s3, dz4tz1@rel32@hi+12
	s_load_b64 s[22:23], s[0:1], 0x0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, zzcon4@rel32@lo+4
	s_addc_u32 s1, s1, zzcon4@rel32@hi+12
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, zzcon5@rel32@lo+4
	s_addc_u32 s29, s29, zzcon5@rel32@hi+12
	s_getpc_b64 s[30:31]
	s_add_u32 s30, s30, dz5tz1@rel32@lo+4
	s_addc_u32 s31, s31, dz5tz1@rel32@hi+12
	s_load_b64 s[26:27], s[0:1], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	s_load_b64 s[30:31], s[30:31], 0x0
	s_load_b64 s[24:25], s[2:3], 0x0
	s_movk_i32 s0, 0x80
	v_add3_u32 v47, v14, s38, 1
	v_add_nc_u32_e64 v44, s0, 16
	s_movk_i32 s0, 0xa0
	s_addk_i32 s33, 0x50
	v_add_nc_u32_e64 v46, s0, 16
	s_add_i32 s42, s10, -3
	s_add_i32 s43, s10, -2
	s_mul_i32 s45, s44, s10
.LBB3_12:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_14 Depth 2
                                        ;     Child Loop BB3_16 Depth 2
                                        ;     Child Loop BB3_20 Depth 2
                                        ;     Child Loop BB3_32 Depth 2
                                        ;     Child Loop BB3_39 Depth 2
                                        ;     Child Loop BB3_43 Depth 2
                                        ;     Child Loop BB3_47 Depth 2
                                        ;     Child Loop BB3_50 Depth 2
                                        ;     Child Loop BB3_52 Depth 2
                                        ;     Child Loop BB3_55 Depth 2
	s_add_i32 s0, s46, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s0, s10
	s_cbranch_scc1 .LBB3_17
; %bb.13:                               ;   in Loop: Header=BB3_12 Depth=1
	v_cvt_f64_i32_e32 v[14:15], s0
	s_mov_b64 s[40:41], 0
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, ce@rel32@lo+4
	s_addc_u32 s39, s39, ce@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[14:15], s[6:7], v[14:15]
.LBB3_14:                               ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x7
	s_load_b64 s[0:1], s[38:39], 0x118
	s_load_b64 s[2:3], s[38:39], 0x190
	s_load_b64 s[48:49], s[38:39], 0xa0
	s_load_b64 s[50:51], s[38:39], 0xc8
	s_load_b64 s[52:53], s[38:39], 0x140
	s_load_b64 s[54:55], s[38:39], 0x1b8
	s_load_b64 s[56:57], s[38:39], 0xf0
	s_load_b64 s[58:59], s[38:39], 0x168
	s_cmp_eq_u32 s40, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s40, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[16:17], v[38:39], s[2:3], s[0:1]
	v_fma_f64 v[18:19], v[36:37], s[54:55], s[52:53]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[16:17], v[38:39], v[16:17], s[48:49]
	s_clause 0x4
	s_load_b64 s[0:1], s[38:39], 0x1e0
	s_load_b64 s[2:3], s[38:39], 0x28
	s_load_b64 s[48:49], s[38:39], 0x0
	s_load_b64 s[52:53], s[38:39], 0x50
	s_load_b64 s[54:55], s[38:39], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[18:19], v[36:37], v[18:19], s[50:51]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[20:21], v[14:15], s[0:1], s[58:59]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s40, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s40, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[38:39], v[16:17], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s40, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[18:19], v[36:37], v[18:19], s[52:53]
	s_add_u32 s40, s40, 1
	s_addc_u32 s41, s41, 0
	s_add_u32 s38, s38, 8
	s_addc_u32 s39, s39, 0
	s_cmp_lg_u32 s40, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[20:21], v[14:15], v[20:21], s[56:57]
	v_fma_f64 v[16:17], v[38:39], v[16:17], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[14:15], v[20:21], s[54:55]
	v_fma_f64 v[16:17], v[36:37], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], v[20:21], v[16:17]
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_cndmask_b32 v8, v8, v16
	v_cndmask_b32_e64 v7, v7, v17, s0
	v_cndmask_b32_e64 v6, v6, v16, s0
	v_cndmask_b32_e64 v5, v5, v17, s1
	v_cndmask_b32_e64 v4, v4, v16, s1
	v_cndmask_b32_e64 v3, v3, v17, s2
	v_cndmask_b32_e64 v2, v2, v16, s2
	v_cndmask_b32_e64 v1, v1, v17, s3
	v_cndmask_b32_e64 v0, v0, v16, s3
	s_cbranch_scc1 .LBB3_14
; %bb.15:                               ; %_ZL21exact_solution_kerneldddPd.exit178.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_mov_b32_e32 v14, v46
	s_mov_b64 s[0:1], 0
.LBB3_16:                               ; %_ZL21exact_solution_kerneldddPd.exit178
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_dual_cndmask_b32 v15, v1, v3 :: v_dual_cndmask_b32 v16, v0, v2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v15, v15, v5 :: v_dual_cndmask_b32 v16, v16, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_cndmask_b32_e32 v15, v15, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v17, v16, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_dual_cndmask_b32 v16, v15, v9 :: v_dual_cndmask_b32 v15, v17, v8
	s_cmp_lg_u32 s0, 5
	scratch_store_b64 v14, v[15:16], off
	v_add_nc_u32_e32 v14, 8, v14
	s_cbranch_scc1 .LBB3_16
.LBB3_17:                               ; %NodeBlock
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_clause 0xa
	scratch_load_b128 v[0:3], off, off offset:88
	scratch_load_b64 v[68:69], off, off offset:168
	scratch_load_b128 v[4:7], off, off offset:240
	scratch_load_b128 v[14:17], off, off offset:56
	scratch_load_b128 v[18:21], off, off offset:72
	scratch_load_b128 v[22:25], off, off offset:288
	scratch_load_b64 v[8:9], off, off offset:336
	scratch_load_b128 v[48:51], off, off offset:320
	scratch_load_b128 v[52:55], off, off offset:136
	scratch_load_b128 v[56:59], off, off offset:152
	scratch_load_b128 v[60:63], off, off offset:272
	v_mul_f64 v[70:71], v[10:11], s[34:35]
	scratch_load_b128 v[64:67], off, off offset:104
	v_mad_u64_u32 v[74:75], null, s46, s9, v[34:35]
	v_mul_f64 v[72:73], v[32:33], s[34:35]
	v_fma_f64 v[75:76], v[28:29], -2.0, v[30:31]
	s_add_i32 s0, s46, s10
	s_mov_b32 s40, 0
	s_add_i32 s1, s0, s10
	v_mad_u64_u32 v[77:78], null, s0, s9, v[34:35]
	s_add_i32 s0, s1, s10
	v_mad_u64_u32 v[78:79], null, s1, s9, v[34:35]
	s_add_i32 s1, s0, s10
	v_mad_u64_u32 v[79:80], null, s0, s9, v[34:35]
	v_mad_u64_u32 v[80:81], null, s1, s9, v[34:35]
	v_mad_u64_u32 v[81:82], null, v74, s8, v[35:36]
	v_mad_u64_u32 v[83:84], null, v77, s8, v[35:36]
	v_mad_u64_u32 v[85:86], null, v78, s8, v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[89:90], null, v80, s8, v[35:36]
	v_ashrrev_i32_e32 v82, 31, v81
	v_mad_u64_u32 v[77:78], null, v79, s8, v[35:36]
	v_ashrrev_i32_e32 v84, 31, v83
	v_ashrrev_i32_e32 v86, 31, v85
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[79:80], 3, v[81:82]
	v_ashrrev_i32_e32 v90, 31, v89
	s_cmp_lt_i32 s46, 2
	v_lshlrev_b64 v[81:82], 3, v[83:84]
	v_lshlrev_b64 v[83:84], 3, v[85:86]
	v_ashrrev_i32_e32 v78, 31, v77
	v_lshlrev_b64 v[85:86], 3, v[89:90]
	v_add_co_u32 v79, vcc_lo, s4, v79
	v_add_co_ci_u32_e32 v80, vcc_lo, s5, v80, vcc_lo
	v_add_f64 v[12:13], v[12:13], v[75:76]
	v_lshlrev_b64 v[77:78], 3, v[77:78]
	v_add_co_u32 v81, vcc_lo, s4, v81
	v_add_co_ci_u32_e32 v82, vcc_lo, s5, v82, vcc_lo
	v_add_co_u32 v83, vcc_lo, s4, v83
	v_add_co_ci_u32_e32 v84, vcc_lo, s5, v84, vcc_lo
	v_add_co_u32 v77, vcc_lo, s4, v77
	v_add_co_ci_u32_e32 v78, vcc_lo, s5, v78, vcc_lo
	v_add_co_u32 v85, vcc_lo, s4, v85
	v_add_co_ci_u32_e32 v86, vcc_lo, s5, v86, vcc_lo
	s_waitcnt vmcnt(11)
	v_fma_f64 v[70:71], v[0:1], s[36:37], -v[70:71]
	s_waitcnt vmcnt(10)
	v_add_f64 v[87:88], v[68:69], -v[32:33]
	v_fma_f64 v[72:73], v[68:69], s[36:37], -v[72:73]
	s_waitcnt vmcnt(8)
	v_mul_f64 v[74:75], v[16:17], v[6:7]
	s_waitcnt vmcnt(7)
	v_mul_f64 v[89:90], v[6:7], v[18:19]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[91:92], v[24:25], -2.0, v[8:9]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[93:94], v[22:23], -2.0, v[50:51]
	scratch_load_b128 v[22:25], off, off offset:120
	s_waitcnt vmcnt(4)
	v_fma_f64 v[2:3], v[2:3], -2.0, v[52:53]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[52:53], v[64:65], -2.0, v[54:55]
	v_mul_f64 v[70:71], v[6:7], v[70:71]
	v_mul_f64 v[87:88], v[87:88], s[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[2:3], v[14:15], v[2:3]
	v_add_f64 v[14:15], v[16:17], v[52:53]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[8:9], v[50:51], v[72:73], -v[70:71]
	v_fma_f64 v[70:71], v[54:55], v[50:51], -v[74:75]
	v_fma_f64 v[72:73], v[50:51], v[56:57], -v[89:90]
	v_fma_f64 v[74:75], v[58:59], v[50:51], v[87:88]
	v_fma_f64 v[87:88], v[62:63], -2.0, v[48:49]
	scratch_load_b128 v[48:51], off, off offset:304
	global_load_b64 v[54:55], v[85:86], off
	v_fma_f64 v[56:57], v[66:67], -2.0, v[56:57]
	v_add_f64 v[66:67], v[58:59], -v[20:21]
	v_add_f64 v[4:5], v[4:5], v[87:88]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[52:53], v[18:19], v[56:57]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[22:23], v[22:23], -2.0, v[58:59]
	v_add_f64 v[22:23], v[20:21], v[22:23]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[50:51], v[60:61], -2.0, v[50:51]
	scratch_load_b128 v[60:63], off, off offset:256
	s_waitcnt vmcnt(1)
	v_fma_f64 v[54:55], -s[12:13], v[8:9], v[54:55]
	v_add_f64 v[8:9], v[0:1], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], s[34:35]
	v_fma_f64 v[8:9], v[20:21], v[6:7], v[8:9]
	v_add_f64 v[6:7], v[6:7], v[93:94]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[48:49], v[62:63], -2.0, v[48:49]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[62:63], v[74:75], -v[8:9]
	scratch_load_b128 v[8:11], off, off offset:224
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[48:49]
	v_add_f64 v[10:11], v[10:11], v[50:51]
	v_add_f64 v[50:51], v[60:61], v[91:92]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[8:9], v[40:41], v[8:9], v[54:55]
	s_clause 0x3
	global_load_b64 v[48:49], v[81:82], off
	global_load_b64 v[54:55], v[83:84], off
	global_load_b64 v[64:65], v[77:78], off
	global_load_b64 v[74:75], v[79:80], off
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[8:9], v[12:13], s[26:27], v[8:9]
	v_fma_f64 v[12:13], v[24:25], -2.0, v[68:69]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], s[28:29], v[50:51], v[8:9]
	v_add_f64 v[0:1], v[0:1], v[12:13]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[48:49], -s[12:13], v[70:71], v[48:49]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[54:55], -s[12:13], v[72:73], v[54:55]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[58:59], -s[12:13], v[62:63], v[64:65]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[24:25], -s[12:13], v[66:67], v[74:75]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], s[16:17], v[10:11], v[48:49]
	v_fma_f64 v[4:5], s[16:17], v[4:5], v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[6:7], s[22:23], v[6:7], v[58:59]
	v_fma_f64 v[16:17], s[14:15], v[2:3], v[24:25]
	v_fma_f64 v[24:25], s[30:31], v[0:1], v[8:9]
	v_fma_f64 v[18:19], s[18:19], v[14:15], v[10:11]
	v_fma_f64 v[20:21], s[20:21], v[52:53], v[4:5]
	v_fma_f64 v[22:23], s[24:25], v[22:23], v[6:7]
	s_cbranch_scc1 .LBB3_22
; %bb.18:                               ; %LeafBlock562
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_cmp_eq_u32 s46, 2
	s_cbranch_scc0 .LBB3_23
; %bb.19:                               ; %.preheader213.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
	v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	s_mov_b64 s[38:39], 0
	s_mov_b32 s41, s33
.LBB3_20:                               ; %.preheader213
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[10:11], off, s41 offset:-40
	scratch_load_b64 v[12:13], off, s41
	s_cmp_eq_u32 s38, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 2
	v_cndmask_b32_e32 v14, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v5, s0
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s3, s41, 40
	v_cndmask_b32_e64 v50, v14, v7, s1
	scratch_load_b64 v[14:15], off, s3
	s_add_i32 s3, s41, 0x50
	s_cmp_eq_u32 s38, 0
	scratch_load_b64 v[48:49], off, s3
	s_cselect_b32 s3, -1, 0
	s_add_i32 s41, s41, 8
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_cmp_eq_u32 s38, 5
	s_waitcnt vmcnt(3)
	v_mul_f64 v[10:11], v[10:11], -4.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], 0x40180000, v[12:13], v[10:11]
	v_cndmask_b32_e32 v12, v0, v2, vcc_lo
	v_cndmask_b32_e64 v13, v50, v9, s2
	v_cndmask_b32_e64 v12, v12, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v6, s1
	v_cndmask_b32_e64 v12, v12, v8, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[10:11], v[14:15], -4.0, v[10:11]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[48:49], v[10:11]
	v_fma_f64 v[10:11], 0xbfd00000, v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_cndmask_b32_e64 v9, v9, v11, s2
	v_cndmask_b32_e64 v8, v8, v10, s2
	v_cndmask_b32_e64 v7, v7, v11, s1
	v_cndmask_b32_e64 v6, v6, v10, s1
	v_cndmask_b32_e64 v5, v5, v11, s0
	v_cndmask_b32_e64 v4, v4, v10, s0
	v_cndmask_b32_e32 v2, v2, v10, vcc_lo
	v_cndmask_b32_e64 v1, v1, v11, s3
	v_cndmask_b32_e64 v0, v0, v10, s3
	s_cbranch_scc0 .LBB3_20
; %bb.21:                               ; %Flow564
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB3_24
.LBB3_22:                               ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_branch .LBB3_25
.LBB3_23:                               ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
.LBB3_24:                               ; %Flow575
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s1, 0
.LBB3_25:                               ; %Flow574
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB3_27
; %bb.26:                               ; %LeafBlock
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_cmp_lg_u32 s46, 1
	s_mov_b32 s40, -1
	s_cselect_b32 s0, -1, 0
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
.LBB3_27:                               ; %Flow576
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_45
; %bb.28:                               ;   in Loop: Header=BB3_12 Depth=1
	s_cmp_gt_u32 s46, 2
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s46, s42
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_33
; %bb.29:                               ;   in Loop: Header=BB3_12 Depth=1
	s_cmp_lg_u32 s46, s42
	s_cbranch_scc0 .LBB3_34
; %bb.30:                               ;   in Loop: Header=BB3_12 Depth=1
	s_cmp_lg_u32 s46, s43
	s_cbranch_scc1 .LBB3_35
; %bb.31:                               ; %.preheader209.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
	v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	s_mov_b64 s[38:39], 0
	s_mov_b32 s40, s11
.LBB3_32:                               ; %.preheader209
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	scratch_load_b64 v[10:11], off, s40 offset:-40
	scratch_load_b64 v[12:13], off, s40
	s_cmp_eq_u32 s38, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 2
	v_cndmask_b32_e32 v14, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v5, s0
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s3, s40, 40
	v_cndmask_b32_e64 v48, v14, v7, s1
	scratch_load_b64 v[14:15], off, s3
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_i32 s40, s40, 8
	s_cmp_eq_u32 s38, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[10:11], v[12:13], -4.0, v[10:11]
	v_cndmask_b32_e32 v12, v0, v2, vcc_lo
	v_cndmask_b32_e64 v13, v48, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v4, s0
	v_cndmask_b32_e64 v12, v12, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v8, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], 0x40140000, v[14:15], v[10:11]
	v_fma_f64 v[10:11], 0xbfd00000, v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_cndmask_b32_e64 v9, v9, v11, s2
	v_cndmask_b32_e64 v8, v8, v10, s2
	v_cndmask_b32_e64 v7, v7, v11, s1
	v_cndmask_b32_e64 v6, v6, v10, s1
	v_cndmask_b32_e64 v5, v5, v11, s0
	v_cndmask_b32_e64 v4, v4, v10, s0
	v_cndmask_b32_e32 v2, v2, v10, vcc_lo
	v_cndmask_b32_e64 v1, v1, v11, s3
	v_cndmask_b32_e64 v0, v0, v10, s3
	s_cbranch_scc0 .LBB3_32
	s_branch .LBB3_36
.LBB3_33:                               ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_branch .LBB3_41
.LBB3_34:                               ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
	s_branch .LBB3_37
.LBB3_35:                               ;   in Loop: Header=BB3_12 Depth=1
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
	v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
	v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
	v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
.LBB3_36:                               ; %Flow566
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, 0
.LBB3_37:                               ; %Flow568
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_40
; %bb.38:                               ; %.preheader207.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_mov_b32_e32 v0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v2, v18
	v_mov_b32_e32 v4, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v6, v22
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	v_dual_mov_b32 v10, v43 :: v_dual_mov_b32 v1, v17
	v_mov_b32_e32 v3, v19
	v_mov_b32_e32 v5, v21
	v_mov_b32_e32 v7, v23
	s_mov_b64 s[38:39], 0
.LBB3_39:                               ; %.preheader207
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x3
	scratch_load_b64 v[11:12], v10, off offset:-120
	scratch_load_b64 v[13:14], v10, off offset:-80
	scratch_load_b64 v[48:49], v10, off offset:-40
	scratch_load_b64 v[50:51], v10, off
	s_cmp_eq_u32 s38, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_cmp_eq_u32 s38, 5
	s_waitcnt vmcnt(2)
	v_fma_f64 v[11:12], v[13:14], -4.0, v[11:12]
	v_dual_cndmask_b32 v13, v1, v3 :: v_dual_cndmask_b32 v14, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, v5, s0
	v_cndmask_b32_e64 v14, v14, v4, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, v7, s1
	v_cndmask_b32_e64 v15, v14, v6, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v13, v9, s2
	v_cndmask_b32_e64 v13, v15, v8, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[11:12], 0x40180000, v[48:49], v[11:12]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[50:51], -4.0, v[11:12]
	v_fma_f64 v[11:12], 0xbfd00000, v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_add_nc_u32 v10, 8, v10
	v_cndmask_b32_e64 v9, v9, v12, s2
	v_cndmask_b32_e64 v8, v8, v11, s2
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v6, v6, v11, s1
	v_cndmask_b32_e64 v5, v5, v12, s0
	v_cndmask_b32_e64 v4, v4, v11, s0
	v_cndmask_b32_e32 v2, v2, v11, vcc_lo
	v_cndmask_b32_e64 v1, v1, v12, s3
	v_cndmask_b32_e64 v0, v0, v11, s3
	s_cbranch_scc0 .LBB3_39
.LBB3_40:                               ; %Flow569
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, 0
.LBB3_41:                               ; %Flow571
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB3_44
; %bb.42:                               ; %.preheader206.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
	v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	s_mov_b64 s[38:39], 0
	s_mov_b32 s40, s33
.LBB3_43:                               ; %.preheader206
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x2
	scratch_load_b64 v[10:11], off, s40 offset:-80
	scratch_load_b64 v[12:13], off, s40 offset:-40
	scratch_load_b64 v[14:15], off, s40
	s_cmp_eq_u32 s38, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 2
	v_cndmask_b32_e32 v48, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v48, v48, v5, s0
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s3, s40, 40
	v_cndmask_b32_e64 v52, v48, v7, s1
	scratch_load_b64 v[48:49], off, s3
	s_add_i32 s3, s40, 0x50
	s_cmp_eq_u32 s38, 0
	scratch_load_b64 v[50:51], off, s3
	s_cselect_b32 s3, -1, 0
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_i32 s40, s40, 8
	s_cmp_eq_u32 s38, 5
	s_waitcnt vmcnt(3)
	v_fma_f64 v[10:11], v[12:13], -4.0, v[10:11]
	v_cndmask_b32_e32 v12, v0, v2, vcc_lo
	v_cndmask_b32_e64 v13, v52, v9, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v4, s0
	v_cndmask_b32_e64 v12, v12, v6, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v8, s2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[10:11], 0x40180000, v[14:15], v[10:11]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[10:11], v[48:49], -4.0, v[10:11]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[50:51], v[10:11]
	v_fma_f64 v[10:11], 0xbfd00000, v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v11, vcc_lo
	v_cndmask_b32_e64 v9, v9, v11, s2
	v_cndmask_b32_e64 v8, v8, v10, s2
	v_cndmask_b32_e64 v7, v7, v11, s1
	v_cndmask_b32_e64 v6, v6, v10, s1
	v_cndmask_b32_e64 v5, v5, v11, s0
	v_cndmask_b32_e64 v4, v4, v10, s0
	v_cndmask_b32_e32 v2, v2, v10, vcc_lo
	v_cndmask_b32_e64 v1, v1, v11, s3
	v_cndmask_b32_e64 v0, v0, v10, s3
	s_cbranch_scc0 .LBB3_43
.LBB3_44:                               ; %Flow572
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s40, 0
.LBB3_45:                               ; %Flow577
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s40
	s_cbranch_vccnz .LBB3_49
; %bb.46:                               ; %.preheader211.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b64 s[38:39], 0
	s_mov_b32 s40, s33
.LBB3_47:                               ; %.preheader211
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s38, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v17, v19, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 3
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v0, v0, v21, s0
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 s2, -1, 0
	s_add_i32 s3, s40, 40
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v0, v23, s1
	s_clause 0x1
	scratch_load_b64 v[0:1], off, s3
	scratch_load_b64 v[2:3], off, s40
	s_add_i32 s3, s40, 0x50
	s_cmp_eq_u32 s38, 0
	scratch_load_b64 v[4:5], off, s3
	s_cselect_b32 s3, -1, 0
	s_add_i32 s40, s40, 8
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_cmp_eq_u32 s38, 5
	s_waitcnt vmcnt(2)
	v_mul_f64 v[0:1], v[0:1], -4.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], 0x40140000, v[2:3], v[0:1]
	v_cndmask_b32_e32 v2, v16, v18, vcc_lo
	v_cndmask_b32_e64 v3, v6, v25, s2
	v_cndmask_b32_e64 v2, v2, v20, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v2, v22, s1
	v_cndmask_b32_e64 v2, v2, v24, s2
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], 0xbfd00000, v[0:1], v[2:3]
	v_cndmask_b32_e32 v19, v19, v1, vcc_lo
	v_cndmask_b32_e64 v25, v25, v1, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v24, v24, v0, s2
	v_cndmask_b32_e64 v23, v23, v1, s1
	v_cndmask_b32_e64 v22, v22, v0, s1
	v_cndmask_b32_e64 v21, v21, v1, s0
	v_cndmask_b32_e64 v20, v20, v0, s0
	v_cndmask_b32_e32 v18, v18, v0, vcc_lo
	v_cndmask_b32_e64 v17, v17, v1, s3
	v_cndmask_b32_e64 v16, v16, v0, s3
	s_cbranch_scc0 .LBB3_47
; %bb.48:                               ; %Flow573
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
	v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
	v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
	v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
	v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
	v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
	v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
	v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
.LBB3_49:                               ; %.loopexit
                                        ;   in Loop: Header=BB3_12 Depth=1
	v_mov_b32_e32 v10, v47
	s_mov_b64 s[2:3], 0
.LBB3_50:                               ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 1
	v_ashrrev_i32_e32 v11, 31, v10
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v13, v0, v2 :: v_dual_cndmask_b32 v14, v1, v3
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[11:12], 3, v[10:11]
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, v4, s0
	v_cndmask_b32_e64 v14, v14, v5, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_add_co_u32 v11, s0, s4, v11
	v_dual_cndmask_b32 v13, v13, v6 :: v_dual_cndmask_b32 v14, v14, v7
	v_add_co_ci_u32_e64 v12, vcc_lo, s5, v12, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v13, v8 :: v_dual_add_nc_u32 v10, s45, v10
	v_cndmask_b32_e64 v14, -v14, -v9, vcc_lo
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[11:12], v[13:14], off
	s_cbranch_scc1 .LBB3_50
; %bb.51:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB3_12 Depth=1
	s_mov_b32 s0, 0
.LBB3_52:                               ; %.preheader
                                        ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s1, v42
	v_add_nc_u32_e64 v10, 0xe0, s0
	s_add_i32 s39, s0, 0xe0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s1, s1, s0
	v_add_nc_u32_e32 v22, 40, v10
	s_add_i32 s2, s1, 40
	v_add_nc_u32_e32 v20, 0x50, v10
	s_add_i32 s3, s1, 0x50
	s_add_i32 s38, s1, 0x78
	s_addk_i32 s1, 0xa0
	s_clause 0x3
	scratch_load_b64 v[10:11], off, s2
	scratch_load_b64 v[12:13], off, s3
	scratch_load_b64 v[14:15], off, s38
	scratch_load_b64 v[16:17], off, s1
	s_clause 0x1
	scratch_load_b64 v[18:19], v22, off
	scratch_load_b64 v[20:21], v20, off
	s_add_i32 s1, s0, 16
	s_add_i32 s0, s0, 8
	s_waitcnt vmcnt(5)
	scratch_store_b64 off, v[10:11], s1
	s_waitcnt vmcnt(4)
	scratch_store_b64 off, v[12:13], s2
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[14:15], s3
	s_waitcnt vmcnt(2)
	scratch_store_b64 off, v[16:17], s38
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[18:19], s39
	s_waitcnt vmcnt(0)
	scratch_store_b64 v22, v[20:21], off
	s_cmp_lg_u32 s0, 40
	s_cbranch_scc1 .LBB3_52
; %bb.53:                               ;   in Loop: Header=BB3_12 Depth=1
	v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
	v_dual_mov_b32 v28, v30 :: v_dual_mov_b32 v29, v31
	v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
	v_dual_mov_b32 v26, v32 :: v_dual_mov_b32 v27, v33
	s_cmp_ge_i32 s46, s43
	s_cbranch_scc1 .LBB3_57
; %bb.54:                               ;   in Loop: Header=BB3_12 Depth=1
	scratch_load_b64 v[14:15], off, off offset:136
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[16:17], null, v[14:15], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[22:23], v[20:21], v[18:19]
	v_fma_f64 v[16:17], -v[16:17], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[22:23]
	v_div_fixup_f64 v[14:15], v[16:17], v[14:15], 1.0
.LBB3_55:                               ;   Parent Loop BB3_12 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v16, s0, v44
	v_add_nc_u32_e32 v18, s0, v45
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 32
	scratch_load_b64 v[16:17], v16, off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[16:17], v[14:15], v[16:17]
	scratch_store_b64 v18, v[16:17], off
	s_cbranch_scc1 .LBB3_55
; %bb.56:                               ;   in Loop: Header=BB3_12 Depth=1
	s_clause 0x3
	scratch_load_b128 v[14:17], off, off offset:312
	scratch_load_b128 v[18:21], off, off offset:144
	scratch_load_b64 v[22:23], off, off offset:328
	scratch_load_b64 v[24:25], off, off offset:160
	s_waitcnt vmcnt(2)
	v_mul_f64 v[20:21], v[16:17], v[20:21]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[30:31], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[14:15], v[18:19], v[20:21]
	v_fma_f64 v[14:15], v[14:15], v[14:15], v[30:31]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[22:23], v[24:25], v[18:19]
	v_fma_f64 v[14:15], v[16:17], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[32:33], v[18:19], 0.5
	scratch_store_b64 off, v[14:15], off offset:304
.LBB3_57:                               ;   in Loop: Header=BB3_12 Depth=1
	v_add_nc_u32_e32 v47, s44, v47
	s_add_i32 s0, s46, 1
	s_cmp_lg_u32 s46, s43
	s_mov_b32 s46, s0
	s_cbranch_scc1 .LBB3_12
.LBB3_58:                               ; %.loopexit217
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL18exact_rhs_kernel_zPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 352
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 95
		.amdhsa_next_free_sgpr 60
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL18exact_rhs_kernel_zPdiii,"axG",@progbits,_ZL18exact_rhs_kernel_zPdiii,comdat
.Lfunc_end3:
	.size	_ZL18exact_rhs_kernel_zPdiii, .Lfunc_end3-_ZL18exact_rhs_kernel_zPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6096
; NumSgprs: 62
; NumVgprs: 95
; ScratchSize: 352
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 62
; NumVGPRsForWavesPerEU: 95
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL17initialize_kernelPdiii,"axG",@progbits,_ZL17initialize_kernelPdiii,comdat
	.globl	_ZL17initialize_kernelPdiii     ; -- Begin function _ZL17initialize_kernelPdiii
	.p2align	8
	.type	_ZL17initialize_kernelPdiii,@function
_ZL17initialize_kernelPdiii:            ; @_ZL17initialize_kernelPdiii
; %bb.0:
	v_cvt_f64_i32_e32 v[1:2], s14
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[8:9], s[0:1], 0x0
	v_cvt_f64_i32_e32 v[3:4], s15
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, dnzm1@rel32@lo+4
	s_addc_u32 s11, s11, dnzm1@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, dnym1@rel32@lo+4
	s_addc_u32 s13, s13, dnym1@rel32@hi+12
	s_load_b64 s[0:1], s[10:11], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	s_mov_b32 s3, 0x3ff00000
	s_mov_b32 s2, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
	s_mov_b32 s3, s2
	s_mov_b64 s[24:25], 0
                                        ; implicit-def: $sgpr18_sgpr19
                                        ; implicit-def: $sgpr20_sgpr21
                                        ; implicit-def: $sgpr22_sgpr23
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s14, s5
	s_add_i32 s10, s14, s6
	s_add_i32 s11, s7, s15
	s_mul_i32 s16, s10, s5
	s_add_i32 s17, s10, s6
	s_mul_i32 s10, s11, s4
	s_add_i32 s16, s16, s15
	v_add_nc_u32_e32 v17, s10, v0
	s_mul_i32 s11, s17, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s11, s11, s15
	v_ashrrev_i32_e32 v18, 31, v17
	v_mad_u64_u32 v[7:8], null, s16, s4, v[0:1]
	v_mad_u64_u32 v[9:10], null, s11, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 3, v[17:18]
	v_mul_f64 v[22:23], s[0:1], v[1:2]
	v_mul_f64 v[18:19], s[12:13], v[3:4]
	s_add_i32 s16, s17, s6
	v_ashrrev_i32_e32 v8, 31, v7
	s_mul_i32 s17, s16, s5
	v_add_co_u32 v3, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v11, vcc_lo
	v_mov_b32_e32 v12, s3
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	s_add_i32 s0, s16, s6
	s_add_i32 s17, s17, s15
	s_mul_i32 s0, s0, s5
	v_ashrrev_i32_e32 v10, 31, v9
	s_add_i32 s0, s0, s15
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	v_mov_b32_e32 v11, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, s17, s4, v[0:1]
	v_mad_u64_u32 v[13:14], null, s0, s4, v[0:1]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dnxm1@rel32@lo+4
	s_addc_u32 s1, s1, dnxm1@rel32@hi+12
	global_store_b64 v[3:4], v[5:6], off
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 3, v[9:10]
	v_ashrrev_i32_e32 v8, 31, v7
	global_store_b64 v[1:2], v[11:12], off
	v_ashrrev_i32_e32 v14, 31, v13
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ce@rel32@lo+4
	s_addc_u32 s3, s3, ce@rel32@hi+12
                                        ; implicit-def: $sgpr12_sgpr13
                                        ; implicit-def: $sgpr16_sgpr17
	v_lshlrev_b64 v[1:2], 3, v[7:8]
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_lshlrev_b64 v[7:8], 3, v[13:14]
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v7, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	s_clause 0x2
	global_store_b64 v[3:4], v[11:12], off
	global_store_b64 v[1:2], v[11:12], off
	global_store_b64 v[7:8], v[5:6], off
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[26:27], s[2:3], 0x118
	s_load_b64 s[28:29], s[2:3], 0x190
	s_load_b64 s[30:31], s[2:3], 0xa0
	s_load_b64 s[34:35], s[2:3], 0xc8
	s_load_b64 s[36:37], s[2:3], 0x140
	s_load_b64 s[38:39], s[2:3], 0x1b8
	s_load_b64 s[40:41], s[2:3], 0xf0
	s_load_b64 s[42:43], s[2:3], 0x168
	s_cmp_eq_u32 s24, 4
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], s[28:29], 0, s[26:27]
	v_fma_f64 v[3:4], v[18:19], s[38:39], s[36:37]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[1:2], v[1:2], 0, s[30:31]
	s_clause 0x4
	s_load_b64 s[26:27], s[2:3], 0x1e0
	s_load_b64 s[28:29], s[2:3], 0x28
	s_load_b64 s[30:31], s[2:3], 0x0
	s_load_b64 s[36:37], s[2:3], 0x50
	s_load_b64 s[38:39], s[2:3], 0x78
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[34:35]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[5:6], v[22:23], s[26:27], s[42:43]
	v_fma_f64 v[1:2], v[1:2], 0, s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[36:37]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[1:2], v[1:2], 0, s[30:31]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[18:19], v[3:4], v[1:2]
	v_fma_f64 v[1:2], v[22:23], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v2
	v_readfirstlane_b32 s26, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cselect_b32 s23, s11, s23
	s_cselect_b32 s22, s26, s22
	s_cmp_eq_u32 s24, 3
	s_cselect_b32 s21, s11, s21
	s_cselect_b32 s20, s26, s20
	s_cmp_eq_u32 s24, 2
	s_cselect_b32 s19, s11, s19
	s_cselect_b32 s18, s26, s18
	s_cmp_eq_u32 s24, 1
	s_cselect_b32 s17, s11, s17
	s_cselect_b32 s16, s26, s16
	s_cmp_eq_u32 s24, 0
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s12, s26, s12
	s_add_u32 s24, s24, 1
	s_addc_u32 s25, s25, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s24, 5
	s_cbranch_scc1 .LBB4_1
; %bb.2:                                ; %_ZL21exact_solution_kerneldddPd.exit.preheader
	s_mov_b64 s[36:37], 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ce@rel32@lo+4
	s_addc_u32 s3, s3, ce@rel32@hi+12
                                        ; implicit-def: $sgpr24_sgpr25
                                        ; implicit-def: $sgpr26_sgpr27
                                        ; implicit-def: $sgpr28_sgpr29
                                        ; implicit-def: $sgpr30_sgpr31
                                        ; implicit-def: $sgpr34_sgpr35
.LBB4_3:                                ; %_ZL21exact_solution_kerneldddPd.exit
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[38:39], s[2:3], 0x118
	s_load_b64 s[40:41], s[2:3], 0x190
	s_load_b64 s[42:43], s[2:3], 0xa0
	s_load_b64 s[44:45], s[2:3], 0xc8
	s_load_b64 s[46:47], s[2:3], 0x140
	s_load_b64 s[48:49], s[2:3], 0x1b8
	s_load_b64 s[50:51], s[2:3], 0xf0
	s_load_b64 s[52:53], s[2:3], 0x168
	s_cmp_eq_u32 s36, 4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], s[38:39], s[40:41]
	v_fma_f64 v[3:4], v[18:19], s[48:49], s[46:47]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[1:2], s[42:43], v[1:2]
	s_clause 0x4
	s_load_b64 s[38:39], s[2:3], 0x1e0
	s_load_b64 s[40:41], s[2:3], 0x28
	s_load_b64 s[42:43], s[2:3], 0x0
	s_load_b64 s[46:47], s[2:3], 0x50
	s_load_b64 s[48:49], s[2:3], 0x78
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[44:45]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[5:6], v[22:23], s[38:39], s[52:53]
	v_add_f64 v[1:2], s[40:41], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[46:47]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], s[42:43], v[1:2]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[18:19], v[3:4], v[1:2]
	v_fma_f64 v[1:2], v[22:23], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v2
	v_readfirstlane_b32 s33, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cselect_b32 s35, s11, s35
	s_cselect_b32 s34, s33, s34
	s_cmp_eq_u32 s36, 3
	s_cselect_b32 s31, s11, s31
	s_cselect_b32 s30, s33, s30
	s_cmp_eq_u32 s36, 2
	s_cselect_b32 s29, s11, s29
	s_cselect_b32 s28, s33, s28
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 s27, s11, s27
	s_cselect_b32 s26, s33, s26
	s_cmp_eq_u32 s36, 0
	s_cselect_b32 s25, s11, s25
	s_cselect_b32 s24, s33, s24
	s_add_u32 s36, s36, 1
	s_addc_u32 s37, s37, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s36, 5
	s_cbranch_scc1 .LBB4_3
; %bb.4:                                ; %_ZL21exact_solution_kerneldddPd.exit203.preheader
	v_cvt_f64_i32_e32 v[1:2], v0
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[36:37]
	s_add_u32 s36, s36, ce@rel32@lo+4
	s_addc_u32 s37, s37, ce@rel32@hi+12
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr9_vgpr10
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[20:21], s[0:1], v[1:2]
                                        ; implicit-def: $vgpr1_vgpr2
.LBB4_5:                                ; %_ZL21exact_solution_kerneldddPd.exit203
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[36:37], 0x118
	s_load_b64 s[2:3], s[36:37], 0x190
	s_load_b64 s[40:41], s[36:37], 0xa0
	s_load_b64 s[42:43], s[36:37], 0xc8
	s_load_b64 s[44:45], s[36:37], 0x140
	s_load_b64 s[46:47], s[36:37], 0x1b8
	s_load_b64 s[48:49], s[36:37], 0xf0
	s_load_b64 s[50:51], s[36:37], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[13:14], s[46:47], 0, s[44:45]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[40:41]
	s_clause 0x4
	s_load_b64 s[0:1], s[36:37], 0x1e0
	s_load_b64 s[2:3], s[36:37], 0x28
	s_load_b64 s[40:41], s[36:37], 0x0
	s_load_b64 s[44:45], s[36:37], 0x50
	s_load_b64 s[46:47], s[36:37], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], 0, s[42:43]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[15:16], v[22:23], s[0:1], s[50:51]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[13:14], v[13:14], 0, s[44:45]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s36, s36, 8
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[48:49]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[46:47]
	v_fma_f64 v[11:12], v[13:14], 0, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[22:23], v[15:16], v[11:12]
	v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v9, v9, v11
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v12, s1
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_cndmask_b32_e64 v4, v4, v12, s2
	v_cndmask_b32_e64 v3, v3, v11, s2
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB4_5
; %bb.6:                                ; %_ZL21exact_solution_kerneldddPd.exit206.preheader
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[36:37]
	s_add_u32 s36, s36, ce@rel32@lo+4
	s_addc_u32 s37, s37, ce@rel32@hi+12
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr13_vgpr14
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $vgpr26_vgpr27
.LBB4_7:                                ; %_ZL21exact_solution_kerneldddPd.exit206
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[36:37], 0x118
	s_load_b64 s[2:3], s[36:37], 0x190
	s_load_b64 s[40:41], s[36:37], 0xa0
	s_load_b64 s[42:43], s[36:37], 0xc8
	s_load_b64 s[44:45], s[36:37], 0x140
	s_load_b64 s[46:47], s[36:37], 0x1b8
	s_load_b64 s[48:49], s[36:37], 0xf0
	s_load_b64 s[50:51], s[36:37], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[28:29], v[20:21], s[2:3], s[0:1]
	v_add_f64 v[30:31], s[44:45], s[46:47]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[28:29], v[20:21], v[28:29], s[40:41]
	s_clause 0x4
	s_load_b64 s[0:1], s[36:37], 0x1e0
	s_load_b64 s[2:3], s[36:37], 0x28
	s_load_b64 s[40:41], s[36:37], 0x0
	s_load_b64 s[44:45], s[36:37], 0x50
	s_load_b64 s[46:47], s[36:37], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[30:31], s[42:43], v[30:31]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[32:33], v[22:23], s[0:1], s[50:51]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[20:21], v[28:29], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_add_f64 v[30:31], s[44:45], v[30:31]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s36, s36, 8
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[22:23], v[32:33], s[48:49]
	v_fma_f64 v[28:29], v[20:21], v[28:29], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[22:23], v[32:33], s[46:47]
	v_add_f64 v[28:29], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[22:23], v[32:33], v[28:29]
	v_dual_cndmask_b32 v27, v27, v29 :: v_dual_cndmask_b32 v26, v26, v28
	v_cndmask_b32_e64 v25, v25, v29, s0
	v_cndmask_b32_e64 v24, v24, v28, s0
	v_cndmask_b32_e64 v16, v16, v29, s1
	v_cndmask_b32_e64 v15, v15, v28, s1
	v_cndmask_b32_e64 v14, v14, v29, s2
	v_cndmask_b32_e64 v13, v13, v28, s2
	v_cndmask_b32_e64 v12, v12, v29, s3
	v_cndmask_b32_e64 v11, v11, v28, s3
	s_cbranch_scc1 .LBB4_7
; %bb.8:                                ; %_ZL21exact_solution_kerneldddPd.exit209.preheader
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[36:37]
	s_add_u32 s36, s36, ce@rel32@lo+4
	s_addc_u32 s37, s37, ce@rel32@hi+12
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr36_vgpr37
.LBB4_9:                                ; %_ZL21exact_solution_kerneldddPd.exit209
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[36:37], 0x118
	s_load_b64 s[2:3], s[36:37], 0x190
	s_load_b64 s[40:41], s[36:37], 0xa0
	s_load_b64 s[42:43], s[36:37], 0xc8
	s_load_b64 s[44:45], s[36:37], 0x140
	s_load_b64 s[46:47], s[36:37], 0x1b8
	s_load_b64 s[48:49], s[36:37], 0xf0
	s_load_b64 s[50:51], s[36:37], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[38:39], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[40:41], v[18:19], s[46:47], s[44:45]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[20:21], v[38:39], s[40:41]
	s_clause 0x4
	s_load_b64 s[0:1], s[36:37], 0x1e0
	s_load_b64 s[2:3], s[36:37], 0x28
	s_load_b64 s[40:41], s[36:37], 0x0
	s_load_b64 s[44:45], s[36:37], 0x50
	s_load_b64 s[46:47], s[36:37], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[40:41], v[18:19], v[40:41], s[42:43]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[42:43], s[0:1], 0, s[50:51]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[20:21], v[38:39], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[40:41], v[18:19], v[40:41], s[44:45]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s36, s36, 8
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[42:43], 0, s[48:49]
	v_fma_f64 v[38:39], v[20:21], v[38:39], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], v[42:43], 0, s[46:47]
	v_fma_f64 v[38:39], v[18:19], v[40:41], v[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[42:43], 0, v[38:39]
	v_dual_cndmask_b32 v37, v37, v39 :: v_dual_cndmask_b32 v36, v36, v38
	v_cndmask_b32_e64 v35, v35, v39, s0
	v_cndmask_b32_e64 v34, v34, v38, s0
	v_cndmask_b32_e64 v33, v33, v39, s1
	v_cndmask_b32_e64 v32, v32, v38, s1
	v_cndmask_b32_e64 v31, v31, v39, s2
	v_cndmask_b32_e64 v30, v30, v38, s2
	v_cndmask_b32_e64 v29, v29, v39, s3
	v_cndmask_b32_e64 v28, v28, v38, s3
	s_cbranch_scc1 .LBB4_9
; %bb.10:                               ; %_ZL21exact_solution_kerneldddPd.exit212.preheader
	s_mov_b64 s[38:39], 0
	s_getpc_b64 s[36:37]
	s_add_u32 s36, s36, ce@rel32@lo+4
	s_addc_u32 s37, s37, ce@rel32@hi+12
                                        ; implicit-def: $vgpr38_vgpr39
                                        ; implicit-def: $vgpr40_vgpr41
                                        ; implicit-def: $vgpr42_vgpr43
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr46_vgpr47
.LBB4_11:                               ; %_ZL21exact_solution_kerneldddPd.exit212
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[36:37], 0x118
	s_load_b64 s[2:3], s[36:37], 0x190
	s_load_b64 s[40:41], s[36:37], 0xa0
	s_load_b64 s[42:43], s[36:37], 0xc8
	s_load_b64 s[44:45], s[36:37], 0x140
	s_load_b64 s[46:47], s[36:37], 0x1b8
	s_load_b64 s[48:49], s[36:37], 0xf0
	s_load_b64 s[50:51], s[36:37], 0x168
	s_cmp_eq_u32 s38, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s38, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[48:49], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[50:51], v[18:19], s[46:47], s[44:45]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[20:21], v[48:49], s[40:41]
	s_clause 0x4
	s_load_b64 s[0:1], s[36:37], 0x1e0
	s_load_b64 s[2:3], s[36:37], 0x28
	s_load_b64 s[40:41], s[36:37], 0x0
	s_load_b64 s[44:45], s[36:37], 0x50
	s_load_b64 s[46:47], s[36:37], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[50:51], v[18:19], v[50:51], s[42:43]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[52:53], s[50:51], s[0:1]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s38, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s38, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[20:21], v[48:49], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s38, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[50:51], v[18:19], v[50:51], s[44:45]
	s_add_u32 s38, s38, 1
	s_addc_u32 s39, s39, 0
	s_add_u32 s36, s36, 8
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s38, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[52:53], s[48:49], v[52:53]
	v_fma_f64 v[48:49], v[20:21], v[48:49], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[52:53], s[46:47], v[52:53]
	v_fma_f64 v[48:49], v[18:19], v[50:51], v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[48:49], v[52:53], v[48:49]
	v_dual_cndmask_b32 v47, v47, v49 :: v_dual_cndmask_b32 v46, v46, v48
	v_cndmask_b32_e64 v45, v45, v49, s0
	v_cndmask_b32_e64 v44, v44, v48, s0
	v_cndmask_b32_e64 v43, v43, v49, s1
	v_cndmask_b32_e64 v42, v42, v48, s1
	v_cndmask_b32_e64 v41, v41, v49, s2
	v_cndmask_b32_e64 v40, v40, v48, s2
	v_cndmask_b32_e64 v39, v39, v49, s3
	v_cndmask_b32_e64 v38, v38, v48, s3
	s_cbranch_scc1 .LBB4_11
; %bb.12:                               ; %_ZL21exact_solution_kerneldddPd.exit215.preheader
	v_add_f64 v[48:49], -v[20:21], 1.0
	v_add_f64 v[50:51], -v[18:19], 1.0
	v_add_f64 v[52:53], -v[22:23], 1.0
	v_mov_b32_e32 v54, v17
	s_mul_i32 s33, s6, s5
	s_mov_b64 s[36:37], 0
	s_mul_i32 s33, s33, s4
.LBB4_13:                               ; %_ZL21exact_solution_kerneldddPd.exit215
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s36, 1
	s_cselect_b32 vcc_lo, -1, 0
	v_dual_cndmask_b32 v55, v12, v14 :: v_dual_cndmask_b32 v56, v2, v4
	s_and_b32 s0, vcc_lo, exec_lo
	v_dual_cndmask_b32 v57, v1, v3 :: v_dual_cndmask_b32 v62, v11, v13
	s_cselect_b32 s1, s26, s24
	s_cselect_b32 s2, s27, s25
	s_cselect_b32 s3, s16, s12
	s_cselect_b32 s11, s17, s13
	s_cmp_eq_u32 s36, 2
	v_cndmask_b32_e32 v61, v28, v30, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s38, s0, exec_lo
	v_cndmask_b32_e64 v56, v56, v6, s0
	v_cndmask_b32_e64 v57, v57, v5, s0
	s_cselect_b32 s2, s29, s2
	s_cselect_b32 s38, s28, s1
	s_cselect_b32 s11, s19, s11
	s_cselect_b32 s3, s18, s3
	s_cmp_eq_u32 s36, 3
	v_cndmask_b32_e64 v55, v55, v16, s0
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v61, v61, v32, s0
	s_and_b32 s39, s1, exec_lo
	v_cndmask_b32_e64 v58, v56, v8, s1
	v_cndmask_b32_e64 v57, v57, v7, s1
	s_cselect_b32 s40, s30, s38
	s_cselect_b32 s41, s31, s2
	s_cselect_b32 s3, s20, s3
	s_cselect_b32 s11, s21, s11
	s_cmp_eq_u32 s36, 4
	v_cndmask_b32_e64 v55, v55, v25, s1
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e64 v62, v62, v15, s0
	v_cndmask_b32_e64 v58, v58, v10, s2
	v_cndmask_b32_e64 v57, v57, v9, s2
	s_and_b32 s38, s2, exec_lo
	s_cselect_b32 s39, s23, s11
	s_cselect_b32 s38, s22, s3
	v_cndmask_b32_e64 v56, v55, v27, s2
	v_mul_f64 v[59:60], v[48:49], s[38:39]
	v_mul_f64 v[57:58], v[50:51], v[57:58]
	v_cndmask_b32_e32 v55, v29, v31, vcc_lo
	v_cndmask_b32_e64 v61, v61, v34, s1
	v_cndmask_b32_e64 v63, v62, v24, s1
	s_cselect_b32 s39, s35, s41
	s_cselect_b32 s38, s34, s40
	v_cndmask_b32_e64 v55, v55, v33, s0
	v_cndmask_b32_e64 v61, v61, v36, s2
	s_add_u32 s36, s36, 1
	s_addc_u32 s37, s37, 0
	s_cmp_lg_u32 s36, 5
	v_cndmask_b32_e64 v55, v55, v35, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v62, v55, v37, s2
	v_cndmask_b32_e64 v55, v63, v26, s2
	v_mul_f64 v[61:62], v[52:53], v[61:62]
	v_fma_f64 v[59:60], v[20:21], s[38:39], v[59:60]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[55:56], v[18:19], v[55:56], v[57:58]
	v_dual_cndmask_b32 v58, v38, v40 :: v_dual_cndmask_b32 v57, v39, v41
	v_cndmask_b32_e64 v58, v58, v42, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v57, v57, v43, s0
	v_cndmask_b32_e64 v63, v58, v44, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v57, v57, v45, s1
	v_cndmask_b32_e64 v58, v57, v47, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v57, v63, v46, s2
	v_fma_f64 v[57:58], v[22:23], v[57:58], v[61:62]
	v_add_f64 v[61:62], v[59:60], v[55:56]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[61:62], v[57:58], v[61:62]
	v_fma_f64 v[61:62], -v[59:60], v[55:56], v[61:62]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[61:62], -v[59:60], v[57:58], v[61:62]
	v_mul_f64 v[59:60], v[59:60], v[55:56]
	v_fma_f64 v[55:56], -v[55:56], v[57:58], v[61:62]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[56:57], v[57:58], v[59:60], v[55:56]
	v_ashrrev_i32_e32 v55, 31, v54
	v_lshlrev_b64 v[58:59], 3, v[54:55]
	v_add_nc_u32_e32 v54, s33, v54
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v58, vcc_lo, s8, v58
	v_add_co_ci_u32_e32 v59, vcc_lo, s9, v59, vcc_lo
	global_store_b64 v[58:59], v[56:57], off
	s_cbranch_scc1 .LBB4_13
; %bb.14:
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_19
; %bb.15:                               ; %.preheader264.preheader
	s_mov_b64 s[2:3], 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ce@rel32@lo+4
	s_addc_u32 s1, s1, ce@rel32@hi+12
                                        ; implicit-def: $sgpr16_sgpr17
.LBB4_16:                               ; %.preheader264
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[26:27], s[0:1], 0x118
	s_load_b64 s[28:29], s[0:1], 0x190
	s_load_b64 s[30:31], s[0:1], 0xa0
	s_load_b64 s[34:35], s[0:1], 0xc8
	s_load_b64 s[36:37], s[0:1], 0x140
	s_load_b64 s[38:39], s[0:1], 0x1b8
	s_load_b64 s[40:41], s[0:1], 0xf0
	s_load_b64 s[42:43], s[0:1], 0x168
	s_cmp_eq_u32 s2, 4
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], s[28:29], 0, s[26:27]
	v_fma_f64 v[3:4], v[18:19], s[38:39], s[36:37]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[1:2], v[1:2], 0, s[30:31]
	s_clause 0x4
	s_load_b64 s[26:27], s[0:1], 0x1e0
	s_load_b64 s[28:29], s[0:1], 0x28
	s_load_b64 s[30:31], s[0:1], 0x0
	s_load_b64 s[36:37], s[0:1], 0x50
	s_load_b64 s[38:39], s[0:1], 0x78
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[34:35]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[5:6], v[22:23], s[26:27], s[42:43]
	v_fma_f64 v[1:2], v[1:2], 0, s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[36:37]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[1:2], v[1:2], 0, s[30:31]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[18:19], v[3:4], v[1:2]
	v_fma_f64 v[1:2], v[22:23], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v2
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cselect_b32 s25, s11, s25
	s_cselect_b32 s24, s13, s24
	s_cmp_eq_u32 s2, 3
	s_cselect_b32 s23, s11, s23
	s_cselect_b32 s22, s13, s22
	s_cmp_eq_u32 s2, 2
	s_cselect_b32 s21, s11, s21
	s_cselect_b32 s20, s13, s20
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 s19, s11, s19
	s_cselect_b32 s18, s13, s18
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s17, s11, s17
	s_cselect_b32 s16, s13, s16
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s2, 5
	s_cbranch_scc1 .LBB4_16
; %bb.17:                               ; %_ZL21exact_solution_kerneldddPd.exit218.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b64 s[0:1], 0
.LBB4_18:                               ; %_ZL21exact_solution_kerneldddPd.exit218
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 s2, s18, s16
	s_cselect_b32 s3, s19, s17
	s_cmp_eq_u32 s0, 2
	s_cselect_b32 s3, s21, s3
	s_cselect_b32 s2, s20, s2
	s_cmp_eq_u32 s0, 3
	s_cselect_b32 s2, s22, s2
	s_cselect_b32 s3, s23, s3
	s_cmp_eq_u32 s0, 4
	s_cselect_b32 s13, s25, s3
	s_cselect_b32 s2, s24, s2
	s_ashr_i32 s11, s10, 31
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s13
	s_lshl_b64 s[2:3], s[10:11], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s2, s8, s2
	s_addc_u32 s3, s9, s3
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_add_i32 s10, s10, s33
	s_cmp_lg_u32 s0, 5
	global_store_b64 v1, v[2:3], s[2:3]
	s_cbranch_scc1 .LBB4_18
.LBB4_19:                               ; %Flow665
	s_or_b32 exec_lo, exec_lo, s12
	v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s17
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	v_dual_mov_b32 v5, s20 :: v_dual_mov_b32 v6, s21
	v_dual_mov_b32 v7, s22 :: v_dual_mov_b32 v8, s23
	v_dual_mov_b32 v9, s24 :: v_dual_mov_b32 v10, s25
	s_add_i32 s0, s4, -1
	s_mov_b32 s10, exec_lo
	v_dual_mov_b32 v11, s26 :: v_dual_mov_b32 v12, s27
	v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v14, s29
	v_dual_mov_b32 v15, s30 :: v_dual_mov_b32 v16, s31
	v_cmpx_eq_u32_e64 s0, v0
	s_cbranch_execz .LBB4_25
; %bb.20:                               ; %.preheader262.preheader
	s_mov_b64 s[2:3], 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ce@rel32@lo+4
	s_addc_u32 s1, s1, ce@rel32@hi+12
.LBB4_21:                               ; %.preheader262
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[12:13], s[0:1], 0x118
	s_load_b64 s[26:27], s[0:1], 0x190
	s_load_b64 s[28:29], s[0:1], 0xa0
	s_load_b64 s[30:31], s[0:1], 0xc8
	s_load_b64 s[34:35], s[0:1], 0x140
	s_load_b64 s[36:37], s[0:1], 0x1b8
	s_load_b64 s[38:39], s[0:1], 0xf0
	s_load_b64 s[40:41], s[0:1], 0x168
	s_cmp_eq_u32 s2, 4
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], s[12:13], s[26:27]
	v_fma_f64 v[3:4], v[18:19], s[36:37], s[34:35]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[1:2], s[28:29], v[1:2]
	s_clause 0x4
	s_load_b64 s[12:13], s[0:1], 0x1e0
	s_load_b64 s[26:27], s[0:1], 0x28
	s_load_b64 s[28:29], s[0:1], 0x0
	s_load_b64 s[34:35], s[0:1], 0x50
	s_load_b64 s[36:37], s[0:1], 0x78
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[30:31]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[5:6], v[22:23], s[12:13], s[40:41]
	v_add_f64 v[1:2], s[26:27], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[18:19], v[3:4], s[34:35]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[1:2], s[28:29], v[1:2]
	v_fma_f64 v[5:6], v[22:23], v[5:6], s[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[18:19], v[3:4], v[1:2]
	v_fma_f64 v[1:2], v[22:23], v[5:6], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s11, v2
	v_readfirstlane_b32 s12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cselect_b32 s25, s11, s25
	s_cselect_b32 s24, s12, s24
	s_cmp_eq_u32 s2, 3
	s_cselect_b32 s23, s11, s23
	s_cselect_b32 s22, s12, s22
	s_cmp_eq_u32 s2, 2
	s_cselect_b32 s21, s11, s21
	s_cselect_b32 s20, s12, s20
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 s19, s11, s19
	s_cselect_b32 s18, s12, s18
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s17, s11, s17
	s_cselect_b32 s16, s12, s16
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s2, 5
	s_cbranch_scc1 .LBB4_21
; %bb.22:                               ; %_ZL21exact_solution_kerneldddPd.exit221.preheader
	v_mov_b32_e32 v1, v17
	s_mov_b64 s[0:1], 0
.LBB4_23:                               ; %_ZL21exact_solution_kerneldddPd.exit221
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 s2, s18, s16
	s_cselect_b32 s3, s19, s17
	s_cmp_eq_u32 s0, 2
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	s_cselect_b32 s3, s21, s3
	s_cselect_b32 s2, s20, s2
	s_cmp_eq_u32 s0, 3
	s_cselect_b32 s2, s22, s2
	s_cselect_b32 s3, s23, s3
	s_cmp_eq_u32 s0, 4
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_cselect_b32 s2, s24, s2
	s_cselect_b32 s3, s25, s3
	v_dual_mov_b32 v4, s2 :: v_dual_add_nc_u32 v1, s33, v1
	v_mov_b32_e32 v5, s3
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 5
	global_store_b64 v[2:3], v[4:5], off
	s_cbranch_scc1 .LBB4_23
; %bb.24:                               ; %Flow662
	v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s17
	v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
	v_dual_mov_b32 v5, s20 :: v_dual_mov_b32 v6, s21
	v_dual_mov_b32 v7, s22 :: v_dual_mov_b32 v8, s23
	v_dual_mov_b32 v9, s24 :: v_dual_mov_b32 v10, s25
	v_dual_mov_b32 v11, s26 :: v_dual_mov_b32 v12, s27
	v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v14, s29
	v_dual_mov_b32 v15, s30 :: v_dual_mov_b32 v16, s31
.LBB4_25:                               ; %Flow663
	s_or_b32 exec_lo, exec_lo, s10
	s_cmp_lg_u32 s15, 0
	s_cbranch_scc1 .LBB4_30
; %bb.26:                               ; %.preheader260.preheader
	s_mov_b64 s[12:13], 0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, ce@rel32@lo+4
	s_addc_u32 s11, s11, ce@rel32@hi+12
.LBB4_27:                               ; %.preheader260
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[10:11], 0x118
	s_load_b64 s[2:3], s[10:11], 0x190
	s_load_b64 s[16:17], s[10:11], 0xa0
	s_load_b64 s[18:19], s[10:11], 0xc8
	s_load_b64 s[20:21], s[10:11], 0x140
	s_load_b64 s[22:23], s[10:11], 0x1b8
	s_load_b64 s[24:25], s[10:11], 0xf0
	s_load_b64 s[26:27], s[10:11], 0x168
	s_cmp_eq_u32 s12, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s12, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[11:12], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[13:14], s[22:23], 0, s[20:21]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_clause 0x4
	s_load_b64 s[0:1], s[10:11], 0x1e0
	s_load_b64 s[2:3], s[10:11], 0x28
	s_load_b64 s[16:17], s[10:11], 0x0
	s_load_b64 s[20:21], s[10:11], 0x50
	s_load_b64 s[22:23], s[10:11], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], 0, s[18:19]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[15:16], v[22:23], s[0:1], s[26:27]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s12, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s12, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s12, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[13:14], v[13:14], 0, s[20:21]
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s12, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[24:25]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[22:23]
	v_fma_f64 v[11:12], v[13:14], 0, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[22:23], v[15:16], v[11:12]
	v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v9, v9, v11
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v12, s1
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_cndmask_b32_e64 v4, v4, v12, s2
	v_cndmask_b32_e64 v3, v3, v11, s2
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB4_27
; %bb.28:                               ; %_ZL21exact_solution_kerneldddPd.exit224.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s7, s4, v[0:1]
	s_mov_b64 s[2:3], 0
.LBB4_29:                               ; %_ZL21exact_solution_kerneldddPd.exit224
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 1
	v_ashrrev_i32_e32 v12, 31, v11
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[12:13], 3, v[11:12]
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v6, s0
	v_cndmask_b32_e64 v15, v15, v5, s0
	s_cselect_b32 vcc_lo, -1, 0
	v_add_nc_u32_e32 v11, s33, v11
	v_add_co_u32 v12, s0, s8, v12
	v_cndmask_b32_e32 v14, v14, v8, vcc_lo
	v_cndmask_b32_e32 v16, v15, v7, vcc_lo
	s_cmp_eq_u32 s2, 4
	v_add_co_ci_u32_e64 v13, vcc_lo, s9, v13, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_dual_cndmask_b32 v15, v14, v10 :: v_dual_cndmask_b32 v14, v16, v9
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[12:13], v[14:15], off
	s_cbranch_scc1 .LBB4_29
.LBB4_30:                               ; %.loopexit259
	s_add_i32 s0, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s15, s0
	s_cbranch_scc1 .LBB4_35
; %bb.31:                               ; %.preheader258.preheader
	s_mov_b64 s[12:13], 0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, ce@rel32@lo+4
	s_addc_u32 s11, s11, ce@rel32@hi+12
.LBB4_32:                               ; %.preheader258
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[10:11], 0x118
	s_load_b64 s[2:3], s[10:11], 0x190
	s_load_b64 s[16:17], s[10:11], 0xa0
	s_load_b64 s[18:19], s[10:11], 0xc8
	s_load_b64 s[20:21], s[10:11], 0x140
	s_load_b64 s[22:23], s[10:11], 0x1b8
	s_load_b64 s[24:25], s[10:11], 0xf0
	s_load_b64 s[26:27], s[10:11], 0x168
	s_cmp_eq_u32 s12, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s12, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[11:12], v[20:21], s[2:3], s[0:1]
	v_add_f64 v[13:14], s[20:21], s[22:23]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_clause 0x4
	s_load_b64 s[0:1], s[10:11], 0x1e0
	s_load_b64 s[2:3], s[10:11], 0x28
	s_load_b64 s[16:17], s[10:11], 0x0
	s_load_b64 s[20:21], s[10:11], 0x50
	s_load_b64 s[22:23], s[10:11], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[13:14], s[18:19], v[13:14]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[15:16], v[22:23], s[0:1], s[26:27]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s12, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s12, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s12, 0
	s_cselect_b32 s3, -1, 0
	v_add_f64 v[13:14], s[20:21], v[13:14]
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s12, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[24:25]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[22:23], v[15:16], s[22:23]
	v_add_f64 v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[22:23], v[15:16], v[11:12]
	v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v9, v9, v11
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v12, s1
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_cndmask_b32_e64 v4, v4, v12, s2
	v_cndmask_b32_e64 v3, v3, v11, s2
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB4_32
; %bb.33:                               ; %_ZL21exact_solution_kerneldddPd.exit227.preheader
	v_mov_b32_e32 v11, v17
	s_mov_b64 s[2:3], 0
.LBB4_34:                               ; %_ZL21exact_solution_kerneldddPd.exit227
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 1
	v_ashrrev_i32_e32 v12, 31, v11
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[12:13], 3, v[11:12]
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v6, s0
	v_cndmask_b32_e64 v15, v15, v5, s0
	s_cselect_b32 vcc_lo, -1, 0
	v_add_nc_u32_e32 v11, s33, v11
	v_add_co_u32 v12, s0, s8, v12
	v_cndmask_b32_e32 v14, v14, v8, vcc_lo
	v_cndmask_b32_e32 v16, v15, v7, vcc_lo
	s_cmp_eq_u32 s2, 4
	v_add_co_ci_u32_e64 v13, vcc_lo, s9, v13, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_dual_cndmask_b32 v15, v14, v10 :: v_dual_cndmask_b32 v14, v16, v9
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[12:13], v[14:15], off
	s_cbranch_scc1 .LBB4_34
.LBB4_35:                               ; %.loopexit257
	s_cmp_lg_u32 s14, 0
	s_cbranch_scc1 .LBB4_40
; %bb.36:                               ; %.preheader256.preheader
	s_mov_b64 s[12:13], 0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, ce@rel32@lo+4
	s_addc_u32 s11, s11, ce@rel32@hi+12
.LBB4_37:                               ; %.preheader256
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[10:11], 0x118
	s_load_b64 s[2:3], s[10:11], 0x190
	s_load_b64 s[16:17], s[10:11], 0xa0
	s_load_b64 s[18:19], s[10:11], 0xc8
	s_load_b64 s[20:21], s[10:11], 0x140
	s_load_b64 s[22:23], s[10:11], 0x1b8
	s_load_b64 s[24:25], s[10:11], 0xf0
	s_load_b64 s[26:27], s[10:11], 0x168
	s_cmp_eq_u32 s12, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s12, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[11:12], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[13:14], v[18:19], s[22:23], s[20:21]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_clause 0x4
	s_load_b64 s[0:1], s[10:11], 0x1e0
	s_load_b64 s[2:3], s[10:11], 0x28
	s_load_b64 s[16:17], s[10:11], 0x0
	s_load_b64 s[20:21], s[10:11], 0x50
	s_load_b64 s[22:23], s[10:11], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[18:19], v[13:14], s[18:19]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[15:16], s[0:1], 0, s[26:27]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s12, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s12, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s12, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[13:14], v[18:19], v[13:14], s[20:21]
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s12, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[15:16], 0, s[24:25]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[15:16], 0, s[22:23]
	v_fma_f64 v[11:12], v[18:19], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], 0, v[11:12]
	v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v9, v9, v11
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v12, s1
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_cndmask_b32_e64 v4, v4, v12, s2
	v_cndmask_b32_e64 v3, v3, v11, s2
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB4_37
; %bb.38:                               ; %_ZL21exact_solution_kerneldddPd.exit230.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, s15, s4, v[0:1]
	s_mov_b64 s[2:3], 0
.LBB4_39:                               ; %_ZL21exact_solution_kerneldddPd.exit230
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 1
	v_ashrrev_i32_e32 v12, 31, v11
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_cndmask_b32_e32 v0, v2, v4, vcc_lo
	v_cndmask_b32_e32 v14, v1, v3, vcc_lo
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[12:13], 3, v[11:12]
	v_add_nc_u32_e32 v11, s33, v11
	v_cndmask_b32_e64 v0, v0, v6, s0
	v_cndmask_b32_e64 v14, v14, v5, s0
	s_cmp_eq_u32 s2, 3
	s_cselect_b32 vcc_lo, -1, 0
	v_add_co_u32 v12, s0, s8, v12
	v_cndmask_b32_e32 v0, v0, v8, vcc_lo
	v_cndmask_b32_e32 v14, v14, v7, vcc_lo
	s_cmp_eq_u32 s2, 4
	v_add_co_ci_u32_e64 v13, vcc_lo, s9, v13, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_dual_cndmask_b32 v15, v0, v10 :: v_dual_cndmask_b32 v14, v14, v9
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[12:13], v[14:15], off
	s_cbranch_scc1 .LBB4_39
.LBB4_40:                               ; %.loopexit255
	s_add_i32 s0, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s14, s0
	s_cbranch_scc1 .LBB4_45
; %bb.41:                               ; %.preheader.preheader
	s_mov_b64 s[6:7], 0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, ce@rel32@lo+4
	s_addc_u32 s5, s5, ce@rel32@hi+12
.LBB4_42:                               ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x7
	s_load_b64 s[0:1], s[4:5], 0x118
	s_load_b64 s[2:3], s[4:5], 0x190
	s_load_b64 s[10:11], s[4:5], 0xa0
	s_load_b64 s[12:13], s[4:5], 0xc8
	s_load_b64 s[14:15], s[4:5], 0x140
	s_load_b64 s[16:17], s[4:5], 0x1b8
	s_load_b64 s[18:19], s[4:5], 0xf0
	s_load_b64 s[20:21], s[4:5], 0x168
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 3
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[11:12], v[20:21], s[2:3], s[0:1]
	v_fma_f64 v[13:14], v[18:19], s[16:17], s[14:15]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[10:11]
	s_clause 0x4
	s_load_b64 s[0:1], s[4:5], 0x1e0
	s_load_b64 s[2:3], s[4:5], 0x28
	s_load_b64 s[10:11], s[4:5], 0x0
	s_load_b64 s[14:15], s[4:5], 0x50
	s_load_b64 s[16:17], s[4:5], 0x78
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[13:14], v[18:19], v[13:14], s[12:13]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[15:16], s[20:21], s[0:1]
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 2
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[2:3]
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	v_fma_f64 v[13:14], v[18:19], v[13:14], s[14:15]
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s6, 5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], s[18:19], v[15:16]
	v_fma_f64 v[11:12], v[20:21], v[11:12], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], s[16:17], v[15:16]
	v_fma_f64 v[11:12], v[18:19], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[15:16], v[11:12]
	v_dual_cndmask_b32 v10, v10, v12 :: v_dual_cndmask_b32 v9, v9, v11
	v_cndmask_b32_e64 v8, v8, v12, s0
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v12, s1
	v_cndmask_b32_e64 v5, v5, v11, s1
	v_cndmask_b32_e64 v4, v4, v12, s2
	v_cndmask_b32_e64 v3, v3, v11, s2
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB4_42
; %bb.43:                               ; %_ZL21exact_solution_kerneldddPd.exit233.preheader
	s_mov_b64 s[2:3], 0
.LBB4_44:                               ; %_ZL21exact_solution_kerneldddPd.exit233
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 1
	v_ashrrev_i32_e32 v18, 31, v17
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v13, v1, v3
	s_cselect_b32 s0, -1, 0
	v_lshlrev_b64 v[11:12], 3, v[17:18]
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v0, v0, v6, s0
	v_cndmask_b32_e64 v13, v13, v5, s0
	s_cselect_b32 vcc_lo, -1, 0
	v_add_nc_u32_e32 v17, s33, v17
	v_add_co_u32 v11, s0, s8, v11
	v_dual_cndmask_b32 v0, v0, v8 :: v_dual_cndmask_b32 v13, v13, v7
	s_cmp_eq_u32 s2, 4
	v_add_co_ci_u32_e64 v12, vcc_lo, s9, v12, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s2, s2, 1
	v_dual_cndmask_b32 v14, v0, v10 :: v_dual_cndmask_b32 v13, v13, v9
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[11:12], v[13:14], off
	s_cbranch_scc1 .LBB4_44
.LBB4_45:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL17initialize_kernelPdiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 64
		.amdhsa_next_free_sgpr 54
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL17initialize_kernelPdiii,"axG",@progbits,_ZL17initialize_kernelPdiii,comdat
.Lfunc_end4:
	.size	_ZL17initialize_kernelPdiii, .Lfunc_end4-_ZL17initialize_kernelPdiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6720
; NumSgprs: 56
; NumVgprs: 64
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 7
; NumSGPRsForWavesPerEU: 56
; NumVGPRsForWavesPerEU: 64
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,"axG",@progbits,_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,comdat
	.globl	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii ; -- Begin function _ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
	.p2align	8
	.type	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,@function
_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii: ; @_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x40
	s_load_b512 s[16:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s15, s5
	s_add_i32 s0, s15, s6
	s_add_i32 s2, s2, s14
	s_mul_i32 s1, s0, s5
	v_mad_u64_u32 v[1:2], null, s2, s4, v[0:1]
	s_add_i32 s1, s1, s14
	s_add_i32 s0, s0, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s30, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s31, v2, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], 1.0
	v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[3:4], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	v_add_co_u32 v7, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v2, vcc_lo
	v_div_fixup_f64 v[3:4], v[5:6], v[3:4], 1.0
	v_mad_u64_u32 v[5:6], null, s1, s4, v[0:1]
	s_mul_i32 s1, s0, s5
	s_add_i32 s0, s0, s6
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, s1, s4, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_mul_i32 s1, s0, s5
	s_add_i32 s0, s0, s6
	s_add_i32 s1, s1, s14
	s_mul_i32 s0, s0, s5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	s_add_i32 s0, s0, s14
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s30, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s31, v6, vcc_lo
	v_add_co_u32 v11, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v12, vcc_lo, s19, v2, vcc_lo
	v_add_co_u32 v9, vcc_lo, s30, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s31, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s20, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v2, vcc_lo
	global_store_b64 v[7:8], v[3:4], off
	global_load_b64 v[7:8], v[5:6], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[7:8], v[3:4], v[7:8]
	global_store_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[9:10], off
	v_mad_u64_u32 v[11:12], null, s1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s30, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s31, v12, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[7:8], v[3:4], v[7:8]
	global_store_b64 v[13:14], v[7:8], off
	global_load_b64 v[7:8], v[11:12], off
	v_add_co_u32 v13, vcc_lo, s22, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s23, v2, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[7:8], v[3:4], v[7:8]
	global_store_b64 v[13:14], v[7:8], off
	s_clause 0x2
	global_load_b64 v[7:8], v[9:10], off
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[9:10], v[11:12], off
	v_mad_u64_u32 v[11:12], null, s0, s4, v[0:1]
	v_add_co_u32 v13, vcc_lo, s28, v1
	v_add_co_ci_u32_e32 v14, vcc_lo, s29, v2, vcc_lo
	v_add_co_u32 v15, vcc_lo, s26, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v12, 31, v11
	v_add_co_ci_u32_e32 v16, vcc_lo, s27, v2, vcc_lo
	s_mov_b32 s0, 0x1eb851eb
	s_mov_b32 s1, 0x3fe1eb85
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s30, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s31, v12, vcc_lo
	s_waitcnt vmcnt(2)
	v_mul_f64 v[7:8], v[7:8], v[7:8]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[5:6], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[5:6], v[5:6], 0.5
	v_mul_f64 v[7:8], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[9:10], v[3:4], v[7:8]
	global_store_b64 v[13:14], v[7:8], off
	global_store_b64 v[15:16], v[9:10], off
	global_load_b64 v[7:8], v[11:12], off
	v_mul_f64 v[9:10], v[3:4], s[0:1]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], -v[3:4], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[9:10], v[3:4]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 8, v0
	v_ldexp_f64 v[3:4], v[3:4], v0
	v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[5:6], v[3:4]
	v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[7:8], v[3:4], v[5:6]
	v_mul_f64 v[5:6], v[5:6], 0.5
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[5:6], v[5:6], v[9:10], v[5:6]
	v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[9:10], v[5:6], v[7:8]
	v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[9:10], v[5:6], v[7:8]
	v_ldexp_f64 v[5:6], v[5:6], v0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v4, v6, v4
	v_add_co_u32 v0, vcc_lo, s24, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v2, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 76
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,"axG",@progbits,_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii,comdat
.Lfunc_end5:
	.size	_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii, .Lfunc_end5-_ZL20compute_rhs_kernel_1PdS_S_S_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 932
; NumSgprs: 34
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,"axG",@progbits,_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,comdat
	.globl	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii ; -- Begin function _ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
	.p2align	8
	.type	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,@function
_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii: ; @_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x48
	s_load_b512 s[16:31], s[0:1], 0x0
	s_mov_b64 s[6:7], 0
                                        ; implicit-def: $vgpr1_vgpr2
	v_mov_b32_e32 v46, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s35, s15, s9
	s_mul_i32 s33, s10, s9
	s_add_i32 s36, s14, s35
	s_mul_i32 s33, s33, s8
	s_mul_i32 s11, s8, s36
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, s11, v0
	v_mov_b32_e32 v11, v13
.LBB6_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	s_cmp_eq_u32 s6, 4
	v_lshlrev_b64 v[14:15], 3, v[11:12]
	v_add_nc_u32_e32 v11, s33, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, s30, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s31, v15, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s2, -1, 0
	global_load_b64 v[14:15], v[14:15], off
	s_cmp_eq_u32 s6, 2
	s_cselect_b32 s3, -1, 0
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 s4, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s5, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 5
	s_waitcnt vmcnt(0)
	v_dual_cndmask_b32 v10, v10, v15 :: v_dual_cndmask_b32 v9, v9, v14
	v_cndmask_b32_e64 v8, v8, v15, s2
	v_cndmask_b32_e64 v7, v7, v14, s2
	v_cndmask_b32_e64 v6, v6, v15, s3
	v_cndmask_b32_e64 v5, v5, v14, s3
	v_cndmask_b32_e64 v4, v4, v15, s4
	v_cndmask_b32_e64 v3, v3, v14, s4
	v_cndmask_b32_e64 v2, v2, v15, s5
	v_cndmask_b32_e64 v1, v1, v14, s5
	s_cbranch_scc1 .LBB6_1
; %bb.2:
	s_cmp_lt_i32 s15, 1
	s_cbranch_scc1 .LBB6_98
; %bb.3:
	s_add_i32 s2, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_ge_i32 s15, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_lt_i32 s14, 1
	s_cselect_b32 s3, -1, 0
	s_or_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB6_98
; %bb.4:
	s_add_i32 s2, s9, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s14, s2
	s_cselect_b32 s3, -1, 0
	s_add_i32 s2, s8, -1
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_ne_u32_e64 s2, 0, v0
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s30, s2
	s_cbranch_execz .LBB6_97
; %bb.5:
	v_mad_u64_u32 v[11:12], null, s14, s8, v[0:1]
	s_mul_i32 s34, s9, s8
	s_load_b64 s[4:5], s[0:1], 0x40
	s_mul_i32 s39, s34, s15
	s_add_i32 s0, s15, s10
	s_mul_i32 s31, s10, 3
	s_mul_i32 s38, s0, s9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v14, s39, v11
	s_add_i32 s0, s0, s31
	s_add_i32 s1, s38, s14
	s_mul_i32 s40, s0, s9
	s_mul_i32 s1, s1, s8
	s_add_i32 s2, s40, s14
	v_add_nc_u32_e32 v16, 1, v14
	s_mul_i32 s2, s2, s8
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v22, s2, v0
	s_ashr_i32 s3, s1, 31
	v_ashrrev_i32_e32 v17, 31, v16
	s_lshl_b32 s37, s10, 1
	v_lshlrev_b64 v[18:19], 3, v[14:15]
	v_ashrrev_i32_e32 v23, 31, v22
	v_add_nc_u32_e32 v14, -1, v14
	v_lshlrev_b64 v[16:17], 3, v[16:17]
	s_sub_i32 s0, s0, s37
	s_mov_b32 s50, 0x55555555
	v_add_co_u32 v20, vcc_lo, s18, v18
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_ci_u32_e32 v21, vcc_lo, s19, v19, vcc_lo
	v_add_co_u32 v26, vcc_lo, s18, v16
	v_add_co_ci_u32_e32 v27, vcc_lo, s19, v17, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v22, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
	global_load_b64 v[34:35], v[20:21], off
	v_add_nc_u32_e32 v20, s1, v0
	v_add_co_u32 v24, s1, s1, v0
	global_load_b64 v[40:41], v[22:23], off
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_co_ci_u32_e64 v25, null, s3, 0, s1
	v_ashrrev_i32_e32 v21, 31, v20
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[36:37], 3, v[14:15]
	v_lshlrev_b64 v[14:15], 3, v[24:25]
	v_add_co_u32 v24, s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v25, null, s3, 0, s2
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_u32 v38, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v39, vcc_lo, s5, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 3, v[24:25]
	v_add_co_u32 v20, vcc_lo, s4, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	s_clause 0x1
	global_load_b64 v[42:43], v[38:39], off offset:8
	global_load_b64 v[44:45], v[20:21], off
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_add_co_u32 v20, vcc_lo, s20, v16
	v_add_co_ci_u32_e32 v21, vcc_lo, s21, v17, vcc_lo
	v_add_co_u32 v22, vcc_lo, s16, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, s17, v17, vcc_lo
	v_add_co_u32 v24, vcc_lo, s16, v18
	v_add_co_ci_u32_e32 v25, vcc_lo, s17, v19, vcc_lo
	v_add_co_u32 v28, vcc_lo, s20, v18
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v19, vcc_lo
	global_load_b64 v[47:48], v[14:15], off offset:8
	s_clause 0x1
	global_load_b64 v[49:50], v[22:23], off
	global_load_b64 v[51:52], v[24:25], off
	s_clause 0x1
	global_load_b64 v[53:54], v[20:21], off
	global_load_b64 v[24:25], v[28:29], off
	v_add_co_u32 v22, vcc_lo, s26, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, s27, v17, vcc_lo
	v_add_co_u32 v20, vcc_lo, s26, v36
	v_add_co_ci_u32_e32 v21, vcc_lo, s27, v37, vcc_lo
	global_load_b64 v[55:56], v[14:15], off offset:-8
	s_clause 0x1
	global_load_b64 v[57:58], v[22:23], off
	global_load_b64 v[59:60], v[20:21], off
	v_add_co_u32 v22, vcc_lo, s24, v16
	v_add_co_ci_u32_e32 v23, vcc_lo, s25, v17, vcc_lo
	v_add_co_u32 v28, vcc_lo, s24, v18
	v_add_co_ci_u32_e32 v29, vcc_lo, s25, v19, vcc_lo
	s_clause 0x1
	global_load_b64 v[61:62], v[22:23], off
	global_load_b64 v[63:64], v[28:29], off
	v_add_co_u32 v22, vcc_lo, s20, v36
	v_add_co_ci_u32_e32 v23, vcc_lo, s21, v37, vcc_lo
	s_ashr_i32 s1, s11, 31
	v_add_co_u32 v30, s2, s11, v0
	s_mul_i32 s42, s0, s9
	global_load_b64 v[65:66], v[22:23], off
	v_add_co_ci_u32_e64 v31, null, s1, 0, s2
	s_add_i32 s1, s42, s14
	s_add_i32 s41, s0, s10
	s_mul_i32 s1, s1, s8
	s_mul_i32 s41, s41, s9
	s_ashr_i32 s2, s1, 31
	v_add_co_u32 v14, s3, s1, v0
	v_add_nc_u32_e32 v20, s1, v0
	v_add_co_ci_u32_e64 v15, null, s2, 0, s3
	s_add_i32 s0, s41, s14
	v_lshlrev_b64 v[30:31], 3, v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	s_mul_i32 s0, s0, s8
	s_mov_b32 s51, 0x3ff55555
	s_ashr_i32 s1, s0, 31
	v_add_co_u32 v22, s2, s0, v0
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_ci_u32_e64 v23, null, s1, 0, s2
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_nc_u32_e32 v28, s0, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_add_co_u32 v20, vcc_lo, s4, v20
	v_lshlrev_b64 v[22:23], 3, v[22:23]
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
	v_ashrrev_i32_e32 v29, 31, v28
	v_add_co_u32 v32, vcc_lo, s24, v36
	v_add_co_ci_u32_e32 v33, vcc_lo, s25, v37, vcc_lo
	v_add_co_u32 v67, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v68, vcc_lo, s5, v23, vcc_lo
	v_lshlrev_b64 v[22:23], 3, v[28:29]
	v_add_co_u32 v28, vcc_lo, s16, v36
	v_add_co_ci_u32_e32 v29, vcc_lo, s17, v37, vcc_lo
	global_load_b64 v[69:70], v[32:33], off
	v_add_co_u32 v32, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v33, vcc_lo, s5, v23, vcc_lo
	global_load_b64 v[71:72], v[28:29], off
	s_clause 0x1
	global_load_b64 v[73:74], v[14:15], off offset:8
	global_load_b128 v[20:23], v[20:21], off offset:-8
	global_load_b64 v[75:76], v[26:27], off
	s_clause 0x1
	global_load_b64 v[67:68], v[67:68], off offset:8
	global_load_b128 v[26:29], v[32:33], off offset:-8
	v_ashrrev_i32_e32 v14, 31, v13
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dx5tx1@rel32@lo+4
	s_addc_u32 s3, s3, dx5tx1@rel32@hi+12
	s_mov_b32 s0, 0x9999999a
	s_load_b64 s[2:3], s[2:3], 0x0
	s_mov_b32 s1, 0x3fd99999
	v_lshlrev_b64 v[12:13], 3, v[13:14]
	v_add_co_u32 v14, vcc_lo, s4, v30
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v31, vcc_lo
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, xxcon3@rel32@lo+4
	s_addc_u32 s7, s7, xxcon3@rel32@hi+12
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v77, vcc_lo, s18, v36
	v_add_co_ci_u32_e32 v78, vcc_lo, s19, v37, vcc_lo
	s_clause 0x1
	global_load_b64 v[79:80], v[14:15], off offset:8
	global_load_b128 v[30:33], v[12:13], off offset:-8
	v_add_co_u32 v12, vcc_lo, s22, v16
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, s22, v18
	v_add_co_ci_u32_e32 v15, vcc_lo, s23, v19, vcc_lo
	global_load_b64 v[38:39], v[38:39], off offset:-8
	global_load_b64 v[77:78], v[77:78], off
	s_clause 0x1
	global_load_b64 v[81:82], v[12:13], off
	global_load_b64 v[16:17], v[14:15], off
	v_add_co_u32 v12, vcc_lo, s22, v36
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v37, vcc_lo
	s_load_b64 s[6:7], s[6:7], 0x0
	s_mov_b32 s43, 0
	global_load_b64 v[36:37], v[12:13], off
	s_waitcnt vmcnt(28)
	v_add_f64 v[14:15], v[34:35], v[34:35]
	s_waitcnt vmcnt(27)
	v_add_f64 v[18:19], v[40:41], v[40:41]
	s_waitcnt vmcnt(24)
	v_fma_f64 v[40:41], v[40:41], -2.0, v[47:48]
	s_waitcnt vmcnt(22)
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[12:13], v[18:19], v[51:52]
	s_waitcnt vmcnt(20)
	v_fma_f64 v[51:52], v[24:25], -2.0, v[53:54]
	s_waitcnt vmcnt(17)
	v_mul_f64 v[83:84], v[59:60], s[0:1]
	s_waitcnt vmcnt(15)
	v_fma_f64 v[53:54], v[63:64], -2.0, v[61:62]
	v_add_f64 v[61:62], v[47:48], -v[57:58]
	v_mul_f64 v[57:58], v[57:58], s[0:1]
	v_add_f64 v[40:41], v[55:56], v[40:41]
	v_fma_f64 v[49:50], v[47:48], v[49:50], -v[12:13]
	s_waitcnt vmcnt(14)
	v_add_f64 v[51:52], v[65:66], v[51:52]
	v_mul_f64 v[65:66], v[34:35], v[14:15]
	v_add_f64 v[61:62], v[61:62], -v[55:56]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[9:10], s[2:3], v[40:41], v[9:10]
	s_mov_b32 s2, 0x66666666
	s_mov_b32 s3, 0x3ff66666
	s_delay_alu instid0(SALU_CYCLE_1)
	v_fma_f64 v[47:48], v[47:48], s[2:3], -v[57:58]
	s_waitcnt vmcnt(13)
	v_add_f64 v[53:54], v[69:70], v[53:54]
	v_fma_f64 v[69:70], v[44:45], -2.0, v[42:43]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[40:41], v[55:56], v[71:72], v[49:50]
	s_waitcnt vmcnt(10)
	v_fma_f64 v[49:50], v[22:23], -2.0, v[73:74]
	s_waitcnt vmcnt(9)
	v_fma_f64 v[65:66], v[75:76], v[75:76], -v[65:66]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[71:72], v[28:29], -2.0, v[67:68]
	v_fma_f64 v[55:56], v[55:56], s[2:3], -v[83:84]
	v_fma_f64 v[34:35], v[34:35], -2.0, v[75:76]
	v_add_f64 v[59:60], v[61:62], v[59:60]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[79:80], v[32:33], -2.0, v[79:80]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[81:82], v[16:17], -2.0, v[81:82]
	v_fma_f64 v[9:10], s[6:7], v[53:54], v[9:10]
	v_add_f64 v[69:70], v[38:39], v[69:70]
	v_mul_f64 v[53:54], v[77:78], v[38:39]
	v_add_f64 v[49:50], v[20:21], v[49:50]
	v_fma_f64 v[65:66], v[77:78], v[77:78], v[65:66]
	v_add_f64 v[71:72], v[26:27], v[71:72]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, xxcon2@rel32@lo+4
	s_addc_u32 s7, s7, xxcon2@rel32@hi+12
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, dx2tx1@rel32@lo+4
	s_addc_u32 s13, s13, dx2tx1@rel32@hi+12
	s_getpc_b64 s[44:45]
	s_add_u32 s44, s44, dx3tx1@rel32@lo+4
	s_addc_u32 s45, s45, dx3tx1@rel32@hi+12
	s_getpc_b64 s[46:47]
	s_add_u32 s46, s46, dx4tx1@rel32@lo+4
	s_addc_u32 s47, s47, dx4tx1@rel32@hi+12
	s_getpc_b64 s[48:49]
	s_add_u32 s48, s48, xxcon4@rel32@lo+4
	s_addc_u32 s49, s49, xxcon4@rel32@hi+12
	s_load_b64 s[6:7], s[6:7], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	s_load_b64 s[44:45], s[44:45], 0x0
	s_load_b64 s[46:47], s[46:47], 0x0
	s_load_b64 s[48:49], s[48:49], 0x0
	v_add_f64 v[34:35], v[34:35], v[77:78]
	v_mul_f64 v[20:21], v[77:78], v[20:21]
	v_mul_f64 v[26:27], v[77:78], v[26:27]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dx1tx1@rel32@lo+4
	s_addc_u32 s3, s3, dx1tx1@rel32@hi+12
	v_add_f64 v[38:39], v[42:43], -v[38:39]
	s_load_b64 s[2:3], s[2:3], 0x0
	v_add_f64 v[30:31], v[30:31], v[79:80]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[61:62], s[6:7], s[50:51]
	s_waitcnt vmcnt(0)
	v_add_f64 v[36:37], v[36:37], v[81:82]
	v_fma_f64 v[3:4], s[12:13], v[69:70], v[3:4]
	v_fma_f64 v[53:54], v[75:76], v[42:43], -v[53:54]
	v_fma_f64 v[5:6], s[44:45], v[49:50], v[5:6]
	v_fma_f64 v[9:10], v[65:66], s[48:49], v[9:10]
	v_fma_f64 v[7:8], s[46:47], v[71:72], v[7:8]
	v_mul_f64 v[49:50], v[77:78], v[55:56]
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, xxcon5@rel32@lo+4
	s_addc_u32 s13, s13, xxcon5@rel32@hi+12
	s_load_b64 s[12:13], s[12:13], 0x0
	v_fma_f64 v[20:21], v[75:76], v[73:74], -v[20:21]
	v_fma_f64 v[26:27], v[75:76], v[67:68], -v[26:27]
	v_fma_f64 v[30:31], s[2:3], v[30:31], v[1:2]
	v_add_f64 v[1:2], v[32:33], v[32:33]
                                        ; implicit-def: $vgpr32_vgpr33
	v_fma_f64 v[3:4], v[34:35], v[61:62], v[3:4]
	v_fma_f64 v[34:35], v[59:60], s[0:1], v[53:54]
	v_fma_f64 v[5:6], s[6:7], v[51:52], v[5:6]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[51:52], s[12:13], v[40:41], v[9:10]
	v_fma_f64 v[42:43], s[6:7], v[36:37], v[7:8]
	v_fma_f64 v[47:48], v[75:76], v[47:48], -v[49:50]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, tx2@rel32@lo+4
	s_addc_u32 s1, s1, tx2@rel32@hi+12
	v_add_f64 v[7:8], v[44:45], v[44:45]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_f64 v[9:10], v[22:23], v[22:23]
	v_add_f64 v[22:23], v[63:64], v[63:64]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[36:37], -s[0:1], v[38:39], v[30:31]
                                        ; implicit-def: $vgpr30_vgpr31
	v_fma_f64 v[38:39], -s[0:1], v[34:35], v[3:4]
	v_add_f64 v[3:4], v[24:25], v[24:25]
	v_fma_f64 v[40:41], -s[0:1], v[20:21], v[5:6]
	v_add_f64 v[20:21], v[28:29], v[28:29]
	v_add_f64 v[5:6], v[16:17], v[16:17]
	v_fma_f64 v[42:43], -s[0:1], v[26:27], v[42:43]
	v_fma_f64 v[44:45], -s[0:1], v[47:48], v[51:52]
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr26_vgpr27
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 1, v0
	s_xor_b32 s44, exec_lo, s1
	s_cbranch_execz .LBB6_11
; %bb.6:                                ; %LeafBlock2368
	s_mov_b32 s0, -1
	s_mov_b32 s45, exec_lo
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
	v_cmpx_eq_u32_e32 2, v0
	s_cbranch_execz .LBB6_10
; %bb.7:                                ; %.preheader1742.preheader
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	s_mov_b64 s[6:7], 0
	s_mov_b32 s12, s11
.LBB6_8:                                ; %.preheader1742
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v47, v27, v33, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v47, v47, v31, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s13, s12, 31
	v_cndmask_b32_e64 v51, v47, v29, s1
	v_add_co_u32 v47, s3, s12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v48, null, s13, 0, s3
	s_lshl_b64 s[46:47], s[12:13], 3
	s_add_u32 s46, s4, s46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	s_addc_u32 s47, s5, s47
	s_cmp_eq_u32 s6, 0
	v_add_co_u32 v47, s3, s4, v47
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v48, s3, s5, v48, s3
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	global_load_b64 v[49:50], v[47:48], off offset:-8
	s_clause 0x1
	s_load_b64 s[48:49], s[46:47], 0x20
	s_load_b64 s[46:47], s[46:47], 0x10
	global_load_b64 v[47:48], v[47:48], off offset:8
	s_add_i32 s12, s12, s33
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(1)
	v_mul_f64 v[49:50], v[49:50], -4.0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[49:50], 0x40180000, s[46:47], v[49:50]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[47:48], v[47:48], -4.0, v[49:50]
	v_cndmask_b32_e32 v49, v26, v32, vcc_lo
	v_cndmask_b32_e64 v50, v51, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v30, s0
	v_cndmask_b32_e64 v49, v49, v28, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v34, s2
	v_add_f64 v[47:48], s[48:49], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v32, v32, v47, vcc_lo
	v_cndmask_b32_e64 v27, v27, v48, s3
	v_cndmask_b32_e64 v26, v26, v47, s3
	v_cndmask_b32_e32 v33, v33, v48, vcc_lo
	v_cndmask_b32_e64 v31, v31, v48, s0
	v_cndmask_b32_e64 v30, v30, v47, s0
	v_cndmask_b32_e64 v29, v29, v48, s1
	v_cndmask_b32_e64 v28, v28, v47, s1
	v_cndmask_b32_e64 v35, v35, v48, s2
	v_cndmask_b32_e64 v34, v34, v47, s2
	s_cbranch_scc0 .LBB6_8
; %bb.9:                                ; %Flow2412
	s_xor_b32 s0, exec_lo, -1
.LBB6_10:                               ; %Flow2423
	s_or_b32 exec_lo, exec_lo, s45
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
.LBB6_11:                               ; %Flow2422
	s_and_not1_saveexec_b32 s1, s44
; %bb.12:                               ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	s_and_not1_b32 s0, s0, exec_lo
	s_mov_b32 s43, exec_lo
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
	s_and_b32 s2, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s2
; %bb.13:                               ; %Flow2424
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s1
	s_cbranch_execz .LBB6_28
; %bb.14:
	s_add_i32 s0, s8, -3
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
	s_mov_b32 s1, exec_lo
	v_cmpx_le_i32_e64 s0, v0
	s_xor_b32 s13, exec_lo, s1
	s_cbranch_execz .LBB6_24
; %bb.15:
	v_cmp_ne_u32_e32 vcc_lo, s0, v0
                                        ; implicit-def: $vgpr34_vgpr35
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s44, exec_lo, s0
	s_cbranch_execz .LBB6_20
; %bb.16:
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
	s_add_i32 s0, s8, -2
	s_mov_b32 s45, exec_lo
	v_cmpx_eq_u32_e64 s0, v0
	s_cbranch_execz .LBB6_19
; %bb.17:                               ; %.preheader1738
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	s_mov_b64 s[6:7], 0
	s_mov_b32 s46, s11
.LBB6_18:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v47, v27, v33, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_add_nc_u32_e32 v51, s46, v0
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v47, v47, v31, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s3, s46, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v53, v47, v29, s1
	v_add_co_u32 v47, s47, v0, s46
	v_add_co_ci_u32_e64 v48, null, 0, s3, s47
	v_ashrrev_i32_e32 v52, 31, v51
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v47, s3, s4, v47
	v_add_co_ci_u32_e64 v48, s3, s5, v48, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v51, s3, s4, v51
	v_add_co_ci_u32_e64 v52, s3, s5, v52, s3
	global_load_b128 v[47:50], v[47:48], off offset:-16
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	global_load_b64 v[51:52], v[51:52], off
	s_addc_u32 s7, s7, 0
	s_add_i32 s46, s46, s33
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v26, v32, vcc_lo
	v_cndmask_b32_e64 v50, v53, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v30, s0
	v_cndmask_b32_e64 v49, v49, v28, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v34, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[47:48], 0x40140000, v[51:52], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v27, v27, v48, s3
	v_cndmask_b32_e64 v26, v26, v47, s3
	v_dual_cndmask_b32 v33, v33, v48 :: v_dual_cndmask_b32 v32, v32, v47
	v_cndmask_b32_e64 v31, v31, v48, s0
	v_cndmask_b32_e64 v30, v30, v47, s0
	v_cndmask_b32_e64 v29, v29, v48, s1
	v_cndmask_b32_e64 v28, v28, v47, s1
	v_cndmask_b32_e64 v35, v35, v48, s2
	v_cndmask_b32_e64 v34, v34, v47, s2
	s_cbranch_scc0 .LBB6_18
.LBB6_19:                               ; %Flow2414
	s_or_b32 exec_lo, exec_lo, s45
.LBB6_20:                               ; %Flow2416
	s_and_not1_saveexec_b32 s44, s44
	s_cbranch_execz .LBB6_23
; %bb.21:                               ; %.preheader1736
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	s_mov_b64 s[6:7], 0
	s_mov_b32 s45, s11
.LBB6_22:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v47, v27, v33, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_add_nc_u32_e32 v51, s45, v0
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v47, v47, v31, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s3, s45, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v55, v47, v29, s1
	v_add_co_u32 v47, s46, v0, s45
	v_add_co_ci_u32_e64 v48, null, 0, s3, s46
	v_ashrrev_i32_e32 v52, 31, v51
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v47, s3, s4, v47
	v_add_co_ci_u32_e64 v48, s3, s5, v48, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v51, s3, s4, v51
	v_add_co_ci_u32_e64 v52, s3, s5, v52, s3
	global_load_b128 v[47:50], v[47:48], off offset:-16
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	global_load_b128 v[51:54], v[51:52], off
	s_addc_u32 s7, s7, 0
	s_add_i32 s45, s45, s33
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v26, v32, vcc_lo
	v_cndmask_b32_e64 v50, v55, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v30, s0
	v_cndmask_b32_e64 v49, v49, v28, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v34, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[47:48], 0x40180000, v[51:52], v[47:48]
	v_fma_f64 v[47:48], v[53:54], -4.0, v[47:48]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	v_cndmask_b32_e64 v27, v27, v48, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v47, s3
	v_dual_cndmask_b32 v33, v33, v48 :: v_dual_cndmask_b32 v32, v32, v47
	v_cndmask_b32_e64 v31, v31, v48, s0
	v_cndmask_b32_e64 v30, v30, v47, s0
	v_cndmask_b32_e64 v29, v29, v48, s1
	v_cndmask_b32_e64 v28, v28, v47, s1
	v_cndmask_b32_e64 v35, v35, v48, s2
	v_cndmask_b32_e64 v34, v34, v47, s2
	s_cbranch_scc0 .LBB6_22
.LBB6_23:                               ; %Flow2417
	s_or_b32 exec_lo, exec_lo, s44
.LBB6_24:                               ; %Flow2419
	s_and_not1_saveexec_b32 s13, s13
	s_cbranch_execz .LBB6_27
; %bb.25:                               ; %.preheader1734
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	s_mov_b64 s[6:7], 0
	s_mov_b32 s44, s11
.LBB6_26:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v47, v27, v33, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_add_nc_u32_e32 v51, s44, v0
	s_cselect_b32 s1, -1, 0
	v_cndmask_b32_e64 v47, v47, v31, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s3, s44, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v57, v47, v29, s1
	v_add_co_u32 v47, s45, v0, s44
	v_add_co_ci_u32_e64 v48, null, 0, s3, s45
	v_ashrrev_i32_e32 v52, 31, v51
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v47, s3, s4, v47
	v_add_co_ci_u32_e64 v48, s3, s5, v48, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v55, s3, s4, v51
	v_add_co_ci_u32_e64 v56, s3, s5, v52, s3
	s_clause 0x2
	global_load_b128 v[47:50], v[47:48], off offset:-16
	global_load_b128 v[51:54], v[55:56], off
	global_load_b64 v[55:56], v[55:56], off offset:16
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_add_i32 s44, s44, s33
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(2)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v26, v32, vcc_lo
	v_cndmask_b32_e64 v50, v57, v35, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v30, s0
	v_cndmask_b32_e64 v49, v49, v28, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v34, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], 0x40180000, v[51:52], v[47:48]
	v_fma_f64 v[47:48], v[53:54], -4.0, v[47:48]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[47:48], v[55:56], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v32, v32, v47, vcc_lo
	v_cndmask_b32_e64 v27, v27, v48, s3
	v_cndmask_b32_e64 v26, v26, v47, s3
	v_cndmask_b32_e32 v33, v33, v48, vcc_lo
	v_cndmask_b32_e64 v31, v31, v48, s0
	v_cndmask_b32_e64 v30, v30, v47, s0
	v_cndmask_b32_e64 v29, v29, v48, s1
	v_cndmask_b32_e64 v28, v28, v47, s1
	v_cndmask_b32_e64 v35, v35, v48, s2
	v_cndmask_b32_e64 v34, v34, v47, s2
	s_cbranch_scc0 .LBB6_26
.LBB6_27:                               ; %Flow2420
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s43, s43, exec_lo
.LBB6_28:                               ; %Flow2425
	s_or_b32 exec_lo, exec_lo, s12
	s_and_saveexec_b32 s44, s43
	s_cbranch_execz .LBB6_32
; %bb.29:                               ; %.preheader1740.preheader
	v_lshlrev_b32_e32 v26, 3, v0
	s_mov_b64 s[6:7], 0
	s_mov_b32 s12, s11
.LBB6_30:                               ; %.preheader1740
                                        ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_dual_cndmask_b32 v27, v37, v39 :: v_dual_cndmask_b32 v30, v36, v38
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	v_cndmask_b32_e64 v27, v27, v41, s0
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s13, s12, 31
	v_cndmask_b32_e64 v30, v30, v40, s0
	s_lshl_b64 s[46:47], s[12:13], 3
	v_cndmask_b32_e64 v29, v27, v43, s1
	s_add_u32 s46, s4, s46
	s_addc_u32 s47, s5, s47
	v_cndmask_b32_e64 v31, v30, v42, s1
	global_load_b64 v[27:28], v26, s[46:47] offset:8
	s_clause 0x1
	s_load_b64 s[48:49], s[46:47], 0x8
	s_load_b64 s[46:47], s[46:47], 0x18
	v_cndmask_b32_e64 v30, v29, v45, s2
	s_cmp_eq_u32 s6, 0
	v_cndmask_b32_e64 v29, v31, v44, s2
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_add_i32 s12, s12, s33
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(0)
	v_mul_f64 v[27:28], v[27:28], -4.0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], 0x40140000, s[48:49], v[27:28]
	v_add_f64 v[27:28], s[46:47], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], 0xbfd00000, v[27:28], v[29:30]
	v_cndmask_b32_e64 v37, v37, v28, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v36, v36, v27, s3
	v_dual_cndmask_b32 v39, v39, v28 :: v_dual_cndmask_b32 v38, v38, v27
	v_cndmask_b32_e64 v41, v41, v28, s0
	v_cndmask_b32_e64 v40, v40, v27, s0
	v_cndmask_b32_e64 v43, v43, v28, s1
	v_cndmask_b32_e64 v42, v42, v27, s1
	v_cndmask_b32_e64 v45, v45, v28, s2
	v_cndmask_b32_e64 v44, v44, v27, s2
	s_cbranch_scc0 .LBB6_30
; %bb.31:                               ; %Flow2421
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v34, v44 :: v_dual_mov_b32 v35, v45
	v_dual_mov_b32 v28, v42 :: v_dual_mov_b32 v29, v43
	v_dual_mov_b32 v30, v40 :: v_dual_mov_b32 v31, v41
	v_dual_mov_b32 v32, v38 :: v_dual_mov_b32 v33, v39
	v_dual_mov_b32 v26, v36 :: v_dual_mov_b32 v27, v37
.LBB6_32:                               ; %Flow2426
	s_or_b32 exec_lo, exec_lo, s44
	s_add_i32 s0, s14, 1
	s_lshl_b32 s1, s8, 1
	s_mul_i32 s2, s0, s8
	s_add_i32 s3, s40, s0
	v_add3_u32 v36, s39, s2, v0
	v_mad_u64_u32 v[38:39], null, s3, s8, v[0:1]
	s_sub_i32 s1, s2, s1
	s_add_i32 s2, s38, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v37, 31, v36
	v_add3_u32 v40, s39, s1, v0
	s_add_i32 s1, s35, s0
	v_mad_u64_u32 v[53:54], null, s2, s8, v[0:1]
	v_ashrrev_i32_e32 v39, 31, v38
	v_lshlrev_b64 v[36:37], 3, v[36:37]
	v_ashrrev_i32_e32 v41, 31, v40
	v_mad_u64_u32 v[42:43], null, s1, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[38:39], 3, v[38:39]
	s_add_i32 s1, s42, s0
	v_add_co_u32 v44, vcc_lo, s20, v36
	v_add_co_ci_u32_e32 v45, vcc_lo, s21, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v38, vcc_lo, s4, v38
	v_add_co_ci_u32_e32 v39, vcc_lo, s5, v39, vcc_lo
	v_lshlrev_b64 v[40:41], 3, v[40:41]
	v_mad_u64_u32 v[47:48], null, s1, s8, v[0:1]
	global_load_b64 v[38:39], v[38:39], off
	s_add_i32 s1, s14, -1
	v_ashrrev_i32_e32 v43, 31, v42
	v_add_co_u32 v48, vcc_lo, s20, v40
	v_add_co_ci_u32_e32 v49, vcc_lo, s21, v41, vcc_lo
	s_add_i32 s40, s40, s1
	s_clause 0x1
	global_load_b64 v[44:45], v[44:45], off
	global_load_b64 v[49:50], v[48:49], off
	v_mad_u64_u32 v[51:52], null, s40, s8, v[0:1]
	v_ashrrev_i32_e32 v48, 31, v47
	v_lshlrev_b64 v[42:43], 3, v[42:43]
	s_add_i32 s42, s42, s1
	s_add_i32 s0, s41, s0
	v_mad_u64_u32 v[55:56], null, s42, s8, v[0:1]
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_ashrrev_i32_e32 v52, 31, v51
	v_add_co_u32 v42, vcc_lo, s4, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, s5, v43, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v47, vcc_lo, s4, v47
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_add_co_u32 v57, vcc_lo, s24, v36
	v_add_co_ci_u32_e32 v58, vcc_lo, s25, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v51, vcc_lo, s4, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	global_load_b64 v[47:48], v[47:48], off
	global_load_b64 v[57:58], v[57:58], off
	global_load_b64 v[51:52], v[51:52], off
	v_ashrrev_i32_e32 v54, 31, v53
	v_mad_u64_u32 v[59:60], null, s0, s8, v[0:1]
	v_ashrrev_i32_e32 v56, 31, v55
	s_add_i32 s38, s38, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[53:54], 3, v[53:54]
	v_mad_u64_u32 v[61:62], null, s38, s8, v[0:1]
	v_lshlrev_b64 v[55:56], 3, v[55:56]
	v_ashrrev_i32_e32 v60, 31, v59
	s_add_i32 s41, s41, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v53, vcc_lo, s4, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s5, v54, vcc_lo
	v_add_co_u32 v55, vcc_lo, s4, v55
	v_lshlrev_b64 v[59:60], 3, v[59:60]
	v_add_co_ci_u32_e32 v56, vcc_lo, s5, v56, vcc_lo
	v_add_co_u32 v62, vcc_lo, s26, v36
	v_add_co_ci_u32_e32 v63, vcc_lo, s27, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v59, vcc_lo, s4, v59
	v_add_co_ci_u32_e32 v60, vcc_lo, s5, v60, vcc_lo
	v_add_co_u32 v64, vcc_lo, s24, v40
	v_add_co_ci_u32_e32 v65, vcc_lo, s25, v41, vcc_lo
	v_add_co_u32 v66, vcc_lo, s26, v40
	v_add_co_ci_u32_e32 v67, vcc_lo, s27, v41, vcc_lo
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[68:69], v[62:63], off
	global_load_b64 v[59:60], v[59:60], off
	global_load_b64 v[63:64], v[64:65], off
	v_mad_u64_u32 v[70:71], null, s41, s8, v[0:1]
	global_load_b64 v[65:66], v[66:67], off
	v_ashrrev_i32_e32 v62, 31, v61
	v_add_co_u32 v72, vcc_lo, s18, v36
	v_add_co_ci_u32_e32 v73, vcc_lo, s19, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[61:62], 3, v[61:62]
	v_ashrrev_i32_e32 v71, 31, v70
	v_add_co_u32 v74, vcc_lo, s22, v36
	v_add_co_ci_u32_e32 v75, vcc_lo, s23, v37, vcc_lo
	v_add_co_u32 v61, vcc_lo, s4, v61
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[70:71], 3, v[70:71]
	v_add_co_ci_u32_e32 v62, vcc_lo, s5, v62, vcc_lo
	v_add_co_u32 v36, vcc_lo, s16, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, s17, v37, vcc_lo
	v_add_co_u32 v70, vcc_lo, s4, v70
	v_add_co_ci_u32_e32 v71, vcc_lo, s5, v71, vcc_lo
	s_clause 0x1
	global_load_b64 v[42:43], v[42:43], off
	global_load_b64 v[55:56], v[55:56], off
	global_load_b64 v[72:73], v[72:73], off
	global_load_b64 v[74:75], v[74:75], off
	global_load_b64 v[36:37], v[36:37], off
	s_clause 0x1
	global_load_b64 v[61:62], v[61:62], off
	global_load_b64 v[70:71], v[70:71], off
	s_add_i32 s0, s35, s1
	v_add_co_u32 v78, vcc_lo, s18, v40
	v_mad_u64_u32 v[76:77], null, s0, s8, v[0:1]
	v_add_co_ci_u32_e32 v79, vcc_lo, s19, v41, vcc_lo
	v_add_co_u32 v80, vcc_lo, s22, v40
	v_add_co_ci_u32_e32 v81, vcc_lo, s23, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v77, 31, v76
	global_load_b64 v[78:79], v[78:79], off
	v_mul_f64 v[24:25], v[24:25], v[3:4]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dy5ty1@rel32@lo+4
	s_addc_u32 s1, s1, dy5ty1@rel32@hi+12
	s_mov_b32 s2, 0x9999999a
	v_lshlrev_b64 v[76:77], 3, v[76:77]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s3, 0x3fd99999
	s_mov_b32 s12, 0x66666666
	s_mov_b32 s13, 0x3ff66666
	s_mov_b32 s44, 0x55555555
	v_add_co_u32 v76, vcc_lo, s4, v76
	v_add_co_ci_u32_e32 v77, vcc_lo, s5, v77, vcc_lo
	v_add_co_u32 v40, vcc_lo, s16, v40
	v_add_co_ci_u32_e32 v41, vcc_lo, s17, v41, vcc_lo
	global_load_b64 v[80:81], v[80:81], off
	global_load_b64 v[76:77], v[76:77], off
	global_load_b64 v[40:41], v[40:41], off
	s_mov_b32 s45, 0x3ff55555
	s_waitcnt vmcnt(21)
	v_add_f64 v[82:83], v[38:39], -v[18:19]
	s_waitcnt vmcnt(20)
	v_fma_f64 v[24:25], v[44:45], v[44:45], -v[24:25]
	s_waitcnt vmcnt(18)
	v_add_f64 v[86:87], v[47:48], -v[9:10]
	s_waitcnt vmcnt(17)
	v_add_f64 v[57:58], v[57:58], -v[22:23]
	s_waitcnt vmcnt(16)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[82:83], v[82:83], v[51:52]
	v_fma_f64 v[24:25], v[49:50], v[49:50], v[24:25]
	s_waitcnt vmcnt(14)
	v_add_f64 v[88:89], v[38:39], -v[68:69]
	v_add_f64 v[84:85], v[53:54], -v[7:8]
	s_waitcnt vmcnt(13)
	v_add_f64 v[90:91], v[59:60], -v[20:21]
	s_waitcnt vmcnt(12)
	v_add_f64 v[57:58], v[57:58], v[63:64]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[34:35], v[82:83], s[0:1], v[34:35]
	s_waitcnt vmcnt(11)
	v_mul_f64 v[63:64], v[65:66], s[2:3]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, yycon3@rel32@lo+4
	s_addc_u32 s1, s1, yycon3@rel32@hi+12
	v_add_f64 v[82:83], v[44:45], -v[3:4]
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_f64 v[67:68], v[68:69], s[2:3]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, yycon2@rel32@lo+4
	s_addc_u32 s7, s7, yycon2@rel32@hi+12
	s_waitcnt vmcnt(10)
	v_add_f64 v[42:43], v[42:43], -v[1:2]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[92:93], v[49:50], v[55:56]
	s_waitcnt vmcnt(8)
	v_add_f64 v[72:73], v[72:73], -v[14:15]
	s_waitcnt vmcnt(7)
	v_add_f64 v[74:75], v[74:75], -v[5:6]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[36:37], v[38:39], v[36:37], -v[12:13]
	v_add_f64 v[86:87], v[86:87], v[55:56]
	v_add_f64 v[88:89], v[88:89], -v[51:52]
	s_waitcnt vmcnt(5)
	v_add_f64 v[84:85], v[84:85], v[61:62]
	s_waitcnt vmcnt(4)
	v_add_f64 v[90:91], v[90:91], v[70:71]
	v_mul_f64 v[61:62], v[49:50], v[61:62]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[34:35], s[0:1], v[57:58], v[34:35]
	v_fma_f64 v[57:58], v[51:52], s[12:13], -v[63:64]
	s_load_b64 s[0:1], s[6:7], 0x0
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, dy2ty1@rel32@lo+4
	s_addc_u32 s7, s7, dy2ty1@rel32@hi+12
	s_getpc_b64 s[38:39]
	s_add_u32 s38, s38, dy3ty1@rel32@lo+4
	s_addc_u32 s39, s39, dy3ty1@rel32@hi+12
	s_getpc_b64 s[40:41]
	s_add_u32 s40, s40, dy4ty1@rel32@lo+4
	s_addc_u32 s41, s41, dy4ty1@rel32@hi+12
	s_getpc_b64 s[42:43]
	s_add_u32 s42, s42, yycon4@rel32@lo+4
	s_addc_u32 s43, s43, yycon4@rel32@hi+12
	s_load_b64 s[6:7], s[6:7], 0x0
	s_load_b64 s[38:39], s[38:39], 0x0
	s_load_b64 s[40:41], s[40:41], 0x0
	s_load_b64 s[42:43], s[42:43], 0x0
	v_mul_f64 v[69:70], v[49:50], v[70:71]
	v_fma_f64 v[38:39], v[38:39], s[12:13], -v[67:68]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[63:64], s[0:1], s[44:45]
	s_waitcnt vmcnt(1)
	v_add_f64 v[42:43], v[42:43], v[76:77]
	v_fma_f64 v[67:68], v[44:45], v[47:48], -v[92:93]
	v_add_f64 v[71:72], v[72:73], v[78:79]
	v_add_f64 v[78:79], v[82:83], v[49:50]
	v_add_f64 v[73:74], v[74:75], v[80:81]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[36:37], v[51:52], v[40:41], v[36:37]
	v_fma_f64 v[30:31], v[86:87], s[38:39], v[30:31]
	v_add_f64 v[47:48], v[47:48], -v[55:56]
	v_add_f64 v[40:41], v[88:89], v[65:66]
	v_fma_f64 v[32:33], s[6:7], v[84:85], v[32:33]
	v_fma_f64 v[28:29], s[40:41], v[90:91], v[28:29]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, dy1ty1@rel32@lo+4
	s_addc_u32 s7, s7, dy1ty1@rel32@hi+12
	v_fma_f64 v[24:25], v[24:25], s[42:43], v[34:35]
	v_mul_f64 v[34:35], v[49:50], v[57:58]
	s_getpc_b64 s[12:13]
	s_add_u32 s12, s12, yycon5@rel32@lo+4
	s_addc_u32 s13, s13, yycon5@rel32@hi+12
	s_load_b64 s[6:7], s[6:7], 0x0
	s_load_b64 s[12:13], s[12:13], 0x0
	v_fma_f64 v[49:50], v[44:45], v[53:54], -v[61:62]
	v_fma_f64 v[51:52], v[44:45], v[59:60], -v[69:70]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[26:27], s[6:7], v[42:43], v[26:27]
	v_fma_f64 v[30:31], v[78:79], v[63:64], v[30:31]
	v_fma_f64 v[40:41], v[40:41], s[2:3], v[67:68]
	v_fma_f64 v[32:33], s[0:1], v[71:72], v[32:33]
	v_fma_f64 v[28:29], s[0:1], v[73:74], v[28:29]
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ty2@rel32@lo+4
	s_addc_u32 s1, s1, ty2@rel32@hi+12
	v_fma_f64 v[24:25], s[12:13], v[36:37], v[24:25]
	v_fma_f64 v[42:43], v[44:45], v[38:39], -v[34:35]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_cmp_lt_i32 s14, 2
	s_mov_b32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[34:35], -s[0:1], v[47:48], v[26:27]
	v_fma_f64 v[38:39], -s[0:1], v[40:41], v[30:31]
	v_fma_f64 v[36:37], -s[0:1], v[49:50], v[32:33]
	v_fma_f64 v[40:41], -s[0:1], v[51:52], v[28:29]
	v_fma_f64 v[42:43], -s[0:1], v[42:43], v[24:25]
	s_mov_b32 s1, -1
	s_cbranch_scc1 .LBB6_37
; %bb.33:                               ; %LeafBlock2372
	s_cmp_eq_u32 s14, 2
	s_cbranch_scc0 .LBB6_38
; %bb.34:                               ; %.preheader1732.preheader
	s_add_i32 s0, s36, 1
	s_add_i32 s1, s35, 4
	v_mov_b32_e32 v24, v34
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v30, v36
	v_mov_b32_e32 v28, v38
	v_mov_b32_e32 v26, v40
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v25, v35
	v_mov_b32_e32 v31, v37
	v_mov_b32_e32 v29, v39
	v_mov_b32_e32 v27, v41
	s_mul_i32 s13, s8, s0
	s_mul_i32 s38, s8, s1
	s_add_i32 s0, s35, 2
	s_add_i32 s1, s36, -1
	s_mul_i32 s39, s8, s0
	s_mul_i32 s40, s8, s1
	s_mov_b64 s[6:7], 0
.LBB6_35:                               ; %.preheader1732
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v47, s40, v44
	v_add_nc_u32_e32 v49, s39, v44
	v_add_nc_u32_e32 v51, s13, v44
	v_add_nc_u32_e32 v53, s38, v44
	s_cmp_eq_u32 s6, 1
	v_ashrrev_i32_e32 v48, 31, v47
	v_ashrrev_i32_e32 v50, 31, v49
	v_ashrrev_i32_e32 v52, 31, v51
	v_ashrrev_i32_e32 v54, 31, v53
	v_add_nc_u32_e32 v44, s33, v44
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[49:50], 3, v[49:50]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_lshlrev_b64 v[53:54], 3, v[53:54]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v47, vcc_lo, s4, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_add_co_u32 v49, vcc_lo, s4, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s5, v50, vcc_lo
	global_load_b64 v[47:48], v[47:48], off
	v_add_co_u32 v51, vcc_lo, s4, v51
	global_load_b64 v[49:50], v[49:50], off
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	v_add_co_u32 v53, vcc_lo, s4, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s5, v54, vcc_lo
	global_load_b64 v[51:52], v[51:52], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[53:54], v[53:54], off
	v_cndmask_b32_e32 v45, v25, v31, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v45, v45, v29, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	v_cndmask_b32_e64 v45, v45, v27, s1
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(3)
	v_mul_f64 v[47:48], v[47:48], -4.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[47:48], 0x40180000, v[49:50], v[47:48]
	v_cndmask_b32_e32 v49, v24, v30, vcc_lo
	v_cndmask_b32_e64 v50, v45, v33, s2
	v_cndmask_b32_e64 v49, v49, v28, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v26, s1
	v_cndmask_b32_e64 v49, v49, v32, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], v[51:52], -4.0, v[47:48]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[47:48], v[53:54], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v25, v25, v48, s3
	v_cndmask_b32_e64 v24, v24, v47, s3
	v_dual_cndmask_b32 v31, v31, v48 :: v_dual_cndmask_b32 v30, v30, v47
	v_cndmask_b32_e64 v29, v29, v48, s0
	v_cndmask_b32_e64 v28, v28, v47, s0
	v_cndmask_b32_e64 v27, v27, v48, s1
	v_cndmask_b32_e64 v26, v26, v47, s1
	v_cndmask_b32_e64 v33, v33, v48, s2
	v_cndmask_b32_e64 v32, v32, v47, s2
	s_cbranch_scc0 .LBB6_35
; %bb.36:                               ; %Flow2397
	s_mov_b32 s0, 0
	s_branch .LBB6_39
.LBB6_37:
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr24_vgpr25
	s_branch .LBB6_40
.LBB6_38:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr24_vgpr25
.LBB6_39:                               ; %Flow2408
	s_mov_b32 s1, 0
.LBB6_40:                               ; %Flow2407
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB6_42
; %bb.41:                               ; %LeafBlock2370
	s_cmp_lg_u32 s14, 1
	s_mov_b32 s12, -1
	s_cselect_b32 s0, -1, 0
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr24_vgpr25
.LBB6_42:                               ; %Flow2409
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_59
; %bb.43:
	s_add_i32 s0, s9, -3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s14, s0
	s_cbranch_scc0 .LBB6_49
; %bb.44:
	s_cmp_lg_u32 s14, s0
	s_cbranch_scc0 .LBB6_50
; %bb.45:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v26, v40 :: v_dual_mov_b32 v27, v41
	v_dual_mov_b32 v28, v38 :: v_dual_mov_b32 v29, v39
	v_dual_mov_b32 v30, v36 :: v_dual_mov_b32 v31, v37
	v_dual_mov_b32 v24, v34 :: v_dual_mov_b32 v25, v35
	s_add_i32 s0, s9, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s14, s0
	s_cbranch_scc1 .LBB6_48
; %bb.46:                               ; %.preheader1728
	v_mov_b32_e32 v24, v34
	v_mov_b32_e32 v30, v36
	v_mov_b32_e32 v28, v38
	v_mov_b32_e32 v26, v40
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v25, v35
	v_mov_b32_e32 v31, v37
	v_mov_b32_e32 v29, v39
	v_mov_b32_e32 v27, v41
	s_add_i32 s0, s36, -1
	s_add_i32 s1, s36, -2
	s_mul_i32 s12, s8, s0
	s_mul_i32 s13, s8, s1
	s_mov_b64 s[6:7], 0
.LBB6_47:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v47, s13, v44
	v_add_nc_u32_e32 v49, s12, v44
	v_add_nc_u32_e32 v51, s11, v44
	s_cmp_eq_u32 s6, 1
	v_add_nc_u32_e32 v44, s33, v44
	v_ashrrev_i32_e32 v48, 31, v47
	v_ashrrev_i32_e32 v50, 31, v49
	v_ashrrev_i32_e32 v52, 31, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[49:50], 3, v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_add_co_u32 v47, vcc_lo, s4, v47
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_add_co_u32 v49, vcc_lo, s4, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s5, v50, vcc_lo
	s_clause 0x1
	global_load_b64 v[47:48], v[47:48], off
	global_load_b64 v[49:50], v[49:50], off
	v_add_co_u32 v51, vcc_lo, s4, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_cndmask_b32_e32 v45, v25, v31, vcc_lo
	global_load_b64 v[51:52], v[51:52], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_cndmask_b32_e64 v45, v45, v29, s0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v45, v45, v27, s1
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v24, v30, vcc_lo
	v_cndmask_b32_e64 v50, v45, v33, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v28, s0
	v_cndmask_b32_e64 v49, v49, v26, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v32, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[47:48], 0x40140000, v[51:52], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v25, v25, v48, s3
	v_cndmask_b32_e64 v24, v24, v47, s3
	v_dual_cndmask_b32 v31, v31, v48 :: v_dual_cndmask_b32 v30, v30, v47
	v_cndmask_b32_e64 v29, v29, v48, s0
	v_cndmask_b32_e64 v28, v28, v47, s0
	v_cndmask_b32_e64 v27, v27, v48, s1
	v_cndmask_b32_e64 v26, v26, v47, s1
	v_cndmask_b32_e64 v33, v33, v48, s2
	v_cndmask_b32_e64 v32, v32, v47, s2
	s_cbranch_scc0 .LBB6_47
.LBB6_48:                               ; %Flow2399
	s_mov_b32 s0, 0
	s_branch .LBB6_51
.LBB6_49:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr24_vgpr25
	s_branch .LBB6_55
.LBB6_50:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $vgpr30_vgpr31
                                        ; implicit-def: $vgpr24_vgpr25
.LBB6_51:                               ; %Flow2401
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_54
; %bb.52:                               ; %.preheader1726
	s_add_i32 s0, s36, 1
	v_mov_b32_e32 v24, v34
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v30, v36
	v_mov_b32_e32 v28, v38
	v_mov_b32_e32 v26, v40
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v25, v35
	v_mov_b32_e32 v31, v37
	v_mov_b32_e32 v29, v39
	v_mov_b32_e32 v27, v41
	s_add_i32 s1, s36, -1
	s_mul_i32 s12, s8, s0
	s_add_i32 s0, s36, -2
	s_mul_i32 s13, s8, s1
	s_mul_i32 s38, s8, s0
	s_mov_b64 s[6:7], 0
.LBB6_53:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v47, s38, v44
	v_add_nc_u32_e32 v49, s13, v44
	v_add_nc_u32_e32 v51, s11, v44
	v_add_nc_u32_e32 v53, s12, v44
	s_cmp_eq_u32 s6, 1
	v_ashrrev_i32_e32 v48, 31, v47
	v_ashrrev_i32_e32 v50, 31, v49
	v_ashrrev_i32_e32 v52, 31, v51
	v_ashrrev_i32_e32 v54, 31, v53
	v_add_nc_u32_e32 v44, s33, v44
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[49:50], 3, v[49:50]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_lshlrev_b64 v[53:54], 3, v[53:54]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v47, vcc_lo, s4, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_add_co_u32 v49, vcc_lo, s4, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s5, v50, vcc_lo
	s_clause 0x1
	global_load_b64 v[47:48], v[47:48], off
	global_load_b64 v[49:50], v[49:50], off
	v_add_co_u32 v51, vcc_lo, s4, v51
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	v_add_co_u32 v53, vcc_lo, s4, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s5, v54, vcc_lo
	global_load_b64 v[51:52], v[51:52], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[53:54], v[53:54], off
	v_cndmask_b32_e32 v45, v25, v31, vcc_lo
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v45, v45, v29, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	v_cndmask_b32_e64 v45, v45, v27, s1
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(2)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v24, v30, vcc_lo
	v_cndmask_b32_e64 v50, v45, v33, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v28, s0
	v_cndmask_b32_e64 v49, v49, v26, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v32, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], 0x40180000, v[51:52], v[47:48]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[47:48], v[53:54], -4.0, v[47:48]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	v_cndmask_b32_e64 v25, v25, v48, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v24, v24, v47, s3
	v_dual_cndmask_b32 v31, v31, v48 :: v_dual_cndmask_b32 v30, v30, v47
	v_cndmask_b32_e64 v29, v29, v48, s0
	v_cndmask_b32_e64 v28, v28, v47, s0
	v_cndmask_b32_e64 v27, v27, v48, s1
	v_cndmask_b32_e64 v26, v26, v47, s1
	v_cndmask_b32_e64 v33, v33, v48, s2
	v_cndmask_b32_e64 v32, v32, v47, s2
	s_cbranch_scc0 .LBB6_53
.LBB6_54:                               ; %Flow2402
	s_mov_b32 s0, 0
.LBB6_55:                               ; %Flow2404
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_58
; %bb.56:                               ; %.preheader1724
	s_add_i32 s0, s36, 1
	s_add_i32 s1, s36, 2
	v_mov_b32_e32 v24, v34
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v30, v36
	v_mov_b32_e32 v28, v38
	v_mov_b32_e32 v26, v40
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v44, v46 :: v_dual_mov_b32 v25, v35
	v_mov_b32_e32 v31, v37
	v_mov_b32_e32 v29, v39
	v_mov_b32_e32 v27, v41
	s_mul_i32 s12, s8, s0
	s_mul_i32 s13, s8, s1
	s_add_i32 s0, s36, -1
	s_add_i32 s1, s36, -2
	s_mul_i32 s38, s8, s0
	s_mul_i32 s39, s8, s1
	s_mov_b64 s[6:7], 0
.LBB6_57:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v47, s39, v44
	v_add_nc_u32_e32 v49, s38, v44
	v_add_nc_u32_e32 v51, s11, v44
	v_add_nc_u32_e32 v53, s12, v44
	v_add_nc_u32_e32 v55, s13, v44
	v_ashrrev_i32_e32 v48, 31, v47
	v_ashrrev_i32_e32 v50, 31, v49
	v_ashrrev_i32_e32 v52, 31, v51
	v_ashrrev_i32_e32 v54, 31, v53
	v_ashrrev_i32_e32 v56, 31, v55
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	v_lshlrev_b64 v[49:50], 3, v[49:50]
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_lshlrev_b64 v[53:54], 3, v[53:54]
	v_lshlrev_b64 v[55:56], 3, v[55:56]
	s_cmp_eq_u32 s6, 1
	v_add_co_u32 v47, vcc_lo, s4, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_add_co_u32 v49, vcc_lo, s4, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s5, v50, vcc_lo
	v_add_co_u32 v51, vcc_lo, s4, v51
	s_clause 0x1
	global_load_b64 v[47:48], v[47:48], off
	global_load_b64 v[49:50], v[49:50], off
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	v_add_co_u32 v53, vcc_lo, s4, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s5, v54, vcc_lo
	global_load_b64 v[51:52], v[51:52], off
	v_add_co_u32 v55, vcc_lo, s4, v55
	global_load_b64 v[53:54], v[53:54], off
	v_add_co_ci_u32_e32 v56, vcc_lo, s5, v56, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_dual_cndmask_b32 v45, v25, v31 :: v_dual_add_nc_u32 v44, s33, v44
	global_load_b64 v[55:56], v[55:56], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	v_cndmask_b32_e64 v45, v45, v29, s0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v45, v45, v27, s1
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(3)
	v_fma_f64 v[47:48], v[49:50], -4.0, v[47:48]
	v_cndmask_b32_e32 v49, v24, v30, vcc_lo
	v_cndmask_b32_e64 v50, v45, v33, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v28, s0
	v_cndmask_b32_e64 v49, v49, v26, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v49, v49, v32, s2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[47:48], 0x40180000, v[51:52], v[47:48]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[47:48], v[53:54], -4.0, v[47:48]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[47:48], v[55:56], v[47:48]
	v_fma_f64 v[47:48], 0xbfd00000, v[47:48], v[49:50]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v25, v25, v48, s3
	v_cndmask_b32_e64 v24, v24, v47, s3
	v_dual_cndmask_b32 v31, v31, v48 :: v_dual_cndmask_b32 v30, v30, v47
	v_cndmask_b32_e64 v29, v29, v48, s0
	v_cndmask_b32_e64 v28, v28, v47, s0
	v_cndmask_b32_e64 v27, v27, v48, s1
	v_cndmask_b32_e64 v26, v26, v47, s1
	v_cndmask_b32_e64 v33, v33, v48, s2
	v_cndmask_b32_e64 v32, v32, v47, s2
	s_cbranch_scc0 .LBB6_57
.LBB6_58:                               ; %Flow2405
	s_mov_b32 s12, 0
.LBB6_59:                               ; %Flow2410
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB6_63
; %bb.60:                               ; %.preheader1730.preheader
	v_mov_b32_e32 v24, v46
	s_add_i32 s36, s36, 1
	s_add_i32 s0, s35, 3
	s_add_i32 s35, s35, 1
	s_mul_i32 s12, s8, s36
	s_mul_i32 s13, s8, s0
	s_mul_i32 s35, s8, s35
	s_mov_b64 s[6:7], 0
.LBB6_61:                               ; %.preheader1730
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v25, s12, v24
	v_add_nc_u32_e32 v27, s35, v24
	v_add_nc_u32_e32 v29, s13, v24
	s_cmp_eq_u32 s6, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v26, 31, v25
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[25:26], 3, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v25, vcc_lo, s4, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v27, vcc_lo, s4, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s4, v29
	s_clause 0x1
	global_load_b64 v[25:26], v[25:26], off
	global_load_b64 v[27:28], v[27:28], off
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[29:30], v[29:30], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(2)
	v_mul_f64 v[25:26], v[25:26], -4.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[25:26], 0x40140000, v[27:28], v[25:26]
	v_dual_cndmask_b32 v27, v35, v37 :: v_dual_cndmask_b32 v28, v34, v36
	v_cndmask_b32_e64 v27, v27, v39, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v28, v38, s0
	v_cndmask_b32_e64 v27, v27, v41, s1
	s_waitcnt vmcnt(0)
	v_add_f64 v[25:26], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v28, v40, s1
	v_cndmask_b32_e64 v28, v27, v43, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v27, v29, v42, s2
	v_fma_f64 v[25:26], 0xbfd00000, v[25:26], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v37, v37, v26 :: v_dual_add_nc_u32 v24, s33, v24
	v_cndmask_b32_e64 v35, v35, v26, s3
	v_cndmask_b32_e64 v34, v34, v25, s3
	v_cndmask_b32_e32 v36, v36, v25, vcc_lo
	v_cndmask_b32_e64 v39, v39, v26, s0
	v_cndmask_b32_e64 v38, v38, v25, s0
	v_cndmask_b32_e64 v41, v41, v26, s1
	v_cndmask_b32_e64 v40, v40, v25, s1
	v_cndmask_b32_e64 v43, v43, v26, s2
	v_cndmask_b32_e64 v42, v42, v25, s2
	s_cbranch_scc0 .LBB6_61
; %bb.62:                               ; %Flow2406
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v32, v42 :: v_dual_mov_b32 v33, v43
	v_dual_mov_b32 v26, v40 :: v_dual_mov_b32 v27, v41
	v_dual_mov_b32 v28, v38 :: v_dual_mov_b32 v29, v39
	v_dual_mov_b32 v30, v36 :: v_dual_mov_b32 v31, v37
	v_dual_mov_b32 v24, v34 :: v_dual_mov_b32 v25, v35
.LBB6_63:                               ; %NodeBlock2380
	s_add_i32 s1, s15, 1
	s_lshl_b32 s2, s34, 1
	s_mul_i32 s0, s34, s1
	s_add_i32 s13, s15, -1
	v_add_nc_u32_e32 v34, s0, v11
	s_sub_i32 s0, s0, s2
	s_add_i32 s2, s1, s10
	v_add_nc_u32_e32 v36, s0, v11
	s_add_i32 s3, s2, s10
	s_mul_i32 s0, s1, s9
	s_add_i32 s6, s3, s37
	s_add_i32 s12, s0, s14
	s_mul_i32 s6, s6, s9
	s_mul_i32 s12, s12, s8
	s_add_i32 s6, s6, s14
	v_ashrrev_i32_e32 v35, 31, v34
	v_add_nc_u32_e32 v38, s12, v0
	v_mad_u64_u32 v[42:43], null, s6, s8, v[0:1]
	v_ashrrev_i32_e32 v37, 31, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[34:35], 3, v[34:35]
	v_ashrrev_i32_e32 v39, 31, v38
	s_add_i32 s1, s31, s1
	s_add_i32 s6, s13, s10
	v_lshlrev_b64 v[36:37], 3, v[36:37]
	v_ashrrev_i32_e32 v43, 31, v42
	v_add_co_u32 v40, vcc_lo, s22, v34
	v_lshlrev_b64 v[38:39], 3, v[38:39]
	v_add_co_ci_u32_e32 v41, vcc_lo, s23, v35, vcc_lo
	v_add_co_u32 v44, vcc_lo, s22, v36
	v_lshlrev_b64 v[42:43], 3, v[42:43]
	v_add_co_ci_u32_e32 v45, vcc_lo, s23, v37, vcc_lo
	v_add_co_u32 v38, vcc_lo, s4, v38
	v_add_co_ci_u32_e32 v39, vcc_lo, s5, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v42, vcc_lo, s4, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, s5, v43, vcc_lo
	s_mul_i32 s1, s1, s9
	s_clause 0x1
	global_load_b64 v[40:41], v[40:41], off
	global_load_b64 v[44:45], v[44:45], off
	s_add_i32 s1, s1, s14
	global_load_b64 v[42:43], v[42:43], off
	v_mad_u64_u32 v[47:48], null, s1, s8, v[0:1]
	s_add_i32 s1, s31, s13
	s_add_i32 s7, s6, s10
	s_mul_i32 s1, s1, s9
	v_mul_f64 v[16:17], v[16:17], v[5:6]
	s_add_i32 s1, s1, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[49:50], null, s1, s8, v[0:1]
	s_mul_i32 s1, s2, s9
	s_add_i32 s2, s7, s37
	v_ashrrev_i32_e32 v48, 31, v47
	s_mul_i32 s2, s2, s9
	s_add_i32 s1, s1, s14
	s_add_i32 s2, s2, s14
	v_mad_u64_u32 v[51:52], null, s1, s8, v[0:1]
	v_mad_u64_u32 v[53:54], null, s2, s8, v[0:1]
	v_lshlrev_b64 v[47:48], 3, v[47:48]
	s_mul_i32 s2, s3, s9
	v_ashrrev_i32_e32 v50, 31, v49
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v52, 31, v51
	v_mad_u64_u32 v[57:58], null, s2, s8, v[0:1]
	v_ashrrev_i32_e32 v54, 31, v53
	v_add_co_u32 v47, vcc_lo, s4, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s5, v48, vcc_lo
	v_lshlrev_b64 v[53:54], 3, v[53:54]
	v_add_co_u32 v55, vcc_lo, s24, v34
	global_load_b64 v[47:48], v[47:48], off
	v_add_co_ci_u32_e32 v56, vcc_lo, s25, v35, vcc_lo
	v_add_co_u32 v53, vcc_lo, s4, v53
	v_add_co_ci_u32_e32 v54, vcc_lo, s5, v54, vcc_lo
	global_load_b64 v[38:39], v[38:39], off
	global_load_b64 v[55:56], v[55:56], off
	global_load_b64 v[53:54], v[53:54], off
	v_lshlrev_b64 v[51:52], 3, v[51:52]
	v_ashrrev_i32_e32 v58, 31, v57
	v_lshlrev_b64 v[49:50], 3, v[49:50]
	s_mul_i32 s2, s6, s9
	s_lshl_b32 s1, s9, 1
	s_add_i32 s2, s2, s14
	v_add_co_u32 v51, vcc_lo, s4, v51
	v_lshlrev_b64 v[57:58], 3, v[57:58]
	v_add_co_ci_u32_e32 v52, vcc_lo, s5, v52, vcc_lo
	v_add_co_u32 v49, vcc_lo, s4, v49
	v_add_co_ci_u32_e32 v50, vcc_lo, s5, v50, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v57, vcc_lo, s4, v57
	v_add_co_ci_u32_e32 v58, vcc_lo, s5, v58, vcc_lo
	v_add_co_u32 v61, vcc_lo, s26, v34
	v_add_co_ci_u32_e32 v62, vcc_lo, s27, v35, vcc_lo
	v_add_co_u32 v63, vcc_lo, s24, v36
	v_add_co_ci_u32_e32 v64, vcc_lo, s25, v37, vcc_lo
	v_add_co_u32 v65, vcc_lo, s26, v36
	v_add_co_ci_u32_e32 v66, vcc_lo, s27, v37, vcc_lo
	s_clause 0x1
	global_load_b64 v[51:52], v[51:52], off
	global_load_b64 v[57:58], v[57:58], off
	global_load_b64 v[61:62], v[61:62], off
	global_load_b64 v[63:64], v[63:64], off
	v_mad_u64_u32 v[59:60], null, s2, s8, v[0:1]
	global_load_b64 v[65:66], v[65:66], off
	s_mul_i32 s2, s7, s9
	v_add_co_u32 v69, vcc_lo, s18, v34
	s_add_i32 s2, s2, s14
	v_add_co_ci_u32_e32 v70, vcc_lo, s19, v35, vcc_lo
	v_mad_u64_u32 v[67:68], null, s2, s8, v[0:1]
	v_ashrrev_i32_e32 v60, 31, v59
	v_add_co_u32 v71, vcc_lo, s20, v34
	v_add_co_ci_u32_e32 v72, vcc_lo, s21, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[59:60], 3, v[59:60]
	v_ashrrev_i32_e32 v68, 31, v67
	global_load_b64 v[49:50], v[49:50], off
	global_load_b64 v[69:70], v[69:70], off
	global_load_b64 v[71:72], v[71:72], off
	s_sub_i32 s0, s0, s1
	v_add_co_u32 v59, vcc_lo, s4, v59
	v_lshlrev_b64 v[67:68], 3, v[67:68]
	v_add_co_ci_u32_e32 v60, vcc_lo, s5, v60, vcc_lo
	v_add_co_u32 v34, vcc_lo, s16, v34
	v_add_co_ci_u32_e32 v35, vcc_lo, s17, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v67, vcc_lo, s4, v67
	v_add_co_ci_u32_e32 v68, vcc_lo, s5, v68, vcc_lo
	global_load_b64 v[34:35], v[34:35], off
	global_load_b64 v[59:60], v[59:60], off
	s_add_i32 s0, s0, s14
	v_add_co_u32 v75, vcc_lo, s18, v36
	global_load_b64 v[67:68], v[67:68], off
	v_mad_u64_u32 v[73:74], null, s0, s8, v[0:1]
	v_add_co_ci_u32_e32 v76, vcc_lo, s19, v37, vcc_lo
	v_add_co_u32 v77, vcc_lo, s20, v36
	v_add_co_ci_u32_e32 v78, vcc_lo, s21, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v74, 31, v73
	global_load_b64 v[75:76], v[75:76], off
	global_load_b64 v[77:78], v[77:78], off
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, dz5tz1@rel32@lo+4
	s_addc_u32 s3, s3, dz5tz1@rel32@hi+12
	s_mov_b32 s6, 0x9999999a
	v_lshlrev_b64 v[73:74], 3, v[73:74]
	s_load_b64 s[2:3], s[2:3], 0x0
	s_mov_b32 s7, 0x3fd99999
	s_mov_b32 s18, 0x66666666
	s_mov_b32 s19, 0x3ff66666
	s_mov_b32 s26, 0x55555555
	v_add_co_u32 v73, vcc_lo, s4, v73
	v_add_co_ci_u32_e32 v74, vcc_lo, s5, v74, vcc_lo
	v_add_co_u32 v36, vcc_lo, s16, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, s17, v37, vcc_lo
	global_load_b64 v[73:74], v[73:74], off
	global_load_b64 v[36:37], v[36:37], off
	s_mov_b32 s27, 0x3ff55555
	s_waitcnt vmcnt(21)
	v_fma_f64 v[16:17], v[40:41], v[40:41], -v[16:17]
	v_add_f64 v[5:6], v[40:41], -v[5:6]
	s_waitcnt vmcnt(19)
	v_add_f64 v[18:19], v[42:43], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[44:45], v[44:45], v[16:17]
	s_waitcnt vmcnt(18)
	v_add_f64 v[20:21], v[47:48], -v[20:21]
	v_add_f64 v[5:6], v[5:6], v[44:45]
	s_waitcnt vmcnt(17)
	v_add_f64 v[1:2], v[38:39], -v[1:2]
	s_waitcnt vmcnt(16)
	v_add_f64 v[22:23], v[55:56], -v[22:23]
	s_waitcnt vmcnt(15)
	v_add_f64 v[18:19], v[18:19], v[53:54]
	s_waitcnt vmcnt(13)
	v_add_f64 v[9:10], v[57:58], -v[9:10]
	v_add_f64 v[7:8], v[51:52], -v[7:8]
	s_waitcnt vmcnt(12)
	v_add_f64 v[55:56], v[42:43], -v[61:62]
	v_mul_f64 v[61:62], v[61:62], s[6:7]
	s_waitcnt vmcnt(11)
	v_add_f64 v[22:23], v[22:23], v[63:64]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[18:19], v[18:19], s[2:3], v[32:33]
	s_waitcnt vmcnt(10)
	v_mul_f64 v[32:33], v[65:66], s[6:7]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, zzcon3@rel32@lo+4
	s_addc_u32 s3, s3, zzcon3@rel32@hi+12
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, zzcon2@rel32@lo+4
	s_addc_u32 s17, s17, zzcon2@rel32@hi+12
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt vmcnt(9)
	v_mul_f64 v[38:39], v[44:45], v[49:50]
	s_waitcnt vmcnt(8)
	v_add_f64 v[14:15], v[69:70], -v[14:15]
	s_waitcnt vmcnt(7)
	v_add_f64 v[3:4], v[71:72], -v[3:4]
	v_add_f64 v[20:21], v[20:21], v[49:50]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[11:12], v[42:43], v[34:35], -v[12:13]
	s_waitcnt vmcnt(5)
	v_add_f64 v[7:8], v[7:8], v[59:60]
	v_add_f64 v[34:35], v[55:56], -v[53:54]
	v_mul_f64 v[55:56], v[44:45], v[59:60]
	s_waitcnt vmcnt(4)
	v_add_f64 v[9:10], v[9:10], v[67:68]
	v_mul_f64 v[59:60], v[44:45], v[67:68]
	v_fma_f64 v[42:43], v[42:43], s[18:19], -v[61:62]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[18:19], s[2:3], v[22:23], v[18:19]
	v_fma_f64 v[22:23], v[53:54], s[18:19], -v[32:33]
	s_load_b64 s[2:3], s[16:17], 0x0
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, dz2tz1@rel32@lo+4
	s_addc_u32 s17, s17, dz2tz1@rel32@hi+12
	s_getpc_b64 s[20:21]
	s_add_u32 s20, s20, dz4tz1@rel32@lo+4
	s_addc_u32 s21, s21, dz4tz1@rel32@hi+12
	s_getpc_b64 s[22:23]
	s_add_u32 s22, s22, dz3tz1@rel32@lo+4
	s_addc_u32 s23, s23, dz3tz1@rel32@hi+12
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, zzcon4@rel32@lo+4
	s_addc_u32 s25, s25, zzcon4@rel32@hi+12
	s_load_b64 s[16:17], s[16:17], 0x0
	s_load_b64 s[20:21], s[20:21], 0x0
	s_load_b64 s[22:23], s[22:23], 0x0
	s_load_b64 s[24:25], s[24:25], 0x0
	v_fma_f64 v[38:39], v[40:41], v[47:48], -v[38:39]
	s_waitcnt vmcnt(3)
	v_add_f64 v[13:14], v[14:15], v[75:76]
	s_waitcnt vmcnt(2)
	v_add_f64 v[3:4], v[3:4], v[77:78]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[32:33], s[2:3], s[26:27]
	s_waitcnt vmcnt(1)
	v_add_f64 v[1:2], v[1:2], v[73:74]
	v_fma_f64 v[20:21], v[20:21], s[20:21], v[26:27]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[11:12], v[53:54], v[36:37], v[11:12]
	v_fma_f64 v[7:8], s[16:17], v[7:8], v[30:31]
	v_add_f64 v[26:27], v[34:35], v[65:66]
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, dz1tz1@rel32@lo+4
	s_addc_u32 s17, s17, dz1tz1@rel32@hi+12
	v_fma_f64 v[9:10], s[22:23], v[9:10], v[28:29]
	s_getpc_b64 s[18:19]
	s_add_u32 s18, s18, zzcon5@rel32@lo+4
	s_addc_u32 s19, s19, zzcon5@rel32@hi+12
	s_load_b64 s[16:17], s[16:17], 0x0
	s_load_b64 s[18:19], s[18:19], 0x0
	v_fma_f64 v[15:16], v[16:17], s[24:25], v[18:19]
	v_mul_f64 v[17:18], v[44:45], v[22:23]
	v_add_f64 v[22:23], v[47:48], -v[49:50]
	v_fma_f64 v[28:29], v[40:41], v[51:52], -v[55:56]
	v_fma_f64 v[30:31], v[40:41], v[57:58], -v[59:60]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[1:2], s[16:17], v[1:2], v[24:25]
	v_fma_f64 v[5:6], v[5:6], v[32:33], v[20:21]
	s_mov_b32 s16, 0
	v_fma_f64 v[7:8], s[2:3], v[13:14], v[7:8]
	v_fma_f64 v[3:4], s[2:3], v[3:4], v[9:10]
	v_fma_f64 v[9:10], v[26:27], s[6:7], v[38:39]
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, tz2@rel32@lo+4
	s_addc_u32 s3, s3, tz2@rel32@hi+12
	s_cmp_lt_i32 s15, 2
	v_fma_f64 v[11:12], s[18:19], v[11:12], v[15:16]
	v_fma_f64 v[13:14], v[40:41], v[42:43], -v[17:18]
	s_load_b64 s[2:3], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[17:18], -s[2:3], v[22:23], v[1:2]
	v_fma_f64 v[19:20], -s[2:3], v[28:29], v[7:8]
	v_fma_f64 v[21:22], -s[2:3], v[30:31], v[3:4]
	v_fma_f64 v[23:24], -s[2:3], v[9:10], v[5:6]
	v_fma_f64 v[25:26], -s[2:3], v[13:14], v[11:12]
	s_mov_b32 s2, -1
	s_cbranch_scc1 .LBB6_68
; %bb.64:                               ; %LeafBlock2378
	s_cmp_eq_u32 s15, 2
	s_cbranch_scc0 .LBB6_69
; %bb.65:                               ; %.preheader1722.preheader
	s_lshl_b32 s0, s9, 2
	s_mul_i32 s2, s9, s13
	s_add_i32 s0, s14, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v19
	v_mov_b32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v7, v23
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v46 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_mov_b32_e32 v6, v22
	v_mov_b32_e32 v8, v24
	s_add_i32 s1, s14, s1
	s_mul_i32 s17, s8, s0
	s_add_i32 s0, s14, s2
	s_mul_i32 s18, s8, s1
	s_mul_i32 s19, s8, s0
	s_mov_b64 s[6:7], 0
.LBB6_66:                               ; %.preheader1722
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v12, s19, v11
	v_add_nc_u32_e32 v14, s18, v11
	v_add_nc_u32_e32 v27, s12, v11
	v_add_nc_u32_e32 v29, s17, v11
	s_cmp_eq_u32 s6, 1
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v28, 31, v27
	v_ashrrev_i32_e32 v30, 31, v29
	v_add_nc_u32_e32 v11, s33, v11
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	global_load_b64 v[12:13], v[12:13], off
	v_add_co_u32 v27, vcc_lo, s4, v27
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s4, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_load_b64 v[27:28], v[27:28], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[29:30], v[29:30], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(3)
	v_mul_f64 v[12:13], v[12:13], -4.0
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], 0x40180000, v[14:15], v[12:13]
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	v_cndmask_b32_e64 v14, v14, v6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v15, v5, s0
	v_cndmask_b32_e64 v14, v14, v8, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, v15, v7, s1
	v_cndmask_b32_e64 v15, v14, v10, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v16, v9, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], v[27:28], -4.0, v[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[29:30], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], 0xbfd00000, v[12:13], v[14:15]
	v_cndmask_b32_e64 v10, v10, v13, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v9, v12, s2
	v_cndmask_b32_e64 v8, v8, v13, s1
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v6, v6, v13, s0
	v_cndmask_b32_e64 v5, v5, v12, s0
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_cndmask_b32_e64 v2, v2, v13, s3
	v_cndmask_b32_e64 v1, v1, v12, s3
	s_cbranch_scc0 .LBB6_66
; %bb.67:                               ; %Flow2382
	s_mov_b32 s0, 0
	s_branch .LBB6_70
.LBB6_68:
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
	s_branch .LBB6_71
.LBB6_69:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
.LBB6_70:                               ; %Flow2393
	s_mov_b32 s2, 0
.LBB6_71:                               ; %Flow2392
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB6_73
; %bb.72:                               ; %LeafBlock2376
	s_cmp_lg_u32 s15, 1
	s_mov_b32 s16, -1
	s_cselect_b32 s0, -1, 0
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
.LBB6_73:                               ; %Flow2394
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_91
; %bb.74:
	s_add_i32 s0, s10, -3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s15, s0
	s_cbranch_scc0 .LBB6_79
; %bb.75:
	s_cmp_lg_u32 s15, s0
	s_cbranch_scc0 .LBB6_80
; %bb.76:
	s_add_i32 s0, s10, -2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s15, s0
	s_cbranch_scc1 .LBB6_81
; %bb.77:                               ; %.preheader1718
	s_add_i32 s0, s15, -2
	s_mul_i32 s1, s9, s13
	s_mul_i32 s0, s9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v19
	v_mov_b32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v7, v23
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v46 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_mov_b32_e32 v6, v22
	v_mov_b32_e32 v8, v24
	s_add_i32 s1, s14, s1
	s_add_i32 s0, s14, s0
	s_mul_i32 s10, s8, s1
	s_mul_i32 s16, s8, s0
	s_mov_b64 s[6:7], 0
.LBB6_78:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v12, s16, v11
	v_add_nc_u32_e32 v14, s10, v11
	v_add_nc_u32_e32 v27, s11, v11
	s_cmp_eq_u32 s6, 1
	v_add_nc_u32_e32 v11, s33, v11
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_add_co_u32 v27, vcc_lo, s4, v27
	s_clause 0x1
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[27:28], v[27:28], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], v[14:15], -4.0, v[12:13]
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v6, s0
	v_cndmask_b32_e64 v15, v15, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v8, s1
	v_cndmask_b32_e64 v16, v15, v7, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v14, v10, s2
	v_cndmask_b32_e64 v14, v16, v9, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], 0x40140000, v[27:28], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], 0xbfd00000, v[12:13], v[14:15]
	v_cndmask_b32_e32 v4, v4, v13, vcc_lo
	v_cndmask_b32_e64 v10, v10, v13, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v12, s2
	v_cndmask_b32_e64 v8, v8, v13, s1
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v6, v6, v13, s0
	v_cndmask_b32_e64 v5, v5, v12, s0
	v_cndmask_b32_e32 v3, v3, v12, vcc_lo
	v_cndmask_b32_e64 v2, v2, v13, s3
	v_cndmask_b32_e64 v1, v1, v12, s3
	s_cbranch_scc0 .LBB6_78
	s_branch .LBB6_82
.LBB6_79:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
	s_branch .LBB6_87
.LBB6_80:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
	s_branch .LBB6_83
.LBB6_81:
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_dual_mov_b32 v3, v19 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v5, v21 :: v_dual_mov_b32 v6, v22
	v_dual_mov_b32 v7, v23 :: v_dual_mov_b32 v8, v24
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v27 :: v_dual_mov_b32 v12, v28
	v_dual_mov_b32 v13, v29 :: v_dual_mov_b32 v14, v30
	v_dual_mov_b32 v15, v31 :: v_dual_mov_b32 v16, v32
.LBB6_82:                               ; %Flow2384
	s_mov_b32 s0, 0
.LBB6_83:                               ; %Flow2386
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_86
; %bb.84:                               ; %.preheader1716
	s_add_i32 s0, s15, -2
	s_mul_i32 s1, s9, s13
	s_mul_i32 s0, s9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v19
	v_mov_b32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v7, v23
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v46 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_mov_b32_e32 v6, v22
	v_mov_b32_e32 v8, v24
	s_add_i32 s1, s14, s1
	s_add_i32 s0, s14, s0
	s_mul_i32 s10, s8, s1
	s_mul_i32 s16, s8, s0
	s_mov_b64 s[6:7], 0
.LBB6_85:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v12, s16, v11
	v_add_nc_u32_e32 v14, s10, v11
	v_add_nc_u32_e32 v27, s11, v11
	v_add_nc_u32_e32 v29, s12, v11
	s_cmp_eq_u32 s6, 1
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v28, 31, v27
	v_ashrrev_i32_e32 v30, 31, v29
	v_add_nc_u32_e32 v11, s33, v11
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_add_co_u32 v27, vcc_lo, s4, v27
	s_clause 0x1
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s4, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_load_b64 v[27:28], v[27:28], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[29:30], v[29:30], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(2)
	v_fma_f64 v[12:13], v[14:15], -4.0, v[12:13]
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v6, s0
	v_cndmask_b32_e64 v15, v15, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v8, s1
	v_cndmask_b32_e64 v16, v15, v7, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v14, v10, s2
	v_cndmask_b32_e64 v14, v16, v9, s2
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], 0x40180000, v[27:28], v[12:13]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[29:30], -4.0, v[12:13]
	v_fma_f64 v[12:13], 0xbfd00000, v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v10, v13, s2
	v_cndmask_b32_e64 v9, v9, v12, s2
	v_cndmask_b32_e64 v8, v8, v13, s1
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v6, v6, v13, s0
	v_cndmask_b32_e64 v5, v5, v12, s0
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_cndmask_b32_e64 v2, v2, v13, s3
	v_cndmask_b32_e64 v1, v1, v12, s3
	s_cbranch_scc0 .LBB6_85
.LBB6_86:                               ; %Flow2387
	s_mov_b32 s0, 0
.LBB6_87:                               ; %Flow2389
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB6_90
; %bb.88:                               ; %.preheader
	s_add_i32 s0, s15, 2
	s_add_i32 s15, s15, -2
	s_mul_i32 s0, s9, s0
	s_mul_i32 s1, s9, s13
	s_add_i32 s0, s14, s0
	s_mul_i32 s2, s9, s15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v3, v19
	v_mov_b32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v7, v23
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v46 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_mov_b32_e32 v6, v22
	v_mov_b32_e32 v8, v24
	s_mul_i32 s10, s8, s0
	s_add_i32 s0, s14, s1
	s_add_i32 s1, s14, s2
	s_mul_i32 s13, s8, s0
	s_mul_i32 s15, s8, s1
	s_mov_b64 s[6:7], 0
.LBB6_89:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v12, s15, v11
	v_add_nc_u32_e32 v14, s13, v11
	v_add_nc_u32_e32 v27, s11, v11
	v_add_nc_u32_e32 v29, s12, v11
	v_add_nc_u32_e32 v31, s10, v11
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	v_ashrrev_i32_e32 v28, 31, v27
	v_ashrrev_i32_e32 v30, 31, v29
	v_ashrrev_i32_e32 v32, 31, v31
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_lshlrev_b64 v[27:28], 3, v[27:28]
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	v_lshlrev_b64 v[31:32], 3, v[31:32]
	s_cmp_eq_u32 s6, 1
	v_add_co_u32 v12, vcc_lo, s4, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_add_co_u32 v27, vcc_lo, s4, v27
	s_clause 0x1
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s4, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
	global_load_b64 v[27:28], v[27:28], off
	v_add_co_u32 v31, vcc_lo, s4, v31
	global_load_b64 v[29:30], v[29:30], off
	v_add_co_ci_u32_e32 v32, vcc_lo, s5, v32, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_add_nc_u32_e32 v11, s33, v11
	global_load_b64 v[31:32], v[31:32], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(3)
	v_fma_f64 v[12:13], v[14:15], -4.0, v[12:13]
	v_dual_cndmask_b32 v14, v2, v4 :: v_dual_cndmask_b32 v15, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v6, s0
	v_cndmask_b32_e64 v15, v15, v5, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v8, s1
	v_cndmask_b32_e64 v16, v15, v7, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v14, v10, s2
	v_cndmask_b32_e64 v14, v16, v9, s2
	s_waitcnt vmcnt(2)
	v_fma_f64 v[12:13], 0x40180000, v[27:28], v[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[29:30], -4.0, v[12:13]
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[31:32], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], 0xbfd00000, v[12:13], v[14:15]
	v_cndmask_b32_e64 v10, v10, v13, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v9, v12, s2
	v_cndmask_b32_e64 v8, v8, v13, s1
	v_cndmask_b32_e64 v7, v7, v12, s1
	v_cndmask_b32_e64 v6, v6, v13, s0
	v_cndmask_b32_e64 v5, v5, v12, s0
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_cndmask_b32_e64 v2, v2, v13, s3
	v_cndmask_b32_e64 v1, v1, v12, s3
	s_cbranch_scc0 .LBB6_89
.LBB6_90:                               ; %Flow2390
	s_mov_b32 s16, 0
.LBB6_91:                               ; %Flow2395
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB6_95
; %bb.92:                               ; %.preheader1720.preheader
	s_mul_i32 s0, s9, 3
	s_add_i32 s1, s14, s9
	s_add_i32 s14, s14, s0
	s_mul_i32 s9, s8, s1
	s_mul_i32 s8, s8, s14
	s_mov_b64 s[6:7], 0
.LBB6_93:                               ; %.preheader1720
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s12, v46
	v_add_nc_u32_e32 v3, s9, v46
	v_add_nc_u32_e32 v5, s8, v46
	s_cmp_eq_u32 s6, 1
	v_add_nc_u32_e32 v46, s33, v46
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	global_load_b64 v[5:6], v[5:6], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s6, 5
	s_waitcnt vmcnt(2)
	v_mul_f64 v[1:2], v[1:2], -4.0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], 0x40140000, v[3:4], v[1:2]
	v_dual_cndmask_b32 v4, v17, v19 :: v_dual_cndmask_b32 v3, v18, v20
	v_cndmask_b32_e64 v4, v4, v21, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v22, s0
	v_cndmask_b32_e64 v3, v3, v24, s1
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[5:6], v[1:2]
	v_cndmask_b32_e64 v5, v4, v23, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v3, v26, s2
	v_cndmask_b32_e64 v3, v5, v25, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], 0xbfd00000, v[1:2], v[3:4]
	v_cndmask_b32_e64 v26, v26, v2, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v25, v25, v1, s2
	v_cndmask_b32_e64 v24, v24, v2, s1
	v_cndmask_b32_e64 v23, v23, v1, s1
	v_cndmask_b32_e64 v22, v22, v2, s0
	v_cndmask_b32_e64 v21, v21, v1, s0
	v_dual_cndmask_b32 v20, v20, v2 :: v_dual_cndmask_b32 v19, v19, v1
	v_cndmask_b32_e64 v18, v18, v2, s3
	v_cndmask_b32_e64 v17, v17, v1, s3
	s_cbranch_scc0 .LBB6_93
; %bb.94:                               ; %Flow2391
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v1, v17 :: v_dual_mov_b32 v2, v18
	v_dual_mov_b32 v3, v19 :: v_dual_mov_b32 v4, v20
	v_dual_mov_b32 v5, v21 :: v_dual_mov_b32 v6, v22
	v_dual_mov_b32 v7, v23 :: v_dual_mov_b32 v8, v24
	v_dual_mov_b32 v9, v25 :: v_dual_mov_b32 v10, v26
	v_dual_mov_b32 v11, v27 :: v_dual_mov_b32 v12, v28
	v_dual_mov_b32 v13, v29 :: v_dual_mov_b32 v14, v30
	v_dual_mov_b32 v15, v31 :: v_dual_mov_b32 v16, v32
.LBB6_95:                               ; %.loopexit1715
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dt@rel32@lo+4
	s_addc_u32 s1, s1, dt@rel32@hi+12
	s_mov_b64 s[6:7], 0
	s_load_b64 s[4:5], s[0:1], 0x0
.LBB6_96:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s6, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s6, 2
	v_dual_cndmask_b32 v11, v2, v4 :: v_dual_cndmask_b32 v12, v1, v3
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s6, 3
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v11, v6, s0
	v_cndmask_b32_e64 v12, v12, v5, s0
	s_cmp_eq_u32 s6, 4
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e64 v11, v11, v8, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v12, v7, s1
	s_cmp_eq_u32 s6, 0
	s_cselect_b32 s3, -1, 0
	v_cndmask_b32_e64 v12, v11, v10, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v13, v9, s2
	s_add_u32 s6, s6, 1
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s6, 5
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[11:12], v[11:12], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v10, v12, s2
	v_cndmask_b32_e64 v9, v9, v11, s2
	v_cndmask_b32_e64 v8, v8, v12, s1
	v_cndmask_b32_e64 v7, v7, v11, s1
	v_cndmask_b32_e64 v6, v6, v12, s0
	v_cndmask_b32_e64 v5, v5, v11, s0
	v_dual_cndmask_b32 v4, v4, v12 :: v_dual_cndmask_b32 v3, v3, v11
	v_cndmask_b32_e64 v2, v2, v12, s3
	v_cndmask_b32_e64 v1, v1, v11, s3
	s_cbranch_scc1 .LBB6_96
.LBB6_97:                               ; %Flow2427
	s_or_b32 exec_lo, exec_lo, s30
.LBB6_98:                               ; %.loopexit
	s_mul_i32 s11, s11, 5
	s_mov_b64 s[2:3], 0
	v_mad_u32_u24 v0, v0, 5, s11
.LBB6_99:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s2, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v1, v3 :: v_dual_add_nc_u32 v11, s2, v0
	v_cndmask_b32_e32 v13, v2, v4, vcc_lo
	s_cmp_eq_u32 s2, 2
	v_ashrrev_i32_e32 v12, 31, v11
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s2, 3
	v_cndmask_b32_e64 v13, v13, v6, s0
	v_cndmask_b32_e64 v14, v14, v5, s0
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 4
	v_cndmask_b32_e32 v13, v13, v8, vcc_lo
	v_cndmask_b32_e32 v15, v14, v7, vcc_lo
	s_cselect_b32 s0, -1, 0
	v_add_co_u32 v11, vcc_lo, s28, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v12, vcc_lo
	v_cndmask_b32_e64 v14, v13, v10, s0
	v_cndmask_b32_e64 v13, v15, v9, s0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s2, 5
	global_store_b64 v[11:12], v[13:14], off
	s_cbranch_scc1 .LBB6_99
; %bb.100:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 84
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 94
		.amdhsa_next_free_sgpr 52
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,"axG",@progbits,_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii,comdat
.Lfunc_end6:
	.size	_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii, .Lfunc_end6-_ZL20compute_rhs_kernel_2PdS_S_S_S_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13784
; NumSgprs: 54
; NumVgprs: 94
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 54
; NumVGPRsForWavesPerEU: 94
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL13txinvr_kernelPdS_S_S_S_S_S_iii,"axG",@progbits,_ZL13txinvr_kernelPdS_S_S_S_S_S_iii,comdat
	.globl	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii ; -- Begin function _ZL13txinvr_kernelPdS_S_S_S_S_S_iii
	.p2align	8
	.type	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii,@function
_ZL13txinvr_kernelPdS_S_S_S_S_S_iii:    ; @_ZL13txinvr_kernelPdS_S_S_S_S_S_iii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x38
	s_add_i32 s4, s15, 1
	v_add_nc_u32_e32 v0, 1, v0
	s_add_i32 s20, s14, 1
	s_load_b256 s[12:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s4, s3
	s_load_b256 s[4:11], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_add_i32 s10, s3, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s10, s2, v[0:1]
	v_mul_u32_u24_e32 v0, 5, v0
	s_mul_i32 s2, s2, 5
	s_mul_i32 s0, s2, s20
	s_mul_i32 s3, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v5, s3, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, bt@rel32@lo+4
	s_addc_u32 s1, s1, bt@rel32@hi+12
	s_mov_b32 s2, 0x9999999a
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v6, 1, v5
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_add_nc_u32_e32 v20, 2, v5
	v_add_nc_u32_e32 v30, 3, v5
	s_mov_b32 s3, 0x3fd99999
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_add_co_u32 v8, vcc_lo, s14, v1
	global_load_b64 v[3:4], v[3:4], off
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v2, vcc_lo
	v_add_co_u32 v10, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v7, vcc_lo
	global_load_b64 v[7:8], v[8:9], off
	global_load_b64 v[12:13], v[10:11], off
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v31, 31, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[14:15], 3, v[5:6]
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[30:31], 3, v[30:31]
	v_add_nc_u32_e32 v5, 4, v5
	v_add_co_u32 v14, vcc_lo, s8, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v17, vcc_lo, s7, v2, vcc_lo
	global_load_b64 v[18:19], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	v_add_co_u32 v24, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v25, vcc_lo, s17, v2, vcc_lo
	v_add_co_u32 v20, vcc_lo, s8, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s9, v21, vcc_lo
	global_load_b64 v[24:25], v[24:25], off
	global_load_b64 v[26:27], v[20:21], off
	v_add_co_u32 v32, vcc_lo, s18, v1
	v_add_co_ci_u32_e32 v33, vcc_lo, s19, v2, vcc_lo
	v_add_co_u32 v30, vcc_lo, s8, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, s9, v31, vcc_lo
	global_load_b64 v[32:33], v[32:33], off
	global_load_b64 v[34:35], v[30:31], off
	v_ashrrev_i32_e32 v6, 31, v5
	v_add_co_u32 v0, vcc_lo, s12, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[38:39], v[5:6], off
	s_waitcnt vmcnt(10)
	v_mul_f64 v[22:23], v[3:4], v[3:4]
	v_div_scale_f64 v[28:29], null, v[22:23], v[22:23], 1.0
	v_div_scale_f64 v[42:43], vcc_lo, 1.0, v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[36:37], v[28:29]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[40:41], -v[28:29], v[36:37], 1.0
	v_fma_f64 v[36:37], v[36:37], v[40:41], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[40:41], -v[28:29], v[36:37], 1.0
	v_fma_f64 v[36:37], v[36:37], v[40:41], v[36:37]
	s_waitcnt vmcnt(8)
	v_mul_f64 v[40:41], v[7:8], v[12:13]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[7:8], v[7:8], v[18:19], -v[12:13]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[12:13], v[32:33], v[18:19], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[44:45], v[42:43], v[36:37]
	v_fma_f64 v[16:17], v[18:19], v[16:17], -v[40:41]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[12:13], v[12:13], -v[0:1]
	v_fma_f64 v[28:29], -v[28:29], v[44:45], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], -v[24:25], v[26:27], v[16:17]
	v_fma_f64 v[24:25], v[24:25], v[18:19], -v[26:27]
	v_div_fmas_f64 v[28:29], v[28:29], v[36:37], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[32:33], v[34:35], v[16:17]
	v_div_fixup_f64 v[22:23], v[28:29], v[22:23], 1.0
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[28:29], v[0:1], s[0:1]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[38:39], v[16:17]
	v_mul_f64 v[0:1], v[0:1], v[24:25]
	v_mul_f64 v[22:23], v[22:23], s[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[3:4], v[28:29]
	v_mul_f64 v[36:37], v[22:23], v[16:17]
	v_fma_f64 v[16:17], -v[22:23], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[36:37]
	v_fma_f64 v[18:19], -v[7:8], v[28:29], v[2:3]
	v_fma_f64 v[2:3], v[7:8], v[28:29], v[2:3]
	s_clause 0x4
	global_store_b64 v[14:15], v[16:17], off
	global_store_b64 v[10:11], v[12:13], off
	global_store_b64 v[20:21], v[0:1], off
	global_store_b64 v[30:31], v[18:19], off
	global_store_b64 v[5:6], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL13txinvr_kernelPdS_S_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 68
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL13txinvr_kernelPdS_S_S_S_S_S_iii,"axG",@progbits,_ZL13txinvr_kernelPdS_S_S_S_S_S_iii,comdat
.Lfunc_end7:
	.size	_ZL13txinvr_kernelPdS_S_S_S_S_S_iii, .Lfunc_end7-_ZL13txinvr_kernelPdS_S_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 828
; NumSgprs: 23
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZL14x_solve_kernelPdS_S_S_S_S_iii,"axG",@progbits,_ZL14x_solve_kernelPdS_S_S_S_S_iii,comdat
	.globl	_ZL14x_solve_kernelPdS_S_S_S_S_iii ; -- Begin function _ZL14x_solve_kernelPdS_S_S_S_S_iii
	.p2align	8
	.type	_ZL14x_solve_kernelPdS_S_S_S_S_iii,@function
_ZL14x_solve_kernelPdS_S_S_S_S_iii:     ; @_ZL14x_solve_kernelPdS_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x30
	v_and_b32_e32 v46, 0x3ff, v0
	v_bfe_u32 v45, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s40, s14, s3
	s_mul_i32 s6, s15, s2
	v_add_nc_u32_e32 v38, s40, v46
	v_add_nc_u32_e32 v39, s6, v45
	s_add_i32 s2, s18, -1
	s_add_i32 s3, s17, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v40, 1, v38
	v_add_nc_u32_e32 v41, 1, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v40
	v_cmp_gt_i32_e64 s2, s3, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB8_86
; %bb.1:
	s_mov_b32 s2, 0
	s_add_i32 s7, s18, -2
	s_mov_b32 s3, s2
	v_mov_b32_e32 v0, 0
	s_lshl_b32 s19, s16, 2
	v_mul_lo_u32 v50, v40, s17
	v_mad_u64_u32 v[4:5], null, s7, s19, v[38:39]
	v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v3, v0
	s_add_i32 s33, s17, -2
	s_mul_i32 s48, s16, 5
	v_mad_u64_u32 v[7:8], null, v4, s33, v[39:40]
	scratch_store_b128 off, v[0:3], off offset:16
	v_mov_b32_e32 v1, 0x3ff00000
	s_clause 0x1
	s_load_b128 s[20:23], s[0:1], 0x20
	s_load_b256 s[8:15], s[0:1], 0x0
	v_add_nc_u32_e32 v53, v50, v41
	s_mul_i32 s47, s16, s7
	s_mov_b32 s24, 0x9999999a
	s_clause 0x1
	scratch_store_b128 off, v[0:3], off offset:32
	scratch_store_b64 off, v[5:6], off offset:48
	v_mad_u64_u32 v[2:3], null, s7, s48, v[38:39]
	v_ashrrev_i32_e32 v8, 31, v7
	v_mad_u64_u32 v[3:4], null, s47, 6, v[38:39]
	v_mad_u64_u32 v[11:12], null, s47, 7, v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_mad_u64_u32 v[9:10], null, v2, s33, v[39:40]
	v_lshl_add_u32 v4, s47, 3, v38
	v_mad_u64_u32 v[12:13], null, v3, s33, v[39:40]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v8, vcc_lo
	v_ashrrev_i32_e32 v10, 31, v9
	v_mad_u64_u32 v[7:8], null, v11, s33, v[39:40]
	global_store_b64 v[2:3], v[5:6], off
	v_ashrrev_i32_e32 v13, 31, v12
	v_lshlrev_b64 v[2:3], 3, v[9:10]
	v_mad_u64_u32 v[9:10], null, v4, s33, v[39:40]
	v_mul_lo_u32 v51, v53, s16
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[11:12], 3, v[12:13]
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v11, vcc_lo, s20, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s21, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s21, v8, vcc_lo
	s_mov_b32 s26, 0x55555555
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s20, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v10, vcc_lo
	s_mov_b32 s28, 0xf5c28f5b
	s_mov_b32 s25, 0x3fb99999
	s_mov_b32 s27, 0x3ff55555
	s_mov_b32 s29, 0x3fff5c28
	s_mov_b64 s[30:31], 0
	s_clause 0x3
	global_store_b64 v[2:3], v[5:6], off
	global_store_b64 v[11:12], v[0:1], off
	global_store_b64 v[7:8], v[5:6], off
	global_store_b64 v[9:10], v[5:6], off
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB8_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, s30, v51
	s_cmp_eq_u32 s30, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s30, 1
	global_load_b64 v[4:5], v[4:5], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s30, 2
	s_cselect_b32 s1, -1, 0
	s_waitcnt vmcnt(1)
	v_mul_f64 v[16:17], v[10:11], s[24:25]
	v_fma_f64 v[10:11], v[10:11], s[24:25], 0x3fe80000
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e64 v9, v9, v5, s1
	v_cndmask_b32_e64 v8, v8, v4, s1
	v_cndmask_b32_e64 v7, v7, v5, s0
	v_cndmask_b32_e64 v6, v6, v4, s0
	v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
	v_fma_f64 v[18:19], v[16:17], s[28:29], 0x3fe80000
	v_fma_f64 v[16:17], v[16:17], s[26:27], 0x3fe80000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v23, v2, v18, vcc_lo
	v_cmp_gt_f64_e64 s2, v[16:17], v[18:19]
	v_cndmask_b32_e64 v20, v15, v19, s1
	v_cndmask_b32_e64 v21, v14, v18, s1
	v_cndmask_b32_e32 v22, v3, v19, vcc_lo
	v_cndmask_b32_e64 v19, v13, v19, s0
	v_cndmask_b32_e64 v18, v12, v18, s0
	v_dual_cndmask_b32 v3, v3, v17 :: v_dual_cndmask_b32 v2, v2, v16
	v_cndmask_b32_e64 v12, v12, v16, s0
	v_cndmask_b32_e64 v13, v13, v17, s0
	v_cndmask_b32_e64 v14, v14, v16, s1
	v_cndmask_b32_e64 v15, v15, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v18, v12, s2
	v_cndmask_b32_e64 v13, v19, v13, s2
	v_cndmask_b32_e64 v16, v22, v3, s2
	v_cndmask_b32_e64 v17, v23, v2, s2
	v_cndmask_b32_e64 v14, v21, v14, s2
	v_cndmask_b32_e64 v15, v20, v15, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v2, v16, v13, s0
	v_cndmask_b32_e64 v18, v17, v12, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v2, v15, s1
	v_cndmask_b32_e64 v2, v18, v14, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e64 s2, v[2:3], v[10:11]
	s_and_b32 s3, s2, s1
	s_and_b32 s4, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v14, v14, v10, s3
	v_cndmask_b32_e64 v12, v12, v10, s4
	v_cndmask_b32_e64 v10, v17, v10, s2
	v_cndmask_b32_e64 v13, v13, v11, s4
	v_cndmask_b32_e64 v16, v16, v11, s2
	v_cndmask_b32_e64 v11, v15, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v10, v12, s0
	v_cndmask_b32_e64 v3, v16, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v2, v14, s1
	v_cndmask_b32_e64 v3, v3, v11, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, 0x3fe80000, v[2:3]
	s_and_b32 s1, s2, s1
	s_and_b32 s0, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v15, v11, 0x3fe80000, s1
	v_cndmask_b32_e64 v13, v13, 0x3fe80000, s0
	v_cndmask_b32_e64 v3, v16, 0x3fe80000, s2
	v_cndmask_b32_e64 v14, v14, 0, s1
	v_cndmask_b32_e64 v12, v12, 0, s0
	v_cndmask_b32_e64 v2, v10, 0, s2
	s_add_u32 s30, s30, 1
	s_addc_u32 s31, s31, 0
	s_cmp_lg_u32 s30, 3
	s_cbranch_scc1 .LBB8_2
; %bb.3:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dtx1@rel32@lo+4
	s_addc_u32 s1, s1, dtx1@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, c2dttx1@rel32@lo+4
	s_addc_u32 s3, s3, c2dttx1@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, dttx2@rel32@lo+4
	s_addc_u32 s25, s25, dttx2@rel32@hi+12
	s_load_b64 s[4:5], s[2:3], 0x0
	s_load_b64 s[2:3], s[24:25], 0x0
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, comz5@rel32@lo+4
	s_addc_u32 s25, s25, comz5@rel32@hi+12
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, comz4@rel32@lo+4
	s_addc_u32 s27, s27, comz4@rel32@hi+12
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, comz1@rel32@lo+4
	s_addc_u32 s29, s29, comz1@rel32@hi+12
	s_load_b64 s[24:25], s[24:25], 0x0
	s_load_b64 s[26:27], s[26:27], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	v_add_nc_u32_e64 v52, 16, 40
	s_mul_i32 s44, s47, s33
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], v[14:15], s[0:1]
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	v_fma_f64 v[10:11], v[12:13], s[4:5], 1.0
	v_add_f64 v[24:25], s[28:29], 0
	s_add_i32 s28, s19, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	s_mul_i32 s28, s7, s28
	v_fma_f64 v[18:19], v[8:9], s[2:3], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[3:4], v[0:1], -s[2:3], -v[2:3]
	v_add_f64 v[16:17], v[10:11], s[24:25]
	v_add3_u32 v0, s40, s28, v46
	v_mov_b32_e32 v1, 0
	s_mov_b32 s28, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s33
	v_mov_b32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v0, v45, v0, s6
	v_add_f64 v[18:19], v[18:19], -s[26:27]
	s_clause 0x2
	scratch_store_b128 off, v[1:4], off offset:56
	scratch_store_b128 off, v[16:19], off offset:72
	scratch_store_b64 off, v[24:25], off offset:88
.LBB8_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s28, v52
	s_add_i32 s28, s28, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s28, 40
	scratch_load_b64 v[2:3], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_add_nc_u32_e32 v0, s44, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[2:3], off
	s_cbranch_scc1 .LBB8_4
; %bb.5:
	v_add3_u32 v0, v45, v50, s6
	s_add_i32 s41, 0x110, 40
	s_mov_b32 s28, 0
	s_mov_b32 s29, s41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v48, v0, 2, v0
	v_add_nc_u32_e32 v0, 5, v48
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v47, s16, v0
.LBB8_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s28, v47
	s_add_i32 s28, s28, 1
	v_add_nc_u32_e32 v2, 5, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v0, vcc_lo, s14, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[0:1], s29 offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[2:3], s29
	s_add_i32 s29, s29, 8
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB8_6
; %bb.7:                                ; %.preheader674
	v_mov_b32_e32 v16, 0
	v_dual_mov_b32 v17, 0x3ff00000 :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v11, v9
	s_add_i32 s45, s16, -2
	v_mov_b32_e32 v19, 0
	v_add_nc_u32_e32 v49, 3, v51
	s_cmp_gt_i32 s16, 2
	s_mul_i32 s42, s18, s17
	s_cselect_b32 s49, -1, 0
	s_cmp_lt_i32 s16, 3
	s_mul_i32 s46, s7, s33
	s_mul_i32 s43, s42, s16
	s_cbranch_scc1 .LBB8_47
; %bb.8:                                ; %.lr.ph
	s_add_i32 s30, s19, 2
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, comz6@rel32@lo+4
	s_addc_u32 s29, s29, comz6@rel32@hi+12
	s_mul_i32 s30, s7, s30
	s_load_b64 s[28:29], s[28:29], 0x0
	v_add3_u32 v0, s40, s30, v46
	v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0x110
	v_mad_u64_u32 v[42:43], null, v51, 5, 10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, v0, s33
	v_add_nc_u32_e32 v54, 0x50, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_dual_mov_b32 v26, 0 :: v_dual_add_nc_u32 v55, 0x50, v2
	v_mov_b32_e32 v57, 0x3ff00000
	s_mov_b32 s30, 0x9999999a
	s_mov_b32 s34, 0x55555555
	s_mov_b32 s36, 0xf5c28f5b
	v_add3_u32 v56, v45, v0, s6
	s_add_i32 s50, s16, -3
	s_mov_b32 s31, 0x3fb99999
	s_mov_b32 s35, 0x3ff55555
	s_mov_b32 s37, 0x3fff5c28
	s_add_i32 s51, s16, -5
	s_mov_b32 s38, 0
	s_mov_b32 s52, 0
.LBB8_9:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_29 Depth 2
                                        ;     Child Loop BB8_34 Depth 2
                                        ;     Child Loop BB8_36 Depth 2
                                        ;     Child Loop BB8_38 Depth 2
                                        ;     Child Loop BB8_40 Depth 2
                                        ;     Child Loop BB8_42 Depth 2
                                        ;     Child Loop BB8_44 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s39, s52, 2
	s_cmp_lg_u32 s52, s50
	s_cbranch_scc0 .LBB8_16
; %bb.10:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_nc_u32_e32 v0, s52, v49
	v_fma_f64 v[34:35], s[4:5], v[14:15], 1.0
	s_cmp_lg_u32 s52, 0
	v_mov_b32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[0:1], v[4:5], s[30:31]
	v_fma_f64 v[4:5], v[4:5], s[30:31], 0x3fe80000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[0:1], s[34:35], 0x3fe80000
	v_fma_f64 v[0:1], v[0:1], s[36:37], 0x3fe80000
	v_cmp_gt_f64_e32 vcc_lo, v[18:19], v[0:1]
	v_dual_cndmask_b32 v1, v1, v19 :: v_dual_cndmask_b32 v0, v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_mul_f64 v[4:5], s[0:1], v[12:13]
	v_cmp_ngt_f64_e32 vcc_lo, 0x3fe80000, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[6:7], -s[2:3], -v[4:5]
	v_cndmask_b32_e32 v21, 0x3fe80000, v1, vcc_lo
	v_cndmask_b32_e32 v20, 0, v0, vcc_lo
	v_mul_f64 v[0:1], s[0:1], v[20:21]
	scratch_store_b128 off, v[26:29], off offset:96
	s_waitcnt vmcnt(0)
	v_fma_f64 v[36:37], s[2:3], v[2:3], -v[0:1]
	s_clause 0x1
	scratch_store_b128 off, v[34:37], off offset:112
	scratch_store_b64 off, v[26:27], off offset:128
	s_cbranch_scc0 .LBB8_17
; %bb.11:                               ;   in Loop: Header=BB8_9 Depth=1
	s_cmp_ge_i32 s39, s50
	s_cbranch_scc0 .LBB8_18
; %bb.12:                               ;   in Loop: Header=BB8_9 Depth=1
	s_cmp_lg_u32 s52, s51
	s_cbranch_scc0 .LBB8_19
; %bb.13:                               ;   in Loop: Header=BB8_9 Depth=1
	v_mov_b32_e32 v43, 0
	v_dual_mov_b32 v44, 0 :: v_dual_mov_b32 v31, v29
	v_mov_b32_e32 v30, v28
	v_dual_mov_b32 v32, v34 :: v_dual_mov_b32 v33, v35
	s_cmp_lg_u32 s39, s45
	s_cbranch_scc1 .LBB8_15
; %bb.14:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_f64 v[60:61], v[28:29], -s[26:27]
	v_add_f64 v[32:33], s[24:25], v[34:35]
	v_dual_mov_b32 v58, v24 :: v_dual_mov_b32 v59, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x1
	scratch_store_b128 off, v[58:61], off offset:96
	scratch_store_b64 off, v[32:33], off offset:112
	v_dual_mov_b32 v30, v60 :: v_dual_mov_b32 v31, v61
.LBB8_15:                               ; %Flow1071
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, 0
	s_branch .LBB8_20
.LBB8_16:                               ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, -1
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB8_31
.LBB8_17:                               ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB8_26
.LBB8_18:                               ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB8_23
.LBB8_19:                               ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
.LBB8_20:                               ; %Flow1072
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s53
	s_cbranch_vccnz .LBB8_22
; %bb.21:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_f64 v[60:61], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[62:63], v[34:35], s[28:29]
	v_add_f64 v[64:65], v[36:37], -s[26:27]
	v_dual_mov_b32 v58, v24 :: v_dual_mov_b32 v59, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x1
	scratch_store_b128 off, v[58:61], off offset:96
	scratch_store_b128 off, v[62:65], off offset:112
	v_dual_mov_b32 v30, v60 :: v_dual_mov_b32 v31, v61
	v_dual_mov_b32 v32, v62 :: v_dual_mov_b32 v33, v63
.LBB8_22:                               ; %Flow1073
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, 0
.LBB8_23:                               ; %Flow1074
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s53
	s_cbranch_vccnz .LBB8_25
; %bb.24:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_f64 v[60:61], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[62:63], v[34:35], s[28:29]
	v_add_f64 v[64:65], v[36:37], -s[26:27]
	v_dual_mov_b32 v58, v24 :: v_dual_mov_b32 v59, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x2
	scratch_store_b128 off, v[58:61], off offset:96
	scratch_store_b128 off, v[62:65], off offset:112
	scratch_store_b64 off, v[24:25], off offset:128
	v_dual_mov_b32 v30, v60 :: v_dual_mov_b32 v31, v61
	v_dual_mov_b32 v32, v62 :: v_dual_mov_b32 v33, v63
.LBB8_25:                               ; %Flow1075
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_mov_b32 s53, 0
.LBB8_26:                               ; %Flow1076
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s53
	s_cbranch_vccnz .LBB8_28
; %bb.27:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_f64 v[30:31], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[32:33], v[34:35], s[28:29]
	v_add_f64 v[22:23], v[36:37], -s[26:27]
	v_mov_b32_e32 v43, 0
	v_mov_b32_e32 v44, 0
	s_clause 0x1
	scratch_store_b128 off, v[30:33], off offset:104
	scratch_store_b128 off, v[22:25], off offset:120
.LBB8_28:                               ;   in Loop: Header=BB8_9 Depth=1
	v_mov_b32_e32 v0, v56
	s_mov_b32 s53, 0
.LBB8_29:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s53, v54
	s_add_i32 s53, s53, 8
	s_cmp_lg_u32 s53, 40
	scratch_load_b64 v[4:5], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], 3, v[0:1]
	v_add_nc_u32_e32 v0, s44, v0
	v_add_co_u32 v18, vcc_lo, s20, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v19, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[18:19], v[4:5], off
	s_cbranch_scc1 .LBB8_29
; %bb.30:                               ;   in Loop: Header=BB8_9 Depth=1
	v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v19, v15
	v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s53, 0
.LBB8_31:                               ; %Flow1077
                                        ;   in Loop: Header=BB8_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s53
	s_cbranch_vccz .LBB8_33
; %bb.32:                               ;   in Loop: Header=BB8_9 Depth=1
	s_add_i32 s53, s39, s19
	s_mov_b32 s39, s38
	v_mad_u64_u32 v[0:1], null, s53, s7, v[38:39]
	v_dual_mov_b32 v27, v26 :: v_dual_mov_b32 v34, s38
	v_dual_mov_b32 v28, v26 :: v_dual_mov_b32 v35, s39
	s_add_i32 s39, s53, s16
	v_dual_mov_b32 v29, v26 :: v_dual_mov_b32 v30, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[1:2], null, v0, s33, v[39:40]
	v_mad_u64_u32 v[3:4], null, s39, s7, v[38:39]
	s_add_i32 s39, s39, s16
	s_clause 0x1
	scratch_store_b128 off, v[26:29], off offset:96
	scratch_store_b64 off, v[34:35], off offset:128
	v_mad_u64_u32 v[4:5], null, s39, s7, v[38:39]
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s39, s39, s16
	v_mad_u64_u32 v[18:19], null, v3, s33, v[39:40]
	v_dual_mov_b32 v27, v57 :: v_dual_mov_b32 v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_mad_u64_u32 v[2:3], null, s39, s7, v[38:39]
	s_add_i32 s39, s39, s16
	v_mad_u64_u32 v[20:21], null, v4, s33, v[39:40]
	v_mad_u64_u32 v[3:4], null, s39, s7, v[38:39]
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_mad_u64_u32 v[4:5], null, v2, s33, v[39:40]
	v_ashrrev_i32_e32 v21, 31, v20
	global_store_b64 v[0:1], v[34:35], off
	v_lshlrev_b64 v[0:1], 3, v[18:19]
	v_mad_u64_u32 v[18:19], null, v3, s33, v[39:40]
	v_lshlrev_b64 v[2:3], 3, v[20:21]
	v_ashrrev_i32_e32 v5, 31, v4
	scratch_store_b128 off, v[26:29], off offset:112
	v_add_co_u32 v28, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v36, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v37, vcc_lo, s21, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 3, v[18:19]
	v_add_co_u32 v58, vcc_lo, s20, v0
	v_mov_b32_e32 v31, 0
	v_add_co_ci_u32_e32 v59, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v60, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v61, vcc_lo, s21, v3, vcc_lo
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v33, 0x3ff00000
	v_dual_mov_b32 v44, v31 :: v_dual_mov_b32 v23, v17
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v43, v30
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v22, v16 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v20, v14 :: v_dual_mov_b32 v21, v15
	v_mov_b32_e32 v19, v13
	s_clause 0x3
	global_store_b64 v[28:29], v[34:35], off
	global_store_b64 v[36:37], v[26:27], off
	global_store_b64 v[58:59], v[34:35], off
	global_store_b64 v[60:61], v[34:35], off
.LBB8_33:                               ;   in Loop: Header=BB8_9 Depth=1
	v_mov_b32_e32 v6, v55
	s_mov_b32 s39, 0
.LBB8_34:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s39, v42
	s_add_i32 s39, s39, 1
	s_cmp_lg_u32 s39, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v6, v[7:8], off
	v_add_nc_u32_e32 v6, 8, v6
	s_cbranch_scc1 .LBB8_34
; %bb.35:                               ;   in Loop: Header=BB8_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:32
	scratch_load_b64 v[12:13], off, off offset:48
	s_mov_b32 s39, 0
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[27:28], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[27:28], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
	v_div_fixup_f64 v[10:11], v[10:11], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[12:13]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB8_36:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s53, s39, 0x110
	s_add_i32 s39, s39, 8
	scratch_load_b64 v[12:13], off, s53
	s_cmp_lg_u32 s39, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s53
	s_cbranch_scc1 .LBB8_36
; %bb.37:                               ;   in Loop: Header=BB8_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s39, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB8_38:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v12, 0x110, s39
	s_add_i32 s53, s39, 0x110
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 24
	v_add_nc_u32_e32 v16, 40, v12
	s_clause 0x1
	scratch_load_b64 v[12:13], off, s53
	scratch_load_b64 v[14:15], v16, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[10:11], v[12:13], v[14:15]
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB8_38
; %bb.39:                               ;   in Loop: Header=BB8_9 Depth=1
	v_fma_f64 v[10:11], -v[6:7], v[43:44], v[30:31]
	v_fma_f64 v[12:13], -v[8:9], v[43:44], v[32:33]
	s_mov_b32 s39, 0
	scratch_store_b128 off, v[10:13], off offset:104
.LBB8_40:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v10, 0x110, s39
	s_add_i32 s53, s39, 0x110
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 24
	v_add_nc_u32_e32 v14, 0x50, v10
	s_clause 0x1
	scratch_load_b64 v[10:11], off, s53
	scratch_load_b64 v[12:13], v14, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], -v[43:44], v[10:11], v[12:13]
	scratch_store_b64 v14, v[10:11], off
	s_cbranch_scc1 .LBB8_40
; %bb.41:                               ;   in Loop: Header=BB8_9 Depth=1
	v_mad_u64_u32 v[10:11], null, s52, s7, v[38:39]
	s_add_i32 s39, s52, s16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, s39, s7, v[38:39]
	s_mov_b32 s39, 0
	v_mad_u64_u32 v[12:13], null, v10, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v11, s33, v[39:40]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	v_add_co_u32 v10, vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s20, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_store_b64 v[10:11], v[6:7], off
	global_store_b64 v[12:13], v[8:9], off
.LBB8_42:                               ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v6, s39, 16
	s_add_i32 s53, s39, 16
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 40
	v_add_nc_u32_e32 v10, 40, v6
	v_add_nc_u32_e32 v8, 0x50, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v10, off
	scratch_load_b64 v[8:9], v8, off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[6:7], s53
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	s_cbranch_scc1 .LBB8_42
; %bb.43:                               ; %.preheader673.preheader
                                        ;   in Loop: Header=BB8_9 Depth=1
	v_mov_b32_e32 v6, v53
	s_mov_b32 s39, 0
.LBB8_44:                               ; %.preheader673
                                        ;   Parent Loop BB8_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x110, s39
	s_add_i32 s53, s39, 0x110
	s_add_i32 s39, s39, 8
	s_cmp_lg_u32 s39, 24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v16, 40, v7
	v_add_nc_u32_e32 v7, 0x50, v7
	s_clause 0x2
	scratch_load_b64 v[8:9], off, s53
	scratch_load_b64 v[10:11], v16, off
	scratch_load_b64 v[12:13], v7, off
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[6:7]
	v_add_nc_u32_e32 v6, s43, v6
	v_add_co_u32 v14, vcc_lo, s22, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s23, v15, vcc_lo
	s_waitcnt vmcnt(2)
	global_store_b64 v[14:15], v[8:9], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[10:11], s53
	s_waitcnt vmcnt(0)
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB8_44
; %bb.45:                               ;   in Loop: Header=BB8_9 Depth=1
	v_add_nc_u32_e32 v56, s46, v56
	v_add_nc_u32_e32 v42, 5, v42
	v_add_nc_u32_e32 v53, s42, v53
	s_add_i32 s52, s52, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s52, s45
	s_cbranch_scc0 .LBB8_48
; %bb.46:                               ;   in Loop: Header=BB8_9 Depth=1
	v_dual_mov_b32 v12, v18 :: v_dual_mov_b32 v13, v19
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v14, v20 :: v_dual_mov_b32 v15, v21
	v_dual_mov_b32 v16, v22 :: v_dual_mov_b32 v17, v23
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	s_branch .LBB8_9
.LBB8_47:
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v8, v18 :: v_dual_mov_b32 v9, v19
	s_branch .LBB8_49
.LBB8_48:                               ; %._crit_edge.loopexit
	s_clause 0x1
	scratch_load_b128 v[16:19], off, off offset:32
	scratch_load_b64 v[8:9], off, off offset:48
.LBB8_49:                               ; %._crit_edge
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[6:7], null, v[16:17], v[16:17], 1.0
	v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[16:17], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[12:13]
	v_div_fixup_f64 v[10:11], v[6:7], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[18:19], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB8_50:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB8_50
; %bb.51:
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB8_52:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v14, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v18, 40, v14
	s_clause 0x1
	scratch_load_b64 v[14:15], off, s1
	scratch_load_b64 v[16:17], v18, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[10:11], v[14:15], v[16:17]
	scratch_store_b64 v18, v[14:15], off
	s_cbranch_scc1 .LBB8_52
; %bb.53:
	v_div_scale_f64 v[10:11], null, v[12:13], v[12:13], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[18:19]
	v_div_fixup_f64 v[10:11], v[10:11], v[12:13], 1.0
.LBB8_54:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s41, s0
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB8_54
; %bb.55:
	v_mad_u64_u32 v[10:11], null, s7, s45, v[38:39]
	s_add_i32 s0, s45, s16
	s_mov_b64 s[4:5], 0
	v_mad_u64_u32 v[11:12], null, s7, s0, v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, v10, s33, v[39:40]
	v_mad_u64_u32 v[14:15], null, v11, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v16, vcc_lo, s20, v10
	v_add_co_ci_u32_e32 v17, vcc_lo, s21, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s20, v12
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_store_b64 v[16:17], v[6:7], off
	global_store_b64 v[10:11], v[8:9], off
.LBB8_56:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s4, v51
	s_cmp_eq_u32 s4, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 s0, -1, 0
	global_load_b64 v[6:7], v[6:7], off
	s_cmp_eq_u32 s4, 0
	s_cselect_b32 s1, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 3
	s_waitcnt vmcnt(0)
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
	v_cndmask_b32_e64 v3, v3, v7, s0
	v_cndmask_b32_e64 v2, v2, v6, s0
	v_cndmask_b32_e64 v1, v1, v7, s1
	v_cndmask_b32_e64 v0, v0, v6, s1
	s_cbranch_scc1 .LBB8_56
; %bb.57:                               ; %.preheader672.preheader
	s_lshl_b32 s0, s47, 2
	v_add_nc_u32_e64 v8, 0x90, 40
	s_add_i32 s0, s40, s0
	v_mov_b32_e32 v9, v39
	s_add_i32 s1, s0, s18
	v_add_nc_u32_e32 v7, s0, v46
	v_add3_u32 v6, s1, v46, -2
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, s33
	v_mul_lo_u32 v6, v6, s33
.LBB8_58:                               ; %.preheader672
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v7, v9
	v_add_nc_u32_e32 v12, v6, v9
	v_add_nc_u32_e32 v14, s0, v52
	v_add_nc_u32_e32 v9, s44, v9
	v_add_nc_u32_e32 v15, s0, v8
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v10, vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s20, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 v14, v[10:11], off offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 v14, v[12:13], off
	s_clause 0x1
	scratch_store_b64 v15, v[10:11], off offset:-40
	scratch_store_b64 v15, v[12:13], off
	s_cbranch_scc1 .LBB8_58
; %bb.59:
	s_clause 0x3
	scratch_load_b64 v[18:19], off, off offset:192
	scratch_load_b64 v[22:23], off, off offset:208
	scratch_load_b64 v[24:25], off, off offset:64
	scratch_load_b64 v[26:27], off, off offset:80
	v_mul_lo_u32 v6, s48, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, v50, s48, v[6:7]
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[20:21]
	v_cndmask_b32_e64 v21, 0, 1, s49
	v_add_co_u32 v14, vcc_lo, s14, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v7, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s49
	s_clause 0x1
	global_load_b128 v[10:13], v[14:15], off offset:24
	global_load_b128 v[6:9], v[14:15], off offset:64
	s_waitcnt vmcnt(5)
	v_fma_f64 v[18:19], -s[2:3], v[0:1], v[18:19]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[22:23], s[2:3], v[4:5], v[22:23]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[0:1], s[2:3], v[0:1], v[24:25]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[24:25], -s[2:3], v[4:5], v[26:27]
	s_clause 0x3
	scratch_store_b64 off, v[18:19], off offset:192
	scratch_store_b64 off, v[22:23], off offset:208
	scratch_store_b64 off, v[0:1], off offset:64
	scratch_store_b64 off, v[24:25], off offset:80
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[10:13], off offset:296
	s_waitcnt vmcnt(0)
	scratch_store_b128 off, v[6:9], off offset:336
	s_cbranch_vccnz .LBB8_71
; %bb.60:                               ; %.preheader671.lr.ph
	s_mul_i32 s0, s18, s16
	s_add_i32 s1, s19, 2
	s_mul_i32 s0, s0, 3
	v_add_nc_u32_e32 v13, 3, v20
	v_add3_u32 v0, s40, s0, v46
	s_mul_i32 s0, s7, s1
	s_lshl_b32 s1, s47, 1
	v_add3_u32 v1, s40, s0, v46
	s_mul_i32 s47, s47, 7
	v_mul_lo_u32 v0, s17, v0
	v_add3_u32 v6, s40, s1, v46
	v_add3_u32 v9, s40, s47, v46
	v_mul_lo_u32 v8, v1, s33
	s_movk_i32 s0, 0x50
	v_dual_mov_b32 v27, 0x110 :: v_dual_add_nc_u32 v20, 4, v20
	v_add_nc_u32_e64 v22, 16, 24
	v_add3_u32 v10, v0, s17, v45
	v_mad_u64_u32 v[0:1], null, v6, s33, s[6:7]
	v_mad_u64_u32 v[6:7], null, v9, s33, s[6:7]
	v_add_nc_u32_e64 v23, 0x90, 24
	v_add_nc_u32_e64 v24, 0x90, s0
	v_add_nc_u32_e64 v25, s0, 16
	v_add3_u32 v1, v45, v8, s6
	v_add3_u32 v26, v10, s6, 1
	s_add_i32 s1, s16, -1
	s_mov_b32 s4, 0
.LBB8_61:                               ; %.preheader671
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_62 Depth 2
                                        ;     Child Loop BB8_66 Depth 2
                                        ;     Child Loop BB8_68 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v1
	s_mov_b32 s0, 0
.LBB8_62:                               ;   Parent Loop BB8_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v10, s0, v25
	v_add_nc_u32_e32 v11, s0, v24
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[8:9], 3, v[7:8]
	v_add_nc_u32_e32 v7, s44, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s20, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	scratch_store_b64 v11, v[8:9], off
	s_cbranch_scc1 .LBB8_62
; %bb.63:                               ;   in Loop: Header=BB8_61 Depth=1
	s_add_i32 s0, s4, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_mul_i32 s5, s0, 5
	s_cmp_ge_i32 s0, s1
	v_add_nc_u32_e32 v7, s5, v13
	v_add_nc_u32_e32 v9, s5, v20
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s14, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	scratch_load_b64 v[18:19], off, off offset:232
	s_clause 0x1
	global_load_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[9:10], off
	scratch_load_b64 v[9:10], off, off offset:104
	s_cbranch_scc1 .LBB8_65
; %bb.64:                               ;   in Loop: Header=BB8_61 Depth=1
	v_add_nc_u32_e32 v28, s4, v49
	s_waitcnt vmcnt(3)
	v_fma_f64 v[18:19], -s[2:3], v[2:3], v[18:19]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[9:10], s[2:3], v[2:3], v[9:10]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 3, v[28:29]
	v_add_co_u32 v28, vcc_lo, s12, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v29, vcc_lo, s13, v29, vcc_lo
	scratch_load_b64 v[30:31], off, off offset:248
	global_load_b64 v[28:29], v[28:29], off
	scratch_load_b64 v[32:33], off, off offset:120
	s_waitcnt vmcnt(1)
	v_fma_f64 v[30:31], s[2:3], v[28:29], v[30:31]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[32:33], -s[2:3], v[28:29], v[32:33]
	v_dual_mov_b32 v4, v28 :: v_dual_mov_b32 v5, v29
	s_clause 0x1
	scratch_store_b64 off, v[30:31], off offset:248
	scratch_store_b64 off, v[32:33], off offset:120
.LBB8_65:                               ;   in Loop: Header=BB8_61 Depth=1
	s_clause 0xd
	scratch_load_b128 v[28:31], off, off offset:160
	scratch_load_b128 v[32:35], off, off offset:32
	scratch_load_b64 v[36:37], off, off offset:176
	scratch_load_b64 v[68:69], off, off offset:48
	scratch_load_b128 v[50:53], off, off offset:296
	scratch_load_b128 v[54:57], off, off offset:192
	scratch_load_b64 v[78:79], off, off offset:208
	scratch_load_b128 v[58:61], off, off offset:336
	scratch_load_b64 v[80:81], off, off offset:224
	scratch_load_b64 v[82:83], off, off offset:240
	scratch_load_b128 v[62:65], off, off offset:64
	scratch_load_b64 v[84:85], off, off offset:80
	scratch_load_b64 v[86:87], off, off offset:96
	scratch_load_b64 v[88:89], off, off offset:112
	s_waitcnt vmcnt(13)
	v_div_scale_f64 v[42:43], null, v[28:29], v[28:29], 1.0
	s_waitcnt vmcnt(12)
	v_div_scale_f64 v[66:67], null, v[32:33], v[32:33], 1.0
	v_div_scale_f64 v[90:91], vcc_lo, 1.0, v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[70:71], v[42:43]
	v_rcp_f64_e32 v[72:73], v[66:67]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[74:75], -v[42:43], v[70:71], 1.0
	v_fma_f64 v[76:77], -v[66:67], v[72:73], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[70:71], v[70:71], v[74:75], v[70:71]
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[74:75], -v[42:43], v[70:71], 1.0
	v_fma_f64 v[76:77], -v[66:67], v[72:73], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[70:71], v[74:75], v[70:71]
	v_div_scale_f64 v[74:75], s0, 1.0, v[32:33], 1.0
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[76:77], v[90:91], v[70:71]
	v_mul_f64 v[92:93], v[74:75], v[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], -v[42:43], v[76:77], v[90:91]
	v_fma_f64 v[66:67], -v[66:67], v[92:93], v[74:75]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[42:43], v[42:43], v[70:71], v[76:77]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[66:67], v[66:67], v[72:73], v[92:93]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[42:43], v[42:43], v[28:29], 1.0
	v_div_fixup_f64 v[70:71], v[66:67], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[28:29], v[30:31], v[42:43]
	s_waitcnt vmcnt(11)
	v_mul_f64 v[30:31], v[42:43], v[36:37]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[32:33], v[42:43], v[50:51]
	v_mul_f64 v[66:67], v[34:35], v[70:71]
	v_mul_f64 v[68:69], v[70:71], v[68:69]
	v_mul_f64 v[34:35], v[70:71], v[52:53]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[50:51], -v[28:29], v[54:55], v[56:57]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[52:53], -v[30:31], v[54:55], v[78:79]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[70:71], -v[28:29], v[80:81], v[18:19]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[72:73], -v[30:31], v[80:81], v[82:83]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[74:75], -v[66:67], v[62:63], v[64:65]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[76:77], -v[68:69], v[62:63], v[84:85]
	v_fma_f64 v[54:55], -v[32:33], v[54:55], v[58:59]
	v_fma_f64 v[56:57], -v[34:35], v[62:63], v[60:61]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[62:63], -v[66:67], v[86:87], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[64:65], -v[68:69], v[86:87], v[88:89]
	v_fma_f64 v[58:59], -v[32:33], v[80:81], v[11:12]
	v_fma_f64 v[60:61], -v[34:35], v[86:87], v[7:8]
	v_mov_b32_e32 v9, v45
	v_mov_b32_e32 v7, v26
	s_clause 0x8
	scratch_store_b128 off, v[28:31], off offset:168
	scratch_store_b128 off, v[50:53], off offset:200
	scratch_store_b128 off, v[70:73], off offset:232
	scratch_store_b128 off, v[66:69], off offset:40
	scratch_store_b128 off, v[74:77], off offset:72
	scratch_store_b128 off, v[32:35], off offset:296
	scratch_store_b128 off, v[54:57], off offset:336
	scratch_store_b128 off, v[62:65], off offset:104
	scratch_store_b128 off, v[58:61], off offset:376
.LBB8_66:                               ;   Parent Loop BB8_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s5, v27
	v_add_nc_u32_e32 v8, s0, v23
	v_add_nc_u32_e32 v12, s0, v22
	v_add_nc_u32_e32 v34, v6, v9
	v_add_nc_u32_e32 v36, v0, v9
	s_add_i32 s5, s5, s0
	scratch_load_b64 v[10:11], v8, off
	s_add_i32 s8, s5, 24
	s_add_i32 s9, s5, 64
	scratch_load_b64 v[18:19], v12, off
	s_addk_i32 s5, 0x68
	s_clause 0x2
	scratch_load_b64 v[28:29], off, s8
	scratch_load_b64 v[30:31], off, s9
	scratch_load_b64 v[32:33], off, s5
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v35, 31, v34
	v_ashrrev_i32_e32 v37, 31, v36
	v_add_nc_u32_e32 v9, s44, v9
	s_add_i32 s0, s0, 8
	v_lshlrev_b64 v[42:43], 3, v[7:8]
	v_lshlrev_b64 v[34:35], 3, v[34:35]
	v_lshlrev_b64 v[36:37], 3, v[36:37]
	v_add_nc_u32_e32 v7, s43, v7
	s_cmp_lg_u32 s0, 16
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v42, vcc_lo, s22, v42
	v_add_co_ci_u32_e32 v43, vcc_lo, s23, v43, vcc_lo
	v_add_co_u32 v34, vcc_lo, s20, v34
	v_add_co_ci_u32_e32 v35, vcc_lo, s21, v35, vcc_lo
	v_add_co_u32 v36, vcc_lo, s20, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, s21, v37, vcc_lo
	s_waitcnt vmcnt(4)
	global_store_b64 v[34:35], v[10:11], off
	s_waitcnt vmcnt(3)
	global_store_b64 v[36:37], v[18:19], off
	s_waitcnt vmcnt(2)
	global_store_b64 v[42:43], v[28:29], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[30:31], s8
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[32:33], s9
	s_cbranch_scc1 .LBB8_66
; %bb.67:                               ; %.preheader670.preheader
                                        ;   in Loop: Header=BB8_61 Depth=1
	s_mov_b32 s0, 0
.LBB8_68:                               ; %.preheader670
                                        ;   Parent Loop BB8_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x90, s0
	v_add_nc_u32_e64 v8, s0, 16
	s_add_i32 s5, s0, 0x90
	s_add_i32 s8, s0, 16
	s_add_i32 s0, s0, 8
	v_add_nc_u32_e32 v28, 40, v7
	v_add_nc_u32_e32 v9, 0x50, v7
	v_add_nc_u32_e32 v29, 40, v8
	v_add_nc_u32_e32 v18, 0x50, v8
	s_cmp_lg_u32 s0, 40
	s_clause 0x1
	scratch_load_b64 v[7:8], v28, off
	scratch_load_b64 v[9:10], v9, off
	s_clause 0x1
	scratch_load_b64 v[11:12], v29, off
	scratch_load_b64 v[18:19], v18, off
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[7:8], s5
	s_waitcnt vmcnt(2)
	scratch_store_b64 v28, v[9:10], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[11:12], s8
	s_waitcnt vmcnt(0)
	scratch_store_b64 v29, v[18:19], off
	s_cbranch_scc1 .LBB8_68
; %bb.69:                               ;   in Loop: Header=BB8_61 Depth=1
	v_add_nc_u32_e32 v1, s46, v1
	v_add_nc_u32_e32 v26, s42, v26
	v_add_nc_u32_e32 v0, s46, v0
	v_add_nc_u32_e32 v6, s46, v6
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, s45
	s_cbranch_scc1 .LBB8_61
; %bb.70:                               ; %._crit_edge703.loopexit
	s_clause 0x3
	scratch_load_b64 v[18:19], off, off offset:192
	scratch_load_b128 v[10:13], off, off offset:296
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b64 v[0:1], off, off offset:64
.LBB8_71:                               ; %._crit_edge703
	s_clause 0x3
	scratch_load_b128 v[2:5], off, off offset:160
	scratch_load_b128 v[22:25], off, off offset:32
	scratch_load_b64 v[26:27], off, off offset:200
	scratch_load_b64 v[30:31], off, off offset:72
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[28:29], null, v[2:3], v[2:3], 1.0
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[32:33], null, v[22:23], v[22:23], 1.0
	v_div_scale_f64 v[51:52], vcc_lo, 1.0, v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_rcp_f64_e32 v[36:37], v[32:33]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[42:43], -v[28:29], v[34:35], 1.0
	v_fma_f64 v[49:50], -v[32:33], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[34:35], v[42:43], v[34:35]
	v_fma_f64 v[36:37], v[36:37], v[49:50], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], -v[28:29], v[34:35], 1.0
	v_fma_f64 v[49:50], -v[32:33], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[34:35], v[34:35], v[42:43], v[34:35]
	v_div_scale_f64 v[42:43], s0, 1.0, v[22:23], 1.0
	v_fma_f64 v[36:37], v[36:37], v[49:50], v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[49:50], v[51:52], v[34:35]
	v_mul_f64 v[53:54], v[42:43], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], -v[28:29], v[49:50], v[51:52]
	v_fma_f64 v[32:33], -v[32:33], v[53:54], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[28:29], v[28:29], v[34:35], v[49:50]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[32:33], v[32:33], v[36:37], v[53:54]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[2:3], v[28:29], v[2:3], 1.0
	v_div_fixup_f64 v[22:23], v[32:33], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[4:5], v[2:3]
	v_mul_f64 v[10:11], v[2:3], v[10:11]
	v_mul_f64 v[2:3], v[24:25], v[22:23]
	v_mul_f64 v[12:13], v[22:23], v[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], -v[4:5], v[18:19], v[26:27]
	v_fma_f64 v[6:7], -v[10:11], v[18:19], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[18:19], -v[2:3], v[0:1], v[30:31]
	v_fma_f64 v[8:9], -v[12:13], v[0:1], v[8:9]
	global_load_b64 v[0:1], v[16:17], off
	v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], v[6:7]
	v_div_scale_f64 v[34:35], vcc_lo, v[6:7], v[22:23], v[6:7]
	v_div_scale_f64 v[26:27], null, v[18:19], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[28:29], v[24:25]
	v_rcp_f64_e32 v[30:31], v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[24:25], v[28:29], 1.0
	v_fma_f64 v[32:33], -v[26:27], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[28:29], v[16:17], v[28:29]
	v_fma_f64 v[28:29], v[30:31], v[32:33], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], -v[24:25], v[16:17], 1.0
	v_fma_f64 v[32:33], -v[26:27], v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[16:17], v[30:31], v[16:17]
	v_div_scale_f64 v[30:31], s0, v[8:9], v[18:19], v[8:9]
	v_fma_f64 v[28:29], v[28:29], v[32:33], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[32:33], v[34:35], v[16:17]
	v_mul_f64 v[36:37], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], -v[24:25], v[32:33], v[34:35]
	v_fma_f64 v[26:27], -v[26:27], v[36:37], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[16:17], v[24:25], v[16:17], v[32:33]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[24:25], v[26:27], v[28:29], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[16:17], v[22:23], v[6:7]
	v_div_fixup_f64 v[8:9], v[24:25], v[18:19], v[8:9]
	s_clause 0x1
	scratch_store_b128 off, v[10:13], off offset:296
	scratch_store_b128 off, v[6:9], off offset:336
.LBB8_72:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v6, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v6, 40, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v6, off
	scratch_load_b64 v[8:9], off, s1
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], -v[0:1], v[6:7], v[8:9]
	scratch_store_b64 off, v[6:7], s1
	s_cbranch_scc1 .LBB8_72
; %bb.73:
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b128 v[10:13], off, off offset:296
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], -v[4:5], v[6:7], v[10:11]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[12:13]
	scratch_store_b128 off, v[0:3], off offset:296
.LBB8_74:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v4, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 40
	v_add_nc_u32_e32 v5, 40, v4
	v_add_nc_u32_e32 v4, 0x50, v4
	s_clause 0x1
	scratch_load_b64 v[0:1], v5, off
	scratch_load_b64 v[2:3], off, s1
	s_waitcnt vmcnt(1)
	scratch_store_b64 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v5, v[2:3], off
	s_cbranch_scc1 .LBB8_74
; %bb.75:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, bt@rel32@lo+4
	s_addc_u32 s1, s1, bt@rel32@hi+12
	v_cmp_ne_u32_e32 vcc_lo, 1, v21
	s_load_b64 s[0:1], s[0:1], 0x0
	s_cbranch_vccnz .LBB8_84
; %bb.76:                               ; %.preheader.lr.ph
	s_add_i32 s2, s16, -3
	v_add_nc_u32_e32 v1, 10, v48
	s_mul_i32 s3, s18, s2
	s_lshl_b32 s4, s16, 1
	v_add3_u32 v0, s40, s3, v46
	s_add_i32 s3, s16, -1
	v_mul_lo_u32 v6, s16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s17, v0
	v_add3_u32 v0, v0, s17, v45
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v7, v0, s6, 1
.LBB8_77:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB8_78 Depth 2
                                        ;     Child Loop BB8_82 Depth 2
	v_mad_u64_u32 v[0:1], null, s2, s7, v[38:39]
	s_add_i32 s5, s2, s16
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[1:2], null, s5, s7, v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v0, s33, v[39:40]
	v_mad_u64_u32 v[4:5], null, v1, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_mov_b32_e32 v4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
.LBB8_78:                               ;   Parent Loop BB8_77 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s8, s6, 0x110
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_nc_u32_e64 v5, 0x110, s6
	v_add_nc_u32_e32 v4, s43, v4
	s_add_i32 s6, s6, 8
	s_cmp_lg_u32 s6, 24
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s22, v8
	v_add_nc_u32_e32 v10, 40, v5
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
	v_add_nc_u32_e32 v5, 0x50, v5
	scratch_load_b64 v[10:11], v10, off
	global_load_b64 v[8:9], v[8:9], off
	scratch_load_b64 v[12:13], v5, off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[8:9], -v[0:1], v[10:11], v[8:9]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[12:13], v[8:9]
	scratch_store_b64 off, v[8:9], s8
	s_cbranch_scc1 .LBB8_78
; %bb.79:                               ;   in Loop: Header=BB8_77 Depth=1
	s_add_i32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s5, s19
	v_mad_u64_u32 v[0:1], null, s5, s18, v[40:41]
	s_add_i32 s8, s6, s16
	v_mad_u64_u32 v[1:2], null, s6, s7, v[38:39]
	s_sub_i32 s6, s8, s19
	v_mad_u64_u32 v[2:3], null, s6, s18, v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v0, s17, v[41:42]
	v_mad_u64_u32 v[8:9], null, v1, s33, v[39:40]
	s_sub_i32 s6, s6, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, v2, s17, v[41:42]
	v_mad_u64_u32 v[1:2], null, s6, s7, v[38:39]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v1, s33, v[39:40]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v8
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v9, vcc_lo
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	global_load_b64 v[12:13], v[2:3], off
	global_load_b64 v[16:17], v[8:9], off
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	scratch_load_b128 v[8:11], off, off offset:336
	v_mad_u64_u32 v[4:5], null, s8, s7, v[38:39]
	v_add_co_u32 v0, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[18:19], v[0:1], off
	global_load_b64 v[20:21], v[2:3], off
	v_mad_u64_u32 v[0:1], null, s5, s7, v[38:39]
	v_mad_u64_u32 v[1:2], null, v4, s33, v[39:40]
	s_add_i32 s5, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_ge_i32 s5, s3
	v_mad_u64_u32 v[3:4], null, v0, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[22:23], v[0:1], off
	scratch_load_b128 v[0:3], off, off offset:376
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(5)
	v_fma_f64 v[8:9], -v[16:17], v[8:9], v[12:13]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[10:11], -v[20:21], v[10:11], v[18:19]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[22:23], v[0:1], v[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], -v[4:5], v[2:3], v[10:11]
	scratch_store_b128 off, v[8:11], off offset:296
	s_cbranch_scc1 .LBB8_81
; %bb.80:                               ;   in Loop: Header=BB8_77 Depth=1
	s_clause 0x1
	scratch_load_b64 v[4:5], off, off offset:368
	scratch_load_b128 v[8:11], off, off offset:352
	v_add_f64 v[12:13], v[0:1], v[2:3]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_f64 v[0:1], v[0:1], s[0:1]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v11, 0x80000000, v11
	v_fma_f64 v[2:3], v[12:13], 0.5, -v[4:5]
	v_fma_f64 v[4:5], v[12:13], 0.5, v[4:5]
	v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v13, v9
	s_clause 0x2
	scratch_store_b128 off, v[10:13], off offset:352
	scratch_store_b128 off, v[0:3], off offset:368
	scratch_store_b64 off, v[4:5], off offset:384
.LBB8_81:                               ;   in Loop: Header=BB8_77 Depth=1
	v_mov_b32_e32 v0, -5
	s_mov_b32 s5, s41
.LBB8_82:                               ;   Parent Loop BB8_77 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s6, s5, 40
	v_add_nc_u32_e32 v10, v6, v0
	s_clause 0x2
	scratch_load_b64 v[1:2], off, s6
	scratch_load_b64 v[3:4], off, s5 offset:-40
	scratch_load_b64 v[8:9], off, s5
	v_add_co_u32 v0, s8, v0, 1
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v10, vcc_lo, s14, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s8
	s_waitcnt vmcnt(2)
	global_store_b64 v[10:11], v[1:2], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[3:4], s5
	s_add_i32 s5, s5, 8
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[8:9], s6
	s_cbranch_vccnz .LBB8_82
; %bb.83:                               ;   in Loop: Header=BB8_77 Depth=1
	v_subrev_nc_u32_e32 v7, s42, v7
	v_add_nc_u32_e32 v6, -5, v6
	s_add_i32 s5, s2, -1
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s2, s5
	s_cbranch_scc1 .LBB8_77
.LBB8_84:                               ; %._crit_edge709
	s_clause 0x2
	scratch_load_b64 v[8:9], off, off offset:384
	scratch_load_b128 v[0:3], off, off offset:368
	scratch_load_b128 v[4:7], off, off offset:352
	s_waitcnt vmcnt(1)
	v_add_f64 v[10:11], v[2:3], v[8:9]
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[10:11], 0.5
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[8:9], s[0:1], v[2:3]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[10:11], -s[0:1], v[0:1], v[12:13]
	v_fma_f64 v[12:13], s[0:1], v[0:1], v[12:13]
	v_xor_b32_e32 v1, 0x80000000, v7
	v_mov_b32_e32 v0, v6
	s_mov_b32 s0, 0
	s_clause 0x2
	global_store_b128 v[14:15], v[0:3], off offset:40
	global_store_b128 v[14:15], v[8:11], off offset:56
	global_store_b64 v[14:15], v[12:13], off offset:72
.LBB8_85:                               ; =>This Inner Loop Header: Depth=1
	scratch_load_b64 v[0:1], off, s41
	v_add_nc_u32_e32 v2, s0, v47
	s_add_i32 s0, s0, 1
	s_add_i32 s41, s41, 8
	s_cmp_lg_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
	s_cbranch_scc1 .LBB8_85
.LBB8_86:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14x_solve_kernelPdS_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 400
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 94
		.amdhsa_next_free_sgpr 54
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14x_solve_kernelPdS_S_S_S_S_iii,"axG",@progbits,_ZL14x_solve_kernelPdS_S_S_S_S_iii,comdat
.Lfunc_end8:
	.size	_ZL14x_solve_kernelPdS_S_S_S_S_iii, .Lfunc_end8-_ZL14x_solve_kernelPdS_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9200
; NumSgprs: 56
; NumVgprs: 94
; ScratchSize: 400
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 56
; NumVGPRsForWavesPerEU: 94
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL14y_solve_kernelPdS_S_S_S_S_iii,"axG",@progbits,_ZL14y_solve_kernelPdS_S_S_S_S_iii,comdat
	.globl	_ZL14y_solve_kernelPdS_S_S_S_S_iii ; -- Begin function _ZL14y_solve_kernelPdS_S_S_S_S_iii
	.p2align	8
	.type	_ZL14y_solve_kernelPdS_S_S_S_S_iii,@function
_ZL14y_solve_kernelPdS_S_S_S_S_iii:     ; @_ZL14y_solve_kernelPdS_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x30
	v_and_b32_e32 v46, 0x3ff, v0
	v_bfe_u32 v42, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s40, s14, s3
	s_mul_i32 s6, s15, s2
	v_add_nc_u32_e32 v38, s40, v46
	v_add_nc_u32_e32 v39, s6, v42
	s_add_i32 s2, s18, -1
	s_add_i32 s3, s16, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v40, 1, v38
	v_add_nc_u32_e32 v41, 1, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v40
	v_cmp_gt_i32_e64 s2, s3, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB9_90
; %bb.1:
	s_add_i32 s7, s18, -2
	s_lshl_b32 s19, s17, 2
	s_mul_i32 s49, s17, s7
	v_mad_u64_u32 v[1:2], null, s7, s19, v[38:39]
	v_mad_u64_u32 v[6:7], null, s49, 5, v[38:39]
	s_add_i32 s33, s16, -2
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x0
	s_load_b128 s[20:23], s[0:1], 0x20
	v_mad_u64_u32 v[11:12], null, s49, 6, v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v1, s33, v[39:40]
	v_mad_u64_u32 v[9:10], null, v6, s33, v[39:40]
	s_mov_b32 s0, 0
	v_mad_u64_u32 v[14:15], null, s49, 7, v[38:39]
	s_mov_b32 s1, s0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v5, 31, v4
	v_mad_u64_u32 v[12:13], null, v11, s33, v[39:40]
	v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
	v_ashrrev_i32_e32 v10, 31, v9
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v3, v0
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_lshl_add_u32 v6, s49, 3, v38
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_ashrrev_i32_e32 v13, 31, v12
	scratch_store_b128 off, v[0:3], off offset:16
	v_mov_b32_e32 v1, 0x3ff00000
	v_mad_u64_u32 v[15:16], null, v14, s33, v[39:40]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_mad_u64_u32 v[17:18], null, v6, s33, v[39:40]
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	v_add_co_u32 v9, vcc_lo, s20, v9
	s_clause 0x1
	scratch_store_b128 off, v[0:3], off offset:32
	scratch_store_b64 off, v[7:8], off offset:48
	v_lshlrev_b64 v[2:3], 3, v[12:13]
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v10, vcc_lo
	v_ashrrev_i32_e32 v16, 31, v15
	s_mul_i32 s0, s17, s16
	s_clause 0x1
	global_store_b64 v[4:5], v[7:8], off
	global_store_b64 v[9:10], v[7:8], off
	v_ashrrev_i32_e32 v18, 31, v17
	v_add_co_u32 v4, vcc_lo, s20, v2
	v_mad_u64_u32 v[11:12], null, s0, v40, v[42:43]
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v3, vcc_lo
	v_lshlrev_b64 v[2:3], 3, v[15:16]
	v_lshlrev_b64 v[9:10], 3, v[17:18]
	s_mov_b32 s24, 0x9999999a
	s_mov_b32 s26, 0x55555555
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v43, v11, s6, 1
	s_mov_b32 s28, 0xf5c28f5b
	v_add_co_u32 v12, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s20, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v10, vcc_lo
	v_mov_b32_e32 v2, v43
	s_mov_b32 s25, 0x3fb99999
	s_mov_b32 s27, 0x3ff55555
	s_mov_b32 s29, 0x3fff5c28
	s_mov_b64 s[30:31], 0
	s_clause 0x2
	global_store_b64 v[4:5], v[0:1], off
	global_store_b64 v[12:13], v[7:8], off
	global_store_b64 v[9:10], v[7:8], off
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB9_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_cmp_eq_u32 s30, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[2:3]
	v_add_co_u32 v16, vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
	global_load_b64 v[16:17], v[16:17], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s30, 1
	global_load_b64 v[10:11], v[10:11], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s30, 2
	v_add_nc_u32_e32 v2, s16, v2
	s_cselect_b32 s1, -1, 0
	s_waitcnt vmcnt(1)
	v_mul_f64 v[18:19], v[16:17], s[24:25]
	v_fma_f64 v[16:17], v[16:17], s[24:25], 0x3fe80000
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v1, v1, v11, vcc_lo
	v_cndmask_b32_e64 v9, v9, v11, s1
	v_cndmask_b32_e64 v8, v8, v10, s1
	v_cndmask_b32_e64 v7, v7, v11, s0
	v_cndmask_b32_e64 v6, v6, v10, s0
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	v_fma_f64 v[20:21], v[18:19], s[28:29], 0x3fe80000
	v_fma_f64 v[18:19], v[18:19], s[26:27], 0x3fe80000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v15, v21, s1
	v_cmp_gt_f64_e64 s2, v[18:19], v[20:21]
	v_cndmask_b32_e64 v22, v14, v20, s1
	v_dual_cndmask_b32 v23, v5, v21 :: v_dual_cndmask_b32 v24, v4, v20
	v_cndmask_b32_e64 v21, v13, v21, s0
	v_cndmask_b32_e64 v20, v12, v20, s0
	v_dual_cndmask_b32 v5, v5, v19 :: v_dual_cndmask_b32 v4, v4, v18
	v_cndmask_b32_e64 v12, v12, v18, s0
	v_cndmask_b32_e64 v13, v13, v19, s0
	v_cndmask_b32_e64 v14, v14, v18, s1
	v_cndmask_b32_e64 v15, v15, v19, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v20, v12, s2
	v_cndmask_b32_e64 v13, v21, v13, s2
	v_cndmask_b32_e64 v5, v23, v5, s2
	v_cndmask_b32_e64 v18, v24, v4, s2
	v_cndmask_b32_e64 v14, v22, v14, s2
	v_cndmask_b32_e64 v15, v3, v15, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, v5, v13, s0
	v_cndmask_b32_e64 v19, v18, v12, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v3, v15, s1
	v_cndmask_b32_e64 v3, v19, v14, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e64 s2, v[3:4], v[16:17]
	s_and_b32 s3, s2, s1
	s_and_b32 s4, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v14, v14, v16, s3
	v_cndmask_b32_e64 v12, v12, v16, s4
	v_cndmask_b32_e64 v16, v18, v16, s2
	v_cndmask_b32_e64 v13, v13, v17, s4
	v_cndmask_b32_e64 v5, v5, v17, s2
	v_cndmask_b32_e64 v15, v15, v17, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v16, v12, s0
	v_cndmask_b32_e64 v4, v5, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v14, s1
	v_cndmask_b32_e64 v4, v4, v15, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, 0x3fe80000, v[3:4]
	s_and_b32 s1, s2, s1
	s_and_b32 s0, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v15, v15, 0x3fe80000, s1
	v_cndmask_b32_e64 v13, v13, 0x3fe80000, s0
	v_cndmask_b32_e64 v5, v5, 0x3fe80000, s2
	v_cndmask_b32_e64 v14, v14, 0, s1
	v_cndmask_b32_e64 v12, v12, 0, s0
	v_cndmask_b32_e64 v4, v16, 0, s2
	s_add_u32 s30, s30, 1
	s_addc_u32 s31, s31, 0
	s_cmp_lg_u32 s30, 3
	s_cbranch_scc1 .LBB9_2
; %bb.3:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dty1@rel32@lo+4
	s_addc_u32 s1, s1, dty1@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, c2dtty1@rel32@lo+4
	s_addc_u32 s3, s3, c2dtty1@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, dtty2@rel32@lo+4
	s_addc_u32 s25, s25, dtty2@rel32@hi+12
	s_load_b64 s[4:5], s[2:3], 0x0
	s_load_b64 s[2:3], s[24:25], 0x0
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, comz5@rel32@lo+4
	s_addc_u32 s25, s25, comz5@rel32@hi+12
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, comz4@rel32@lo+4
	s_addc_u32 s27, s27, comz4@rel32@hi+12
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, comz1@rel32@lo+4
	s_addc_u32 s29, s29, comz1@rel32@hi+12
	s_load_b64 s[24:25], s[24:25], 0x0
	s_load_b64 s[26:27], s[26:27], 0x0
	s_load_b64 s[28:29], s[28:29], 0x0
	v_add_nc_u32_e64 v50, 16, 40
	s_mul_i32 s46, s49, s33
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[2:3], v[14:15], s[0:1]
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	v_fma_f64 v[10:11], v[12:13], s[4:5], 1.0
	v_add_f64 v[24:25], s[28:29], 0
	s_add_i32 s28, s19, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	s_mul_i32 s28, s7, s28
	v_fma_f64 v[18:19], v[8:9], s[2:3], -v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[3:4], v[0:1], -s[2:3], -v[4:5]
	v_add_f64 v[16:17], v[10:11], s[24:25]
	v_add3_u32 v0, s40, s28, v46
	v_mov_b32_e32 v1, 0
	s_mov_b32 s28, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s33
	v_mov_b32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v0, v42, v0, s6
	v_add_f64 v[18:19], v[18:19], -s[26:27]
	s_clause 0x2
	scratch_store_b128 off, v[1:4], off offset:56
	scratch_store_b128 off, v[16:19], off offset:72
	scratch_store_b64 off, v[24:25], off offset:88
.LBB9_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s28, v50
	s_add_i32 s28, s28, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s28, 40
	scratch_load_b64 v[2:3], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_add_nc_u32_e32 v0, s46, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[2:3], off
	s_cbranch_scc1 .LBB9_4
; %bb.5:
	v_mul_lo_u32 v0, v40, s17
	s_mul_i32 s42, s16, 5
	s_add_i32 s41, 0x110, 40
	s_mov_b32 s28, 0
	s_mov_b32 s29, s41
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, v0, 5, 5
	v_mul_lo_u32 v47, v0, s42
	v_lshl_add_u32 v2, v39, 2, v39
	v_mul_lo_u32 v1, s16, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v1, v1, v2, 5
	v_add3_u32 v2, v47, v2, 5
.LBB9_6:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, s28, v2
	v_add_nc_u32_e32 v10, s28, v1
	s_add_i32 s28, s28, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s14, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[3:4], s29 offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[10:11], s29
	s_add_i32 s29, s29, 8
	s_cmp_eq_u32 s28, 3
	s_cbranch_scc0 .LBB9_6
; %bb.7:                                ; %.preheader674
	s_add_i32 s47, s17, -2
	s_cmp_gt_i32 s17, 2
	v_mov_b32_e32 v16, 0
	s_cselect_b32 s50, -1, 0
	s_cmp_lt_i32 s17, 3
	v_dual_mov_b32 v17, 0x3ff00000 :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v11, v9
	v_mov_b32_e32 v19, 0
	v_add_nc_u32_e32 v49, 3, v0
	v_mul_u32_u24_e32 v48, 5, v42
	s_cselect_b32 s45, -1, 0
	s_mul_i32 s43, s18, s16
	s_and_b32 vcc_lo, exec_lo, s45
	s_mul_i32 s48, s7, s33
	s_mul_i32 s44, s43, s17
	s_cbranch_vccnz .LBB9_47
; %bb.8:                                ; %.lr.ph
	v_dual_mov_b32 v3, 16 :: v_dual_add_nc_u32 v0, 2, v0
	s_add_i32 s30, s19, 2
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, comz6@rel32@lo+4
	s_addc_u32 s29, s29, comz6@rel32@hi+12
	s_mul_i32 s30, s7, s30
	v_mul_lo_u32 v4, s16, v0
	s_load_b64 s[28:29], s[28:29], 0x0
	v_add3_u32 v2, s40, s30, v46
	s_mul_i32 s30, s6, 5
	v_mad_u64_u32 v[0:1], null, s16, v40, v[42:43]
	v_dual_mov_b32 v5, 0x110 :: v_dual_mov_b32 v26, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v16, v2, s33
	v_mad_u64_u32 v[1:2], null, v4, 5, s[30:31]
	v_add_nc_u32_e32 v51, 0x50, v3
	v_add_nc_u32_e32 v52, 0x50, v5
	v_add3_u32 v53, v0, s6, 1
	v_mov_b32_e32 v56, 0x3ff00000
	s_mov_b32 s30, 0x9999999a
	v_add3_u32 v54, v42, v16, s6
	v_add3_u32 v55, v1, v48, 5
	s_mov_b32 s34, 0x55555555
	s_mov_b32 s36, 0xf5c28f5b
	s_add_i32 s51, s17, -3
	s_mov_b32 s31, 0x3fb99999
	s_mov_b32 s35, 0x3ff55555
	s_mov_b32 s37, 0x3fff5c28
	s_add_i32 s52, s17, -5
	s_mov_b32 s38, 0
	s_mov_b32 s53, 0
.LBB9_9:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB9_29 Depth 2
                                        ;     Child Loop BB9_34 Depth 2
                                        ;     Child Loop BB9_36 Depth 2
                                        ;     Child Loop BB9_38 Depth 2
                                        ;     Child Loop BB9_40 Depth 2
                                        ;     Child Loop BB9_42 Depth 2
                                        ;     Child Loop BB9_44 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s39, s53, 2
	s_cmp_lg_u32 s53, s51
	s_cbranch_scc0 .LBB9_16
; %bb.10:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_nc_u32_e32 v2, s53, v49
	v_fma_f64 v[34:35], s[4:5], v[14:15], 1.0
	s_cmp_lg_u32 s53, 0
	v_mov_b32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s16, v[41:42]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v2, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[0:1], v[4:5], s[30:31]
	v_fma_f64 v[4:5], v[4:5], s[30:31], 0x3fe80000
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[0:1], s[34:35], 0x3fe80000
	v_fma_f64 v[0:1], v[0:1], s[36:37], 0x3fe80000
	v_cmp_gt_f64_e32 vcc_lo, v[18:19], v[0:1]
	v_dual_cndmask_b32 v1, v1, v19 :: v_dual_cndmask_b32 v0, v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_mul_f64 v[4:5], s[0:1], v[12:13]
	v_cmp_ngt_f64_e32 vcc_lo, 0x3fe80000, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[6:7], -s[2:3], -v[4:5]
	v_cndmask_b32_e32 v21, 0x3fe80000, v1, vcc_lo
	v_cndmask_b32_e32 v20, 0, v0, vcc_lo
	v_mul_f64 v[0:1], s[0:1], v[20:21]
	scratch_store_b128 off, v[26:29], off offset:96
	s_waitcnt vmcnt(0)
	v_fma_f64 v[36:37], s[2:3], v[2:3], -v[0:1]
	s_clause 0x1
	scratch_store_b128 off, v[34:37], off offset:112
	scratch_store_b64 off, v[26:27], off offset:128
	s_cbranch_scc0 .LBB9_17
; %bb.11:                               ;   in Loop: Header=BB9_9 Depth=1
	s_cmp_ge_i32 s39, s51
	s_cbranch_scc0 .LBB9_18
; %bb.12:                               ;   in Loop: Header=BB9_9 Depth=1
	s_cmp_lg_u32 s53, s52
	s_cbranch_scc0 .LBB9_19
; %bb.13:                               ;   in Loop: Header=BB9_9 Depth=1
	v_dual_mov_b32 v44, 0 :: v_dual_mov_b32 v31, v29
	v_dual_mov_b32 v45, 0 :: v_dual_mov_b32 v30, v28
	v_dual_mov_b32 v32, v34 :: v_dual_mov_b32 v33, v35
	s_cmp_lg_u32 s39, s47
	s_cbranch_scc1 .LBB9_15
; %bb.14:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_f64 v[59:60], v[28:29], -s[26:27]
	v_add_f64 v[32:33], s[24:25], v[34:35]
	v_dual_mov_b32 v57, v24 :: v_dual_mov_b32 v58, v25
	v_dual_mov_b32 v45, v25 :: v_dual_mov_b32 v44, v24
	s_clause 0x1
	scratch_store_b128 off, v[57:60], off offset:96
	scratch_store_b64 off, v[32:33], off offset:112
	v_dual_mov_b32 v30, v59 :: v_dual_mov_b32 v31, v60
.LBB9_15:                               ; %Flow1071
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, 0
	s_branch .LBB9_20
.LBB9_16:                               ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, -1
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB9_31
.LBB9_17:                               ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB9_26
.LBB9_18:                               ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB9_23
.LBB9_19:                               ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, -1
                                        ; implicit-def: $vgpr44_vgpr45
                                        ; implicit-def: $vgpr30_vgpr31
.LBB9_20:                               ; %Flow1073
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s54
	s_cbranch_vccnz .LBB9_22
; %bb.21:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_f64 v[59:60], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[61:62], v[34:35], s[28:29]
	v_add_f64 v[63:64], v[36:37], -s[26:27]
	v_dual_mov_b32 v57, v24 :: v_dual_mov_b32 v58, v25
	v_dual_mov_b32 v45, v25 :: v_dual_mov_b32 v44, v24
	s_clause 0x1
	scratch_store_b128 off, v[57:60], off offset:96
	scratch_store_b128 off, v[61:64], off offset:112
	v_dual_mov_b32 v30, v59 :: v_dual_mov_b32 v31, v60
	v_dual_mov_b32 v32, v61 :: v_dual_mov_b32 v33, v62
.LBB9_22:                               ; %Flow1074
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, 0
.LBB9_23:                               ; %Flow1076
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s54
	s_cbranch_vccnz .LBB9_25
; %bb.24:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_f64 v[59:60], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[61:62], v[34:35], s[28:29]
	v_add_f64 v[63:64], v[36:37], -s[26:27]
	v_dual_mov_b32 v57, v24 :: v_dual_mov_b32 v58, v25
	v_dual_mov_b32 v45, v25 :: v_dual_mov_b32 v44, v24
	s_clause 0x2
	scratch_store_b128 off, v[57:60], off offset:96
	scratch_store_b128 off, v[61:64], off offset:112
	scratch_store_b64 off, v[24:25], off offset:128
	v_dual_mov_b32 v30, v59 :: v_dual_mov_b32 v31, v60
	v_dual_mov_b32 v32, v61 :: v_dual_mov_b32 v33, v62
.LBB9_25:                               ; %Flow1077
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_mov_b32 s54, 0
.LBB9_26:                               ; %Flow1079
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s54
	s_cbranch_vccnz .LBB9_28
; %bb.27:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_f64 v[30:31], v[28:29], -s[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[32:33], v[34:35], s[28:29]
	v_add_f64 v[22:23], v[36:37], -s[26:27]
	v_mov_b32_e32 v44, 0
	v_mov_b32_e32 v45, 0
	s_clause 0x1
	scratch_store_b128 off, v[30:33], off offset:104
	scratch_store_b128 off, v[22:25], off offset:120
.LBB9_28:                               ;   in Loop: Header=BB9_9 Depth=1
	v_mov_b32_e32 v0, v54
	s_mov_b32 s54, 0
.LBB9_29:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s54, v51
	s_add_i32 s54, s54, 8
	s_cmp_lg_u32 s54, 40
	scratch_load_b64 v[4:5], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], 3, v[0:1]
	v_add_nc_u32_e32 v0, s46, v0
	v_add_co_u32 v18, vcc_lo, s20, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v19, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[18:19], v[4:5], off
	s_cbranch_scc1 .LBB9_29
; %bb.30:                               ;   in Loop: Header=BB9_9 Depth=1
	v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v19, v15
	v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s54, 0
.LBB9_31:                               ; %Flow1081
                                        ;   in Loop: Header=BB9_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s54
	s_cbranch_vccz .LBB9_33
; %bb.32:                               ;   in Loop: Header=BB9_9 Depth=1
	s_add_i32 s54, s39, s19
	s_mov_b32 s39, s38
	v_mad_u64_u32 v[0:1], null, s54, s7, v[38:39]
	v_dual_mov_b32 v27, v26 :: v_dual_mov_b32 v34, s38
	v_dual_mov_b32 v28, v26 :: v_dual_mov_b32 v35, s39
	s_add_i32 s39, s54, s17
	v_dual_mov_b32 v29, v26 :: v_dual_mov_b32 v30, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[1:2], null, v0, s33, v[39:40]
	v_mad_u64_u32 v[3:4], null, s39, s7, v[38:39]
	s_add_i32 s39, s39, s17
	s_clause 0x1
	scratch_store_b128 off, v[26:29], off offset:96
	scratch_store_b64 off, v[34:35], off offset:128
	v_mad_u64_u32 v[4:5], null, s39, s7, v[38:39]
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s39, s39, s17
	v_mad_u64_u32 v[18:19], null, v3, s33, v[39:40]
	v_dual_mov_b32 v27, v56 :: v_dual_mov_b32 v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_mad_u64_u32 v[2:3], null, s39, s7, v[38:39]
	s_add_i32 s39, s39, s17
	v_mad_u64_u32 v[20:21], null, v4, s33, v[39:40]
	v_mad_u64_u32 v[3:4], null, s39, s7, v[38:39]
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_mad_u64_u32 v[4:5], null, v2, s33, v[39:40]
	v_ashrrev_i32_e32 v21, 31, v20
	global_store_b64 v[0:1], v[34:35], off
	v_lshlrev_b64 v[0:1], 3, v[18:19]
	v_mad_u64_u32 v[18:19], null, v3, s33, v[39:40]
	v_lshlrev_b64 v[2:3], 3, v[20:21]
	v_ashrrev_i32_e32 v5, 31, v4
	scratch_store_b128 off, v[26:29], off offset:112
	v_add_co_u32 v28, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v29, vcc_lo, s21, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v36, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v37, vcc_lo, s21, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 3, v[18:19]
	v_add_co_u32 v57, vcc_lo, s20, v0
	v_mov_b32_e32 v31, 0
	v_add_co_ci_u32_e32 v58, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v59, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v60, vcc_lo, s21, v3, vcc_lo
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v45, v31
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v23, v17
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v33, 0x3ff00000
	v_dual_mov_b32 v44, v30 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v22, v16 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v20, v14 :: v_dual_mov_b32 v21, v15
	v_mov_b32_e32 v19, v13
	s_clause 0x3
	global_store_b64 v[28:29], v[34:35], off
	global_store_b64 v[36:37], v[26:27], off
	global_store_b64 v[57:58], v[34:35], off
	global_store_b64 v[59:60], v[34:35], off
.LBB9_33:                               ;   in Loop: Header=BB9_9 Depth=1
	v_mov_b32_e32 v6, v52
	s_mov_b32 s39, 0
.LBB9_34:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s39, v55
	s_add_i32 s39, s39, 1
	s_cmp_lg_u32 s39, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s14, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v6, v[7:8], off
	v_add_nc_u32_e32 v6, 8, v6
	s_cbranch_scc1 .LBB9_34
; %bb.35:                               ;   in Loop: Header=BB9_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:32
	scratch_load_b64 v[12:13], off, off offset:48
	s_mov_b32 s39, 0
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[27:28], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[27:28], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
	v_div_fixup_f64 v[10:11], v[10:11], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[12:13]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB9_36:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s54, s39, 0x110
	s_add_i32 s39, s39, 8
	scratch_load_b64 v[12:13], off, s54
	s_cmp_lg_u32 s39, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s54
	s_cbranch_scc1 .LBB9_36
; %bb.37:                               ;   in Loop: Header=BB9_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s39, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB9_38:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v12, 0x110, s39
	s_add_i32 s54, s39, 0x110
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 24
	v_add_nc_u32_e32 v16, 40, v12
	s_clause 0x1
	scratch_load_b64 v[12:13], off, s54
	scratch_load_b64 v[14:15], v16, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[10:11], v[12:13], v[14:15]
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB9_38
; %bb.39:                               ;   in Loop: Header=BB9_9 Depth=1
	v_fma_f64 v[10:11], -v[6:7], v[44:45], v[30:31]
	v_fma_f64 v[12:13], -v[8:9], v[44:45], v[32:33]
	s_mov_b32 s39, 0
	scratch_store_b128 off, v[10:13], off offset:104
.LBB9_40:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v10, 0x110, s39
	s_add_i32 s54, s39, 0x110
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 24
	v_add_nc_u32_e32 v14, 0x50, v10
	s_clause 0x1
	scratch_load_b64 v[10:11], off, s54
	scratch_load_b64 v[12:13], v14, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], -v[44:45], v[10:11], v[12:13]
	scratch_store_b64 v14, v[10:11], off
	s_cbranch_scc1 .LBB9_40
; %bb.41:                               ;   in Loop: Header=BB9_9 Depth=1
	v_mad_u64_u32 v[10:11], null, s53, s7, v[38:39]
	s_add_i32 s39, s53, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, s39, s7, v[38:39]
	s_mov_b32 s39, 0
	v_mad_u64_u32 v[12:13], null, v10, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v11, s33, v[39:40]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	v_add_co_u32 v10, vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s20, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_store_b64 v[10:11], v[6:7], off
	global_store_b64 v[12:13], v[8:9], off
.LBB9_42:                               ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v6, s39, 16
	s_add_i32 s54, s39, 16
	s_add_i32 s39, s39, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s39, 40
	v_add_nc_u32_e32 v10, 40, v6
	v_add_nc_u32_e32 v8, 0x50, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v10, off
	scratch_load_b64 v[8:9], v8, off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[6:7], s54
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	s_cbranch_scc1 .LBB9_42
; %bb.43:                               ; %.preheader673.preheader
                                        ;   in Loop: Header=BB9_9 Depth=1
	v_mov_b32_e32 v6, v53
	s_mov_b32 s39, 0
.LBB9_44:                               ; %.preheader673
                                        ;   Parent Loop BB9_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x110, s39
	s_add_i32 s54, s39, 0x110
	s_add_i32 s39, s39, 8
	s_cmp_lg_u32 s39, 24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v16, 40, v7
	v_add_nc_u32_e32 v7, 0x50, v7
	s_clause 0x2
	scratch_load_b64 v[8:9], off, s54
	scratch_load_b64 v[10:11], v16, off
	scratch_load_b64 v[12:13], v7, off
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[6:7]
	v_add_nc_u32_e32 v6, s44, v6
	v_add_co_u32 v14, vcc_lo, s22, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s23, v15, vcc_lo
	s_waitcnt vmcnt(2)
	global_store_b64 v[14:15], v[8:9], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[10:11], s54
	s_waitcnt vmcnt(0)
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB9_44
; %bb.45:                               ;   in Loop: Header=BB9_9 Depth=1
	v_add_nc_u32_e32 v54, s48, v54
	v_add_nc_u32_e32 v55, s42, v55
	v_add_nc_u32_e32 v53, s43, v53
	s_add_i32 s53, s53, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s53, s47
	s_cbranch_scc0 .LBB9_48
; %bb.46:                               ;   in Loop: Header=BB9_9 Depth=1
	v_dual_mov_b32 v12, v18 :: v_dual_mov_b32 v13, v19
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v14, v20 :: v_dual_mov_b32 v15, v21
	v_dual_mov_b32 v16, v22 :: v_dual_mov_b32 v17, v23
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	s_branch .LBB9_9
.LBB9_47:
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v8, v18 :: v_dual_mov_b32 v9, v19
	s_branch .LBB9_49
.LBB9_48:                               ; %._crit_edge.loopexit
	s_clause 0x1
	scratch_load_b128 v[16:19], off, off offset:32
	scratch_load_b64 v[8:9], off, off offset:48
.LBB9_49:                               ; %._crit_edge
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[6:7], null, v[16:17], v[16:17], 1.0
	v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[16:17], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[12:13]
	v_div_fixup_f64 v[10:11], v[6:7], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[18:19], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB9_50:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB9_50
; %bb.51:
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB9_52:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v14, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v18, 40, v14
	s_clause 0x1
	scratch_load_b64 v[14:15], off, s1
	scratch_load_b64 v[16:17], v18, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[10:11], v[14:15], v[16:17]
	scratch_store_b64 v18, v[14:15], off
	s_cbranch_scc1 .LBB9_52
; %bb.53:
	v_div_scale_f64 v[10:11], null, v[12:13], v[12:13], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[18:19]
	v_div_fixup_f64 v[10:11], v[10:11], v[12:13], 1.0
.LBB9_54:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s41, s0
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB9_54
; %bb.55:
	v_mad_u64_u32 v[10:11], null, s7, s47, v[38:39]
	s_add_i32 s0, s47, s17
	s_mov_b64 s[4:5], 0
	v_mad_u64_u32 v[11:12], null, s7, s0, v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, v10, s33, v[39:40]
	v_mad_u64_u32 v[14:15], null, v11, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v18, vcc_lo, s20, v10
	v_add_co_ci_u32_e32 v19, vcc_lo, s21, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s20, v12
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_store_b64 v[18:19], v[6:7], off
	global_store_b64 v[10:11], v[8:9], off
.LBB9_56:                               ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v44, 31, v43
	s_cmp_eq_u32 s4, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[43:44]
	v_add_co_u32 v6, vcc_lo, s12, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 s0, -1, 0
	global_load_b64 v[6:7], v[6:7], off
	s_cmp_eq_u32 s4, 0
	v_add_nc_u32_e32 v43, s16, v43
	s_cselect_b32 s1, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 3
	s_waitcnt vmcnt(0)
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
	v_cndmask_b32_e64 v3, v3, v7, s0
	v_cndmask_b32_e64 v2, v2, v6, s0
	v_cndmask_b32_e64 v1, v1, v7, s1
	v_cndmask_b32_e64 v0, v0, v6, s1
	s_cbranch_scc1 .LBB9_56
; %bb.57:                               ; %.preheader672.preheader
	s_lshl_b32 s0, s49, 2
	v_add_nc_u32_e64 v8, 0x90, 40
	s_add_i32 s0, s40, s0
	v_mov_b32_e32 v9, v39
	s_add_i32 s1, s0, s18
	v_add_nc_u32_e32 v7, s0, v46
	v_add3_u32 v6, s1, v46, -2
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, s33
	v_mul_lo_u32 v6, v6, s33
.LBB9_58:                               ; %.preheader672
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v7, v9
	v_add_nc_u32_e32 v12, v6, v9
	v_add_nc_u32_e32 v14, s0, v50
	v_add_nc_u32_e32 v9, s46, v9
	v_add_nc_u32_e32 v15, s0, v8
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v10, vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s20, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s21, v13, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 v14, v[10:11], off offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 v14, v[12:13], off
	s_clause 0x1
	scratch_store_b64 v15, v[10:11], off offset:-40
	scratch_store_b64 v15, v[12:13], off
	s_cbranch_scc1 .LBB9_58
; %bb.59:
	v_lshl_add_u32 v25, v41, 2, v41
	s_clause 0x3
	scratch_load_b64 v[27:28], off, off offset:192
	scratch_load_b64 v[29:30], off, off offset:208
	scratch_load_b64 v[31:32], off, off offset:64
	scratch_load_b64 v[33:34], off, off offset:80
	v_add_nc_u32_e32 v26, s42, v47
	v_add_nc_u32_e32 v6, 3, v25
	v_add_nc_u32_e32 v7, 4, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v20, v6, v47
	v_add_nc_u32_e32 v22, v7, v47
	v_add_nc_u32_e32 v6, v26, v6
	v_add_nc_u32_e32 v8, v26, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[10:11], 3, v[20:21]
	v_lshlrev_b64 v[12:13], 3, v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s14, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s14, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v7, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v9, vcc_lo
	s_clause 0x3
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[6:7], v[14:15], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[8:9], v[16:17], off
	s_and_not1_b32 vcc_lo, exec_lo, s50
	s_waitcnt vmcnt(7)
	v_fma_f64 v[23:24], -s[2:3], v[0:1], v[27:28]
	s_waitcnt vmcnt(6)
	v_fma_f64 v[27:28], s[2:3], v[4:5], v[29:30]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[0:1], s[2:3], v[0:1], v[31:32]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[29:30], -s[2:3], v[4:5], v[33:34]
	s_clause 0x3
	scratch_store_b64 off, v[23:24], off offset:192
	scratch_store_b64 off, v[27:28], off offset:208
	scratch_store_b64 off, v[0:1], off offset:64
	scratch_store_b64 off, v[29:30], off offset:80
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[10:13], off offset:296
	s_waitcnt vmcnt(0)
	scratch_store_b128 off, v[6:9], off offset:336
	s_cbranch_vccnz .LBB9_71
; %bb.60:                               ; %.preheader671.lr.ph
	s_mul_i32 s4, s18, s17
	s_add_i32 s1, s19, 2
	s_mul_i32 s0, s4, 3
	v_add_nc_u32_e64 v13, 16, 24
	v_add3_u32 v0, s40, s0, v46
	s_mul_i32 s0, s7, s1
	s_movk_i32 s1, 0x50
	v_add3_u32 v1, s40, s0, v46
	s_lshl_b32 s0, s49, 1
	v_mul_lo_u32 v0, s16, v0
	s_mul_i32 s49, s49, 7
	v_add3_u32 v6, s40, s0, v46
	v_mul_lo_u32 v8, v1, s33
	v_add3_u32 v9, s40, s49, v46
	v_add_nc_u32_e64 v21, 0x90, s1
	v_add_nc_u32_e64 v27, s1, 16
	s_add_i32 s1, s17, -1
	v_add3_u32 v10, v0, s16, v42
	v_mad_u64_u32 v[0:1], null, v6, s33, s[6:7]
	v_mad_u64_u32 v[6:7], null, v9, s33, s[6:7]
	v_add3_u32 v1, v42, v8, s6
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v28, v10, s6, 1
	s_mul_i32 s4, s4, s16
	s_mov_b32 s5, 0
.LBB9_61:                               ; %.preheader671
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB9_62 Depth 2
                                        ;     Child Loop BB9_66 Depth 2
                                        ;     Child Loop BB9_68 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v1
	s_mov_b32 s0, 0
.LBB9_62:                               ;   Parent Loop BB9_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v10, s0, v27
	v_add_nc_u32_e32 v11, s0, v21
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[8:9], 3, v[7:8]
	v_add_nc_u32_e32 v7, s46, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s20, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	scratch_store_b64 v11, v[8:9], off
	s_cbranch_scc1 .LBB9_62
; %bb.63:                               ;   in Loop: Header=BB9_61 Depth=1
	s_add_i32 s0, s5, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_mul_i32 s8, s42, s0
	s_cmp_ge_i32 s0, s1
	v_add_nc_u32_e32 v7, s8, v20
	v_add_nc_u32_e32 v9, s8, v22
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s14, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	scratch_load_b64 v[23:24], off, off offset:232
	s_clause 0x1
	global_load_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[9:10], off
	scratch_load_b64 v[9:10], off, off offset:104
	s_cbranch_scc1 .LBB9_65
; %bb.64:                               ;   in Loop: Header=BB9_61 Depth=1
	v_add_nc_u32_e32 v31, s5, v49
	s_waitcnt vmcnt(3)
	v_fma_f64 v[23:24], -s[2:3], v[2:3], v[23:24]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[9:10], s[2:3], v[2:3], v[9:10]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	v_mad_u64_u32 v[29:30], null, v31, s16, v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[29:30], 3, v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s12, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v30, vcc_lo
	scratch_load_b64 v[31:32], off, off offset:248
	global_load_b64 v[29:30], v[29:30], off
	scratch_load_b64 v[33:34], off, off offset:120
	s_waitcnt vmcnt(1)
	v_fma_f64 v[31:32], s[2:3], v[29:30], v[31:32]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[33:34], -s[2:3], v[29:30], v[33:34]
	v_dual_mov_b32 v4, v29 :: v_dual_mov_b32 v5, v30
	s_clause 0x1
	scratch_store_b64 off, v[31:32], off offset:248
	scratch_store_b64 off, v[33:34], off offset:120
.LBB9_65:                               ;   in Loop: Header=BB9_61 Depth=1
	s_clause 0xd
	scratch_load_b128 v[29:32], off, off offset:160
	scratch_load_b128 v[33:36], off, off offset:32
	scratch_load_b64 v[43:44], off, off offset:176
	scratch_load_b64 v[68:69], off, off offset:48
	scratch_load_b128 v[50:53], off, off offset:296
	scratch_load_b128 v[54:57], off, off offset:192
	scratch_load_b64 v[80:81], off, off offset:208
	scratch_load_b128 v[58:61], off, off offset:336
	scratch_load_b64 v[82:83], off, off offset:224
	scratch_load_b64 v[84:85], off, off offset:240
	scratch_load_b128 v[62:65], off, off offset:64
	scratch_load_b64 v[86:87], off, off offset:80
	scratch_load_b64 v[88:89], off, off offset:96
	scratch_load_b64 v[90:91], off, off offset:112
	s_waitcnt vmcnt(13)
	v_div_scale_f64 v[66:67], null, v[29:30], v[29:30], 1.0
	s_waitcnt vmcnt(12)
	v_div_scale_f64 v[70:71], null, v[33:34], v[33:34], 1.0
	v_div_scale_f64 v[92:93], vcc_lo, 1.0, v[29:30], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[72:73], v[66:67]
	v_rcp_f64_e32 v[74:75], v[70:71]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[76:77], -v[66:67], v[72:73], 1.0
	v_fma_f64 v[78:79], -v[70:71], v[74:75], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	v_fma_f64 v[74:75], v[74:75], v[78:79], v[74:75]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[76:77], -v[66:67], v[72:73], 1.0
	v_fma_f64 v[78:79], -v[70:71], v[74:75], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	v_div_scale_f64 v[76:77], s0, 1.0, v[33:34], 1.0
	v_fma_f64 v[74:75], v[74:75], v[78:79], v[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[78:79], v[92:93], v[72:73]
	v_mul_f64 v[94:95], v[76:77], v[74:75]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[66:67], -v[66:67], v[78:79], v[92:93]
	v_fma_f64 v[70:71], -v[70:71], v[94:95], v[76:77]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[66:67], v[66:67], v[72:73], v[78:79]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[70:71], v[70:71], v[74:75], v[94:95]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[66:67], v[66:67], v[29:30], 1.0
	v_div_fixup_f64 v[70:71], v[70:71], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[29:30], v[31:32], v[66:67]
	s_waitcnt vmcnt(11)
	v_mul_f64 v[31:32], v[66:67], v[43:44]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[33:34], v[66:67], v[50:51]
	v_mul_f64 v[66:67], v[35:36], v[70:71]
	v_mul_f64 v[68:69], v[70:71], v[68:69]
	v_mul_f64 v[35:36], v[70:71], v[52:53]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[50:51], -v[29:30], v[54:55], v[56:57]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[52:53], -v[31:32], v[54:55], v[80:81]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[70:71], -v[29:30], v[82:83], v[23:24]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[72:73], -v[31:32], v[82:83], v[84:85]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[74:75], -v[66:67], v[62:63], v[64:65]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[76:77], -v[68:69], v[62:63], v[86:87]
	v_fma_f64 v[54:55], -v[33:34], v[54:55], v[58:59]
	v_fma_f64 v[56:57], -v[35:36], v[62:63], v[60:61]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[62:63], -v[66:67], v[88:89], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[64:65], -v[68:69], v[88:89], v[90:91]
	v_fma_f64 v[58:59], -v[33:34], v[82:83], v[11:12]
	v_fma_f64 v[60:61], -v[35:36], v[88:89], v[7:8]
	v_mov_b32_e32 v9, v42
	v_mov_b32_e32 v7, v28
	s_clause 0x8
	scratch_store_b128 off, v[29:32], off offset:168
	scratch_store_b128 off, v[50:53], off offset:200
	scratch_store_b128 off, v[70:73], off offset:232
	scratch_store_b128 off, v[66:69], off offset:40
	scratch_store_b128 off, v[74:77], off offset:72
	scratch_store_b128 off, v[33:36], off offset:296
	scratch_store_b128 off, v[54:57], off offset:336
	scratch_store_b128 off, v[62:65], off offset:104
	scratch_store_b128 off, v[58:61], off offset:376
.LBB9_66:                               ;   Parent Loop BB9_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, 0x110 :: v_dual_add_nc_u32 v35, v6, v9
	v_add_nc_u32_e64 v8, 0x90, 24
	v_add_nc_u32_e32 v12, s0, v13
	v_add_nc_u32_e32 v43, v0, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_readfirstlane_b32 s8, v10
	v_ashrrev_i32_e32 v36, 31, v35
	v_add_nc_u32_e32 v8, s0, v8
	scratch_load_b64 v[23:24], v12, off
	v_ashrrev_i32_e32 v44, 31, v43
	s_add_i32 s8, s8, s0
	v_lshlrev_b64 v[35:36], 3, v[35:36]
	s_add_i32 s9, s8, 24
	s_add_i32 s10, s8, 64
	scratch_load_b64 v[10:11], v8, off
	s_addk_i32 s8, 0x68
	s_clause 0x2
	scratch_load_b64 v[29:30], off, s9
	scratch_load_b64 v[31:32], off, s10
	scratch_load_b64 v[33:34], off, s8
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[43:44], 3, v[43:44]
	v_add_nc_u32_e32 v9, s46, v9
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[50:51], 3, v[7:8]
	v_add_nc_u32_e32 v7, s4, v7
	s_cmp_lg_u32 s0, 16
	v_add_co_u32 v50, vcc_lo, s22, v50
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v51, vcc_lo, s23, v51, vcc_lo
	v_add_co_u32 v35, vcc_lo, s20, v35
	v_add_co_ci_u32_e32 v36, vcc_lo, s21, v36, vcc_lo
	v_add_co_u32 v43, vcc_lo, s20, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, s21, v44, vcc_lo
	s_waitcnt vmcnt(3)
	s_clause 0x1
	global_store_b64 v[35:36], v[10:11], off
	global_store_b64 v[43:44], v[23:24], off
	s_waitcnt vmcnt(2)
	global_store_b64 v[50:51], v[29:30], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[31:32], s9
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[33:34], s10
	s_cbranch_scc1 .LBB9_66
; %bb.67:                               ; %.preheader670.preheader
                                        ;   in Loop: Header=BB9_61 Depth=1
	s_mov_b32 s0, 0
.LBB9_68:                               ; %.preheader670
                                        ;   Parent Loop BB9_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x90, s0
	v_add_nc_u32_e64 v8, s0, 16
	s_add_i32 s8, s0, 0x90
	s_add_i32 s9, s0, 16
	s_add_i32 s0, s0, 8
	v_add_nc_u32_e32 v29, 40, v7
	v_add_nc_u32_e32 v9, 0x50, v7
	v_add_nc_u32_e32 v30, 40, v8
	v_add_nc_u32_e32 v23, 0x50, v8
	s_cmp_lg_u32 s0, 40
	s_clause 0x1
	scratch_load_b64 v[7:8], v29, off
	scratch_load_b64 v[9:10], v9, off
	s_clause 0x1
	scratch_load_b64 v[11:12], v30, off
	scratch_load_b64 v[23:24], v23, off
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[7:8], s8
	s_waitcnt vmcnt(2)
	scratch_store_b64 v29, v[9:10], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[11:12], s9
	s_waitcnt vmcnt(0)
	scratch_store_b64 v30, v[23:24], off
	s_cbranch_scc1 .LBB9_68
; %bb.69:                               ;   in Loop: Header=BB9_61 Depth=1
	v_add_nc_u32_e32 v1, s48, v1
	v_add_nc_u32_e32 v28, s43, v28
	v_add_nc_u32_e32 v0, s48, v0
	v_add_nc_u32_e32 v6, s48, v6
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s5, s47
	s_cbranch_scc1 .LBB9_61
; %bb.70:                               ; %._crit_edge703.loopexit
	s_clause 0x3
	scratch_load_b64 v[23:24], off, off offset:192
	scratch_load_b128 v[10:13], off, off offset:296
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b64 v[0:1], off, off offset:64
.LBB9_71:                               ; %._crit_edge703
	s_clause 0x3
	scratch_load_b128 v[2:5], off, off offset:160
	scratch_load_b128 v[27:30], off, off offset:32
	scratch_load_b64 v[20:21], off, off offset:200
	scratch_load_b64 v[33:34], off, off offset:72
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[31:32], null, v[2:3], v[2:3], 1.0
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[35:36], null, v[27:28], v[27:28], 1.0
	v_div_scale_f64 v[55:56], vcc_lo, 1.0, v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[43:44], v[31:32]
	v_rcp_f64_e32 v[49:50], v[35:36]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[51:52], -v[31:32], v[43:44], 1.0
	v_fma_f64 v[53:54], -v[35:36], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[43:44], v[43:44], v[51:52], v[43:44]
	v_fma_f64 v[49:50], v[49:50], v[53:54], v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[51:52], -v[31:32], v[43:44], 1.0
	v_fma_f64 v[53:54], -v[35:36], v[49:50], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[43:44], v[43:44], v[51:52], v[43:44]
	v_div_scale_f64 v[51:52], s0, 1.0, v[27:28], 1.0
	v_fma_f64 v[49:50], v[49:50], v[53:54], v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[53:54], v[55:56], v[43:44]
	v_mul_f64 v[57:58], v[51:52], v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[31:32], -v[31:32], v[53:54], v[55:56]
	v_fma_f64 v[35:36], -v[35:36], v[57:58], v[51:52]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[31:32], v[31:32], v[43:44], v[53:54]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[35:36], v[35:36], v[49:50], v[57:58]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[2:3], v[31:32], v[2:3], 1.0
	v_div_fixup_f64 v[27:28], v[35:36], v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[4:5], v[2:3]
	v_mul_f64 v[10:11], v[2:3], v[10:11]
	v_mul_f64 v[2:3], v[29:30], v[27:28]
	v_mul_f64 v[12:13], v[27:28], v[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], -v[4:5], v[23:24], v[20:21]
	v_fma_f64 v[6:7], -v[10:11], v[23:24], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], -v[2:3], v[0:1], v[33:34]
	v_fma_f64 v[8:9], -v[12:13], v[0:1], v[8:9]
	global_load_b64 v[0:1], v[18:19], off
	v_div_scale_f64 v[27:28], null, v[20:21], v[20:21], v[6:7]
	v_div_scale_f64 v[43:44], vcc_lo, v[6:7], v[20:21], v[6:7]
	v_div_scale_f64 v[29:30], null, v[22:23], v[22:23], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[31:32], v[27:28]
	v_rcp_f64_e32 v[33:34], v[29:30]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[27:28], v[31:32], 1.0
	v_fma_f64 v[35:36], -v[29:30], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[31:32], v[18:19], v[31:32]
	v_fma_f64 v[31:32], v[33:34], v[35:36], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[33:34], -v[27:28], v[18:19], 1.0
	v_fma_f64 v[35:36], -v[29:30], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[33:34], v[18:19]
	v_div_scale_f64 v[33:34], s0, v[8:9], v[22:23], v[8:9]
	v_fma_f64 v[31:32], v[31:32], v[35:36], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[35:36], v[43:44], v[18:19]
	v_mul_f64 v[49:50], v[33:34], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[27:28], v[35:36], v[43:44]
	v_fma_f64 v[29:30], -v[29:30], v[49:50], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[18:19], v[27:28], v[18:19], v[35:36]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[27:28], v[29:30], v[31:32], v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[18:19], v[20:21], v[6:7]
	v_div_fixup_f64 v[8:9], v[27:28], v[22:23], v[8:9]
	s_clause 0x1
	scratch_store_b128 off, v[10:13], off offset:296
	scratch_store_b128 off, v[6:9], off offset:336
.LBB9_72:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v6, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v6, 40, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v6, off
	scratch_load_b64 v[8:9], off, s1
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], -v[0:1], v[6:7], v[8:9]
	scratch_store_b64 off, v[6:7], s1
	s_cbranch_scc1 .LBB9_72
; %bb.73:
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b128 v[10:13], off, off offset:296
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], -v[4:5], v[6:7], v[10:11]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[12:13]
	scratch_store_b128 off, v[0:3], off offset:296
.LBB9_74:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v4, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 40
	v_add_nc_u32_e32 v5, 40, v4
	v_add_nc_u32_e32 v4, 0x50, v4
	s_clause 0x1
	scratch_load_b64 v[0:1], v5, off
	scratch_load_b64 v[2:3], off, s1
	s_waitcnt vmcnt(1)
	scratch_store_b64 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v5, v[2:3], off
	s_cbranch_scc1 .LBB9_74
; %bb.75:
	v_add_nc_u32_e32 v6, v47, v25
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, bt@rel32@lo+4
	s_addc_u32 s1, s1, bt@rel32@hi+12
	s_and_not1_b32 vcc_lo, exec_lo, s45
	s_cbranch_vccnz .LBB9_77
; %bb.76:                               ; %.._crit_edge709_crit_edge
	v_add_nc_u32_e32 v0, v47, v25
	s_mov_b32 s2, 0
	s_branch .LBB9_78
.LBB9_77:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
.LBB9_78:                               ; %Flow1068
	s_load_b64 s[0:1], s[0:1], 0x0
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB9_88
; %bb.79:                               ; %.preheader.lr.ph
	v_mad_u64_u32 v[0:1], null, v38, 5, 10
	s_add_i32 s2, s17, -3
	s_lshl_b32 s4, s17, 1
	s_mul_i32 s3, s18, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s17, v0, -5
	v_add3_u32 v2, s40, s3, v46
	s_add_i32 s3, s17, -1
	v_mul_lo_u32 v3, s16, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s16, v1
	v_mad_u64_u32 v[1:2], null, s6, 5, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v3, s16, v42
	v_add3_u32 v7, v0, s6, 1
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v8, v1, v48, 5
.LBB9_80:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB9_81 Depth 2
                                        ;     Child Loop BB9_85 Depth 2
	v_mad_u64_u32 v[0:1], null, s2, s7, v[38:39]
	s_add_i32 s5, s2, s17
	s_mov_b32 s6, 0
	v_mad_u64_u32 v[1:2], null, s5, s7, v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v0, s33, v[39:40]
	v_mad_u64_u32 v[4:5], null, v1, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_mov_b32_e32 v4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
.LBB9_81:                               ;   Parent Loop BB9_80 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s8, s6, 0x110
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[9:10], 3, v[4:5]
	v_add_nc_u32_e64 v5, 0x110, s6
	v_add_nc_u32_e32 v4, s44, v4
	s_add_i32 s6, s6, 8
	s_cmp_lg_u32 s6, 24
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s22, v9
	v_add_nc_u32_e32 v11, 40, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
	v_add_nc_u32_e32 v5, 0x50, v5
	scratch_load_b64 v[11:12], v11, off
	global_load_b64 v[9:10], v[9:10], off
	scratch_load_b64 v[18:19], v5, off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[9:10], -v[0:1], v[11:12], v[9:10]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[18:19], v[9:10]
	scratch_store_b64 off, v[9:10], s8
	s_cbranch_scc1 .LBB9_81
; %bb.82:                               ;   in Loop: Header=BB9_80 Depth=1
	s_add_i32 s5, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s5, s19
	v_mad_u64_u32 v[0:1], null, s5, s18, v[40:41]
	s_add_i32 s8, s6, s17
	v_mad_u64_u32 v[1:2], null, s6, s7, v[38:39]
	s_sub_i32 s6, s8, s19
	v_mad_u64_u32 v[2:3], null, s6, s18, v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v0, s16, v[41:42]
	v_mad_u64_u32 v[9:10], null, v1, s33, v[39:40]
	s_sub_i32 s6, s6, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, v2, s16, v[41:42]
	v_mad_u64_u32 v[1:2], null, s6, s7, v[38:39]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v1, s33, v[39:40]
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s20, v9
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v10, vcc_lo
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	global_load_b64 v[18:19], v[2:3], off
	global_load_b64 v[20:21], v[9:10], off
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	scratch_load_b128 v[9:12], off, off offset:336
	v_mad_u64_u32 v[4:5], null, s8, s7, v[38:39]
	v_add_co_u32 v0, vcc_lo, s22, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[22:23], v[0:1], off
	global_load_b64 v[27:28], v[2:3], off
	v_mad_u64_u32 v[0:1], null, s5, s7, v[38:39]
	v_mad_u64_u32 v[1:2], null, v4, s33, v[39:40]
	s_add_i32 s5, s2, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_ge_i32 s5, s3
	v_mad_u64_u32 v[3:4], null, v0, s33, v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s20, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v3, vcc_lo
	global_load_b64 v[29:30], v[0:1], off
	scratch_load_b128 v[0:3], off, off offset:376
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(5)
	v_fma_f64 v[9:10], -v[20:21], v[9:10], v[18:19]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[11:12], -v[27:28], v[11:12], v[22:23]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], -v[29:30], v[0:1], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[11:12], -v[4:5], v[2:3], v[11:12]
	scratch_store_b128 off, v[9:12], off offset:296
	s_cbranch_scc1 .LBB9_84
; %bb.83:                               ;   in Loop: Header=BB9_80 Depth=1
	s_clause 0x1
	scratch_load_b128 v[9:12], off, off offset:352
	scratch_load_b64 v[4:5], off, off offset:368
	v_add_f64 v[18:19], v[0:1], v[2:3]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[0:1], s[0:1]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[9:10], v[9:10], s[0:1]
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v5, 0x80000000, v5
	v_fma_f64 v[20:21], v[18:19], 0.5, -v[9:10]
	v_fma_f64 v[0:1], v[18:19], 0.5, v[9:10]
	v_dual_mov_b32 v18, v11 :: v_dual_mov_b32 v19, v12
	s_clause 0x2
	scratch_store_b128 off, v[2:5], off offset:352
	scratch_store_b128 off, v[18:21], off offset:368
	scratch_store_b64 off, v[0:1], off offset:384
.LBB9_84:                               ;   in Loop: Header=BB9_80 Depth=1
	s_mov_b32 s5, 0
	s_mov_b32 s6, s41
.LBB9_85:                               ;   Parent Loop BB9_80 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s6, 40
	s_clause 0x2
	scratch_load_b64 v[0:1], off, s6
	scratch_load_b64 v[2:3], off, s6 offset:-40
	scratch_load_b64 v[4:5], off, s8
	v_add_nc_u32_e32 v9, s5, v8
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s14, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[2:3], s6
	s_add_i32 s6, s6, 8
	s_cmp_lg_u32 s5, 5
	scratch_store_b64 off, v[0:1], s8
	s_waitcnt vmcnt(0)
	global_store_b64 v[9:10], v[4:5], off
	s_cbranch_scc1 .LBB9_85
; %bb.86:                               ;   in Loop: Header=BB9_80 Depth=1
	v_subrev_nc_u32_e32 v7, s43, v7
	v_subrev_nc_u32_e32 v8, s42, v8
	s_add_i32 s5, s2, -1
	s_cmp_gt_i32 s2, 0
	s_mov_b32 s2, s5
	s_cbranch_scc1 .LBB9_80
; %bb.87:
	v_mov_b32_e32 v0, v6
.LBB9_88:                               ; %._crit_edge709
	s_clause 0x2
	scratch_load_b128 v[1:4], off, off offset:368
	scratch_load_b64 v[9:10], off, off offset:384
	scratch_load_b128 v[5:8], off, off offset:352
	s_waitcnt vmcnt(2)
	v_xor_b32_e32 v2, 0x80000000, v2
	s_waitcnt vmcnt(1)
	v_add_f64 v[11:12], v[3:4], v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[9:10], v[11:12], 0.5
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[3:4], s[0:1], v[3:4]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -s[0:1], v[5:6], v[9:10]
	v_fma_f64 v[5:6], s[0:1], v[5:6], v[9:10]
	v_add_nc_u32_e32 v9, v26, v25
	s_mov_b32 s0, 0
	v_add_nc_u32_e32 v18, 1, v9
	v_add_nc_u32_e32 v20, 2, v9
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v19, 31, v18
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[20:21], 3, v[20:21]
	v_add_co_u32 v18, vcc_lo, s14, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
	v_add_co_u32 v20, vcc_lo, s14, v20
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v21, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	s_clause 0x4
	global_store_b64 v[18:19], v[1:2], off
	global_store_b64 v[20:21], v[7:8], off
	global_store_b64 v[14:15], v[11:12], off
	global_store_b64 v[9:10], v[3:4], off
	global_store_b64 v[16:17], v[5:6], off
.LBB9_89:                               ; =>This Inner Loop Header: Depth=1
	scratch_load_b64 v[1:2], off, s41
	v_add_nc_u32_e32 v3, s0, v0
	s_add_i32 s0, s0, 1
	s_add_i32 s41, s41, 8
	s_cmp_lg_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s14, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[3:4], v[1:2], off
	s_cbranch_scc1 .LBB9_89
.LBB9_90:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14y_solve_kernelPdS_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 400
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 96
		.amdhsa_next_free_sgpr 55
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14y_solve_kernelPdS_S_S_S_S_iii,"axG",@progbits,_ZL14y_solve_kernelPdS_S_S_S_S_iii,comdat
.Lfunc_end9:
	.size	_ZL14y_solve_kernelPdS_S_S_S_S_iii, .Lfunc_end9-_ZL14y_solve_kernelPdS_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9596
; NumSgprs: 57
; NumVgprs: 96
; ScratchSize: 400
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 57
; NumVGPRsForWavesPerEU: 96
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,"axG",@progbits,_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,comdat
	.globl	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii ; -- Begin function _ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
	.p2align	8
	.type	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,@function
_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii: ; @_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b128 s[24:27], s[0:1], 0x50
	v_and_b32_e32 v46, 0x3ff, v0
	v_bfe_u32 v45, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s54, s14, s3
	s_mul_i32 s6, s15, s2
	v_add_nc_u32_e32 v40, s54, v46
	v_add_nc_u32_e32 v41, s6, v45
	s_add_i32 s2, s25, -1
	s_add_i32 s3, s24, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v39, 1, v40
	v_add_nc_u32_e32 v38, 1, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v39
	v_cmp_gt_i32_e64 s2, s3, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB10_86
; %bb.1:
	s_add_i32 s7, s25, -2
	s_lshl_b32 s27, s26, 2
	s_mov_b32 s2, 0
	v_mad_u64_u32 v[4:5], null, s27, s7, v[40:41]
	s_mov_b32 s3, s2
	v_mov_b32_e32 v0, 0
	s_add_i32 s33, s24, -2
	s_mul_i32 s58, s26, s7
	v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[7:8], null, v4, s33, v[41:42]
	v_mad_u64_u32 v[9:10], null, s58, 5, v[40:41]
	v_mov_b32_e32 v1, v0
	v_mov_b32_e32 v2, v0
	v_mov_b32_e32 v3, v0
	v_mad_u64_u32 v[10:11], null, s58, 6, v[40:41]
	s_load_b128 s[28:31], s[0:1], 0x40
	v_ashrrev_i32_e32 v8, 31, v7
	scratch_store_b128 off, v[0:3], off offset:16
	v_mov_b32_e32 v1, 0x3ff00000
	v_mad_u64_u32 v[11:12], null, v9, s33, v[41:42]
	s_clause 0x1
	scratch_store_b128 off, v[0:3], off offset:32
	scratch_store_b64 off, v[5:6], off offset:48
	v_lshlrev_b64 v[2:3], 3, v[7:8]
	v_mad_u64_u32 v[7:8], null, v10, s33, v[41:42]
	v_ashrrev_i32_e32 v12, 31, v11
	v_mad_u64_u32 v[9:10], null, s58, 7, v[40:41]
	v_lshl_add_u32 v4, s58, 3, v40
	s_load_b512 s[8:23], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[10:11], 3, v[11:12]
	v_ashrrev_i32_e32 v8, 31, v7
	s_mov_b32 s34, 0x9999999a
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s28, v2
	v_mad_u64_u32 v[12:13], null, v9, s33, v[41:42]
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_ci_u32_e32 v3, vcc_lo, s29, v3, vcc_lo
	v_add_co_u32 v9, vcc_lo, s28, v10
	v_mad_u64_u32 v[14:15], null, v4, s33, v[41:42]
	v_add_co_ci_u32_e32 v10, vcc_lo, s29, v11, vcc_lo
	v_add_co_u32 v7, vcc_lo, s28, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s29, v8, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_clause 0x2
	global_store_b64 v[2:3], v[5:6], off
	global_store_b64 v[9:10], v[5:6], off
	global_store_b64 v[7:8], v[0:1], off
	v_mul_lo_u32 v10, s24, v39
	v_lshlrev_b64 v[2:3], 3, v[12:13]
	v_lshlrev_b64 v[0:1], 3, v[14:15]
	s_mov_b32 s36, 0x55555555
	s_mov_b32 s38, 0xf5c28f5b
	s_mov_b32 s35, 0x3fb99999
	s_mov_b32 s37, 0x3ff55555
	v_add_co_u32 v7, vcc_lo, s28, v2
	v_add3_u32 v11, v45, v10, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s29, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v2, 1, v11
	s_mov_b32 s39, 0x3fff5c28
	s_mul_i32 s52, s25, s24
	s_mov_b64 s[40:41], 0
	s_clause 0x1
	global_store_b64 v[7:8], v[5:6], off
	global_store_b64 v[0:1], v[5:6], off
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB10_2:                               ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_cmp_eq_u32 s40, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[2:3]
	v_add_co_u32 v18, vcc_lo, s8, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
	global_load_b64 v[18:19], v[18:19], off
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s40, 1
	global_load_b64 v[16:17], v[16:17], off
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s40, 2
	v_add_nc_u32_e32 v2, s52, v2
	s_cselect_b32 s1, -1, 0
	s_waitcnt vmcnt(1)
	v_mul_f64 v[20:21], v[18:19], s[34:35]
	v_fma_f64 v[18:19], v[18:19], s[34:35], 1.0
	s_waitcnt vmcnt(0)
	v_cndmask_b32_e32 v1, v1, v17, vcc_lo
	v_cndmask_b32_e64 v9, v9, v17, s1
	v_cndmask_b32_e64 v8, v8, v16, s1
	v_cndmask_b32_e64 v7, v7, v17, s0
	v_cndmask_b32_e64 v6, v6, v16, s0
	v_cndmask_b32_e32 v0, v0, v16, vcc_lo
	v_fma_f64 v[22:23], v[20:21], s[38:39], 1.0
	v_fma_f64 v[20:21], v[20:21], s[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v15, v23, s1
	v_cmp_gt_f64_e64 s2, v[20:21], v[22:23]
	v_cndmask_b32_e64 v24, v14, v22, s1
	v_dual_cndmask_b32 v25, v5, v23 :: v_dual_cndmask_b32 v26, v4, v22
	v_cndmask_b32_e64 v23, v13, v23, s0
	v_cndmask_b32_e64 v22, v12, v22, s0
	v_dual_cndmask_b32 v5, v5, v21 :: v_dual_cndmask_b32 v4, v4, v20
	v_cndmask_b32_e64 v12, v12, v20, s0
	v_cndmask_b32_e64 v13, v13, v21, s0
	v_cndmask_b32_e64 v14, v14, v20, s1
	v_cndmask_b32_e64 v15, v15, v21, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v22, v12, s2
	v_cndmask_b32_e64 v13, v23, v13, s2
	v_cndmask_b32_e64 v5, v25, v5, s2
	v_cndmask_b32_e64 v20, v26, v4, s2
	v_cndmask_b32_e64 v14, v24, v14, s2
	v_cndmask_b32_e64 v15, v3, v15, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, v5, v13, s0
	v_cndmask_b32_e64 v21, v20, v12, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v3, v15, s1
	v_cndmask_b32_e64 v3, v21, v14, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f64_e64 s2, v[3:4], v[18:19]
	s_and_b32 s3, s2, s1
	s_and_b32 s4, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v14, v14, v18, s3
	v_cndmask_b32_e64 v12, v12, v18, s4
	v_cndmask_b32_e64 v18, v20, v18, s2
	v_cndmask_b32_e64 v13, v13, v19, s4
	v_cndmask_b32_e64 v5, v5, v19, s2
	v_cndmask_b32_e64 v15, v15, v19, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v18, v12, s0
	v_cndmask_b32_e64 v4, v5, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v14, s1
	v_cndmask_b32_e64 v4, v4, v15, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s2, 1.0, v[3:4]
	s_and_b32 s1, s2, s1
	s_and_b32 s0, s2, s0
	s_and_b32 s2, s2, vcc_lo
	v_cndmask_b32_e64 v15, v15, 0x3ff00000, s1
	v_cndmask_b32_e64 v13, v13, 0x3ff00000, s0
	v_cndmask_b32_e64 v5, v5, 0x3ff00000, s2
	v_cndmask_b32_e64 v14, v14, 0, s1
	v_cndmask_b32_e64 v12, v12, 0, s0
	v_cndmask_b32_e64 v4, v18, 0, s2
	s_add_u32 s40, s40, 1
	s_addc_u32 s41, s41, 0
	s_cmp_lg_u32 s40, 3
	s_cbranch_scc1 .LBB10_2
; %bb.3:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, dtz1@rel32@lo+4
	s_addc_u32 s1, s1, dtz1@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, c2dttz1@rel32@lo+4
	s_addc_u32 s3, s3, c2dttz1@rel32@hi+12
	s_load_b64 s[0:1], s[0:1], 0x0
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, dttz2@rel32@lo+4
	s_addc_u32 s5, s5, dttz2@rel32@hi+12
	s_load_b64 s[36:37], s[2:3], 0x0
	s_load_b64 s[34:35], s[4:5], 0x0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, comz5@rel32@lo+4
	s_addc_u32 s3, s3, comz5@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, comz4@rel32@lo+4
	s_addc_u32 s5, s5, comz4@rel32@hi+12
	s_getpc_b64 s[42:43]
	s_add_u32 s42, s42, comz1@rel32@lo+4
	s_addc_u32 s43, s43, comz1@rel32@hi+12
	s_load_b64 s[38:39], s[2:3], 0x0
	s_load_b64 s[40:41], s[4:5], 0x0
	s_load_b64 s[2:3], s[42:43], 0x0
	v_add_nc_u32_e64 v48, 16, 40
	s_mul_i32 s55, s58, s33
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[2:3], v[14:15], s[0:1]
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	v_fma_f64 v[16:17], v[12:13], s[36:37], 1.0
	v_add_f64 v[24:25], s[2:3], 0
	s_add_i32 s2, s27, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	s_mul_i32 s2, s7, s2
	v_fma_f64 v[18:19], v[8:9], s[34:35], -v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[3:4], v[0:1], -s[34:35], -v[4:5]
	v_add_f64 v[16:17], v[16:17], s[38:39]
	v_add3_u32 v0, s54, s2, v46
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v0, v0, s33
	v_mov_b32_e32 v2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v0, v45, v0, s6
	v_add_f64 v[18:19], v[18:19], -s[40:41]
	s_clause 0x2
	scratch_store_b128 off, v[1:4], off offset:56
	scratch_store_b128 off, v[16:19], off offset:72
	scratch_store_b64 off, v[24:25], off offset:88
.LBB10_4:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v1, s2, v48
	s_add_i32 s2, s2, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s2, 40
	scratch_load_b64 v[2:3], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	v_add_nc_u32_e32 v0, s55, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s28, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s29, v5, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[4:5], v[2:3], off
	s_cbranch_scc1 .LBB10_4
; %bb.5:
	v_mad_u64_u32 v[42:43], null, v11, 5, 5
	s_mul_i32 s4, s52, 5
	s_add_i32 s53, 0x110, 40
	s_ashr_i32 s5, s4, 31
	s_mov_b32 s42, 0
	s_lshl_b64 s[2:3], s[4:5], 3
	s_mov_b32 s5, s53
.LBB10_6:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s42, v42
	s_add_i32 s42, s42, 1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s22, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s23, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v0, s2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[0:1], s5 offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[2:3], s5
	s_add_i32 s5, s5, 8
	s_cmp_eq_u32 s42, 3
	s_cbranch_scc0 .LBB10_6
; %bb.7:                                ; %.preheader794
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v16, 0
	v_dual_mov_b32 v17, 0x3ff00000 :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v10, v8 :: v_dual_add_nc_u32 v49, v10, v38
	s_add_i32 s56, s26, -2
	v_mov_b32_e32 v19, 0
	v_mul_u32_u24_e32 v47, 5, v45
	s_cmp_gt_i32 s26, 2
	s_mul_i32 s59, s26, s25
	s_cselect_b32 s60, -1, 0
	s_cmp_lt_i32 s26, 3
	s_mul_i32 s57, s7, s33
	s_mul_i32 s5, s59, s24
	s_cbranch_scc1 .LBB10_47
; %bb.8:                                ; %.lr.ph
	v_lshl_add_u32 v2, s25, 1, v40
	s_add_i32 s44, s27, 2
	s_getpc_b64 s[42:43]
	s_add_u32 s42, s42, comz6@rel32@lo+4
	s_addc_u32 s43, s43, comz6@rel32@hi+12
	s_mul_i32 s44, s7, s44
	s_load_b64 s[42:43], s[42:43], 0x0
	v_mad_u64_u32 v[0:1], null, s24, v2, s[24:25]
	v_add3_u32 v1, s54, s44, v46
	s_mul_i32 s44, s6, 5
	v_dual_mov_b32 v3, 16 :: v_dual_mov_b32 v54, 0x3ff00000
	s_mov_b32 s46, 0x55555555
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v4, v1, s33
	v_mad_u64_u32 v[1:2], null, v0, 5, s[44:45]
	v_mov_b32_e32 v0, 0x110
	v_dual_mov_b32 v55, v49 :: v_dual_add_nc_u32 v50, 0x50, v3
	v_mov_b32_e32 v26, 0
	s_mov_b32 s44, 0x9999999a
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v51, 0x50, v0
	v_add3_u32 v52, v45, v4, s6
	v_add3_u32 v53, v1, v47, 5
	s_mov_b32 s48, 0xf5c28f5b
	s_add_i32 s61, s26, -3
	s_mov_b32 s45, 0x3fb99999
	s_mov_b32 s47, 0x3ff55555
	s_mov_b32 s49, 0x3fff5c28
	s_add_i32 s62, s26, -5
	s_mov_b32 s50, 0
	s_mov_b32 s63, 0
.LBB10_9:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB10_29 Depth 2
                                        ;     Child Loop BB10_34 Depth 2
                                        ;     Child Loop BB10_36 Depth 2
                                        ;     Child Loop BB10_38 Depth 2
                                        ;     Child Loop BB10_40 Depth 2
                                        ;     Child Loop BB10_42 Depth 2
                                        ;     Child Loop BB10_44 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s51, s63, 2
	s_cmp_lg_u32 s63, s61
	s_cbranch_scc0 .LBB10_16
; %bb.10:                               ;   in Loop: Header=BB10_9 Depth=1
	s_add_i32 s64, s63, 3
	v_fma_f64 v[34:35], s[36:37], v[14:15], 1.0
	v_mad_u64_u32 v[0:1], null, s64, s25, v[39:40]
	s_cmp_lg_u32 s63, 0
	v_mov_b32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v0, s24, v[38:39]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v2, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_load_b64 v[4:5], v[2:3], off
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[0:1], v[4:5], s[44:45]
	v_fma_f64 v[4:5], v[4:5], s[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[0:1], s[46:47], 1.0
	v_fma_f64 v[0:1], v[0:1], s[48:49], 1.0
	v_cmp_gt_f64_e32 vcc_lo, v[18:19], v[0:1]
	v_dual_cndmask_b32 v1, v1, v19 :: v_dual_cndmask_b32 v0, v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
	v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_mul_f64 v[4:5], s[0:1], v[12:13]
	v_cmp_ngt_f64_e32 vcc_lo, 1.0, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[6:7], -s[34:35], -v[4:5]
	v_cndmask_b32_e32 v21, 0x3ff00000, v1, vcc_lo
	v_cndmask_b32_e32 v20, 0, v0, vcc_lo
	v_mul_f64 v[0:1], s[0:1], v[20:21]
	scratch_store_b128 off, v[26:29], off offset:96
	s_waitcnt vmcnt(0)
	v_fma_f64 v[36:37], s[34:35], v[2:3], -v[0:1]
	s_clause 0x1
	scratch_store_b128 off, v[34:37], off offset:112
	scratch_store_b64 off, v[26:27], off offset:128
	s_cbranch_scc0 .LBB10_17
; %bb.11:                               ;   in Loop: Header=BB10_9 Depth=1
	s_cmp_ge_i32 s51, s61
	s_cbranch_scc0 .LBB10_18
; %bb.12:                               ;   in Loop: Header=BB10_9 Depth=1
	s_cmp_lg_u32 s63, s62
	s_cbranch_scc0 .LBB10_19
; %bb.13:                               ;   in Loop: Header=BB10_9 Depth=1
	v_mov_b32_e32 v43, 0
	v_dual_mov_b32 v44, 0 :: v_dual_mov_b32 v31, v29
	v_mov_b32_e32 v30, v28
	v_dual_mov_b32 v32, v34 :: v_dual_mov_b32 v33, v35
	s_cmp_lg_u32 s51, s56
	s_cbranch_scc1 .LBB10_15
; %bb.14:                               ;   in Loop: Header=BB10_9 Depth=1
	v_add_f64 v[58:59], v[28:29], -s[40:41]
	v_add_f64 v[32:33], s[38:39], v[34:35]
	v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v57, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x1
	scratch_store_b128 off, v[56:59], off offset:96
	scratch_store_b64 off, v[32:33], off offset:112
	v_dual_mov_b32 v30, v58 :: v_dual_mov_b32 v31, v59
.LBB10_15:                              ; %Flow1202
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, 0
	s_branch .LBB10_20
.LBB10_16:                              ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, -1
                                        ; implicit-def: $vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB10_31
.LBB10_17:                              ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB10_26
.LBB10_18:                              ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
	s_branch .LBB10_23
.LBB10_19:                              ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, -1
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr30_vgpr31
.LBB10_20:                              ; %Flow1203
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s64
	s_cbranch_vccnz .LBB10_22
; %bb.21:                               ;   in Loop: Header=BB10_9 Depth=1
	v_add_f64 v[58:59], v[28:29], -s[40:41]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[60:61], v[34:35], s[42:43]
	v_add_f64 v[62:63], v[36:37], -s[40:41]
	v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v57, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x1
	scratch_store_b128 off, v[56:59], off offset:96
	scratch_store_b128 off, v[60:63], off offset:112
	v_dual_mov_b32 v30, v58 :: v_dual_mov_b32 v31, v59
	v_dual_mov_b32 v32, v60 :: v_dual_mov_b32 v33, v61
.LBB10_22:                              ; %Flow1204
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, 0
.LBB10_23:                              ; %Flow1205
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s64
	s_cbranch_vccnz .LBB10_25
; %bb.24:                               ;   in Loop: Header=BB10_9 Depth=1
	v_add_f64 v[58:59], v[28:29], -s[40:41]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[60:61], v[34:35], s[42:43]
	v_add_f64 v[62:63], v[36:37], -s[40:41]
	v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v57, v25
	v_dual_mov_b32 v44, v25 :: v_dual_mov_b32 v43, v24
	s_clause 0x2
	scratch_store_b128 off, v[56:59], off offset:96
	scratch_store_b128 off, v[60:63], off offset:112
	scratch_store_b64 off, v[24:25], off offset:128
	v_dual_mov_b32 v30, v58 :: v_dual_mov_b32 v31, v59
	v_dual_mov_b32 v32, v60 :: v_dual_mov_b32 v33, v61
.LBB10_25:                              ; %Flow1206
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_mov_b32 s64, 0
.LBB10_26:                              ; %Flow1207
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s64
	s_cbranch_vccnz .LBB10_28
; %bb.27:                               ;   in Loop: Header=BB10_9 Depth=1
	v_add_f64 v[30:31], v[28:29], -s[40:41]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[32:33], v[34:35], s[42:43]
	v_add_f64 v[22:23], v[36:37], -s[40:41]
	v_mov_b32_e32 v43, 0
	v_mov_b32_e32 v44, 0
	s_clause 0x1
	scratch_store_b128 off, v[30:33], off offset:104
	scratch_store_b128 off, v[22:25], off offset:120
.LBB10_28:                              ;   in Loop: Header=BB10_9 Depth=1
	v_mov_b32_e32 v0, v52
	s_mov_b32 s64, 0
.LBB10_29:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s64, v50
	s_add_i32 s64, s64, 8
	s_cmp_lg_u32 s64, 40
	scratch_load_b64 v[4:5], v1, off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[18:19], 3, v[0:1]
	v_add_nc_u32_e32 v0, s55, v0
	v_add_co_u32 v18, vcc_lo, s28, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, s29, v19, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[18:19], v[4:5], off
	s_cbranch_scc1 .LBB10_29
; %bb.30:                               ;   in Loop: Header=BB10_9 Depth=1
	v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v19, v15
	v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s64, 0
.LBB10_31:                              ; %Flow1208
                                        ;   in Loop: Header=BB10_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s64
	s_cbranch_vccz .LBB10_33
; %bb.32:                               ;   in Loop: Header=BB10_9 Depth=1
	s_add_i32 s64, s51, s27
	s_mov_b32 s51, s50
	v_mad_u64_u32 v[0:1], null, s64, s7, v[40:41]
	v_dual_mov_b32 v27, v26 :: v_dual_mov_b32 v34, s50
	v_dual_mov_b32 v28, v26 :: v_dual_mov_b32 v35, s51
	s_add_i32 s51, s64, s26
	v_dual_mov_b32 v29, v26 :: v_dual_mov_b32 v30, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_u64_u32 v[1:2], null, v0, s33, v[41:42]
	v_mad_u64_u32 v[3:4], null, s51, s7, v[40:41]
	s_add_i32 s51, s51, s26
	s_clause 0x1
	scratch_store_b128 off, v[26:29], off offset:96
	scratch_store_b64 off, v[34:35], off offset:128
	v_mad_u64_u32 v[4:5], null, s51, s7, v[40:41]
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s51, s51, s26
	v_mad_u64_u32 v[18:19], null, v3, s33, v[41:42]
	v_dual_mov_b32 v27, v54 :: v_dual_mov_b32 v32, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_mad_u64_u32 v[2:3], null, s51, s7, v[40:41]
	s_add_i32 s51, s51, s26
	v_mad_u64_u32 v[20:21], null, v4, s33, v[41:42]
	v_mad_u64_u32 v[3:4], null, s51, s7, v[40:41]
	v_add_co_u32 v0, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s29, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_mad_u64_u32 v[4:5], null, v2, s33, v[41:42]
	v_ashrrev_i32_e32 v21, 31, v20
	global_store_b64 v[0:1], v[34:35], off
	v_lshlrev_b64 v[0:1], 3, v[18:19]
	v_mad_u64_u32 v[18:19], null, v3, s33, v[41:42]
	v_lshlrev_b64 v[2:3], 3, v[20:21]
	v_ashrrev_i32_e32 v5, 31, v4
	scratch_store_b128 off, v[26:29], off offset:112
	v_add_co_u32 v28, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v29, vcc_lo, s29, v1, vcc_lo
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v36, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v37, vcc_lo, s29, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 3, v[18:19]
	v_add_co_u32 v56, vcc_lo, s28, v0
	v_mov_b32_e32 v31, 0
	v_add_co_ci_u32_e32 v57, vcc_lo, s29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v58, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v59, vcc_lo, s29, v3, vcc_lo
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v33, 0x3ff00000
	v_dual_mov_b32 v44, v31 :: v_dual_mov_b32 v23, v17
	v_dual_mov_b32 v18, v12 :: v_dual_mov_b32 v43, v30
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v22, v16 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v20, v14 :: v_dual_mov_b32 v21, v15
	v_mov_b32_e32 v19, v13
	s_clause 0x3
	global_store_b64 v[28:29], v[34:35], off
	global_store_b64 v[36:37], v[26:27], off
	global_store_b64 v[56:57], v[34:35], off
	global_store_b64 v[58:59], v[34:35], off
.LBB10_33:                              ;   in Loop: Header=BB10_9 Depth=1
	v_mov_b32_e32 v6, v51
	s_mov_b32 s51, 0
.LBB10_34:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s51, v53
	s_add_i32 s51, s51, 1
	s_cmp_lg_u32 s51, 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v6, v[7:8], off
	v_add_nc_u32_e32 v6, 8, v6
	s_cbranch_scc1 .LBB10_34
; %bb.35:                               ;   in Loop: Header=BB10_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:32
	scratch_load_b64 v[12:13], off, off offset:48
	s_mov_b32 s51, 0
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[27:28], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[27:28], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[16:17], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[16:17]
	v_div_fixup_f64 v[10:11], v[10:11], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[12:13]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB10_36:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s64, s51, 0x110
	s_add_i32 s51, s51, 8
	scratch_load_b64 v[12:13], off, s64
	s_cmp_lg_u32 s51, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s64
	s_cbranch_scc1 .LBB10_36
; %bb.37:                               ;   in Loop: Header=BB10_9 Depth=1
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s51, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB10_38:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v12, 0x110, s51
	s_add_i32 s64, s51, 0x110
	s_add_i32 s51, s51, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s51, 24
	v_add_nc_u32_e32 v16, 40, v12
	s_clause 0x1
	scratch_load_b64 v[12:13], off, s64
	scratch_load_b64 v[14:15], v16, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], -v[10:11], v[12:13], v[14:15]
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB10_38
; %bb.39:                               ;   in Loop: Header=BB10_9 Depth=1
	v_fma_f64 v[10:11], -v[6:7], v[43:44], v[30:31]
	v_fma_f64 v[12:13], -v[8:9], v[43:44], v[32:33]
	s_mov_b32 s51, 0
	scratch_store_b128 off, v[10:13], off offset:104
.LBB10_40:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v10, 0x110, s51
	s_add_i32 s64, s51, 0x110
	s_add_i32 s51, s51, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s51, 24
	v_add_nc_u32_e32 v14, 0x50, v10
	s_clause 0x1
	scratch_load_b64 v[10:11], off, s64
	scratch_load_b64 v[12:13], v14, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], -v[43:44], v[10:11], v[12:13]
	scratch_store_b64 v14, v[10:11], off
	s_cbranch_scc1 .LBB10_40
; %bb.41:                               ;   in Loop: Header=BB10_9 Depth=1
	v_mad_u64_u32 v[10:11], null, s63, s7, v[40:41]
	s_add_i32 s51, s63, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, s51, s7, v[40:41]
	s_mov_b32 s51, 0
	v_mad_u64_u32 v[12:13], null, v10, s33, v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v11, s33, v[41:42]
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	v_add_co_u32 v10, vcc_lo, s28, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s29, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s28, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s29, v13, vcc_lo
	s_clause 0x1
	global_store_b64 v[10:11], v[6:7], off
	global_store_b64 v[12:13], v[8:9], off
.LBB10_42:                              ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e64 v6, s51, 16
	s_add_i32 s64, s51, 16
	s_add_i32 s51, s51, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s51, 40
	v_add_nc_u32_e32 v10, 40, v6
	v_add_nc_u32_e32 v8, 0x50, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v10, off
	scratch_load_b64 v[8:9], v8, off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[6:7], s64
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	s_cbranch_scc1 .LBB10_42
; %bb.43:                               ; %.preheader793.preheader
                                        ;   in Loop: Header=BB10_9 Depth=1
	v_mov_b32_e32 v6, v55
	s_mov_b32 s51, 0
.LBB10_44:                              ; %.preheader793
                                        ;   Parent Loop BB10_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x110, s51
	s_add_i32 s64, s51, 0x110
	s_add_i32 s51, s51, 8
	s_cmp_lg_u32 s51, 24
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v16, 40, v7
	v_add_nc_u32_e32 v7, 0x50, v7
	s_clause 0x2
	scratch_load_b64 v[8:9], off, s64
	scratch_load_b64 v[10:11], v16, off
	scratch_load_b64 v[12:13], v7, off
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 3, v[6:7]
	v_add_nc_u32_e32 v6, s5, v6
	v_add_co_u32 v14, vcc_lo, s30, v14
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, s31, v15, vcc_lo
	s_waitcnt vmcnt(2)
	global_store_b64 v[14:15], v[8:9], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[10:11], s64
	s_waitcnt vmcnt(0)
	scratch_store_b64 v16, v[12:13], off
	s_cbranch_scc1 .LBB10_44
; %bb.45:                               ;   in Loop: Header=BB10_9 Depth=1
	v_add_nc_u32_e32 v52, s57, v52
	v_add_nc_u32_e32 v53, s4, v53
	v_add_nc_u32_e32 v55, s52, v55
	s_add_i32 s63, s63, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s63, s56
	s_cbranch_scc0 .LBB10_48
; %bb.46:                               ;   in Loop: Header=BB10_9 Depth=1
	v_dual_mov_b32 v12, v18 :: v_dual_mov_b32 v13, v19
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v14, v20 :: v_dual_mov_b32 v15, v21
	v_dual_mov_b32 v16, v22 :: v_dual_mov_b32 v17, v23
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
	s_branch .LBB10_9
.LBB10_47:
	v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
	v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
	v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
	v_dual_mov_b32 v8, v18 :: v_dual_mov_b32 v9, v19
	s_branch .LBB10_49
.LBB10_48:                              ; %._crit_edge.loopexit
	s_clause 0x1
	scratch_load_b128 v[16:19], off, off offset:32
	scratch_load_b64 v[8:9], off, off offset:48
.LBB10_49:                              ; %._crit_edge
	s_waitcnt vmcnt(1)
	v_div_scale_f64 v[6:7], null, v[16:17], v[16:17], 1.0
	v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[16:17], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[6:7], -v[6:7], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[12:13]
	v_div_fixup_f64 v[10:11], v[6:7], v[16:17], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[6:7], v[18:19], v[10:11]
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	scratch_store_b128 off, v[6:9], off offset:40
.LBB10_50:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB10_50
; %bb.51:
	s_clause 0x1
	scratch_load_b128 v[10:13], off, off offset:64
	scratch_load_b64 v[14:15], off, off offset:80
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(1)
	v_fma_f64 v[12:13], -v[6:7], v[10:11], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[8:9], v[10:11], v[14:15]
	scratch_store_b128 off, v[12:15], off offset:72
.LBB10_52:                              ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v14, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v18, 40, v14
	s_clause 0x1
	scratch_load_b64 v[14:15], off, s1
	scratch_load_b64 v[16:17], v18, off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[14:15], -v[10:11], v[14:15], v[16:17]
	scratch_store_b64 v18, v[14:15], off
	s_cbranch_scc1 .LBB10_52
; %bb.53:
	v_div_scale_f64 v[10:11], null, v[12:13], v[12:13], 1.0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	v_fma_f64 v[10:11], -v[10:11], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[18:19]
	v_div_fixup_f64 v[10:11], v[10:11], v[12:13], 1.0
.LBB10_54:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s1, s53, s0
	s_add_i32 s0, s0, 8
	scratch_load_b64 v[12:13], off, s1
	s_cmp_lg_u32 s0, 24
	s_waitcnt vmcnt(0)
	v_mul_f64 v[12:13], v[10:11], v[12:13]
	scratch_store_b64 off, v[12:13], s1
	s_cbranch_scc1 .LBB10_54
; %bb.55:
	v_mad_u64_u32 v[10:11], null, s56, s7, v[40:41]
	s_add_i32 s0, s56, s26
	s_mov_b64 s[8:9], 0
	v_mad_u64_u32 v[11:12], null, s0, s7, v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, v10, s33, v[41:42]
	v_mad_u64_u32 v[14:15], null, v11, s33, v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[12:13]
	v_lshlrev_b64 v[12:13], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v21, vcc_lo, s28, v10
	v_add_co_ci_u32_e32 v22, vcc_lo, s29, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s28, v12
	v_add_co_ci_u32_e32 v12, vcc_lo, s29, v13, vcc_lo
	v_mov_b32_e32 v10, v49
	s_clause 0x1
	global_store_b64 v[21:22], v[6:7], off
	global_store_b64 v[11:12], v[8:9], off
.LBB10_56:                              ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v11, 31, v10
	s_cmp_eq_u32 s8, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[10:11]
	v_add_co_u32 v6, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s8, 1
	s_cselect_b32 s0, -1, 0
	global_load_b64 v[6:7], v[6:7], off
	s_cmp_eq_u32 s8, 0
	v_add_nc_u32_e32 v10, s52, v10
	s_cselect_b32 s1, -1, 0
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_cmp_lg_u32 s8, 3
	s_waitcnt vmcnt(0)
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
	v_cndmask_b32_e64 v3, v3, v7, s0
	v_cndmask_b32_e64 v2, v2, v6, s0
	v_cndmask_b32_e64 v1, v1, v7, s1
	v_cndmask_b32_e64 v0, v0, v6, s1
	s_cbranch_scc1 .LBB10_56
; %bb.57:                               ; %.preheader792.preheader
	s_lshl_b32 s0, s58, 2
	v_add_nc_u32_e64 v8, 0x90, 40
	s_add_i32 s0, s54, s0
	v_mov_b32_e32 v9, v41
	s_add_i32 s1, s0, s25
	v_add_nc_u32_e32 v7, s0, v46
	v_add3_u32 v6, s1, v46, -2
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v7, s33
	v_mul_lo_u32 v6, v6, s33
.LBB10_58:                              ; %.preheader792
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, v7, v9
	v_add_nc_u32_e32 v12, v6, v9
	v_add_nc_u32_e32 v14, s0, v48
	v_add_nc_u32_e32 v9, s55, v9
	v_add_nc_u32_e32 v15, s0, v8
	v_ashrrev_i32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v13, 31, v12
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 3, v[12:13]
	v_add_co_u32 v10, vcc_lo, s28, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v11, vcc_lo, s29, v11, vcc_lo
	v_add_co_u32 v12, vcc_lo, s28, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v13, vcc_lo, s29, v13, vcc_lo
	s_clause 0x1
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 v14, v[10:11], off offset:-40
	s_waitcnt vmcnt(0)
	scratch_store_b64 v14, v[12:13], off
	s_clause 0x1
	scratch_store_b64 v15, v[10:11], off offset:-40
	scratch_store_b64 v15, v[12:13], off
	s_cbranch_scc1 .LBB10_58
; %bb.59:
	s_clause 0x3
	scratch_load_b64 v[23:24], off, off offset:192
	scratch_load_b64 v[28:29], off, off offset:208
	scratch_load_b64 v[30:31], off, off offset:64
	scratch_load_b64 v[32:33], off, off offset:80
	v_lshl_add_u32 v14, v49, 2, v49
	v_cndmask_b32_e64 v25, 0, 1, s60
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v26, 3, v14
	v_add_nc_u32_e32 v27, 4, v14
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v6, s4, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, s4, v27
	v_lshlrev_b64 v[10:11], 3, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, s22, v10
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_ci_u32_e32 v20, vcc_lo, s23, v11, vcc_lo
	v_add_co_u32 v15, vcc_lo, s22, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v16, vcc_lo, s23, v7, vcc_lo
	v_add_co_u32 v17, vcc_lo, s22, v8
	v_add_co_ci_u32_e32 v18, vcc_lo, s23, v9, vcc_lo
	s_clause 0x2
	global_load_b128 v[10:13], v[19:20], off offset:24
	global_load_b64 v[6:7], v[15:16], off
	global_load_b64 v[8:9], v[17:18], off
	s_and_not1_b32 vcc_lo, exec_lo, s60
	s_waitcnt vmcnt(6)
	v_fma_f64 v[23:24], -s[34:35], v[0:1], v[23:24]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[28:29], s[34:35], v[4:5], v[28:29]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[0:1], s[34:35], v[0:1], v[30:31]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[30:31], -s[34:35], v[4:5], v[32:33]
	s_clause 0x3
	scratch_store_b64 off, v[23:24], off offset:192
	scratch_store_b64 off, v[28:29], off offset:208
	scratch_store_b64 off, v[0:1], off offset:64
	scratch_store_b64 off, v[30:31], off offset:80
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[10:13], off offset:296
	s_waitcnt vmcnt(0)
	scratch_store_b128 off, v[6:9], off offset:336
	s_cbranch_vccnz .LBB10_71
; %bb.60:                               ; %.preheader791.lr.ph
	s_mul_i32 s59, s59, 3
	s_add_i32 s0, s27, 2
	v_add3_u32 v0, s54, s59, v46
	s_mul_i32 s0, s7, s0
	s_lshl_b32 s1, s58, 1
	v_add3_u32 v1, s54, s0, v46
	s_mul_i32 s58, s58, 7
	v_mul_lo_u32 v0, s24, v0
	v_add3_u32 v6, s54, s1, v46
	v_add3_u32 v9, s54, s58, v46
	v_mul_lo_u32 v8, v1, s33
	s_movk_i32 s0, 0x50
	s_add_i32 s1, s26, -1
	v_add_nc_u32_e64 v13, 0x90, s0
	v_add_nc_u32_e64 v28, s0, 16
	v_add3_u32 v10, v0, s24, v45
	v_mad_u64_u32 v[0:1], null, v6, s33, s[6:7]
	v_mad_u64_u32 v[6:7], null, v9, s33, s[6:7]
	v_add3_u32 v1, v45, v8, s6
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v29, v10, s6, 1
	s_mov_b32 s8, 0
.LBB10_61:                              ; %.preheader791
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB10_62 Depth 2
                                        ;     Child Loop BB10_66 Depth 2
                                        ;     Child Loop BB10_68 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v1
	s_mov_b32 s0, 0
.LBB10_62:                              ;   Parent Loop BB10_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_add_nc_u32_e32 v10, s0, v28
	v_add_nc_u32_e32 v11, s0, v13
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s0, 40
	v_lshlrev_b64 v[8:9], 3, v[7:8]
	v_add_nc_u32_e32 v7, s55, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s28, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s29, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v10, v[8:9], off
	scratch_store_b64 v11, v[8:9], off
	s_cbranch_scc1 .LBB10_62
; %bb.63:                               ;   in Loop: Header=BB10_61 Depth=1
	s_add_i32 s0, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_mul_i32 s9, s4, s0
	s_cmp_ge_i32 s0, s1
	v_add_nc_u32_e32 v7, s9, v26
	v_add_nc_u32_e32 v9, s9, v27
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v10, 31, v9
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v7, vcc_lo, s22, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s22, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
	scratch_load_b64 v[23:24], off, off offset:232
	s_clause 0x1
	global_load_b64 v[11:12], v[7:8], off
	global_load_b64 v[7:8], v[9:10], off
	scratch_load_b64 v[9:10], off, off offset:104
	s_cbranch_scc1 .LBB10_65
; %bb.64:                               ;   in Loop: Header=BB10_61 Depth=1
	s_add_i32 s0, s8, 3
	s_waitcnt vmcnt(3)
	v_fma_f64 v[23:24], -s[34:35], v[2:3], v[23:24]
	v_mad_u64_u32 v[30:31], null, s0, s25, v[39:40]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[9:10], s[34:35], v[2:3], v[9:10]
	v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, v30, s24, v[38:39]
	v_ashrrev_i32_e32 v32, 31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[30:31], 3, v[31:32]
	v_add_co_u32 v30, vcc_lo, s16, v30
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v31, vcc_lo, s17, v31, vcc_lo
	scratch_load_b64 v[32:33], off, off offset:248
	global_load_b64 v[30:31], v[30:31], off
	scratch_load_b64 v[34:35], off, off offset:120
	s_waitcnt vmcnt(1)
	v_fma_f64 v[32:33], s[34:35], v[30:31], v[32:33]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[34:35], -s[34:35], v[30:31], v[34:35]
	v_dual_mov_b32 v4, v30 :: v_dual_mov_b32 v5, v31
	s_clause 0x1
	scratch_store_b64 off, v[32:33], off offset:248
	scratch_store_b64 off, v[34:35], off offset:120
.LBB10_65:                              ;   in Loop: Header=BB10_61 Depth=1
	s_clause 0xd
	scratch_load_b128 v[30:33], off, off offset:160
	scratch_load_b128 v[34:37], off, off offset:32
	scratch_load_b64 v[43:44], off, off offset:176
	scratch_load_b64 v[66:67], off, off offset:48
	scratch_load_b128 v[48:51], off, off offset:296
	scratch_load_b128 v[52:55], off, off offset:192
	scratch_load_b64 v[78:79], off, off offset:208
	scratch_load_b128 v[56:59], off, off offset:336
	scratch_load_b64 v[80:81], off, off offset:224
	scratch_load_b64 v[82:83], off, off offset:240
	scratch_load_b128 v[60:63], off, off offset:64
	scratch_load_b64 v[84:85], off, off offset:80
	scratch_load_b64 v[86:87], off, off offset:96
	scratch_load_b64 v[88:89], off, off offset:112
	s_waitcnt vmcnt(13)
	v_div_scale_f64 v[64:65], null, v[30:31], v[30:31], 1.0
	s_waitcnt vmcnt(12)
	v_div_scale_f64 v[68:69], null, v[34:35], v[34:35], 1.0
	v_div_scale_f64 v[90:91], vcc_lo, 1.0, v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[70:71], v[64:65]
	v_rcp_f64_e32 v[72:73], v[68:69]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[74:75], -v[64:65], v[70:71], 1.0
	v_fma_f64 v[76:77], -v[68:69], v[72:73], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[70:71], v[70:71], v[74:75], v[70:71]
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[74:75], -v[64:65], v[70:71], 1.0
	v_fma_f64 v[76:77], -v[68:69], v[72:73], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[70:71], v[70:71], v[74:75], v[70:71]
	v_div_scale_f64 v[74:75], s0, 1.0, v[34:35], 1.0
	v_fma_f64 v[72:73], v[72:73], v[76:77], v[72:73]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[76:77], v[90:91], v[70:71]
	v_mul_f64 v[92:93], v[74:75], v[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[64:65], -v[64:65], v[76:77], v[90:91]
	v_fma_f64 v[68:69], -v[68:69], v[92:93], v[74:75]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[64:65], v[64:65], v[70:71], v[76:77]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[68:69], v[68:69], v[72:73], v[92:93]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[64:65], v[64:65], v[30:31], 1.0
	v_div_fixup_f64 v[68:69], v[68:69], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[30:31], v[32:33], v[64:65]
	s_waitcnt vmcnt(11)
	v_mul_f64 v[32:33], v[64:65], v[43:44]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[34:35], v[64:65], v[48:49]
	v_mul_f64 v[64:65], v[36:37], v[68:69]
	v_mul_f64 v[66:67], v[68:69], v[66:67]
	v_mul_f64 v[36:37], v[68:69], v[50:51]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[48:49], -v[30:31], v[52:53], v[54:55]
	s_waitcnt vmcnt(7)
	v_fma_f64 v[50:51], -v[32:33], v[52:53], v[78:79]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[68:69], -v[30:31], v[80:81], v[23:24]
	s_waitcnt vmcnt(4)
	v_fma_f64 v[70:71], -v[32:33], v[80:81], v[82:83]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[72:73], -v[64:65], v[60:61], v[62:63]
	s_waitcnt vmcnt(2)
	v_fma_f64 v[74:75], -v[66:67], v[60:61], v[84:85]
	v_fma_f64 v[52:53], -v[34:35], v[52:53], v[56:57]
	v_fma_f64 v[54:55], -v[36:37], v[60:61], v[58:59]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[60:61], -v[64:65], v[86:87], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[62:63], -v[66:67], v[86:87], v[88:89]
	v_fma_f64 v[56:57], -v[34:35], v[80:81], v[11:12]
	v_fma_f64 v[58:59], -v[36:37], v[86:87], v[7:8]
	v_mov_b32_e32 v9, v45
	v_mov_b32_e32 v7, v29
	s_clause 0x8
	scratch_store_b128 off, v[30:33], off offset:168
	scratch_store_b128 off, v[48:51], off offset:200
	scratch_store_b128 off, v[68:71], off offset:232
	scratch_store_b128 off, v[64:67], off offset:40
	scratch_store_b128 off, v[72:75], off offset:72
	scratch_store_b128 off, v[34:37], off offset:296
	scratch_store_b128 off, v[52:55], off offset:336
	scratch_store_b128 off, v[60:63], off offset:104
	scratch_store_b128 off, v[56:59], off offset:376
.LBB10_66:                              ;   Parent Loop BB10_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, 0x110 :: v_dual_add_nc_u32 v43, v0, v9
	v_add_nc_u32_e64 v8, 0x90, 24
	v_add_nc_u32_e32 v36, v6, v9
	v_add_nc_u32_e32 v9, s55, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_readfirstlane_b32 s9, v10
	v_add_nc_u32_e64 v10, 16, 24
	v_add_nc_u32_e32 v8, s0, v8
	v_ashrrev_i32_e32 v37, 31, v36
	v_ashrrev_i32_e32 v44, 31, v43
	s_add_i32 s9, s9, s0
	v_add_nc_u32_e32 v12, s0, v10
	s_add_i32 s36, s9, 24
	s_add_i32 s37, s9, 64
	scratch_load_b64 v[10:11], v8, off
	s_addk_i32 s9, 0x68
	scratch_load_b64 v[23:24], v12, off
	s_clause 0x2
	scratch_load_b64 v[30:31], off, s36
	scratch_load_b64 v[32:33], off, s37
	scratch_load_b64 v[34:35], off, s9
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[36:37], 3, v[36:37]
	v_lshlrev_b64 v[43:44], 3, v[43:44]
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[48:49], 3, v[7:8]
	v_add_nc_u32_e32 v7, s5, v7
	s_cmp_lg_u32 s0, 16
	v_add_co_u32 v48, vcc_lo, s30, v48
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v49, vcc_lo, s31, v49, vcc_lo
	v_add_co_u32 v36, vcc_lo, s28, v36
	v_add_co_ci_u32_e32 v37, vcc_lo, s29, v37, vcc_lo
	v_add_co_u32 v43, vcc_lo, s28, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, s29, v44, vcc_lo
	s_waitcnt vmcnt(4)
	global_store_b64 v[36:37], v[10:11], off
	s_waitcnt vmcnt(3)
	global_store_b64 v[43:44], v[23:24], off
	s_waitcnt vmcnt(2)
	global_store_b64 v[48:49], v[30:31], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[32:33], s36
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[34:35], s37
	s_cbranch_scc1 .LBB10_66
; %bb.67:                               ; %.preheader790.preheader
                                        ;   in Loop: Header=BB10_61 Depth=1
	s_mov_b32 s0, 0
.LBB10_68:                              ; %.preheader790
                                        ;   Parent Loop BB10_61 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e64 v7, 0x90, s0
	v_add_nc_u32_e64 v8, s0, 16
	s_add_i32 s9, s0, 0x90
	s_add_i32 s36, s0, 16
	s_add_i32 s0, s0, 8
	v_add_nc_u32_e32 v30, 40, v7
	v_add_nc_u32_e32 v9, 0x50, v7
	v_add_nc_u32_e32 v31, 40, v8
	v_add_nc_u32_e32 v23, 0x50, v8
	s_cmp_lg_u32 s0, 40
	s_clause 0x1
	scratch_load_b64 v[7:8], v30, off
	scratch_load_b64 v[9:10], v9, off
	s_clause 0x1
	scratch_load_b64 v[11:12], v31, off
	scratch_load_b64 v[23:24], v23, off
	s_waitcnt vmcnt(3)
	scratch_store_b64 off, v[7:8], s9
	s_waitcnt vmcnt(2)
	scratch_store_b64 v30, v[9:10], off
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[11:12], s36
	s_waitcnt vmcnt(0)
	scratch_store_b64 v31, v[23:24], off
	s_cbranch_scc1 .LBB10_68
; %bb.69:                               ;   in Loop: Header=BB10_61 Depth=1
	v_add_nc_u32_e32 v1, s57, v1
	v_add_nc_u32_e32 v29, s52, v29
	v_add_nc_u32_e32 v0, s57, v0
	v_add_nc_u32_e32 v6, s57, v6
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s8, s56
	s_cbranch_scc1 .LBB10_61
; %bb.70:                               ; %._crit_edge823.loopexit
	s_clause 0x3
	scratch_load_b64 v[23:24], off, off offset:192
	scratch_load_b128 v[10:13], off, off offset:296
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b64 v[0:1], off, off offset:64
.LBB10_71:                              ; %._crit_edge823
	s_clause 0x3
	scratch_load_b128 v[2:5], off, off offset:160
	scratch_load_b128 v[26:29], off, off offset:32
	scratch_load_b64 v[30:31], off, off offset:200
	scratch_load_b64 v[34:35], off, off offset:72
	s_waitcnt vmcnt(3)
	v_div_scale_f64 v[32:33], null, v[2:3], v[2:3], 1.0
	s_waitcnt vmcnt(2)
	v_div_scale_f64 v[36:37], null, v[26:27], v[26:27], 1.0
	v_div_scale_f64 v[54:55], vcc_lo, 1.0, v[2:3], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[43:44], v[32:33]
	v_rcp_f64_e32 v[48:49], v[36:37]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[50:51], -v[32:33], v[43:44], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[43:44], v[43:44], v[50:51], v[43:44]
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[50:51], -v[32:33], v[43:44], 1.0
	v_fma_f64 v[52:53], -v[36:37], v[48:49], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[43:44], v[43:44], v[50:51], v[43:44]
	v_div_scale_f64 v[50:51], s0, 1.0, v[26:27], 1.0
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[52:53], v[54:55], v[43:44]
	v_mul_f64 v[56:57], v[50:51], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], -v[32:33], v[52:53], v[54:55]
	v_fma_f64 v[36:37], -v[36:37], v[56:57], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[32:33], v[32:33], v[43:44], v[52:53]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[36:37], v[36:37], v[48:49], v[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[2:3], v[32:33], v[2:3], 1.0
	v_div_fixup_f64 v[26:27], v[36:37], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[4:5], v[2:3]
	v_mul_f64 v[10:11], v[2:3], v[10:11]
	v_mul_f64 v[2:3], v[28:29], v[26:27]
	v_mul_f64 v[12:13], v[26:27], v[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], -v[4:5], v[23:24], v[30:31]
	v_fma_f64 v[6:7], -v[10:11], v[23:24], v[6:7]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], -v[2:3], v[0:1], v[34:35]
	v_fma_f64 v[8:9], -v[12:13], v[0:1], v[8:9]
	global_load_b64 v[0:1], v[21:22], off
	v_div_scale_f64 v[28:29], null, v[26:27], v[26:27], v[6:7]
	v_div_scale_f64 v[43:44], vcc_lo, v[6:7], v[26:27], v[6:7]
	v_div_scale_f64 v[30:31], null, v[23:24], v[23:24], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[32:33], v[28:29]
	v_rcp_f64_e32 v[34:35], v[30:31]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[28:29], v[32:33], 1.0
	v_fma_f64 v[36:37], -v[30:31], v[34:35], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[32:33], v[21:22], v[32:33]
	v_fma_f64 v[32:33], v[34:35], v[36:37], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], -v[28:29], v[21:22], 1.0
	v_fma_f64 v[36:37], -v[30:31], v[32:33], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[34:35], v[21:22]
	v_div_scale_f64 v[34:35], s0, v[8:9], v[23:24], v[8:9]
	v_fma_f64 v[32:33], v[32:33], v[36:37], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[36:37], v[43:44], v[21:22]
	v_mul_f64 v[48:49], v[34:35], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], -v[28:29], v[36:37], v[43:44]
	v_fma_f64 v[30:31], -v[30:31], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[21:22], v[28:29], v[21:22], v[36:37]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0
	v_div_fmas_f64 v[28:29], v[30:31], v[32:33], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[21:22], v[26:27], v[6:7]
	v_div_fixup_f64 v[8:9], v[28:29], v[23:24], v[8:9]
	s_clause 0x1
	scratch_store_b128 off, v[10:13], off offset:296
	scratch_store_b128 off, v[6:9], off offset:336
.LBB10_72:                              ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v6, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 24
	v_add_nc_u32_e32 v6, 40, v6
	s_clause 0x1
	scratch_load_b64 v[6:7], v6, off
	scratch_load_b64 v[8:9], off, s1
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], -v[0:1], v[6:7], v[8:9]
	scratch_store_b64 off, v[6:7], s1
	s_cbranch_scc1 .LBB10_72
; %bb.73:
	s_clause 0x1
	scratch_load_b128 v[6:9], off, off offset:336
	scratch_load_b128 v[10:13], off, off offset:296
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], -v[4:5], v[6:7], v[10:11]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[12:13]
	scratch_store_b128 off, v[0:3], off offset:296
.LBB10_74:                              ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v4, 0x110, s0
	s_add_i32 s1, s0, 0x110
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s0, 40
	v_add_nc_u32_e32 v5, 40, v4
	v_add_nc_u32_e32 v4, 0x50, v4
	s_clause 0x1
	scratch_load_b64 v[0:1], v5, off
	scratch_load_b64 v[2:3], off, s1
	s_waitcnt vmcnt(1)
	scratch_store_b64 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	scratch_store_b64 v5, v[2:3], off
	s_cbranch_scc1 .LBB10_74
; %bb.75:
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, bt@rel32@lo+4
	s_addc_u32 s1, s1, bt@rel32@hi+12
	v_cmp_ne_u32_e32 vcc_lo, 1, v25
	s_load_b64 s[0:1], s[0:1], 0x0
	s_cbranch_vccnz .LBB10_84
; %bb.76:                               ; %.preheader.lr.ph
	s_add_i32 s8, s26, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s25, s8
	v_add3_u32 v2, s54, s9, v46
	s_add_i32 s9, s26, -3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s34, s25, s9
	v_mad_u64_u32 v[0:1], null, v2, 5, 5
	v_add3_u32 v1, s54, s34, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, s24, v1
	v_mul_lo_u32 v0, s24, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[1:2], null, s6, 5, v[0:1]
	v_add3_u32 v0, v3, s24, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v6, v0, s6, 1
	v_add3_u32 v7, v1, v47, 5
	s_lshl_b32 s6, s26, 1
.LBB10_77:                              ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB10_78 Depth 2
                                        ;     Child Loop BB10_82 Depth 2
	v_mad_u64_u32 v[0:1], null, s9, s7, v[40:41]
	s_add_i32 s34, s9, s26
	s_mov_b32 s35, 0
	v_mad_u64_u32 v[1:2], null, s34, s7, v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v0, s33, v[41:42]
	v_mad_u64_u32 v[4:5], null, v1, s33, v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	v_mov_b32_e32 v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s29, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[2:3], v[2:3], off
.LBB10_78:                              ;   Parent Loop BB10_77 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s36, s35, 0x110
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[8:9], 3, v[4:5]
	v_add_nc_u32_e64 v5, 0x110, s35
	v_add_nc_u32_e32 v4, s5, v4
	s_add_i32 s35, s35, 8
	s_cmp_lg_u32 s35, 24
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s30, v8
	v_add_nc_u32_e32 v10, 40, v5
	v_add_co_ci_u32_e32 v9, vcc_lo, s31, v9, vcc_lo
	v_add_nc_u32_e32 v5, 0x50, v5
	scratch_load_b64 v[10:11], v10, off
	global_load_b64 v[8:9], v[8:9], off
	scratch_load_b64 v[12:13], v5, off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[8:9], -v[0:1], v[10:11], v[8:9]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[12:13], v[8:9]
	scratch_store_b64 off, v[8:9], s36
	s_cbranch_scc1 .LBB10_78
; %bb.79:                               ;   in Loop: Header=BB10_77 Depth=1
	s_add_i32 s34, s34, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s35, s34, s27
	v_mad_u64_u32 v[0:1], null, s34, s25, v[39:40]
	s_add_i32 s36, s35, s26
	v_mad_u64_u32 v[1:2], null, s35, s7, v[40:41]
	s_sub_i32 s35, s36, s27
	v_mad_u64_u32 v[2:3], null, s35, s25, v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v0, s24, v[38:39]
	v_mad_u64_u32 v[8:9], null, v1, s33, v[41:42]
	s_sub_i32 s35, s35, s6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[0:1], null, v2, s24, v[38:39]
	v_mad_u64_u32 v[1:2], null, s35, s7, v[40:41]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v1, s33, v[41:42]
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s30, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s31, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s28, v8
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s29, v9, vcc_lo
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	global_load_b64 v[12:13], v[2:3], off
	global_load_b64 v[21:22], v[8:9], off
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	scratch_load_b128 v[8:11], off, off offset:336
	v_mad_u64_u32 v[4:5], null, s36, s7, v[40:41]
	v_add_co_u32 v0, vcc_lo, s30, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s31, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s29, v3, vcc_lo
	global_load_b64 v[23:24], v[0:1], off
	global_load_b64 v[25:26], v[2:3], off
	v_mad_u64_u32 v[0:1], null, s34, s7, v[40:41]
	v_mad_u64_u32 v[1:2], null, v4, s33, v[41:42]
	s_add_i32 s34, s9, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_ge_i32 s34, s8
	v_mad_u64_u32 v[3:4], null, v0, s33, v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s29, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s28, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s29, v3, vcc_lo
	global_load_b64 v[27:28], v[0:1], off
	scratch_load_b128 v[0:3], off, off offset:376
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(5)
	v_fma_f64 v[8:9], -v[21:22], v[8:9], v[12:13]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[10:11], -v[25:26], v[10:11], v[23:24]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[27:28], v[0:1], v[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[10:11], -v[4:5], v[2:3], v[10:11]
	scratch_store_b128 off, v[8:11], off offset:296
	s_cbranch_scc1 .LBB10_81
; %bb.80:                               ;   in Loop: Header=BB10_77 Depth=1
	v_mad_u64_u32 v[4:5], null, s34, s25, v[39:40]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, s24, v[38:39]
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 3, v[8:9]
	v_add_co_u32 v8, vcc_lo, s20, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v5, vcc_lo
	global_load_b64 v[12:13], v[8:9], off
	v_add_co_u32 v8, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v5, vcc_lo
	v_add_co_u32 v25, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v26, vcc_lo, s11, v5, vcc_lo
	global_load_b64 v[21:22], v[8:9], off
	scratch_load_b128 v[8:11], off, off offset:352
	global_load_b64 v[25:26], v[25:26], off
	v_add_co_u32 v29, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v30, vcc_lo, s13, v5, vcc_lo
	scratch_load_b64 v[33:34], off, off offset:368
	v_add_co_u32 v43, vcc_lo, s18, v4
	global_load_b64 v[29:30], v[29:30], off
	v_add_co_ci_u32_e32 v44, vcc_lo, s19, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	global_load_b64 v[43:44], v[43:44], off
	global_load_b64 v[4:5], v[4:5], off
	s_waitcnt vmcnt(7) lgkmcnt(0)
	v_mul_f64 v[23:24], v[12:13], s[0:1]
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[27:28], null, v[21:22], v[21:22], v[23:24]
	v_div_scale_f64 v[45:46], vcc_lo, v[23:24], v[21:22], v[23:24]
	v_rcp_f64_e32 v[31:32], v[27:28]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[35:36], -v[27:28], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[31:32], v[35:36], v[31:32]
	v_fma_f64 v[35:36], -v[27:28], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[31:32], v[35:36], v[31:32]
	v_mul_f64 v[35:36], v[45:46], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], -v[27:28], v[35:36], v[45:46]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[45:46], v[25:26], v[10:11]
	v_mul_f64 v[10:11], v[12:13], v[10:11]
	v_div_fmas_f64 v[27:28], v[27:28], v[31:32], v[35:36]
	v_add_f64 v[31:32], v[0:1], v[2:3]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[35:36], v[29:30], v[8:9], -v[45:46]
	v_mul_f64 v[45:46], v[21:22], v[21:22]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	v_div_fixup_f64 v[27:28], v[27:28], v[21:22], v[23:24]
	v_mul_f64 v[35:36], v[12:13], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[2:3], 0x40040000, v[45:46]
	v_mul_f64 v[0:1], v[0:1], v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[31:32], v[27:28], v[33:34]
	v_mul_f64 v[27:28], v[31:32], v[27:28]
	s_waitcnt vmcnt(1)
	v_fma_f64 v[31:32], v[43:44], v[21:22], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[2:3], v[27:28], v[31:32]
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[4:5], v[21:22], v[0:1]
	v_fma_f64 v[4:5], v[4:5], v[0:1], v[23:24]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[12:13], v[8:9], v[27:28]
	v_fma_f64 v[23:24], v[25:26], v[21:22], -v[10:11]
	s_clause 0x2
	scratch_store_b64 off, v[4:5], off offset:384
	scratch_store_b128 off, v[0:3], off offset:368
	scratch_store_b128 off, v[21:24], off offset:352
.LBB10_81:                              ;   in Loop: Header=BB10_77 Depth=1
	s_mov_b32 s34, 0
	s_mov_b32 s35, s53
.LBB10_82:                              ;   Parent Loop BB10_77 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s36, s35, 40
	s_clause 0x2
	scratch_load_b64 v[0:1], off, s35
	scratch_load_b64 v[2:3], off, s35 offset:-40
	scratch_load_b64 v[4:5], off, s36
	v_add_nc_u32_e32 v8, s34, v7
	s_add_i32 s34, s34, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s22, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[2:3], s35
	s_add_i32 s35, s35, 8
	s_cmp_lg_u32 s34, 5
	scratch_store_b64 off, v[0:1], s36
	s_waitcnt vmcnt(0)
	global_store_b64 v[8:9], v[4:5], off
	s_cbranch_scc1 .LBB10_82
; %bb.83:                               ;   in Loop: Header=BB10_77 Depth=1
	v_subrev_nc_u32_e32 v6, s52, v6
	v_subrev_nc_u32_e32 v7, s4, v7
	s_add_i32 s34, s9, -1
	s_cmp_gt_i32 s9, 0
	s_mov_b32 s9, s34
	s_cbranch_scc1 .LBB10_77
.LBB10_84:                              ; %._crit_edge829
	v_add_nc_u32_e32 v2, s25, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, s24, v[38:39]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s20, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v9, vcc_lo
	global_load_b64 v[10:11], v[0:1], off
	v_add_co_u32 v0, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v9, vcc_lo
	global_load_b64 v[12:13], v[0:1], off
	scratch_load_b128 v[0:3], off, off offset:352
	global_load_b64 v[23:24], v[4:5], off
	v_add_co_u32 v27, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v28, vcc_lo, s13, v9, vcc_lo
	s_clause 0x1
	scratch_load_b128 v[4:7], off, off offset:368
	scratch_load_b64 v[29:30], off, off offset:384
	global_load_b64 v[27:28], v[27:28], off
	v_add_co_u32 v35, vcc_lo, s18, v8
	v_add_co_ci_u32_e32 v36, vcc_lo, s19, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s14, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v9, vcc_lo
	global_load_b64 v[35:36], v[35:36], off
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(8) lgkmcnt(0)
	v_mul_f64 v[21:22], v[10:11], s[0:1]
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(7)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[25:26], null, v[12:13], v[12:13], v[21:22]
	v_div_scale_f64 v[37:38], vcc_lo, v[21:22], v[12:13], v[21:22]
	v_rcp_f64_e32 v[31:32], v[25:26]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[33:34], -v[25:26], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32]
	v_fma_f64 v[33:34], -v[25:26], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[31:32], v[33:34], v[31:32]
	v_mul_f64 v[33:34], v[37:38], v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], -v[25:26], v[33:34], v[37:38]
	s_waitcnt vmcnt(5)
	v_mul_f64 v[37:38], v[23:24], v[2:3]
	v_mul_f64 v[2:3], v[10:11], v[2:3]
	v_div_fmas_f64 v[25:26], v[25:26], v[31:32], v[33:34]
	s_waitcnt vmcnt(3)
	v_add_f64 v[31:32], v[6:7], v[29:30]
	s_waitcnt vmcnt(2)
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[33:34], v[27:28], v[0:1], -v[37:38]
	v_add_f64 v[6:7], v[6:7], -v[29:30]
	v_add_co_u32 v19, vcc_lo, v19, s2
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v20, vcc_lo
	v_div_fixup_f64 v[25:26], v[25:26], v[12:13], v[21:22]
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	v_mul_f64 v[33:34], v[10:11], v[33:34]
	v_mul_f64 v[6:7], v[21:22], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[4:5], v[25:26], v[31:32], v[4:5]
	v_mul_f64 v[12:13], 0x40040000, v[12:13]
	v_mul_f64 v[25:26], v[25:26], v[31:32]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[4:5], v[35:36], v[33:34]
	v_mul_f64 v[21:22], v[27:28], v[4:5]
	v_fma_f64 v[2:3], v[23:24], v[4:5], -v[2:3]
	v_fma_f64 v[12:13], v[12:13], v[25:26], v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[10:11], v[0:1], v[21:22]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[12:13], v[8:9], v[6:7], v[12:13]
	v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
	v_add_nc_u32_e32 v9, s4, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 2, v9
	v_add_nc_u32_e32 v10, 1, v9
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v8, vcc_lo, s22, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, s22, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v11, vcc_lo, s23, v11, vcc_lo
	s_clause 0x4
	global_store_b64 v[17:18], v[12:13], off
	global_store_b64 v[15:16], v[6:7], off
	global_store_b64 v[8:9], v[0:1], off
	global_store_b64 v[10:11], v[2:3], off
	global_store_b64 v[19:20], v[4:5], off
.LBB10_85:                              ; =>This Inner Loop Header: Depth=1
	scratch_load_b64 v[0:1], off, s53
	v_add_nc_u32_e32 v2, s0, v42
	s_add_i32 s0, s0, 1
	s_add_i32 s53, s53, 8
	s_cmp_lg_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s22, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
	s_cbranch_scc1 .LBB10_85
.LBB10_86:                              ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 400
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 94
		.amdhsa_next_free_sgpr 65
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,"axG",@progbits,_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii,comdat
.Lfunc_end10:
	.size	_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii, .Lfunc_end10-_ZL14z_solve_kernelPdS_S_S_S_S_S_S_S_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10184
; NumSgprs: 67
; NumVgprs: 94
; ScratchSize: 400
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 67
; NumVGPRsForWavesPerEU: 94
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.section	.text._ZL10add_kernelPdS_iii,"axG",@progbits,_ZL10add_kernelPdS_iii,comdat
	.globl	_ZL10add_kernelPdS_iii          ; -- Begin function _ZL10add_kernelPdS_iii
	.p2align	8
	.type	_ZL10add_kernelPdS_iii,@function
_ZL10add_kernelPdS_iii:                 ; @_ZL10add_kernelPdS_iii
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v5, v0, 10, 10
	s_add_i32 s8, s15, 1
	v_and_b32_e32 v0, 0x3ff, v0
	s_add_i32 s10, s14, 1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, v5, s6, s[8:9]
	s_mul_i32 s6, s8, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s6, s10
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s6, s4, v[0:1]
	v_mad_u64_u32 v[3:4], null, v1, s5, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, v2, 2, v2
	v_mul_lo_u32 v3, v3, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v1, v1, v5, 5
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v3, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[4:5], v[2:3], off offset:8
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[4:5]
	global_store_b64 v[2:3], v[0:1], off offset:8
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL10add_kernelPdS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL10add_kernelPdS_iii,"axG",@progbits,_ZL10add_kernelPdS_iii,comdat
.Lfunc_end11:
	.size	_ZL10add_kernelPdS_iii, .Lfunc_end11-_ZL10add_kernelPdS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	tx1                     ; @tx1
	.type	tx1,@object
	.section	.bss,"aw",@nobits
	.globl	tx1
	.p2align	3, 0x0
tx1:
	.quad	0x0000000000000000              ; double 0
	.size	tx1, 8

	.protected	tx2                     ; @tx2
	.type	tx2,@object
	.globl	tx2
	.p2align	3, 0x0
tx2:
	.quad	0x0000000000000000              ; double 0
	.size	tx2, 8

	.protected	tx3                     ; @tx3
	.type	tx3,@object
	.globl	tx3
	.p2align	3, 0x0
tx3:
	.quad	0x0000000000000000              ; double 0
	.size	tx3, 8

	.protected	ty1                     ; @ty1
	.type	ty1,@object
	.globl	ty1
	.p2align	3, 0x0
ty1:
	.quad	0x0000000000000000              ; double 0
	.size	ty1, 8

	.protected	ty2                     ; @ty2
	.type	ty2,@object
	.globl	ty2
	.p2align	3, 0x0
ty2:
	.quad	0x0000000000000000              ; double 0
	.size	ty2, 8

	.protected	ty3                     ; @ty3
	.type	ty3,@object
	.globl	ty3
	.p2align	3, 0x0
ty3:
	.quad	0x0000000000000000              ; double 0
	.size	ty3, 8

	.protected	tz1                     ; @tz1
	.type	tz1,@object
	.globl	tz1
	.p2align	3, 0x0
tz1:
	.quad	0x0000000000000000              ; double 0
	.size	tz1, 8

	.protected	tz2                     ; @tz2
	.type	tz2,@object
	.globl	tz2
	.p2align	3, 0x0
tz2:
	.quad	0x0000000000000000              ; double 0
	.size	tz2, 8

	.protected	tz3                     ; @tz3
	.type	tz3,@object
	.globl	tz3
	.p2align	3, 0x0
tz3:
	.quad	0x0000000000000000              ; double 0
	.size	tz3, 8

	.protected	bt                      ; @bt
	.type	bt,@object
	.globl	bt
	.p2align	3, 0x0
bt:
	.quad	0x0000000000000000              ; double 0
	.size	bt, 8

	.protected	dt                      ; @dt
	.type	dt,@object
	.globl	dt
	.p2align	3, 0x0
dt:
	.quad	0x0000000000000000              ; double 0
	.size	dt, 8

	.protected	dtdssp                  ; @dtdssp
	.type	dtdssp,@object
	.globl	dtdssp
	.p2align	3, 0x0
dtdssp:
	.quad	0x0000000000000000              ; double 0
	.size	dtdssp, 8

	.protected	dnxm1                   ; @dnxm1
	.type	dnxm1,@object
	.globl	dnxm1
	.p2align	3, 0x0
dnxm1:
	.quad	0x0000000000000000              ; double 0
	.size	dnxm1, 8

	.protected	dnym1                   ; @dnym1
	.type	dnym1,@object
	.globl	dnym1
	.p2align	3, 0x0
dnym1:
	.quad	0x0000000000000000              ; double 0
	.size	dnym1, 8

	.protected	dnzm1                   ; @dnzm1
	.type	dnzm1,@object
	.globl	dnzm1
	.p2align	3, 0x0
dnzm1:
	.quad	0x0000000000000000              ; double 0
	.size	dnzm1, 8

	.protected	dtx1                    ; @dtx1
	.type	dtx1,@object
	.globl	dtx1
	.p2align	3, 0x0
dtx1:
	.quad	0x0000000000000000              ; double 0
	.size	dtx1, 8

	.protected	dttx2                   ; @dttx2
	.type	dttx2,@object
	.globl	dttx2
	.p2align	3, 0x0
dttx2:
	.quad	0x0000000000000000              ; double 0
	.size	dttx2, 8

	.protected	dty1                    ; @dty1
	.type	dty1,@object
	.globl	dty1
	.p2align	3, 0x0
dty1:
	.quad	0x0000000000000000              ; double 0
	.size	dty1, 8

	.protected	dtty2                   ; @dtty2
	.type	dtty2,@object
	.globl	dtty2
	.p2align	3, 0x0
dtty2:
	.quad	0x0000000000000000              ; double 0
	.size	dtty2, 8

	.protected	dtz1                    ; @dtz1
	.type	dtz1,@object
	.globl	dtz1
	.p2align	3, 0x0
dtz1:
	.quad	0x0000000000000000              ; double 0
	.size	dtz1, 8

	.protected	dttz2                   ; @dttz2
	.type	dttz2,@object
	.globl	dttz2
	.p2align	3, 0x0
dttz2:
	.quad	0x0000000000000000              ; double 0
	.size	dttz2, 8

	.protected	c2dttx1                 ; @c2dttx1
	.type	c2dttx1,@object
	.globl	c2dttx1
	.p2align	3, 0x0
c2dttx1:
	.quad	0x0000000000000000              ; double 0
	.size	c2dttx1, 8

	.protected	c2dtty1                 ; @c2dtty1
	.type	c2dtty1,@object
	.globl	c2dtty1
	.p2align	3, 0x0
c2dtty1:
	.quad	0x0000000000000000              ; double 0
	.size	c2dtty1, 8

	.protected	c2dttz1                 ; @c2dttz1
	.type	c2dttz1,@object
	.globl	c2dttz1
	.p2align	3, 0x0
c2dttz1:
	.quad	0x0000000000000000              ; double 0
	.size	c2dttz1, 8

	.protected	comz1                   ; @comz1
	.type	comz1,@object
	.globl	comz1
	.p2align	3, 0x0
comz1:
	.quad	0x0000000000000000              ; double 0
	.size	comz1, 8

	.protected	comz4                   ; @comz4
	.type	comz4,@object
	.globl	comz4
	.p2align	3, 0x0
comz4:
	.quad	0x0000000000000000              ; double 0
	.size	comz4, 8

	.protected	comz5                   ; @comz5
	.type	comz5,@object
	.globl	comz5
	.p2align	3, 0x0
comz5:
	.quad	0x0000000000000000              ; double 0
	.size	comz5, 8

	.protected	comz6                   ; @comz6
	.type	comz6,@object
	.globl	comz6
	.p2align	3, 0x0
comz6:
	.quad	0x0000000000000000              ; double 0
	.size	comz6, 8

	.protected	c3c4tx3                 ; @c3c4tx3
	.type	c3c4tx3,@object
	.globl	c3c4tx3
	.p2align	3, 0x0
c3c4tx3:
	.quad	0x0000000000000000              ; double 0
	.size	c3c4tx3, 8

	.protected	c3c4ty3                 ; @c3c4ty3
	.type	c3c4ty3,@object
	.globl	c3c4ty3
	.p2align	3, 0x0
c3c4ty3:
	.quad	0x0000000000000000              ; double 0
	.size	c3c4ty3, 8

	.protected	c3c4tz3                 ; @c3c4tz3
	.type	c3c4tz3,@object
	.globl	c3c4tz3
	.p2align	3, 0x0
c3c4tz3:
	.quad	0x0000000000000000              ; double 0
	.size	c3c4tz3, 8

	.protected	xxcon1                  ; @xxcon1
	.type	xxcon1,@object
	.globl	xxcon1
	.p2align	3, 0x0
xxcon1:
	.quad	0x0000000000000000              ; double 0
	.size	xxcon1, 8

	.protected	xxcon2                  ; @xxcon2
	.type	xxcon2,@object
	.globl	xxcon2
	.p2align	3, 0x0
xxcon2:
	.quad	0x0000000000000000              ; double 0
	.size	xxcon2, 8

	.protected	xxcon3                  ; @xxcon3
	.type	xxcon3,@object
	.globl	xxcon3
	.p2align	3, 0x0
xxcon3:
	.quad	0x0000000000000000              ; double 0
	.size	xxcon3, 8

	.protected	xxcon4                  ; @xxcon4
	.type	xxcon4,@object
	.globl	xxcon4
	.p2align	3, 0x0
xxcon4:
	.quad	0x0000000000000000              ; double 0
	.size	xxcon4, 8

	.protected	xxcon5                  ; @xxcon5
	.type	xxcon5,@object
	.globl	xxcon5
	.p2align	3, 0x0
xxcon5:
	.quad	0x0000000000000000              ; double 0
	.size	xxcon5, 8

	.protected	dx1tx1                  ; @dx1tx1
	.type	dx1tx1,@object
	.globl	dx1tx1
	.p2align	3, 0x0
dx1tx1:
	.quad	0x0000000000000000              ; double 0
	.size	dx1tx1, 8

	.protected	dx2tx1                  ; @dx2tx1
	.type	dx2tx1,@object
	.globl	dx2tx1
	.p2align	3, 0x0
dx2tx1:
	.quad	0x0000000000000000              ; double 0
	.size	dx2tx1, 8

	.protected	dx3tx1                  ; @dx3tx1
	.type	dx3tx1,@object
	.globl	dx3tx1
	.p2align	3, 0x0
dx3tx1:
	.quad	0x0000000000000000              ; double 0
	.size	dx3tx1, 8

	.protected	dx4tx1                  ; @dx4tx1
	.type	dx4tx1,@object
	.globl	dx4tx1
	.p2align	3, 0x0
dx4tx1:
	.quad	0x0000000000000000              ; double 0
	.size	dx4tx1, 8

	.protected	dx5tx1                  ; @dx5tx1
	.type	dx5tx1,@object
	.globl	dx5tx1
	.p2align	3, 0x0
dx5tx1:
	.quad	0x0000000000000000              ; double 0
	.size	dx5tx1, 8

	.protected	yycon1                  ; @yycon1
	.type	yycon1,@object
	.globl	yycon1
	.p2align	3, 0x0
yycon1:
	.quad	0x0000000000000000              ; double 0
	.size	yycon1, 8

	.protected	yycon2                  ; @yycon2
	.type	yycon2,@object
	.globl	yycon2
	.p2align	3, 0x0
yycon2:
	.quad	0x0000000000000000              ; double 0
	.size	yycon2, 8

	.protected	yycon3                  ; @yycon3
	.type	yycon3,@object
	.globl	yycon3
	.p2align	3, 0x0
yycon3:
	.quad	0x0000000000000000              ; double 0
	.size	yycon3, 8

	.protected	yycon4                  ; @yycon4
	.type	yycon4,@object
	.globl	yycon4
	.p2align	3, 0x0
yycon4:
	.quad	0x0000000000000000              ; double 0
	.size	yycon4, 8

	.protected	yycon5                  ; @yycon5
	.type	yycon5,@object
	.globl	yycon5
	.p2align	3, 0x0
yycon5:
	.quad	0x0000000000000000              ; double 0
	.size	yycon5, 8

	.protected	dy1ty1                  ; @dy1ty1
	.type	dy1ty1,@object
	.globl	dy1ty1
	.p2align	3, 0x0
dy1ty1:
	.quad	0x0000000000000000              ; double 0
	.size	dy1ty1, 8

	.protected	dy2ty1                  ; @dy2ty1
	.type	dy2ty1,@object
	.globl	dy2ty1
	.p2align	3, 0x0
dy2ty1:
	.quad	0x0000000000000000              ; double 0
	.size	dy2ty1, 8

	.protected	dy3ty1                  ; @dy3ty1
	.type	dy3ty1,@object
	.globl	dy3ty1
	.p2align	3, 0x0
dy3ty1:
	.quad	0x0000000000000000              ; double 0
	.size	dy3ty1, 8

	.protected	dy4ty1                  ; @dy4ty1
	.type	dy4ty1,@object
	.globl	dy4ty1
	.p2align	3, 0x0
dy4ty1:
	.quad	0x0000000000000000              ; double 0
	.size	dy4ty1, 8

	.protected	dy5ty1                  ; @dy5ty1
	.type	dy5ty1,@object
	.globl	dy5ty1
	.p2align	3, 0x0
dy5ty1:
	.quad	0x0000000000000000              ; double 0
	.size	dy5ty1, 8

	.protected	zzcon1                  ; @zzcon1
	.type	zzcon1,@object
	.globl	zzcon1
	.p2align	3, 0x0
zzcon1:
	.quad	0x0000000000000000              ; double 0
	.size	zzcon1, 8

	.protected	zzcon2                  ; @zzcon2
	.type	zzcon2,@object
	.globl	zzcon2
	.p2align	3, 0x0
zzcon2:
	.quad	0x0000000000000000              ; double 0
	.size	zzcon2, 8

	.protected	zzcon3                  ; @zzcon3
	.type	zzcon3,@object
	.globl	zzcon3
	.p2align	3, 0x0
zzcon3:
	.quad	0x0000000000000000              ; double 0
	.size	zzcon3, 8

	.protected	zzcon4                  ; @zzcon4
	.type	zzcon4,@object
	.globl	zzcon4
	.p2align	3, 0x0
zzcon4:
	.quad	0x0000000000000000              ; double 0
	.size	zzcon4, 8

	.protected	zzcon5                  ; @zzcon5
	.type	zzcon5,@object
	.globl	zzcon5
	.p2align	3, 0x0
zzcon5:
	.quad	0x0000000000000000              ; double 0
	.size	zzcon5, 8

	.protected	dz1tz1                  ; @dz1tz1
	.type	dz1tz1,@object
	.globl	dz1tz1
	.p2align	3, 0x0
dz1tz1:
	.quad	0x0000000000000000              ; double 0
	.size	dz1tz1, 8

	.protected	dz2tz1                  ; @dz2tz1
	.type	dz2tz1,@object
	.globl	dz2tz1
	.p2align	3, 0x0
dz2tz1:
	.quad	0x0000000000000000              ; double 0
	.size	dz2tz1, 8

	.protected	dz3tz1                  ; @dz3tz1
	.type	dz3tz1,@object
	.globl	dz3tz1
	.p2align	3, 0x0
dz3tz1:
	.quad	0x0000000000000000              ; double 0
	.size	dz3tz1, 8

	.protected	dz4tz1                  ; @dz4tz1
	.type	dz4tz1,@object
	.globl	dz4tz1
	.p2align	3, 0x0
dz4tz1:
	.quad	0x0000000000000000              ; double 0
	.size	dz4tz1, 8

	.protected	dz5tz1                  ; @dz5tz1
	.type	dz5tz1,@object
	.globl	dz5tz1
	.p2align	3, 0x0
dz5tz1:
	.quad	0x0000000000000000              ; double 0
	.size	dz5tz1, 8

	.protected	ce                      ; @ce
	.type	ce,@object
	.globl	ce
	.p2align	4, 0x0
ce:
	.zero	520
	.size	ce, 520

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym tx1
	.addrsig_sym tx2
	.addrsig_sym tx3
	.addrsig_sym ty1
	.addrsig_sym ty2
	.addrsig_sym ty3
	.addrsig_sym tz1
	.addrsig_sym tz2
	.addrsig_sym tz3
	.addrsig_sym bt
	.addrsig_sym dt
	.addrsig_sym dtdssp
	.addrsig_sym dnxm1
	.addrsig_sym dnym1
	.addrsig_sym dnzm1
	.addrsig_sym dtx1
	.addrsig_sym dttx2
	.addrsig_sym dty1
	.addrsig_sym dtty2
	.addrsig_sym dtz1
	.addrsig_sym dttz2
	.addrsig_sym c2dttx1
	.addrsig_sym c2dtty1
	.addrsig_sym c2dttz1
	.addrsig_sym comz1
	.addrsig_sym comz4
	.addrsig_sym comz5
	.addrsig_sym comz6
	.addrsig_sym c3c4tx3
	.addrsig_sym c3c4ty3
	.addrsig_sym c3c4tz3
	.addrsig_sym xxcon1
	.addrsig_sym xxcon2
	.addrsig_sym xxcon3
	.addrsig_sym xxcon4
	.addrsig_sym xxcon5
	.addrsig_sym dx1tx1
	.addrsig_sym dx2tx1
	.addrsig_sym dx3tx1
	.addrsig_sym dx4tx1
	.addrsig_sym dx5tx1
	.addrsig_sym yycon1
	.addrsig_sym yycon2
	.addrsig_sym yycon3
	.addrsig_sym yycon4
	.addrsig_sym yycon5
	.addrsig_sym dy1ty1
	.addrsig_sym dy2ty1
	.addrsig_sym dy3ty1
	.addrsig_sym dy4ty1
	.addrsig_sym dy5ty1
	.addrsig_sym zzcon1
	.addrsig_sym zzcon2
	.addrsig_sym zzcon3
	.addrsig_sym zzcon4
	.addrsig_sym zzcon5
	.addrsig_sym dz1tz1
	.addrsig_sym dz2tz1
	.addrsig_sym dz3tz1
	.addrsig_sym dz4tz1
	.addrsig_sym dz5tz1
	.addrsig_sym ce
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL21exact_rhs_kernel_initPdiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL21exact_rhs_kernel_initPdiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
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    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
