#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>

/* change dimension size as needed */
const int dimension = 4096 ;
const int blocksize = 64;
const int K = 4;
const int tilewidth = 2 ;


struct timeval tv; 

__global__ void gpuSmMM( float *Ad , float *Bd , float *Cd , int dimention )
{

        //Taking shared array to break the MAtrix in Tile widht and fatch them in that array per ele
          __shared__ float Ads [tilewidth][tilewidth] ;
          __shared__ float Bds [tilewidth][tilewidth] ;
         // calculate thread id
          unsigned int col = tilewidth*blockIdx.x + threadIdx.x ;
          unsigned int row = tilewidth*blockIdx.y + threadIdx.y ;
        for (int m = 0 ; m<dimention/tilewidth ; m++ ) // m indicate number of phase
			{
            Ads[threadIdx.y][threadIdx.x] =  Ad[row*dimention + (m*tilewidth + threadIdx.x)]  ;
            Bds[threadIdx.y][threadIdx.x] =  Bd[ ( m*tilewidth + threadIdx.y) * dimention + col] ;
         __syncthreads() ; // for syncronizeing the threads
         // Do for tile
				for ( int k1 = 0; k1<tilewidth ; k1++ )
                       Cd[row*dimention + col]+= Ads[threadIdx.x][k1] * Bds[k1][threadIdx.y] ;
         __syncthreads() ; // for syncronizeing the threads

			}
}


int main(int argc, char *argv[])
{
cudaEvent_t start_i, stop_i,start_mc_h2d, stop_mc_h2d,start_mc_d2h, stop_mc_d2h,start_pl, stop_pl;
		float time_i,time_mc_h2d,time_mc_d2h,time_pl;

		cudaEventCreate(&start_i);
		cudaEventCreate(&stop_i);
		
		cudaEventCreate(&start_mc_h2d);
		cudaEventCreate(&stop_mc_h2d);

		cudaEventCreate(&start_mc_d2h);
		cudaEventCreate(&stop_mc_d2h);
		
		cudaEventCreate(&start_pl);
		cudaEventCreate(&stop_pl);
		
		int i, j;
        float *A, *B, *C;// start, end;
		float *Ad, *Bd, *Cd;

		cudaEventRecord( start_i, 0 );
		
        A = (float*)malloc(dimension*dimension*sizeof(float));
        B = (float*)malloc(dimension*dimension*sizeof(float));
        C = (float*)malloc(dimension*dimension*sizeof(float));		
		
        srand(292);



        for(i = 0; i < dimension; i++)
                for(j = 0; j < dimension; j++)
                {   
                        A[dimension*i+j] = (rand()/(RAND_MAX + 1.0));
                        B[dimension*i+j] = (rand()/(RAND_MAX + 1.0));
                        C[dimension*i+j] = 0.0;
                }   
				
		cudaEventRecord( stop_i, 0 );
		cudaEventSynchronize( stop_i );
		
		cudaEventElapsedTime( &time_i, start_i, stop_i );


		cudaEventRecord( start_mc_h2d, 0 );
		
		cudaMalloc( (void**)&Ad, dimension*dimension*sizeof(float) );
		cudaMemcpy( Ad, A, dimension*dimension*sizeof(float), cudaMemcpyHostToDevice );

		cudaMalloc( (void**)&Bd, dimension*dimension*sizeof(float) );
		cudaMemcpy( Bd, B, dimension*dimension*sizeof(float), cudaMemcpyHostToDevice );
		
		cudaMalloc( (void**)&Cd, dimension*dimension*sizeof(float) );

		cudaEventRecord( stop_mc_h2d, 0 );
		cudaEventSynchronize( stop_mc_h2d );
		
		cudaEventElapsedTime( &time_mc_h2d, start_mc_h2d, stop_mc_h2d );

		

        //start = timestamp();

		cudaEventRecord( start_pl, 0 );
		dim3 threadBlock(blocksize,blocksize);
		dim3 grid(K,K);
		
		gpuSmMM<<<grid,threadBlock>>>( Ad,Bd,Cd,dimension);

        //end = timestamp();

		cudaEventRecord( stop_pl, 0 );
		cudaEventSynchronize( stop_pl );
		
		cudaEventElapsedTime( &time_pl, start_pl, stop_pl );

		cudaEventRecord( start_mc_d2h, 0 );
		cudaMemcpy(C,Cd,dimension*dimension*sizeof(float),cudaMemcpyDeviceToHost);
		cudaEventRecord( stop_mc_d2h, 0 );
		cudaEventSynchronize( stop_mc_d2h );
		
		cudaEventElapsedTime( &time_mc_d2h, start_mc_d2h, stop_mc_d2h );

		
		//printf("IT: %f ", time_i);
		printf("MC: %f ", ( time_mc_d2h + time_mc_h2d ) );
		printf("PLT: %f \n ", time_pl);
		//printf("T:%f .... \n\n", (time_pl + time_mc_d2h + time_mc_h2d+time_i));

		
        //printf("\nsecs:%f\n", end-start);

		cudaEventDestroy( start_i );
		cudaEventDestroy( stop_i );

		cudaEventDestroy( start_mc_d2h );
		cudaEventDestroy( stop_mc_d2h );

		cudaEventDestroy( start_mc_h2d );
		cudaEventDestroy( stop_mc_h2d );
		
		cudaEventDestroy( start_pl );
		cudaEventDestroy( stop_pl );
		
        free(A);
        free(B);
        free(C);
		cudaFree(Ad);
		cudaFree(Bd);
		cudaFree(Cd);

        return 0;
}

	.file	"tmpxft_00343d59_00000000-6_gpuShMatMul1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i
	.type	_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7gpuSmMMPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i
	.globl	_Z7gpuSmMMPfS_S_i
	.type	_Z7gpuSmMMPfS_S_i, @function
_Z7gpuSmMMPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2053:
	.size	_Z7gpuSmMMPfS_S_i, .-_Z7gpuSmMMPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"MC: %f "
.LC3:
	.string	"PLT: %f \n "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$67108864, %edi
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$67108864, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$292, %edi
	movq	%rax, %rbx
	call	srand@PLT
.L9:
	movq	%r14, %r13
	movl	$4096, %r15d
	salq	$14, %r13
.L10:
	call	rand@PLT
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r12,%r13)
	call	rand@PLT
	movl	$0x00000000, (%rbx,%r13)
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%rbp,%r13)
	addq	$4, %r13
	decl	%r15d
	jne	.L10
	incq	%r14
	cmpq	$4096, %r14
	jne	.L9
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	8(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	88(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movq	88(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	leaq	96(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movq	96(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	leaq	104(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$274877907008, %rdx
	movl	$1, %esi
	movabsq	$17179869188, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movl	$4096, %ecx
	movq	88(%rsp), %rdi
	call	_Z31__device_stub__Z7gpuSmMMPfS_S_iPfS_S_i
.L12:
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	80(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$67108864, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	64(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	64(%rsp), %rdx
	movq	56(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movss	16(%rsp), %xmm0
	addss	12(%rsp), %xmm0
	movb	$1, %al
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC3(%rip), %rsi
	movb	$1, %al
	cvtss2sd	20(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	56(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	64(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	72(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	80(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z7gpuSmMMPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7gpuSmMMPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	tv
	.bss
	.align 16
	.type	tv, @object
	.size	tv, 16
tv:
	.zero	16
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1040187392
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/time.h>

/* change dimension size as needed */
const int dimension = 4096 ;
const int blocksize = 64;
const int K = 4;
const int tilewidth = 2 ;


struct timeval tv; 

__global__ void gpuSmMM( float *Ad , float *Bd , float *Cd , int dimention )
{

        //Taking shared array to break the MAtrix in Tile widht and fatch them in that array per ele
          __shared__ float Ads [tilewidth][tilewidth] ;
          __shared__ float Bds [tilewidth][tilewidth] ;
         // calculate thread id
          unsigned int col = tilewidth*blockIdx.x + threadIdx.x ;
          unsigned int row = tilewidth*blockIdx.y + threadIdx.y ;
        for (int m = 0 ; m<dimention/tilewidth ; m++ ) // m indicate number of phase
			{
            Ads[threadIdx.y][threadIdx.x] =  Ad[row*dimention + (m*tilewidth + threadIdx.x)]  ;
            Bds[threadIdx.y][threadIdx.x] =  Bd[ ( m*tilewidth + threadIdx.y) * dimention + col] ;
         __syncthreads() ; // for syncronizeing the threads
         // Do for tile
				for ( int k1 = 0; k1<tilewidth ; k1++ )
                       Cd[row*dimention + col]+= Ads[threadIdx.x][k1] * Bds[k1][threadIdx.y] ;
         __syncthreads() ; // for syncronizeing the threads

			}
}


int main(int argc, char *argv[])
{
hipEvent_t start_i, stop_i,start_mc_h2d, stop_mc_h2d,start_mc_d2h, stop_mc_d2h,start_pl, stop_pl;
		float time_i,time_mc_h2d,time_mc_d2h,time_pl;

		hipEventCreate(&start_i);
		hipEventCreate(&stop_i);
		
		hipEventCreate(&start_mc_h2d);
		hipEventCreate(&stop_mc_h2d);

		hipEventCreate(&start_mc_d2h);
		hipEventCreate(&stop_mc_d2h);
		
		hipEventCreate(&start_pl);
		hipEventCreate(&stop_pl);
		
		int i, j;
        float *A, *B, *C;// start, end;
		float *Ad, *Bd, *Cd;

		hipEventRecord( start_i, 0 );
		
        A = (float*)malloc(dimension*dimension*sizeof(float));
        B = (float*)malloc(dimension*dimension*sizeof(float));
        C = (float*)malloc(dimension*dimension*sizeof(float));		
		
        srand(292);



        for(i = 0; i < dimension; i++)
                for(j = 0; j < dimension; j++)
                {   
                        A[dimension*i+j] = (rand()/(RAND_MAX + 1.0));
                        B[dimension*i+j] = (rand()/(RAND_MAX + 1.0));
                        C[dimension*i+j] = 0.0;
                }   
				
		hipEventRecord( stop_i, 0 );
		hipEventSynchronize( stop_i );
		
		hipEventElapsedTime( &time_i, start_i, stop_i );


		hipEventRecord( start_mc_h2d, 0 );
		
		hipMalloc( (void**)&Ad, dimension*dimension*sizeof(float) );
		hipMemcpy( Ad, A, dimension*dimension*sizeof(float), hipMemcpyHostToDevice );

		hipMalloc( (void**)&Bd, dimension*dimension*sizeof(float) );
		hipMemcpy( Bd, B, dimension*dimension*sizeof(float), hipMemcpyHostToDevice );
		
		hipMalloc( (void**)&Cd, dimension*dimension*sizeof(float) );

		hipEventRecord( stop_mc_h2d, 0 );
		hipEventSynchronize( stop_mc_h2d );
		
		hipEventElapsedTime( &time_mc_h2d, start_mc_h2d, stop_mc_h2d );

		

        //start = timestamp();

		hipEventRecord( start_pl, 0 );
		dim3 threadBlock(blocksize,blocksize);
		dim3 grid(K,K);
		
		gpuSmMM<<<grid,threadBlock>>>( Ad,Bd,Cd,dimension);

        //end = timestamp();

		hipEventRecord( stop_pl, 0 );
		hipEventSynchronize( stop_pl );
		
		hipEventElapsedTime( &time_pl, start_pl, stop_pl );

		hipEventRecord( start_mc_d2h, 0 );
		hipMemcpy(C,Cd,dimension*dimension*sizeof(float),hipMemcpyDeviceToHost);
		hipEventRecord( stop_mc_d2h, 0 );
		hipEventSynchronize( stop_mc_d2h );
		
		hipEventElapsedTime( &time_mc_d2h, start_mc_d2h, stop_mc_d2h );

		
		//printf("IT: %f ", time_i);
		printf("MC: %f ", ( time_mc_d2h + time_mc_h2d ) );
		printf("PLT: %f \n ", time_pl);
		//printf("T:%f .... \n\n", (time_pl + time_mc_d2h + time_mc_h2d+time_i));

		
        //printf("\nsecs:%f\n", end-start);

		hipEventDestroy( start_i );
		hipEventDestroy( stop_i );

		hipEventDestroy( start_mc_d2h );
		hipEventDestroy( stop_mc_d2h );

		hipEventDestroy( start_mc_h2d );
		hipEventDestroy( stop_mc_h2d );
		
		hipEventDestroy( start_pl );
		hipEventDestroy( stop_pl );
		
        free(A);
        free(B);
        free(C);
		hipFree(Ad);
		hipFree(Bd);
		hipFree(Cd);

        return 0;
}

	.text
	.file	"gpuShMatMul1.hip"
	.globl	_Z22__device_stub__gpuSmMMPfS_S_i # -- Begin function _Z22__device_stub__gpuSmMMPfS_S_i
	.type	_Z22__device_stub__gpuSmMMPfS_S_i,@function
_Z22__device_stub__gpuSmMMPfS_S_i:      # @_Z22__device_stub__gpuSmMMPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7gpuSmMMPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__gpuSmMMPfS_S_i, .Lfunc_end0-_Z22__device_stub__gpuSmMMPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x3e00000000000000              # double 4.6566128730773926E-10
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	88(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	leaq	56(%rsp), %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	48(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %rbp
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %r14
	movl	$67108864, %edi                 # imm = 0x4000000
	callq	malloc
	movq	%rax, %r15
	movl	$292, %edi                      # imm = 0x124
	callq	srand
	movl	$16384, %r13d                   # imm = 0x4000
	movq	%rbp, 112(%rsp)                 # 8-byte Spill
	movq	%r14, 104(%rsp)                 # 8-byte Spill
	movq	%r15, 96(%rsp)                  # 8-byte Spill
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%ebx, %ebx
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbp,%rbx,4)
	callq	rand
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%rbx,4)
	movl	$0, (%r15,%rbx,4)
	incq	%rbx
	cmpq	$4096, %rbx                     # imm = 0x1000
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r12
	addq	%r13, %r15
	addq	%r13, %r14
	addq	%r13, %rbp
	cmpq	$4096, %r12                     # imm = 0x1000
	jne	.LBB1_1
# %bb.4:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	88(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	132(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	80(%rsp), %r12
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	112(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %r12
	movl	$67108864, %esi                 # imm = 0x4000000
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	104(%rsp), %r14                 # 8-byte Reload
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	56(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	68(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$17179869188, %rdi              # imm = 0x400000004
	movabsq	$274877907008, %rdx             # imm = 0x4000000040
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	80(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z22__device_stub__gpuSmMMPfS_S_i
.LBB1_6:
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	124(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	32(%rsp), %rsi
	movl	$67108864, %edx                 # imm = 0x4000000
	movq	96(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	48(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	128(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventElapsedTime
	movss	(%r13), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	addss	68(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	88(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	48(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	movq	56(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipEventDestroy
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7gpuSmMMPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	tv,@object                      # @tv
	.bss
	.globl	tv
	.p2align	3, 0x0
tv:
	.zero	16
	.size	tv, 16

	.type	_Z7gpuSmMMPfS_S_i,@object       # @_Z7gpuSmMMPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z7gpuSmMMPfS_S_i
	.p2align	3, 0x0
_Z7gpuSmMMPfS_S_i:
	.quad	_Z22__device_stub__gpuSmMMPfS_S_i
	.size	_Z7gpuSmMMPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"MC: %f "
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"PLT: %f \n "
	.size	.L.str.1, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7gpuSmMMPfS_S_i"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__gpuSmMMPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7gpuSmMMPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7gpuSmMMPfS_S_i       ; -- Begin function _Z7gpuSmMMPfS_S_i
	.globl	_Z7gpuSmMMPfS_S_i
	.p2align	8
	.type	_Z7gpuSmMMPfS_S_i,@function
_Z7gpuSmMMPfS_S_i:                      ; @_Z7gpuSmMMPfS_S_i
; %bb.0:
	s_load_b32 s4, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 2
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_bfe_u32 v8, v0, 10, 10
	v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0x3ff, v0
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v0, s15, 1, v8
	s_lshl_b32 s5, s14, 1
	v_mul_lo_u32 v9, v8, s4
	s_lshr_b32 s8, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	s_add_i32 s8, s4, s8
	v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
	v_lshlrev_b32_e32 v4, 2, v2
	v_lshlrev_b32_e32 v7, 3, v2
	v_add3_u32 v2, v2, v9, s5
	s_lshl_b32 s4, s4, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v6, v8, 3, v4
	v_add_nc_u32_e32 v0, s5, v3
	v_lshl_add_u32 v8, v8, 2, 16
	s_ashr_i32 s5, s8, 1
	v_add_nc_u32_e32 v9, 16, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_mov_b32_e32 v0, v3
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[10:11], 2, v[0:1]
	v_add_nc_u32_e32 v0, 2, v0
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	s_cmp_eq_u32 s5, 0
	v_lshlrev_b64 v[12:13], 2, v[2:3]
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	v_add_nc_u32_e32 v2, s4, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	global_load_b32 v3, v[10:11], off
	global_load_b32 v10, v[12:13], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v6, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_b32 v3, v[4:5], off
	ds_load_b64 v[10:11], v7
	ds_load_2addr_b32 v[12:13], v8 offset1:2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v3, v10, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v11, v13
	global_store_b32 v[4:5], v3, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7gpuSmMMPfS_S_i
		.amdhsa_group_segment_fixed_size 32
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7gpuSmMMPfS_S_i, .Lfunc_end0-_Z7gpuSmMMPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7gpuSmMMPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7gpuSmMMPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
