#include <cuComplex.h>
#include <cuda.h>
#include <cuda_runtime.h>

__host__ __device__ double carg(const cuFloatComplex &z) {
  return atan2(cuCimagf(z), cuCrealf(z));
}
__host__ __device__ cuFloatComplex conj(const cuFloatComplex &z) {
  return make_cuFloatComplex(z.x, -z.y);
}

__global__ void calc_beta_err_kernel(cuFloatComplex *in, float *polarity,
                                     int current_symbol_index,
                                     cuFloatComplex *last_symbol, float bw,
                                     float freq, float *beta, float *err,
                                     int n) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;

  if (i < n) {
    cuFloatComplex *current_symbol = &in[i * 64];
    cuFloatComplex pp0, pp1, pp2, pp3;

    if (i > 0) {
      pp0 = in[(i - 1) * 64 + 11];
      pp1 = in[(i - 1) * 64 + 25];
      pp2 = in[(i - 1) * 64 + 39];
      pp3 = in[(i - 1) * 64 + 53];
    } else {
      pp0 = last_symbol[11];
      pp1 = last_symbol[25];
      pp2 = last_symbol[39];
      pp3 = last_symbol[53];
    }

    float p = polarity[(current_symbol_index + i - 2) % 127];

    if (current_symbol_index + i <= 2) {
      pp1 = cuCmulf(pp1, make_cuFloatComplex(-1.0, 0.0));
    } else {
      float last_p = polarity[(current_symbol_index + i - 2 - 1) % 127];
      pp0 = cuCmulf(pp0, make_cuFloatComplex(last_p, 0.0));
      pp1 = cuCmulf(pp1, make_cuFloatComplex(last_p, 0.0));
      pp2 = cuCmulf(pp2, make_cuFloatComplex(last_p, 0.0));
      pp3 = cuCmulf(pp3, make_cuFloatComplex(-last_p, 0.0));
    }

    if ((current_symbol_index + i) < 2) {
      beta[i] = carg(
          make_cuFloatComplex(current_symbol[11].x - current_symbol[25].x +
                                  current_symbol[39].x + current_symbol[53].x,
                              current_symbol[11].y - current_symbol[25].y +
                                  current_symbol[39].y + current_symbol[53].y));
    } else {
      beta[i] = carg(make_cuFloatComplex(
          (current_symbol[11].x * p) + (current_symbol[39].x * p) +
              (current_symbol[25].x * p) + (current_symbol[53].x * -p),
          (current_symbol[11].y * p) + (current_symbol[39].y * p) +
              (current_symbol[25].y * p) + (current_symbol[53].y * -p)));
    }

    err[i] = carg(cuCaddf(
        cuCaddf((make_cuFloatComplex(cuCmulf(pp0, current_symbol[11]).x * p,
                                     -cuCmulf(pp0, current_symbol[11]).y * p)),
                (make_cuFloatComplex(cuCmulf(pp1, current_symbol[25]).x * p,
                                     -cuCmulf(pp1, current_symbol[25]).y * p))),
        cuCaddf(
            (make_cuFloatComplex(cuCmulf(pp2, current_symbol[39]).x * p,
                                 -cuCmulf(pp2, current_symbol[39]).y * p)),
            (make_cuFloatComplex(cuCmulf(pp3, current_symbol[53]).x * -p,
                                 -cuCmulf(pp3, current_symbol[53]).y * -p)))));

    err[i] *= (bw / (2 * M_PI * freq * 80));
  }
}

__global__ void correct_sampling_offset_kernel(cuFloatComplex *in,
                                               cuFloatComplex *out,
                                               int start_idx, float freq_offset,
                                               int n) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;

  if (i < n) {

    int symbol_index = i / 64;
    int sample_index = i % 64;

    // // compensate sampling offset
    // for(int i = 0; i < 64; i++) {
    // 	current_symbol[i] *= exp(gr_complex(0,
    // 2*M_PI*d_current_symbol*80*(d_epsilon0 + d_er)*(i-32)/64));
    // }

    float x = -freq_offset * (float)(start_idx + symbol_index) *
              (float)(sample_index - 32) / 64;
    out[i] = cuCmulf(in[i], make_cuFloatComplex(cos(x), sin(x)));
  }
}

__global__ void multiply_phase_kernel(cuFloatComplex *in, cuFloatComplex *out,
                                      float *beta, int n) {
  
  // beta applies for an entire symbol
  int i = blockIdx.x * blockDim.x + threadIdx.x;
  if (i < n) {
    // e ix = cos x + i sin x
    out[i] = cuCmulf(in[i], make_cuFloatComplex(cos(beta[i/64]), sin(beta[i/64])));
  }
}

void exec_calc_beta_err(cuFloatComplex *in, float *polarity,
                        int current_symbol_index, cuFloatComplex *last_symbol,
                        float bw, float freq, float *beta, float *err, int n,
                        int grid_size, int block_size, cudaStream_t stream) {
  calc_beta_err_kernel<<<grid_size, block_size, 0, stream>>>(
      in, polarity, current_symbol_index, last_symbol, bw, freq, beta, err, n);
}

void get_block_and_grid_calc_beta_err(int *minGrid, int *minBlock) {
  cudaOccupancyMaxPotentialBlockSize(minGrid, minBlock, calc_beta_err_kernel, 0,
                                     0);
}

void exec_correct_sampling_offset(cuFloatComplex *in, cuFloatComplex *out,
                                  int start_idx, float freq_offset, int n,
                                  int grid_size, int block_size,
                                  cudaStream_t stream) {
  correct_sampling_offset_kernel<<<grid_size, block_size, 0, stream>>>(
      in, out, start_idx, freq_offset, n);
}

void exec_multiply_phase(cuFloatComplex *in, cuFloatComplex *out, float *beta,
                         int n, int grid_size, int block_size,
                         cudaStream_t stream) {
  multiply_phase_kernel<<<grid_size, block_size, 0, stream>>>(in, out, beta, n);
}
	.file	"tmpxft_00336f47_00000000-6_frame_equalizer.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2039:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2039:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4cargRK6float2
	.type	_Z4cargRK6float2, @function
_Z4cargRK6float2:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movss	4(%rdi), %xmm0
	movss	(%rdi), %xmm1
	call	atan2f@PLT
	popq	%rdx
	.cfi_def_cfa_offset 8
	cvtss2sd	%xmm0, %xmm0
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z4cargRK6float2, .-_Z4cargRK6float2
	.globl	_Z4conjRK6float2
	.type	_Z4conjRK6float2, @function
_Z4conjRK6float2:
.LFB2032:
	.cfi_startproc
	endbr64
	movss	4(%rdi), %xmm0
	xorps	.LC0(%rip), %xmm0
	movl	(%rdi), %edx
	movd	%xmm0, %eax
	salq	$32, %rax
	orq	%rax, %rdx
	movq	%rdx, %xmm0
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z4conjRK6float2, .-_Z4conjRK6float2
	.globl	_Z32get_block_and_grid_calc_beta_errPiS_
	.type	_Z32get_block_and_grid_calc_beta_errPiS_, @function
_Z32get_block_and_grid_calc_beta_errPiS_:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	testq	%rdi, %rdi
	je	.L5
	movq	%rsi, %r12
	testq	%rsi, %rsi
	je	.L5
	movq	%rdi, %r13
	leaq	16(%rsp), %rdi
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	jne	.L5
	movl	16(%rsp), %edx
	leaq	20(%rsp), %rdi
	movl	$39, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L5
	movl	16(%rsp), %edx
	leaq	24(%rsp), %rdi
	movl	$10, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L5
	movl	16(%rsp), %edx
	leaq	28(%rsp), %rdi
	movl	$1, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L5
	movl	16(%rsp), %edx
	leaq	32(%rsp), %rdi
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L5
	leaq	40(%rsp), %rdi
	leaq	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i(%rip), %rsi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	jne	.L5
	movl	20(%rsp), %eax
	movl	64(%rsp), %ebp
	movl	24(%rsp), %r9d
	movl	%eax, (%rsp)
	movl	28(%rsp), %eax
	cmpl	%eax, %ebp
	cmovg	%eax, %ebp
	xorl	%r10d, %r10d
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
	leal	-1(%r9,%rbp), %ebx
	movl	%ebx, %eax
	cltd
	idivl	%r9d
	subl	%edx, %ebx
.L10:
	testl	%ebx, %ebx
	jle	.L12
	cmpl	%ebx, %ebp
	movl	%ebx, %edx
	leaq	36(%rsp), %rdi
	movl	%r10d, 12(%rsp)
	cmovle	%ebp, %edx
	leaq	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i(%rip), %rsi
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	%r9d, 8(%rsp)
	movl	%edx, 4(%rsp)
	call	cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
	testl	%eax, %eax
	jne	.L5
	movl	4(%rsp), %edx
	movl	36(%rsp), %eax
	movl	12(%rsp), %r10d
	movl	8(%rsp), %r9d
	movl	%edx, %ecx
	imull	%eax, %ecx
	cmpl	%r10d, %ecx
	jle	.L11
	movl	%ecx, %r10d
	movl	%eax, %r14d
	movl	%edx, %r15d
.L11:
	cmpl	%r10d, (%rsp)
	je	.L12
	subl	%r9d, %ebx
	jmp	.L10
.L12:
	imull	32(%rsp), %r14d
	movl	%r14d, 0(%r13)
	movl	%r15d, (%r12)
.L5:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z32get_block_and_grid_calc_beta_errPiS_, .-_Z32get_block_and_grid_calc_beta_errPiS_
	.globl	_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i
	.type	_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i, @function
_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movl	%edx, 44(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L18:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i, .-_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i
	.globl	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i
	.type	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i, @function
_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i
	.cfi_endproc
.LFE2062:
	.size	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i, .-_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i
	.globl	_Z18exec_calc_beta_errP6float2PfiS0_ffS1_S1_iiiP11CUstream_st
	.type	_Z18exec_calc_beta_errP6float2PfiS0_ffS1_S1_iiiP11CUstream_st, @function
_Z18exec_calc_beta_errP6float2PfiS0_ffS1_S1_iiiP11CUstream_st:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	xorl	%r8d, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	128(%rsp), %eax
	movl	120(%rsp), %edx
	movq	%rdi, (%rsp)
	movq	136(%rsp), %r9
	movss	%xmm0, 12(%rsp)
	movl	112(%rsp), %ebx
	movl	%eax, 36(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	44(%rsp), %ecx
	movl	%edx, 24(%rsp)
	movq	36(%rsp), %rdx
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	movss	%xmm1, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	8(%rsp), %xmm1
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L23
	movl	%ebx, 112(%rsp)
	movq	(%rsp), %rdi
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movq	%r15, %r9
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%r14, %r8
	movq	%r13, %rcx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z61__device_stub__Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_iP6float2PfiS0_ffS1_S1_i
.L23:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z18exec_calc_beta_errP6float2PfiS0_ffS1_S1_iiiP11CUstream_st, .-_Z18exec_calc_beta_errP6float2PfiS0_ffS1_S1_iiiP11CUstream_st
	.globl	_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi
	.type	_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi, @function
_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z30correct_sampling_offset_kernelP6float2S0_ifi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L26:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi, .-_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi
	.globl	_Z30correct_sampling_offset_kernelP6float2S0_ifi
	.type	_Z30correct_sampling_offset_kernelP6float2S0_ifi, @function
_Z30correct_sampling_offset_kernelP6float2S0_ifi:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi
	.cfi_endproc
.LFE2064:
	.size	_Z30correct_sampling_offset_kernelP6float2S0_ifi, .-_Z30correct_sampling_offset_kernelP6float2S0_ifi
	.globl	_Z28exec_correct_sampling_offsetP6float2S0_ifiiiP11CUstream_st
	.type	_Z28exec_correct_sampling_offsetP6float2S0_ifiiiP11CUstream_st, @function
_Z28exec_correct_sampling_offsetP6float2S0_ifiiiP11CUstream_st:
.LFB2035:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movl	%r9d, 36(%rsp)
	movq	96(%rsp), %r9
	movq	%rax, 40(%rsp)
	movl	44(%rsp), %ecx
	movl	%r8d, 24(%rsp)
	movq	36(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	movss	%xmm0, 12(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movss	12(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L31
	addq	$56, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movl	%r12d, %edx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z62__device_stub__Z30correct_sampling_offset_kernelP6float2S0_ifiP6float2S0_ifi
.L31:
	.cfi_restore_state
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z28exec_correct_sampling_offsetP6float2S0_ifiiiP11CUstream_st, .-_Z28exec_correct_sampling_offsetP6float2S0_ifiiiP11CUstream_st
	.globl	_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi
	.type	_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi, @function
_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z21multiply_phase_kernelP6float2S0_Pfi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L34:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi, .-_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi
	.globl	_Z21multiply_phase_kernelP6float2S0_Pfi
	.type	_Z21multiply_phase_kernelP6float2S0_Pfi, @function
_Z21multiply_phase_kernelP6float2S0_Pfi:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi
	.cfi_endproc
.LFE2066:
	.size	_Z21multiply_phase_kernelP6float2S0_Pfi, .-_Z21multiply_phase_kernelP6float2S0_Pfi
	.globl	_Z19exec_multiply_phaseP6float2S0_PfiiiP11CUstream_st
	.type	_Z19exec_multiply_phaseP6float2S0_PfiiiP11CUstream_st, @function
_Z19exec_multiply_phaseP6float2S0_PfiiiP11CUstream_st:
.LFB2036:
	.cfi_startproc
	endbr64
	movabsq	$4294967297, %rax
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rdi, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	%r9d, 20(%rsp)
	movq	80(%rsp), %r9
	movq	%rax, 24(%rsp)
	movl	28(%rsp), %ecx
	movl	%r8d, 8(%rsp)
	movq	20(%rsp), %rdx
	xorl	%r8d, %r8d
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%r13d, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z53__device_stub__Z21multiply_phase_kernelP6float2S0_PfiP6float2S0_Pfi
.L39:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z19exec_multiply_phaseP6float2S0_PfiiiP11CUstream_st, .-_Z19exec_multiply_phaseP6float2S0_PfiiiP11CUstream_st
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z21multiply_phase_kernelP6float2S0_Pfi"
.LC2:
	.string	"_Z30correct_sampling_offset_kernelP6float2S0_ifi"
.LC3:
	.string	"_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21multiply_phase_kernelP6float2S0_Pfi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30correct_sampling_offset_kernelP6float2S0_ifi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20calc_beta_err_kernelP6float2PfiS0_ffS1_S1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2068:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC0:
	.long	-2147483648
	.long	0
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_complex.h>
#include <hip/hip_runtime.h>


__host__ __device__ double carg(const hipFloatComplex &z) {
  return atan2(hipCimagf(z), hipCrealf(z));
}
__host__ __device__ hipFloatComplex conj(const hipFloatComplex &z) {
  return make_hipFloatComplex(z.x, -z.y);
}

__global__ void calc_beta_err_kernel(hipFloatComplex *in, float *polarity,
                                     int current_symbol_index,
                                     hipFloatComplex *last_symbol, float bw,
                                     float freq, float *beta, float *err,
                                     int n) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;

  if (i < n) {
    hipFloatComplex *current_symbol = &in[i * 64];
    hipFloatComplex pp0, pp1, pp2, pp3;

    if (i > 0) {
      pp0 = in[(i - 1) * 64 + 11];
      pp1 = in[(i - 1) * 64 + 25];
      pp2 = in[(i - 1) * 64 + 39];
      pp3 = in[(i - 1) * 64 + 53];
    } else {
      pp0 = last_symbol[11];
      pp1 = last_symbol[25];
      pp2 = last_symbol[39];
      pp3 = last_symbol[53];
    }

    float p = polarity[(current_symbol_index + i - 2) % 127];

    if (current_symbol_index + i <= 2) {
      pp1 = hipCmulf(pp1, make_hipFloatComplex(-1.0, 0.0));
    } else {
      float last_p = polarity[(current_symbol_index + i - 2 - 1) % 127];
      pp0 = hipCmulf(pp0, make_hipFloatComplex(last_p, 0.0));
      pp1 = hipCmulf(pp1, make_hipFloatComplex(last_p, 0.0));
      pp2 = hipCmulf(pp2, make_hipFloatComplex(last_p, 0.0));
      pp3 = hipCmulf(pp3, make_hipFloatComplex(-last_p, 0.0));
    }

    if ((current_symbol_index + i) < 2) {
      beta[i] = carg(
          make_hipFloatComplex(current_symbol[11].x - current_symbol[25].x +
                                  current_symbol[39].x + current_symbol[53].x,
                              current_symbol[11].y - current_symbol[25].y +
                                  current_symbol[39].y + current_symbol[53].y));
    } else {
      beta[i] = carg(make_hipFloatComplex(
          (current_symbol[11].x * p) + (current_symbol[39].x * p) +
              (current_symbol[25].x * p) + (current_symbol[53].x * -p),
          (current_symbol[11].y * p) + (current_symbol[39].y * p) +
              (current_symbol[25].y * p) + (current_symbol[53].y * -p)));
    }

    err[i] = carg(hipCaddf(
        hipCaddf((make_hipFloatComplex(hipCmulf(pp0, current_symbol[11]).x * p,
                                     -hipCmulf(pp0, current_symbol[11]).y * p)),
                (make_hipFloatComplex(hipCmulf(pp1, current_symbol[25]).x * p,
                                     -hipCmulf(pp1, current_symbol[25]).y * p))),
        hipCaddf(
            (make_hipFloatComplex(hipCmulf(pp2, current_symbol[39]).x * p,
                                 -hipCmulf(pp2, current_symbol[39]).y * p)),
            (make_hipFloatComplex(hipCmulf(pp3, current_symbol[53]).x * -p,
                                 -hipCmulf(pp3, current_symbol[53]).y * -p)))));

    err[i] *= (bw / (2 * M_PI * freq * 80));
  }
}

__global__ void correct_sampling_offset_kernel(hipFloatComplex *in,
                                               hipFloatComplex *out,
                                               int start_idx, float freq_offset,
                                               int n) {
  int i = blockIdx.x * blockDim.x + threadIdx.x;

  if (i < n) {

    int symbol_index = i / 64;
    int sample_index = i % 64;

    // // compensate sampling offset
    // for(int i = 0; i < 64; i++) {
    // 	current_symbol[i] *= exp(gr_complex(0,
    // 2*M_PI*d_current_symbol*80*(d_epsilon0 + d_er)*(i-32)/64));
    // }

    float x = -freq_offset * (float)(start_idx + symbol_index) *
              (float)(sample_index - 32) / 64;
    out[i] = hipCmulf(in[i], make_hipFloatComplex(cos(x), sin(x)));
  }
}

__global__ void multiply_phase_kernel(hipFloatComplex *in, hipFloatComplex *out,
                                      float *beta, int n) {
  
  // beta applies for an entire symbol
  int i = blockIdx.x * blockDim.x + threadIdx.x;
  if (i < n) {
    // e ix = cos x + i sin x
    out[i] = hipCmulf(in[i], make_hipFloatComplex(cos(beta[i/64]), sin(beta[i/64])));
  }
}

void exec_calc_beta_err(hipFloatComplex *in, float *polarity,
                        int current_symbol_index, hipFloatComplex *last_symbol,
                        float bw, float freq, float *beta, float *err, int n,
                        int grid_size, int block_size, hipStream_t stream) {
  calc_beta_err_kernel<<<grid_size, block_size, 0, stream>>>(
      in, polarity, current_symbol_index, last_symbol, bw, freq, beta, err, n);
}

void get_block_and_grid_calc_beta_err(int *minGrid, int *minBlock) {
  hipOccupancyMaxPotentialBlockSize(minGrid, minBlock, calc_beta_err_kernel, 0,
                                     0);
}

void exec_correct_sampling_offset(hipFloatComplex *in, hipFloatComplex *out,
                                  int start_idx, float freq_offset, int n,
                                  int grid_size, int block_size,
                                  hipStream_t stream) {
  correct_sampling_offset_kernel<<<grid_size, block_size, 0, stream>>>(
      in, out, start_idx, freq_offset, n);
}

void exec_multiply_phase(hipFloatComplex *in, hipFloatComplex *out, float *beta,
                         int n, int grid_size, int block_size,
                         hipStream_t stream) {
  multiply_phase_kernel<<<grid_size, block_size, 0, stream>>>(in, out, beta, n);
}
	.text
	.file	"frame_equalizer.hip"
	.globl	_Z4cargRK15HIP_vector_typeIfLj2EE # -- Begin function _Z4cargRK15HIP_vector_typeIfLj2EE
	.type	_Z4cargRK15HIP_vector_typeIfLj2EE,@function
_Z4cargRK15HIP_vector_typeIfLj2EE:      # @_Z4cargRK15HIP_vector_typeIfLj2EE
	.cfi_startproc
# %bb.0:
	cvtss2sd	4(%rdi), %xmm0
	cvtss2sd	(%rdi), %xmm1
	jmp	atan2                           # TAILCALL
.Lfunc_end0:
	.size	_Z4cargRK15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z4cargRK15HIP_vector_typeIfLj2EE
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z4conjRK15HIP_vector_typeIfLj2EE
.LCPI1_0:
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.long	0x80000000                      # float -0
	.text
	.globl	_Z4conjRK15HIP_vector_typeIfLj2EE
	.type	_Z4conjRK15HIP_vector_typeIfLj2EE,@function
_Z4conjRK15HIP_vector_typeIfLj2EE:      # @_Z4conjRK15HIP_vector_typeIfLj2EE
	.cfi_startproc
# %bb.0:
	movss	(%rdi), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	4(%rdi), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	xorps	.LCPI1_0(%rip), %xmm1
	movss	%xmm0, -8(%rsp)
	movss	%xmm1, -4(%rsp)
	movsd	-8(%rsp), %xmm0                 # xmm0 = mem[0],zero
	retq
.Lfunc_end1:
	.size	_Z4conjRK15HIP_vector_typeIfLj2EE, .Lfunc_end1-_Z4conjRK15HIP_vector_typeIfLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i # -- Begin function _Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.type	_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i,@function
_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i: # @_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	16(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	12(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	48(%rsp), %r11
	movq	%r8, (%r11)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, .Lfunc_end2-_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi # -- Begin function _Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.type	_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi,@function
_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi: # @_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	4(%rsp), %r8
	movl	%ecx, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi, .Lfunc_end3-_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi # -- Begin function _Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.type	_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi,@function
_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi: # @_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi, .Lfunc_end4-_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.cfi_endproc
                                        # -- End function
	.globl	_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t # -- Begin function _Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t
	.type	_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t,@function
_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t: # @_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, %rbx
	movq	%r8, %r14
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movq	%rcx, %r15
	movl	%edx, %ebp
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	80(%rsp), %edx
	movl	72(%rsp), %edi
	movq	88(%rsp), %r9
	btsq	$32, %rdi
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB5_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB5_2:
	.cfi_def_cfa_offset 64
	movq	%r13, %rdi
	movq	%r12, %rsi
	movl	%ebp, %edx
	movq	%r15, %rcx
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movq	%r14, %r8
	movq	%rbx, %r9
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i # TAILCALL
.Lfunc_end5:
	.size	_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t, .Lfunc_end5-_Z18exec_calc_beta_errP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_iiiP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z32get_block_and_grid_calc_beta_errPiS_ # -- Begin function _Z32get_block_and_grid_calc_beta_errPiS_
	.type	_Z32get_block_and_grid_calc_beta_errPiS_,@function
_Z32get_block_and_grid_calc_beta_errPiS_: # @_Z32get_block_and_grid_calc_beta_errPiS_
	.cfi_startproc
# %bb.0:
	movl	$_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	jmp	hipOccupancyMaxPotentialBlockSize # TAILCALL
.Lfunc_end6:
	.size	_Z32get_block_and_grid_calc_beta_errPiS_, .Lfunc_end6-_Z32get_block_and_grid_calc_beta_errPiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t # -- Begin function _Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t
	.type	_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t,@function
_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t: # @_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebx
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	%edx, %ebp
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	48(%rsp), %rax
	movl	%r8d, %edi
	btsq	$32, %rdi
	movl	%r9d, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rax, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB7_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_2:
	.cfi_def_cfa_offset 48
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebp, %edx
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi # TAILCALL
.Lfunc_end7:
	.size	_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t, .Lfunc_end7-_Z28exec_correct_sampling_offsetP15HIP_vector_typeIfLj2EES1_ifiiiP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.globl	_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t # -- Begin function _Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t
	.type	_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t,@function
_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t: # @_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %ebx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	48(%rsp), %rax
	movl	%r8d, %edi
	btsq	$32, %rdi
	movl	%r9d, %edx
	btsq	$32, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%rax, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi # TAILCALL
.Lfunc_end8:
	.size	_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t, .Lfunc_end8-_Z19exec_multiply_phaseP15HIP_vector_typeIfLj2EES1_PfiiiP12ihipStream_t
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i,@object # @_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.section	.rodata,"a",@progbits
	.globl	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.p2align	3, 0x0
_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i:
	.quad	_Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.size	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, 8

	.type	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi,@object # @_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.globl	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.p2align	3, 0x0
_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi:
	.quad	_Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.size	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi, 8

	.type	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi,@object # @_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.globl	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.p2align	3, 0x0
_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi:
	.quad	_Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.size	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i"
	.size	.L__unnamed_1, 65

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi"
	.size	.L__unnamed_2, 66

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi"
	.size	.L__unnamed_3, 57

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.addrsig_sym _Z45__device_stub__correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.addrsig_sym _Z36__device_stub__multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.addrsig_sym _Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.addrsig_sym _Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i ; -- Begin function _Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.globl	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
	.p2align	8
	.type	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i,@function
_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i: ; @_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_14
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mov_b32 s22, exec_lo
                                        ; implicit-def: $sgpr8_sgpr9
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $sgpr12_sgpr13
                                        ; implicit-def: $sgpr10_sgpr11
                                        ; implicit-def: $sgpr16_sgpr17
                                        ; implicit-def: $sgpr14_sgpr15
                                        ; implicit-def: $sgpr20_sgpr21
                                        ; implicit-def: $sgpr18_sgpr19
	v_cmpx_gt_i32_e32 1, v1
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_load_b64 s[20:21], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s20, 0x58
	s_addc_u32 s3, s21, 0
	s_add_u32 s8, s20, 0x5c
	s_addc_u32 s9, s21, 0
	s_add_u32 s10, s20, 0xc8
	s_addc_u32 s11, s21, 0
	s_add_u32 s12, s20, 0xcc
	s_addc_u32 s13, s21, 0
	s_add_u32 s14, s20, 0x138
	s_addc_u32 s15, s21, 0
	s_add_u32 s16, s20, 0x13c
	s_addc_u32 s17, s21, 0
	s_add_u32 s18, s20, 0x1a8
	s_addc_u32 s19, s21, 0
	s_add_u32 s20, s20, 0x1ac
	s_addc_u32 s21, s21, 0
.LBB0_3:                                ; %Flow482
	s_or_saveexec_b32 s22, s22
	v_dual_mov_b32 v5, s18 :: v_dual_lshlrev_b32 v2, 6, v1
	v_dual_mov_b32 v6, s19 :: v_dual_mov_b32 v15, s20
	v_dual_mov_b32 v18, s17 :: v_dual_mov_b32 v3, s10
	v_dual_mov_b32 v16, s21 :: v_dual_mov_b32 v9, s14
	v_dual_mov_b32 v4, s11 :: v_dual_mov_b32 v11, s12
	v_mov_b32_e32 v8, s3
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v17, s16
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v7, s2
	s_xor_b32 exec_lo, exec_lo, s22
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_subrev_nc_u32_e32 v3, 53, v2
	v_subrev_nc_u32_e32 v5, 39, v2
	v_subrev_nc_u32_e32 v7, 25, v2
	v_add_nc_u32_e32 v9, -11, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[15:16], 3, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v3, 4
	v_lshlrev_b64 v[5:6], 3, v[9:10]
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v4, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v16, vcc_lo
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v17, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v15, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v6, vcc_lo
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s22
	s_load_b32 s2, s[0:1], 0x10
	global_load_b32 v13, v[13:14], off
	global_load_b32 v14, v[7:8], off
	global_load_b32 v11, v[11:12], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v19, s2, v1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, -2, v19
	v_mul_hi_i32 v20, 0x81020409, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, v20, v0
	v_lshrrev_b32_e32 v21, 31, v20
	v_ashrrev_i32_e32 v20, 6, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, v20, v21
	v_mul_lo_u32 v20, 0x7f, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, v0, v20
	v_ashrrev_i32_e32 v21, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	v_add_co_u32 v20, vcc_lo, s6, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v21, vcc_lo
	global_load_b32 v7, v[17:18], off
	global_load_b32 v9, v[9:10], off
	global_load_b32 v8, v[15:16], off
	global_load_b32 v5, v[5:6], off
	global_load_b32 v0, v[20:21], off
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr6
	v_cmpx_lt_i32_e32 2, v19
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_waitcnt vmcnt(2)
	v_dual_mul_f32 v15, 0, v8 :: v_dual_add_nc_u32 v4, -3, v19
	v_mul_f32_e32 v12, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v6, 0x2040811, v4
	v_sub_nc_u32_e32 v10, v4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v10, 1, v10
	v_add_nc_u32_e32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v6, 6, v6
	v_mul_lo_u32 v6, 0x7f, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v6
	v_lshlrev_b32_e32 v4, 2, v4
	global_load_b32 v4, v4, s[6:7]
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v6, 0, v13 :: v_dual_mul_f32 v7, v4, v7
	v_mul_f32_e32 v10, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v16, v4, v14, -v6
	v_mul_f32_e32 v13, v4, v13
	v_dual_mul_f32 v8, v4, v8 :: v_dual_fmac_f32 v7, 0, v9
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f32 v6, v4, v3, -v10
	v_mul_f32_e32 v10, v4, v11
	v_fma_f32 v11, v4, v9, -v12
	v_fma_f32 v4, v5, -v4, -v15
	v_fmac_f32_e32 v13, 0, v14
	v_fma_f32 v8, v5, 0, -v8
	v_fmac_f32_e32 v10, 0, v3
	v_mov_b32_e32 v14, v16
	v_mov_b32_e32 v5, v4
	v_mov_b32_e32 v9, v11
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr3
.LBB0_7:                                ; %Flow481
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_waitcnt vmcnt(5)
	v_fma_f32 v6, 0x80000000, v11, -v3
	v_fma_f32 v10, v3, 0, -v11
.LBB0_9:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(5)
	v_ashrrev_i32_e32 v3, 31, v2
                                        ; implicit-def: $vgpr11
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v2, v[3:4], off offset:88
	v_cmpx_lt_i32_e32 1, v19
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_clause 0x3
	global_load_b64 v[11:12], v[3:4], off offset:312
	global_load_b32 v19, v[3:4], off offset:92
	global_load_b64 v[15:16], v[3:4], off offset:424
	global_load_b64 v[17:18], v[3:4], off offset:200
	s_mov_b32 s2, 0x3b2d2a58
	s_waitcnt vmcnt(3)
	v_mul_f32_e32 v11, v0, v11
	v_mul_f32_e32 v12, v0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v0, v2
	s_waitcnt vmcnt(2)
	v_fmac_f32_e32 v12, v0, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v0, v17
	v_fmac_f32_e32 v12, v0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v0, v15, v11
	v_fma_f32 v11, -v0, v16, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_class_f32_e64 s4, v2, 0x204
	v_max_f32_e64 v12, |v2|, |v11|
	v_min_f32_e64 v16, |v2|, |v11|
	v_cmp_gt_f32_e64 vcc_lo, |v11|, |v2|
	v_cmp_class_f32_e64 s5, v11, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e32 v15, v12
	v_frexp_exp_i32_f32_e32 v12, v12
	v_frexp_exp_i32_f32_e32 v17, v16
	v_frexp_mant_f32_e32 v16, v16
	v_rcp_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v17, v12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, v16, v15
	v_ldexp_f32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v12, v12
	v_fmaak_f32 v16, s2, v15, 0xbc7a590c
	v_cmp_eq_f32_e64 s2, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3d29fb3f
	v_fmaak_f32 v16, v15, v16, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3dd931b2
	v_fmaak_f32 v16, v15, v16, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3e4cb8bf
	v_fmaak_f32 v16, v15, v16, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v15, v16
	v_fmac_f32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, 0x3fc90fdb, v12
	v_cndmask_b32_e32 v12, v12, v15, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, 0x40490fdb, v12
	v_cndmask_b32_e64 v16, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v2
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_mov_b32 v15, 0x4016cbe4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v12, v16, s2
	v_cndmask_b32_e32 v15, 0x3f490fdb, v15, vcc_lo
	s_and_b32 vcc_lo, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v12, v15, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_bfi_b32 v11, 0x7fffffff, v2, v11
                                        ; implicit-def: $vgpr2
.LBB0_11:                               ; %Flow
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_13
; %bb.12:
	s_clause 0x3
	global_load_b64 v[11:12], v[3:4], off offset:312
	global_load_b64 v[15:16], v[3:4], off offset:424
	global_load_b64 v[17:18], v[3:4], off offset:200
	global_load_b32 v19, v[3:4], off offset:92
	s_mov_b32 s2, 0x3b2d2a58
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v2, v2, v17 :: v_dual_sub_f32 v17, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v2, v2, v11 :: v_dual_add_f32 v11, v17, v12
	v_dual_add_f32 v2, v2, v15 :: v_dual_add_f32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_class_f32_e64 s4, v2, 0x204
	v_max_f32_e64 v12, |v2|, |v11|
	v_min_f32_e64 v16, |v2|, |v11|
	v_cmp_gt_f32_e64 vcc_lo, |v11|, |v2|
	v_cmp_class_f32_e64 s5, v11, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_frexp_mant_f32_e32 v15, v12
	v_frexp_exp_i32_f32_e32 v12, v12
	v_frexp_exp_i32_f32_e32 v17, v16
	v_frexp_mant_f32_e32 v16, v16
	v_rcp_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v17, v12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, v16, v15
	v_ldexp_f32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v12, v12
	v_fmaak_f32 v16, s2, v15, 0xbc7a590c
	v_cmp_eq_f32_e64 s2, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3d29fb3f
	v_fmaak_f32 v16, v15, v16, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3dd931b2
	v_fmaak_f32 v16, v15, v16, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v16, v15, v16, 0x3e4cb8bf
	v_fmaak_f32 v16, v15, v16, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v15, v15, v16
	v_fmac_f32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, 0x3fc90fdb, v12
	v_cndmask_b32_e32 v12, v12, v15, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v15, 0x40490fdb, v12
	v_cndmask_b32_e64 v16, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v2
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_mov_b32 v15, 0x4016cbe4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, v12, v16, s2
	v_cndmask_b32_e32 v15, 0x3f490fdb, v15, vcc_lo
	s_and_b32 vcc_lo, s4, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v12, v15, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v2
	v_cndmask_b32_e32 v2, 0x7fc00000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_bfi_b32 v11, 0x7fffffff, v2, v11
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s3
	s_load_b128 s[4:7], s[0:1], 0x28
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x20
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x401921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v15, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v2, vcc_lo
	v_cvt_f64_f32_e32 v[19:20], s1
	v_cvt_f64_f32_e32 v[21:22], s0
	s_mov_b32 s0, 0x3b2d2a58
	global_store_b32 v[15:16], v11, off
	s_clause 0x3
	global_load_b64 v[11:12], v[3:4], off offset:88
	global_load_b64 v[15:16], v[3:4], off offset:200
	global_load_b64 v[17:18], v[3:4], off offset:312
	global_load_b64 v[3:4], v[3:4], off offset:424
	v_mul_f64 v[19:20], v[19:20], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], 0x40540000, v[19:20]
	v_div_scale_f64 v[23:24], null, v[19:20], v[19:20], v[21:22]
	v_div_scale_f64 v[29:30], vcc_lo, v[21:22], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[25:26], v[23:24]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0
	v_fma_f64 v[25:26], v[25:26], v[27:28], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0
	v_fma_f64 v[25:26], v[25:26], v[27:28], v[25:26]
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v28, v10, v16 :: v_dual_mul_f32 v31, v7, v18
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v32, v8, v4
	v_mul_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v5, v5, v3, -v32
	v_mul_f32_e32 v16, v6, v16
	v_fma_f32 v6, v6, v15, -v28
	v_fmac_f32_e32 v4, v8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v5, v0, v5
	v_dual_mul_f32 v27, v13, v12 :: v_dual_fmac_f32 v16, v10, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v12, v14, v12 :: v_dual_mul_f32 v3, v0, v6
	v_fma_f32 v14, v14, v11, -v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v12, v13, v11 :: v_dual_fmac_f32 v3, v0, v14
	v_mul_f32_e32 v18, v9, v18
	v_fma_f32 v9, v9, v17, -v31
	v_mul_f32_e32 v6, v0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, v7, v17
	v_fma_f32 v5, v0, v9, -v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v6, v0, -v16, -v6
	v_mul_f32_e32 v7, v0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v0, v0, v4, -v7
	v_add_f32_e32 v7, v3, v5
	v_mul_f64 v[3:4], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v6, v0
	v_max_f32_e64 v5, |v7|, |v0|
	v_min_f32_e64 v8, |v7|, |v0|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_frexp_mant_f32_e32 v6, v5
	v_frexp_exp_i32_f32_e32 v5, v5
	v_frexp_exp_i32_f32_e32 v9, v8
	v_frexp_mant_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v6, v6
	v_sub_nc_u32_e32 v5, v9, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, v8, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v8, v6, v5
	v_mul_f32_e32 v9, v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v5, s0, v9, 0xbc7a590c
	v_cmp_gt_i32_e64 s0, 0, v7
	v_fmaak_f32 v10, v9, v5, 0x3d29fb3f
	v_fma_f64 v[5:6], -v[23:24], v[3:4], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v10, v9, v10, 0xbd97d4d7
	v_fmaak_f32 v10, v9, v10, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v10, v9, v10, 0xbe1160e6
	v_fmaak_f32 v10, v9, v10, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v10, v9, v10, 0xbeaaaa62
	v_mul_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, v8, v9
	v_div_fmas_f64 v[3:4], v[5:6], v[25:26], v[3:4]
	v_sub_f32_e32 v9, 0x3fc90fdb, v8
	v_cmp_gt_f32_e64 vcc_lo, |v0|, |v7|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v5, v8, v9 :: v_dual_mov_b32 v8, 0x4016cbe4
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v9, 0, 0x40490fdb, s0
	v_cmp_class_f32_e64 s0, v7, 0x204
	v_sub_f32_e32 v6, 0x40490fdb, v5
	v_cmp_class_f32_e64 s1, v0, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cndmask_b32_e32 v6, 0x3f490fdb, v8, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v0, v7
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	v_div_fixup_f64 v[3:4], v[3:4], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v0, 0x7fffffff, v5, v0
	v_cvt_f64_f32_e32 v[5:6], v0
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], v[5:6]
	v_cvt_f32_f64_e32 v3, v[3:4]
	global_store_b32 v[0:1], v3, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i, .Lfunc_end0-_Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2572
; NumSgprs: 25
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi ; -- Begin function _Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.globl	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
	.p2align	8
	.type	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi,@function
_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi: ; @_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s6, v4
	s_cbranch_execz .LBB1_10
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_ashrrev_i32_e32 v5, 31, v4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_lshrrev_b32_e32 v5, 26, v5
	v_add_nc_u32_e32 v5, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 6, v5
	v_and_b32_e32 v5, 0xffffffc0, v5
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_nc_u32_e32 v6, s4, v6
	v_sub_nc_u32_e32 v4, v4, v5
	global_load_b64 v[2:3], v[2:3], off
	v_cvt_f32_i32_e32 v5, v6
	v_subrev_nc_u32_e32 v4, 32, v4
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, s5, v5
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v5, v4
	v_mul_f32_e32 v4, 0xbc800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, 0x7fffffff, v4
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v4|
	v_lshrrev_b32_e32 v8, 23, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s4
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v18, v5, s0, 0x800000
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, v7
	v_add_nc_u32_e32 v7, 0xffffff88, v8
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v16, v7
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v7
	v_mov_b32_e32 v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v6, v12, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	v_add_nc_u32_e32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mov_b32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	v_mov_b32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	v_mov_b32_e32 v9, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v16, v10, s0
	v_cndmask_b32_e64 v13, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_sub_nc_u32_e32 v15, 32, v7
	v_cndmask_b32_e64 v14, v14, v9, s0
	v_cndmask_b32_e64 v6, v9, v6, s0
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v11, v11, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s1
	v_cndmask_b32_e64 v6, v14, v6, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v13, v11, v15
	v_alignbit_b32 v12, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v10, v6, v15
	v_cndmask_b32_e32 v7, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
	v_bfe_u32 v11, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v7, v9, 30
	v_alignbit_b32 v9, v9, v10, 30
	v_alignbit_b32 v6, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 0, v11
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_xor_b32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v12
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v6, v9, v6, v10
	v_lshrrev_b32_e32 v10, 29, v7
	v_lshrrev_b32_e32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v12, v6, 9
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v11, v7
	v_clz_i32_u32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, 0.5, v10
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v16
	v_sub_nc_u32_e32 v17, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v9, v6, v17
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v12
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v10
	v_fmac_f32_e32 v9, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v13, v9
.LBB1_3:                                ; %Flow52
	s_or_saveexec_b32 s0, s5
	v_mul_f32_e64 v11, 0x3f22f983, |v4|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v11
	v_fma_f32 v6, 0xbfc90fda, v7, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v11, 0
	v_and_or_b32 v19, v5, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v19, 0
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v10, v13
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v19, v[10:11]
	v_add_nc_u32_e32 v8, 0xffffff88, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v8
	v_mov_b32_e32 v10, v14
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v19, v[10:11]
	v_cndmask_b32_e32 v9, v13, v9, vcc_lo
	v_add_nc_u32_e32 v8, v17, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v10, v15
	v_cmp_lt_u32_e64 s0, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v19, v[10:11]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v18, v8
	v_mov_b32_e32 v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v8
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v10, v17
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v11, v16, v14 :: v_dual_add_nc_u32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v10, v14, v12
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v17, v11, s0
	v_cndmask_b32_e64 v14, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v15, s0
	v_sub_nc_u32_e32 v16, 32, v8
	v_cndmask_b32_e64 v15, v15, v10, s0
	v_cndmask_b32_e64 v9, v10, v9, s0
	v_cndmask_b32_e64 v14, v14, v12, s1
	v_cndmask_b32_e64 v12, v12, v11, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v15, s1
	v_cndmask_b32_e64 v9, v15, v9, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v14, v12, v16
	v_alignbit_b32 v13, v12, v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v11, v9, v16
	v_cndmask_b32_e32 v8, v17, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v13, v12 :: v_dual_cndmask_b32 v11, v15, v11
	v_bfe_u32 v12, v8, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v8, v10, 30
	v_alignbit_b32 v10, v10, v11, 30
	v_alignbit_b32 v9, v11, v9, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 0, v12
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v10, v14
	v_xor_b32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v15, v13
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	v_alignbit_b32 v13, v13, v10, v11
	v_alignbit_b32 v9, v10, v9, v11
	v_lshrrev_b32_e32 v11, 29, v8
	v_lshrrev_b32_e32 v8, 30, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v13, v9, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v14, v10
	v_or_b32_e32 v16, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v9, v10, v9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v13, v16
	v_add_lshl_u32 v13, v14, v15, 23
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3fc90fda, v10, -v14
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v10, v10, 0x33a22168, v13
	v_or_b32_e32 v9, v9, v11
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v9
	v_dual_add_f32 v9, v14, v10 :: v_dual_add_nc_u32 v10, v12, v8
.LBB1_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s4
; %bb.8:
	v_rndne_f32_e32 v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v4|
	v_cvt_i32_f32_e32 v10, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v9, v8, 0xa7c234c4, v9
; %bb.9:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, v6, v6 :: v_dual_mul_f32 v11, v9, v9
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v5, v5, v4
	v_dual_fmaak_f32 v12, s0, v8, 0x3c0881c4 :: v_dual_fmaak_f32 v15, s0, v11, 0x3c0881c4
	v_dual_fmaak_f32 v13, s1, v8, 0xbab64f3b :: v_dual_and_b32 v14, 1, v7
	v_dual_fmaak_f32 v16, s1, v11, 0xbab64f3b :: v_dual_and_b32 v17, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v12, v8, v12, 0xbe2aaa9d :: v_dual_lshlrev_b32 v7, 30, v7
	v_dual_fmaak_f32 v13, v8, v13, 0x3d2aabf7 :: v_dual_fmaak_f32 v16, v11, v16, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, v11, v15, 0xbe2aaa9d :: v_dual_mul_f32 v12, v8, v12
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_dual_fmaak_f32 v13, v8, v13, 0xbf000004 :: v_dual_fmaak_f32 v16, v11, v16, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v15, v11, v15 :: v_dual_fmac_f32 v6, v6, v12
	v_lshlrev_b32_e32 v10, 30, v10
	v_fma_f32 v8, v8, v13, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v11, v11, v16, 1.0
	v_fmac_f32_e32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, -v6, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_dual_cndmask_b32 v8, v11, v9 :: v_dual_and_b32 v7, 0x80000000, v7
	v_and_b32_e32 v9, 0x80000000, v10
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v7, v6
	v_xor3_b32 v5, v5, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v3, v4
	v_mul_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v2, v6, -v7
	v_fmac_f32_e32 v5, v3, v6
	global_store_b64 v[0:1], v[4:5], off
.LBB1_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi, .Lfunc_end1-_Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2032
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi ; -- Begin function _Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.globl	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
	.p2align	8
	.type	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi,@function
_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi: ; @_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB2_10
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 26, v2
	v_add_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 6, v0
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v0
	global_load_b32 v4, v[3:4], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, 0x7fffffff, v4
	v_cmp_ngt_f32_e64 s4, 0x48000000, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v8, 23, v5
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s0
	s_cbranch_execz .LBB2_3
; %bb.2:
	s_mov_b32 s0, 0x7fffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v18, v5, s0, 0x800000
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v9, v7
	v_add_nc_u32_e32 v7, 0xffffff88, v8
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	v_mov_b32_e32 v9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, v16, v7
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v7
	v_mov_b32_e32 v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, 0, 0xffffffe0, s0
	v_cndmask_b32_e32 v6, v12, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	v_add_nc_u32_e32 v7, v17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v7
	v_mov_b32_e32 v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	v_mov_b32_e32 v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	v_mov_b32_e32 v9, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_dual_cndmask_b32 v14, v14, v12 :: v_dual_cndmask_b32 v9, v13, v11
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v16, v10, s0
	v_cndmask_b32_e64 v13, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_sub_nc_u32_e32 v15, 32, v7
	v_cndmask_b32_e64 v14, v14, v9, s0
	v_cndmask_b32_e64 v6, v9, v6, s0
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v11, v11, v10, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v14, s1
	v_cndmask_b32_e64 v6, v14, v6, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v13, v11, v15
	v_alignbit_b32 v12, v11, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v10, v6, v15
	v_cndmask_b32_e32 v7, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v10, v14, v10
	v_bfe_u32 v11, v7, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v7, v9, 30
	v_alignbit_b32 v9, v9, v10, 30
	v_alignbit_b32 v6, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 0, v11
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v13
	v_xor_b32_e32 v6, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v12
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 31, v14
	v_lshlrev_b32_e32 v16, 23, v14
	v_alignbit_b32 v12, v12, v9, v10
	v_alignbit_b32 v6, v9, v6, v10
	v_lshrrev_b32_e32 v10, 29, v7
	v_lshrrev_b32_e32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v12, v6, 9
	v_lshlrev_b32_e32 v10, 31, v10
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v7, v11, v7
	v_clz_i32_u32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v15, 0.5, v10
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, v15, v16
	v_sub_nc_u32_e32 v17, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v9, v6, v17
	v_or_b32_e32 v9, v12, v15
	v_add_lshl_u32 v12, v13, v14, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v6, 9, v6
	v_mul_f32_e32 v13, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v12
	v_fma_f32 v12, 0x3fc90fda, v9, -v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, 0x33000000, v6
	v_fmamk_f32 v9, v9, 0x33a22168, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v6, v6, v10
	v_fmac_f32_e32 v9, 0x3fc90fda, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v6, v13, v9
.LBB2_3:                                ; %Flow45
	s_or_saveexec_b32 s0, s5
	v_mul_f32_e64 v11, 0x3f22f983, |v4|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v11
	v_fma_f32 v6, 0xbfc90fda, v7, |v4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v6, v7, 0xb3a22168, v6
	v_fmamk_f32 v6, v7, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v7, v7
; %bb.5:                                ; %_ZL3cosf.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s0, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB2_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v11, 0
	v_and_or_b32 v19, v5, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v19, 0
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v10, v13
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v19, v[10:11]
	v_add_nc_u32_e32 v8, 0xffffff88, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v8
	v_mov_b32_e32 v10, v14
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v19, v[10:11]
	v_cndmask_b32_e32 v9, v13, v9, vcc_lo
	v_add_nc_u32_e32 v8, v17, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v10, v15
	v_cmp_lt_u32_e64 s0, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v19, v[10:11]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v18, v8
	v_mov_b32_e32 v10, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v8
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v10, v17
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v19, v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v11, v16, v14 :: v_dual_add_nc_u32 v8, v10, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v10, v14, v12
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v17, v11, s0
	v_cndmask_b32_e64 v14, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v15, s0
	v_sub_nc_u32_e32 v16, 32, v8
	v_cndmask_b32_e64 v15, v15, v10, s0
	v_cndmask_b32_e64 v9, v10, v9, s0
	v_cndmask_b32_e64 v14, v14, v12, s1
	v_cndmask_b32_e64 v12, v12, v11, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v15, s1
	v_cndmask_b32_e64 v9, v15, v9, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v14, v12, v16
	v_alignbit_b32 v13, v12, v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v11, v9, v16
	v_cndmask_b32_e32 v8, v17, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v13, v12 :: v_dual_cndmask_b32 v11, v15, v11
	v_bfe_u32 v12, v8, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v8, v10, 30
	v_alignbit_b32 v10, v10, v11, 30
	v_alignbit_b32 v9, v11, v9, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 0, v12
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v10, v10, v14
	v_xor_b32_e32 v9, v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v15, v13
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	v_alignbit_b32 v13, v13, v10, v11
	v_alignbit_b32 v9, v10, v9, v11
	v_lshrrev_b32_e32 v11, 29, v8
	v_lshrrev_b32_e32 v8, 30, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v13, v9, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v14, v10
	v_or_b32_e32 v16, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v9, v10, v9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v13, v16
	v_add_lshl_u32 v13, v14, v15, 23
	v_lshrrev_b32_e32 v9, 9, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3fc90fda, v10, -v14
	v_add_nc_u32_e32 v9, 0x33000000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v10, v10, 0x33a22168, v13
	v_or_b32_e32 v9, v9, v11
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v9
	v_dual_add_f32 v9, v14, v10 :: v_dual_add_nc_u32 v10, v12, v8
.LBB2_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s4
; %bb.8:
	v_rndne_f32_e32 v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0xbfc90fda, v8, |v4|
	v_cvt_i32_f32_e32 v10, v8
	v_fmamk_f32 v9, v8, 0xb3a22168, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v9, v8, 0xa7c234c4, v9
; %bb.9:                                ; %_ZL3sinf.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v8, v6, v6 :: v_dual_mul_f32 v11, v9, v9
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v5, v5, v4
	v_dual_fmaak_f32 v12, s0, v8, 0x3c0881c4 :: v_dual_fmaak_f32 v15, s0, v11, 0x3c0881c4
	v_dual_fmaak_f32 v13, s1, v8, 0xbab64f3b :: v_dual_and_b32 v14, 1, v7
	v_dual_fmaak_f32 v16, s1, v11, 0xbab64f3b :: v_dual_and_b32 v17, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v12, v8, v12, 0xbe2aaa9d :: v_dual_lshlrev_b32 v7, 30, v7
	v_dual_fmaak_f32 v13, v8, v13, 0x3d2aabf7 :: v_dual_fmaak_f32 v16, v11, v16, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v15, v11, v15, 0xbe2aaa9d :: v_dual_mul_f32 v12, v8, v12
	v_cmp_eq_u32_e32 vcc_lo, 0, v14
	v_dual_fmaak_f32 v13, v8, v13, 0xbf000004 :: v_dual_fmaak_f32 v16, v11, v16, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v15, v11, v15 :: v_dual_fmac_f32 v6, v6, v12
	v_lshlrev_b32_e32 v10, 30, v10
	v_fma_f32 v8, v8, v13, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v11, v11, v16, 1.0
	v_fmac_f32_e32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, -v6, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_dual_cndmask_b32 v8, v11, v9 :: v_dual_and_b32 v7, 0x80000000, v7
	v_and_b32_e32 v9, 0x80000000, v10
	v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v6, v7, v6
	v_xor3_b32 v5, v5, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
	v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v3, v4
	v_mul_f32_e32 v5, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v2, v6, -v7
	v_fmac_f32_e32 v5, v3, v6
	global_store_b64 v[0:1], v[4:5], off
.LBB2_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi, .Lfunc_end2-_Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2036
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z20calc_beta_err_kernelP15HIP_vector_typeIfLj2EEPfiS1_ffS2_S2_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z30correct_sampling_offset_kernelP15HIP_vector_typeIfLj2EES1_ifi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21multiply_phase_kernelP15HIP_vector_typeIfLj2EES1_Pfi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
