/*
* Rayhana ZIARA
* produit matrice vecteur
*/

#include <stdlib.h>
#include <stdio.h>

/*
* DESCRIPTION : kernel concernant le produit matrice vecteur
* PARAMETRES : matrice A, vecteur v, vecteur r et taille des vecteurs
* RETOUR : /
*/
__global__ void matVect(float *A, float *v, float *r, int size) 
{
  float resultat = 0.0;
  int index = blockIdx.x * blockDim.x + threadIdx.x;

  if(index > size)
  {
    printf("ERREUR - Index > size\n");
    return;
  }

  for(int i = 0; i < size; i++)
    resultat += A[i * size + index] * v[i];

  r[index] = resultat;
}

/*
* DESCRIPTION : fonction d'affichage de matrice et de vecteur
* PARAMETRES : matrice à afficher, nb ligne et nb colonne de A, 
* RETOUR : /
*/
void affichage(float *M, int ligne, int colonne)
{
  for(int i = 0; i < ligne; i++)
  {
    for(int j = 0; j < colonne; j++)
      fprintf(stdout, "%lf\t", M[i * ligne + j]);
    fprintf(stdout, "\n");
  }
  fprintf(stdout, "\n");
}

int main(int argc, char **argv)
{
  // declaration des variables du produit matrice vecteur
  // variables du hote
  float *A, *v, *r; 
  int n; // taille de la matrice et du vecteur

  // variables du device
  float *d_A, *d_v, *d_r;

  if(argc != 2)
  {
    fprintf(stderr, "ERREUR - Veuillez entrez la taille de A en parametre d'execution. Merci'\n./exam_rz n \n");
    return -1;
  }

  n = atoi(argv[1]); // taille de la matrice A(n * n) et du vecteur v (n)

  // allocation memoire dans le hote pour la matrice A et le vecteur d
  A = (float*)malloc(n * n * sizeof(float));
  v = (float*)malloc(n * sizeof(float));
  r = (float*)malloc(n * sizeof(float));

  // initialisation de la matrice A (matrice stockée en 1D) et du vecteur v
  for(int i = 0; i < n; i++)
  {
    v[i] = i * n;
    for(int j = 0; j < n; j++)
      A[i * n + j] = i * n + j;
  }

  // allocation memoire dans le device pour les equivalents de matrice A et du vecteur v
  cudaMalloc((void**)&d_A, n * n * sizeof(float));
  cudaMalloc((void**)&d_v, n * sizeof(float));
  cudaMalloc((void**)&d_r, n * sizeof(float));

  // copie de la matrice A et du vecteur v dans le device
  cudaMemcpy(d_A, A, n * n * sizeof(float), cudaMemcpyHostToDevice);
  cudaMemcpy(d_v, v, n * sizeof(float), cudaMemcpyHostToDevice);

  // appel du kernel
  dim3 threads(4, 4); // 32*16
  dim3 blocks;
  blocks.x = (n + threads.x - 1) / threads.x;
  blocks.y = (n + threads.y - 1) / threads.y;
  matVect<<<blocks, threads>>>(d_A, d_v, d_r, n);

  // attente de tous les threads
  cudaThreadSynchronize();

  // copie de la matrice equivalente C dans le hote
  cudaMemcpy(r, d_r, n * sizeof(float), cudaMemcpyDeviceToHost);

  fprintf(stdout, "Matrice A\n");
  affichage(A, n, n);
  fprintf(stdout, "Vecteur v\n");
  affichage(v, 1, n);
  fprintf(stdout, "Vecteur r\n");
  affichage(r, 1, n);

  // liberation memoire hote
  free(A);
  free(v);
  free(r);

  // liberation memoire device
  cudaFree(d_A);
  cudaFree(d_v);
  cudaFree(d_r);

  return 0;
}

	.file	"tmpxft_0039d13e_00000000-6_matvec.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%lf\t"
.LC1:
	.string	"\n"
	.text
	.globl	_Z9affichagePfii
	.type	_Z9affichagePfii, @function
_Z9affichagePfii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	%edx, 12(%rsp)
.L3:
	cmpl	%ebx, %r13d
	jge	.L5
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,4), %r14
.L6:
	movq	stdout(%rip), %rdi
	cmpl	%r15d, 12(%rsp)
	jle	.L9
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	(%r14,%r15,4), %xmm0
	call	__fprintf_chk@PLT
	incq	%r15
	jmp	.L6
.L9:
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	incl	%r13d
	addl	%ebx, %r12d
	movl	$2, %esi
	call	__fprintf_chk@PLT
	jmp	.L3
.L5:
	movq	stdout(%rip), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	$2, %esi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__fprintf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z9affichagePfii, .-_Z9affichagePfii
	.globl	_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i
	.type	_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z7matVectPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i
	.globl	_Z7matVectPfS_S_i
	.type	_Z7matVectPfS_S_i, @function
_Z7matVectPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z7matVectPfS_S_i, .-_Z7matVectPfS_S_i
	.section	.rodata.str1.1
.LC2:
	.string	"ERREUR - Veuillez entrez la taille de A en parametre d'execution. Merci'\n./exam_rz n \n"
.LC3:
	.string	"Matrice A\n"
.LC4:
	.string	"Vecteur v\n"
.LC5:
	.string	"Vecteur r\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	je	.L16
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	call	__fprintf_chk@PLT
	orl	$-1, %eax
	jmp	.L15
.L16:
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movslq	%eax, %rbp
	movl	%ebp, %r12d
	movq	%rbp, %rbx
	imull	%ebp, %r12d
	salq	$2, %rbp
	movslq	%r12d, %r12
	salq	$2, %r12
	movq	%r12, %rdi
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	xorl	%edx, %edx
	movq	%rax, %r15
.L18:
	cmpl	%edx, %ebx
	jle	.L25
	cvtsi2ssl	%ecx, %xmm0
	xorl	%eax, %eax
	movss	%xmm0, 0(%r13,%rdx,4)
.L19:
	leal	(%rcx,%rax), %edi
	cvtsi2ssl	%edi, %xmm0
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	cmpl	%eax, %ebx
	jg	.L19
	incq	%rdx
	addl	%ebx, %ecx
	addq	%rbp, %rsi
	jmp	.L18
.L25:
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	3(%rbx), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$2, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$17179869188, %rdx
	movl	%eax, 44(%rsp)
	movl	%eax, 48(%rsp)
	movq	44(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebx, %ecx
	movq	8(%rsp), %rdi
	call	_Z31__device_stub__Z7matVectPfS_S_iPfS_S_i
.L21:
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rsi
	movq	%rbp, %rdx
	movq	%r15, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	stdout(%rip), %rdi
	leaq	.LC3(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	%ebx, %edx
	movl	%ebx, %esi
	movq	%r14, %rdi
	call	_Z9affichagePfii
	movq	stdout(%rip), %rdi
	leaq	.LC4(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	%ebx, %edx
	movl	$1, %esi
	movq	%r13, %rdi
	call	_Z9affichagePfii
	movq	stdout(%rip), %rdi
	leaq	.LC5(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	%ebx, %edx
	movl	$1, %esi
	movq	%r15, %rdi
	call	_Z9affichagePfii
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r15, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L15:
	movq	56(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z7matVectPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7matVectPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
* Rayhana ZIARA
* produit matrice vecteur
*/


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>

/*
* DESCRIPTION : kernel concernant le produit matrice vecteur
* PARAMETRES : matrice A, vecteur v, vecteur r et taille des vecteurs
* RETOUR : /
*/
__global__ void matVect(float *A, float *v, float *r, int size) 
{
  float resultat = 0.0;
  int index = blockIdx.x * blockDim.x + threadIdx.x;

  if(index > size)
  {
    printf("ERREUR - Index > size\n");
    return;
  }

  for(int i = 0; i < size; i++)
    resultat += A[i * size + index] * v[i];

  r[index] = resultat;
}

/*
* DESCRIPTION : fonction d'affichage de matrice et de vecteur
* PARAMETRES : matrice à afficher, nb ligne et nb colonne de A, 
* RETOUR : /
*/
void affichage(float *M, int ligne, int colonne)
{
  for(int i = 0; i < ligne; i++)
  {
    for(int j = 0; j < colonne; j++)
      fprintf(stdout, "%lf\t", M[i * ligne + j]);
    fprintf(stdout, "\n");
  }
  fprintf(stdout, "\n");
}

int main(int argc, char **argv)
{
  // declaration des variables du produit matrice vecteur
  // variables du hote
  float *A, *v, *r; 
  int n; // taille de la matrice et du vecteur

  // variables du device
  float *d_A, *d_v, *d_r;

  if(argc != 2)
  {
    fprintf(stderr, "ERREUR - Veuillez entrez la taille de A en parametre d'execution. Merci'\n./exam_rz n \n");
    return -1;
  }

  n = atoi(argv[1]); // taille de la matrice A(n * n) et du vecteur v (n)

  // allocation memoire dans le hote pour la matrice A et le vecteur d
  A = (float*)malloc(n * n * sizeof(float));
  v = (float*)malloc(n * sizeof(float));
  r = (float*)malloc(n * sizeof(float));

  // initialisation de la matrice A (matrice stockée en 1D) et du vecteur v
  for(int i = 0; i < n; i++)
  {
    v[i] = i * n;
    for(int j = 0; j < n; j++)
      A[i * n + j] = i * n + j;
  }

  // allocation memoire dans le device pour les equivalents de matrice A et du vecteur v
  hipMalloc((void**)&d_A, n * n * sizeof(float));
  hipMalloc((void**)&d_v, n * sizeof(float));
  hipMalloc((void**)&d_r, n * sizeof(float));

  // copie de la matrice A et du vecteur v dans le device
  hipMemcpy(d_A, A, n * n * sizeof(float), hipMemcpyHostToDevice);
  hipMemcpy(d_v, v, n * sizeof(float), hipMemcpyHostToDevice);

  // appel du kernel
  dim3 threads(4, 4); // 32*16
  dim3 blocks;
  blocks.x = (n + threads.x - 1) / threads.x;
  blocks.y = (n + threads.y - 1) / threads.y;
  matVect<<<blocks, threads>>>(d_A, d_v, d_r, n);

  // attente de tous les threads
  hipDeviceSynchronize();

  // copie de la matrice equivalente C dans le hote
  hipMemcpy(r, d_r, n * sizeof(float), hipMemcpyDeviceToHost);

  fprintf(stdout, "Matrice A\n");
  affichage(A, n, n);
  fprintf(stdout, "Vecteur v\n");
  affichage(v, 1, n);
  fprintf(stdout, "Vecteur r\n");
  affichage(r, 1, n);

  // liberation memoire hote
  free(A);
  free(v);
  free(r);

  // liberation memoire device
  hipFree(d_A);
  hipFree(d_v);
  hipFree(d_r);

  return 0;
}

	.text
	.file	"matvec.hip"
	.globl	_Z22__device_stub__matVectPfS_S_i # -- Begin function _Z22__device_stub__matVectPfS_S_i
	.type	_Z22__device_stub__matVectPfS_S_i,@function
_Z22__device_stub__matVectPfS_S_i:      # @_Z22__device_stub__matVectPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7matVectPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__matVectPfS_S_i, .Lfunc_end0-_Z22__device_stub__matVectPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9affichagePfii                # -- Begin function _Z9affichagePfii
	.type	_Z9affichagePfii,@function
_Z9affichagePfii:                       # @_Z9affichagePfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, 4(%rsp)                   # 4-byte Spill
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%esi, %ebp
	movl	%esi, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	4(%rsp), %r12d                  # 4-byte Reload
	xorl	%r13d, %r13d
	xorl	%r14d, %r14d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	cmpl	$0, 4(%rsp)                     # 4-byte Folded Reload
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbx
	xorl	%r15d, %r15d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	stdout(%rip), %rdi
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str, %esi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	stdout(%rip), %rsi
	movl	$10, %edi
	callq	fputc@PLT
	incq	%r14
	addl	%ebp, %r13d
	cmpq	16(%rsp), %r14                  # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge14
	movq	stdout(%rip), %rsi
	movl	$10, %edi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fputc@PLT                       # TAILCALL
.Lfunc_end1:
	.size	_Z9affichagePfii, .Lfunc_end1-_Z9affichagePfii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	cmpl	$2, %edi
	jne	.LBB2_1
# %bb.2:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movl	%eax, %ebp
	imull	%ebp, %ebp
	shlq	$2, %rbp
	movq	%rbp, %rdi
	callq	malloc
	movq	%rax, %r14
	movslq	%ebx, %r13
	shlq	$2, %r13
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r13, %rdi
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	testl	%ebx, %ebx
	jle	.LBB2_7
# %bb.3:                                # %.lr.ph69
	movl	%ebx, %eax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB2_4:                                # %.lr.ph.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_5 Depth 2
	movl	%ebx, %esi
	imull	%edx, %esi
	xorps	%xmm0, %xmm0
	cvtsi2ss	%esi, %xmm0
	movl	%ecx, %esi
	leaq	(%r14,%rsi,4), %rsi
	movss	%xmm0, (%r15,%rdx,4)
	xorl	%edi, %edi
.LBB2_5:                                # %.lr.ph
                                        #   Parent Loop BB2_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rcx,%rdi), %r8d
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r8d, %xmm0
	movss	%xmm0, (%rsi,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %rax
	jne	.LBB2_5
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB2_4 Depth=1
	incq	%rdx
	addq	%rax, %rcx
	cmpq	%rax, %rdx
	jne	.LBB2_4
.LBB2_7:                                # %._crit_edge70
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	%r14, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebx, %eax
	addl	$3, %eax
	shrl	$2, %eax
	movq	%rax, %rdi
	shlq	$32, %rdi
	orq	%rax, %rdi
	xorl	%ebp, %ebp
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_9
# %bb.8:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	%ebx, %ecx
	callq	_Z22__device_stub__matVectPfS_S_i
.LBB2_9:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movq	32(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movq	%r13, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	stdout(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$10, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%ebx, %edx
	callq	_Z9affichagePfii
	movq	stdout(%rip), %rcx
	movl	$.L.str.4, %edi
	movl	$10, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%r15, %rdi
	movl	$1, %esi
	movl	%ebx, %edx
	callq	_Z9affichagePfii
	movq	stdout(%rip), %rcx
	movl	$.L.str.5, %edi
	movl	$10, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movq	%r12, %rdi
	movl	$1, %esi
	movl	%ebx, %edx
	callq	_Z9affichagePfii
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
.LBB2_10:
	movl	%ebp, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_1:
	.cfi_def_cfa_offset 96
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
	movl	$86, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$-1, %ebp
	jmp	.LBB2_10
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7matVectPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7matVectPfS_S_i,@object       # @_Z7matVectPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z7matVectPfS_S_i
	.p2align	3, 0x0
_Z7matVectPfS_S_i:
	.quad	_Z22__device_stub__matVectPfS_S_i
	.size	_Z7matVectPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%lf\t"
	.size	.L.str, 5

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"ERREUR - Veuillez entrez la taille de A en parametre d'execution. Merci'\n./exam_rz n \n"
	.size	.L.str.2, 87

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Matrice A\n"
	.size	.L.str.3, 11

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Vecteur v\n"
	.size	.L.str.4, 11

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Vecteur r\n"
	.size	.L.str.5, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7matVectPfS_S_i"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__matVectPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7matVectPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7matVectPfS_S_i       ; -- Begin function _Z7matVectPfS_S_i
	.globl	_Z7matVectPfS_S_i
	.p2align	8
	.type	_Z7matVectPfS_S_i,@function
_Z7matVectPfS_S_i:                      ; @_Z7matVectPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s9, s[0:1], 0x18
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_ge_i32_e64 s9, v1
	s_xor_b32 s8, exec_lo, s4
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader27
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v2, v1
	s_mov_b32 s10, s9
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_waitcnt lgkmcnt(0)
	s_load_b32 s11, s[6:7], 0x0
	s_add_i32 s10, s10, -1
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_nc_u32_e32 v2, s9, v2
	s_cmp_eq_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s11, v3
	s_cbranch_scc0 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_5:                                ; %Flow308
	s_and_not1_saveexec_b32 s0, s8
	s_cbranch_execz .LBB0_147
; %bb.6:
	s_load_b64 s[2:3], s[2:3], 0x50
	v_mbcnt_lo_u32_b32 v2, -1, 0
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v7, v2
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v7
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_12
; %bb.7:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[10:11], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v3, s[2:3] offset:40
	global_load_b64 v[4:5], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v0, v0, v10
	v_and_b32_e32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, v0, 24
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[10:11]
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB0_9:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v10
	v_and_b32_e32 v6, v5, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v4, 24, v[8:9]
	v_mad_u64_u32 v[4:5], null, v6, 24, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v4
	global_load_b64 v[8:9], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_9
; %bb.10:                               ; %Flow304
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_11:                               ; %Flow306
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_12:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v8, 0
	v_readfirstlane_b32 s4, v0
	v_readfirstlane_b32 s5, v1
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[9:10], v8, s[2:3] offset:40
	global_load_b128 v[3:6], v8, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v9
	v_readfirstlane_b32 s7, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v8
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v4, vcc_lo
	v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
	global_store_b128 v[0:1], v[9:12], off offset:8
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[7:8]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v5, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	v_dual_mov_b32 v7, 33 :: v_dual_mov_b32 v10, v8
	v_mov_b32_e32 v9, v8
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
	v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
	s_clause 0x3
	global_store_b128 v[0:1], v[7:10], off
	global_store_b128 v[0:1], v[11:14], off offset:16
	global_store_b128 v[0:1], v[11:14], off offset:32
	global_store_b128 v[0:1], v[11:14], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_22
; %bb.15:
	v_mov_b32_e32 v11, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
	global_load_b64 v[5:6], v11, s[2:3] offset:40
	v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, s5, v6
	v_and_b32_e32 v5, s4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v6, 24
	v_mul_hi_u32 v7, v5, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_add_co_u32 v9, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
	global_store_b64 v[9:10], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[7:8], v[14:15]
	s_cbranch_execz .LBB0_18
; %bb.16:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB0_17:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5
	s_sleep 1
	global_store_b64 v[9:10], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
	v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_17
.LBB0_18:                               ; %Flow302
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v8, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v7, s10, 0
	global_load_b64 v[5:6], v8, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB0_20
; %bb.19:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v7, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[5:6], v[7:8], off offset:8
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[5:6], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_22
; %bb.21:
	global_load_b32 v5, v[5:6], off offset:24
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_22:                               ; %Flow303
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v3, vcc_lo, v3, s9
	v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_23:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=1
	global_load_b32 v5, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_25:                               ;   in Loop: Header=BB0_23 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_23 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_28
.LBB0_27:                               ;   in Loop: Header=BB0_23 Depth=1
	s_mov_b32 s1, -1
.LBB0_28:                               ; %Flow297
                                        ;   in Loop: Header=BB0_23 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_23
; %bb.29:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_33
; %bb.30:
	v_mov_b32_e32 v9, 0
	s_clause 0x2
	global_load_b64 v[5:6], v9, s[2:3] offset:40
	global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
	global_load_b64 v[7:8], v9, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v12, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v12, s4
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
	v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
	v_and_b32_e32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v3, v5
	v_mul_lo_u32 v6, v6, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v12, v5, 24
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v6, v12, v6
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v7, v5
	v_mov_b32_e32 v5, v10
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_mov_b32_e32 v6, v11
	global_store_b64 v[7:8], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_33
; %bb.31:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_32:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[7:8], v[5:6], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
	v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_32
.LBB0_33:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_mov_b32 s0, -1
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB0_119
; %bb.34:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v8, v1 :: v_dual_and_b32 v7, -3, v0
	v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v5, 2
	v_mov_b32_e32 v6, 1
	s_mov_b64 s[6:7], 23
.LBB0_35:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_38 Depth 2
                                        ;     Child Loop BB0_45 Depth 2
                                        ;     Child Loop BB0_53 Depth 2
                                        ;     Child Loop BB0_61 Depth 2
                                        ;     Child Loop BB0_69 Depth 2
                                        ;     Child Loop BB0_77 Depth 2
                                        ;     Child Loop BB0_85 Depth 2
                                        ;     Child Loop BB0_93 Depth 2
                                        ;     Child Loop BB0_101 Depth 2
                                        ;     Child Loop BB0_107 Depth 2
                                        ;     Child Loop BB0_116 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_40
; %bb.36:                               ;   in Loop: Header=BB0_35 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_39
; %bb.37:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB0_38:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v3, v28, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v9, v3, v9
	v_or_b32_e32 v10, v4, v10
	s_cbranch_scc1 .LBB0_38
.LBB0_39:                               ; %Flow272
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB0_40:                               ; %Flow274
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[9:10], v28, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB0_42:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_47
; %bb.43:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v11, 0
	v_mov_b32_e32 v12, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_46
; %bb.44:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_45:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v11, v3, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v12, v4, v12
	s_cbranch_scc1 .LBB0_45
.LBB0_46:                               ; %Flow267
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_48
.LBB0_47:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $sgpr14
.LBB0_48:                               ; %Flow269
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[11:12], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_50:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_55
; %bb.51:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v13, 0
	v_mov_b32_e32 v14, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_54
; %bb.52:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_53:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v13, v3, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v14, v4, v14
	s_cbranch_scc1 .LBB0_53
.LBB0_54:                               ; %Flow262
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_56
.LBB0_55:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_56:                               ; %Flow264
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[13:14], v28, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_58:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_63
; %bb.59:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_62
; %bb.60:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_61:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v15, v3, v15
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v16, v4, v16
	s_cbranch_scc1 .LBB0_61
.LBB0_62:                               ; %Flow257
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_64
.LBB0_63:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr14
.LBB0_64:                               ; %Flow259
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[15:16], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_66:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_71
; %bb.67:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_70
; %bb.68:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_69:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v17, v3, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v4, v18
	s_cbranch_scc1 .LBB0_69
.LBB0_70:                               ; %Flow252
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB0_72
.LBB0_71:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB0_72:                               ; %Flow254
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[17:18], v28, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_74:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB0_79
; %bb.75:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB0_78
; %bb.76:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB0_77:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v3, v28, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v19, v3, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v4, v20
	s_cbranch_scc1 .LBB0_77
.LBB0_78:                               ; %Flow247
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr19_vgpr20
                                        ; implicit-def: $sgpr14
.LBB0_80:                               ; %Flow249
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[19:20], v28, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_82:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_87
; %bb.83:                               ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_86
; %bb.84:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB0_85:                               ; %.preheader.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v3, v28, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v27, 0xffff, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s10, v[27:28]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v21, v3, v21
	v_or_b32_e32 v22, v4, v22
	s_cbranch_scc1 .LBB0_85
.LBB0_86:                               ; %Flow242
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB0_88
.LBB0_87:                               ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s10, -1
.LBB0_88:                               ; %Flow244
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB0_90
; %bb.89:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[21:22], v28, s[0:1]
.LBB0_90:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	v_mov_b32_e32 v27, v2
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v27
	v_cmp_eq_u32_e64 s0, s0, v27
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_96
; %bb.91:                               ;   in Loop: Header=BB0_35 Depth=1
	global_load_b64 v[25:26], v28, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v28, s[2:3] offset:40
	global_load_b64 v[23:24], v28, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v26
	v_and_b32_e32 v3, v3, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v29, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v29, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v23, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v24, v4, vcc_lo
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[25:26]
	s_cbranch_execz .LBB0_95
; %bb.92:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s11, 0
.LBB0_93:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[23:24], v28, s[2:3] offset:40
	global_load_b64 v[29:30], v28, s[2:3]
	v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v25, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v23, v23, v25
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v23, 24, v[29:30]
	v_and_b32_e32 v29, v24, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, v29, 24, v[4:5]
	v_mov_b32_e32 v4, v23
	global_load_b64 v[23:24], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[25:26]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_93
; %bb.94:                               ; %Flow237
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB0_95:                               ; %Flow239
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_96:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[29:30], v28, s[2:3] offset:40
	global_load_b128 v[23:26], v28, s[2:3]
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v29
	v_readfirstlane_b32 s13, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_35 Depth=1
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, v28
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v29, vcc_lo, v23, s15
	v_add_co_ci_u32_e32 v30, vcc_lo, s16, v24, vcc_lo
	global_store_b128 v[29:30], v[3:6], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v3, 2, v7
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_cndmask_b32_e32 v7, v3, v7, vcc_lo
	v_lshlrev_b64 v[3:4], 6, v[27:28]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v25, vcc_lo, v25, s12
	v_add_co_ci_u32_e32 v26, vcc_lo, s13, v26, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v25, v3
	v_and_or_b32 v7, 0xffffff1f, v7, s16
	v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[11:14], off offset:16
	global_store_b128 v[3:4], v[15:18], off offset:32
	global_store_b128 v[3:4], v[19:22], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_106
; %bb.99:                               ;   in Loop: Header=BB0_35 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v28, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v28, s[2:3] offset:40
	v_dual_mov_b32 v13, s10 :: v_dual_mov_b32 v14, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v7
	v_readfirstlane_b32 s17, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v11, vcc_lo, v23, s16
	v_add_co_ci_u32_e32 v12, vcc_lo, s17, v24, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[11:12], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v28, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB0_102
; %bb.100:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s16, 0
.LBB0_101:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
	s_sleep 1
	global_store_b64 v[11:12], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v28, v[7:10], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_101
.LBB0_102:                              ; %Flow235
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[7:8], v28, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v9, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v9
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_35 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v27, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[27:28], off offset:8
.LBB0_104:                              ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[9:10], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	s_cbranch_vccnz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_35 Depth=1
	global_load_b32 v27, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v27
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[9:10], v[27:28], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_106:                              ; %Flow236
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v7, vcc_lo, v23, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_107:                              ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v9, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_107 Depth=2
	global_load_b32 v9, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v9, 1, v9
.LBB0_109:                              ;   in Loop: Header=BB0_107 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v9
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_107 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_112
.LBB0_111:                              ;   in Loop: Header=BB0_107 Depth=2
	s_mov_b32 s1, -1
.LBB0_112:                              ; %Flow230
                                        ;   in Loop: Header=BB0_107 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_107
; %bb.113:                              ;   in Loop: Header=BB0_35 Depth=1
	global_load_b128 v[7:10], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_117
; %bb.114:                              ;   in Loop: Header=BB0_35 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v28, s[2:3] offset:40
	global_load_b64 v[13:14], v28, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v28, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
	v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
	v_and_b32_e32 v4, v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v9, v3
	v_mul_hi_u32 v15, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v11, v3
	v_mov_b32_e32 v11, v13
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v4, v15, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v12, v14
	global_store_b64 v[3:4], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v28, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_117
; %bb.115:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_mov_b32 s0, 0
.LBB0_116:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v28, v[9:12], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
	v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_116
.LBB0_117:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_35 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_eq_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_35
; %bb.118:                              ; %Flow275
	s_mov_b32 s0, 0
.LBB0_119:                              ; %Flow291
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_147
; %bb.120:
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_126
; %bb.121:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[8:9], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_125
; %bb.122:                              ; %.preheader3.i.i.i25.preheader
	s_mov_b32 s5, 0
.LBB0_123:                              ; %.preheader3.i.i.i25
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[2:3] offset:40
	global_load_b64 v[10:11], v3, s[2:3]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB0_123
; %bb.124:                              ; %Flow288
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_125:                              ; %Flow290
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_126:                              ; %.loopexit4.i.i.i20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[2:3] offset:40
	global_load_b128 v[4:7], v3, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_128
; %bb.127:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_128:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v9, s15
	v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB0_136
; %bb.129:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v6, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_132
; %bb.130:                              ; %.preheader1.i.i.i23.preheader
	s_mov_b32 s10, 0
.LBB0_131:                              ; %.preheader1.i.i.i23
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_131
.LBB0_132:                              ; %Flow286
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_134
; %bb.133:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_134:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_136
; %bb.135:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_136:                              ; %Flow287
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_137:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_139
; %bb.138:                              ;   in Loop: Header=BB0_137 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_139:                              ;   in Loop: Header=BB0_137 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_141
; %bb.140:                              ;   in Loop: Header=BB0_137 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_142
.LBB0_141:                              ;   in Loop: Header=BB0_137 Depth=1
	s_mov_b32 s1, -1
.LBB0_142:                              ; %Flow281
                                        ;   in Loop: Header=BB0_137 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_137
; %bb.143:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_147
; %bb.144:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_147
; %bb.145:                              ; %.preheader.i.i.i22.preheader
	s_mov_b32 s0, 0
.LBB0_146:                              ; %.preheader.i.i.i22
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_146
.LBB0_147:                              ; %__ockl_printf_append_string_n.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7matVectPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7matVectPfS_S_i, .Lfunc_end0-_Z7matVectPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5532
; NumSgprs: 20
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"ERREUR - Index > size\n"
	.size	.str, 23

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         112
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7matVectPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z7matVectPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
