#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768

//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{	
	int tid = threadIdx.x;
	for(int j = 0; j < unsize; j++){
		if (j == 0){
			out_array[tid * unsize] = in_array[tid * unsize];
		} else {
			for(int k = 0; k <= j; k++) {
				out_array[tid * unsize + j] += in_array[tid * unsize + k];
			}
		}
	}
}

//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
	int tid = threadIdx.x;
	if (tid <= maxid) {
		int maxstep = unsize * (int)(powf(2, idx - 1));
		for(int j = 0; j < maxstep; j++) {
			int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
			in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
		}		
	}
	
	
}

void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
	int *array_d;
	int *tmp_one;
	int unsize = size/(blocks * threads);
	
	
	dim3 dim_grid(blocks, 1, 1);
	dim3 dim_block(threads, 1, 1);

	// allocate tmp_d
	cudaMalloc((void **)&tmp_one, size * sizeof(int));
	//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
	cudaMalloc((void **)&array_d, size * sizeof(int));
	//copy data from host to device
	cudaMemcpy(array_d, array_h, size * sizeof(int),
		   cudaMemcpyHostToDevice);
	
	cudaMemset(tmp_one, 0, size * sizeof(int));
	//do stage 1
	prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
	
	if (steps !=0) {
		int maxtid = 0;
		//do stage 2
		for (int i = 1; i <= steps; i++) {
			maxtid = (int)pow(2, steps-i) - 1;
			prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
		}
	}
	
		cudaMemcpy(array_h, tmp_one, size * sizeof(int), cudaMemcpyDeviceToHost);
	
	cudaFree(array_d);
	cudaFree(tmp_one);
}



void prepare_numbers(int **array, int count)
{
	int *numbers = (int *)malloc(count * sizeof(int));

	// load array
	for (int i = 0; i < count; i++) {
		numbers[i] = 1;
	}

	*array = numbers;
}

void print_array(int *array, int count)
{
	for (int i = 0; i < count; i++) {
		printf("%d\t", array[i]);
	}
	printf("\n");
}

int main()
{
	int blocks, threads, max, stepTwo;
	int *array;
    float calTime;
	cudaEvent_t start, end;
	cudaEventCreate(&start);
	cudaEventCreate(&end);

	blocks = NUM_BLOCKS;
	threads = BLOCK_SIZE;
	stepTwo = 8;
	max = NUM_MEM;

	// pre-init numbers
	array = NULL;
	prepare_numbers(&array, max);

	cudaEventRecord(start, 0);
	prefixsum(blocks, threads, stepTwo, array, max);
	cudaEventRecord(end, 0);
	cudaEventSynchronize(end);
	cudaEventElapsedTime(&calTime, start, end);

	// print array
//	print_array(array, max);
	printf("the elapsed time with %d threads is %.10f\n", threads, calTime);

	free(array);

	return 0;
}

	.file	"tmpxft_002263de_00000000-6_prefix.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2046:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2046:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15prepare_numbersPPii
	.type	_Z15prepare_numbersPPii, @function
_Z15prepare_numbersPPii:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	movslq	%esi, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	salq	$2, %rdi
	pushq	%rdx
	.cfi_def_cfa_offset 32
	call	malloc@PLT
	xorl	%edx, %edx
.L3:
	cmpl	%edx, %ebx
	jle	.L7
	movl	$1, (%rax,%rdx,4)
	incq	%rdx
	jmp	.L3
.L7:
	movq	%rax, 0(%rbp)
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z15prepare_numbersPPii, .-_Z15prepare_numbersPPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d\t"
.LC1:
	.string	"\n"
	.text
	.globl	_Z11print_arrayPii
	.type	_Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
.L9:
	cmpl	%ebx, %ebp
	jle	.L12
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L9
.L12:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC1(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2042:
	.size	_Z11print_arrayPii, .-_Z11print_arrayPii
	.globl	_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
	.type	_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, @function
_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9prefixOnePiS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, .-_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
	.globl	_Z9prefixOnePiS_ii
	.type	_Z9prefixOnePiS_ii, @function
_Z9prefixOnePiS_ii:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
	.cfi_endproc
.LFE2069:
	.size	_Z9prefixOnePiS_ii, .-_Z9prefixOnePiS_ii
	.globl	_Z31__device_stub__Z9prefixTwoPiiiiPiiii
	.type	_Z31__device_stub__Z9prefixTwoPiiiiPiiii, @function
_Z31__device_stub__Z9prefixTwoPiiiiPiiii:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9prefixTwoPiiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z31__device_stub__Z9prefixTwoPiiiiPiiii, .-_Z31__device_stub__Z9prefixTwoPiiiiPiiii
	.globl	_Z9prefixTwoPiiii
	.type	_Z9prefixTwoPiiii, @function
_Z9prefixTwoPiiii:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z9prefixTwoPiiiiPiiii
	.cfi_endproc
.LFE2071:
	.size	_Z9prefixTwoPiiii, .-_Z9prefixTwoPiiii
	.globl	_Z9prefixsumiiiPii
	.type	_Z9prefixsumiiiPii, @function
_Z9prefixsumiiiPii:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rcx, %r13
	movl	%edi, %ecx
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	imull	%esi, %ecx
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movslq	%r8d, %rbx
	movq	%rbx, %rbp
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movl	%ebx, %eax
	salq	$2, %rbx
	movl	%edi, 32(%rsp)
	cltd
	movl	%esi, 44(%rsp)
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	idivl	%ecx
	movl	%eax, %r14d
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	%rax, 48(%rsp)
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movq	%rbx, %rdx
	call	cudaMemset@PLT
	movl	52(%rsp), %ecx
	movl	40(%rsp), %esi
	xorl	%r9d, %r9d
	movq	44(%rsp), %rdx
	movq	32(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r14d, %edx
	call	_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
.L24:
	testl	%r12d, %r12d
	jne	.L30
.L28:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L30:
	movl	$1, %ebp
.L25:
	cmpl	%r12d, %ebp
	jg	.L28
	movl	%r12d, %eax
	movsd	.LC2(%rip), %xmm0
	subl	%ebp, %eax
	cvtsi2sdl	%eax, %xmm1
	call	pow@PLT
	movl	52(%rsp), %ecx
	movl	40(%rsp), %esi
	xorl	%r9d, %r9d
	movq	44(%rsp), %rdx
	movq	32(%rsp), %rdi
	xorl	%r8d, %r8d
	movsd	%xmm0, 8(%rsp)
	call	__cudaPushCallConfiguration@PLT
	movsd	8(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L26
	cvttsd2sil	%xmm0, %edx
	movq	24(%rsp), %rdi
	movl	%ebp, %ecx
	movl	%r14d, %esi
	decl	%edx
	call	_Z31__device_stub__Z9prefixTwoPiiiiPiiii
.L26:
	incl	%ebp
	jmp	.L25
.L29:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z9prefixsumiiiPii, .-_Z9prefixsumiiiPii
	.section	.rodata.str1.1
.LC3:
	.string	"the elapsed time with %d threads is %.10f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	16(%rsp), %rdi
	movl	$32768, %esi
	call	_Z15prepare_numbersPPii
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	16(%rsp), %rbx
	movl	$32768, %r8d
	movl	$8, %edx
	movl	$256, %esi
	movl	$1, %edi
	movq	%rbx, %rcx
	call	_Z9prefixsumiiiPii
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	$2, %edi
	movl	$256, %edx
	movb	$1, %al
	leaq	.LC3(%rip), %rsi
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z9prefixTwoPiiii"
.LC5:
	.string	"_Z9prefixOnePiS_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2073:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9prefixTwoPiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9prefixOnePiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2073:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1073741824
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "hip/hip_runtime.h"


#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768

//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{	
	int tid = threadIdx.x;
	for(int j = 0; j < unsize; j++){
		if (j == 0){
			out_array[tid * unsize] = in_array[tid * unsize];
		} else {
			for(int k = 0; k <= j; k++) {
				out_array[tid * unsize + j] += in_array[tid * unsize + k];
			}
		}
	}
}

//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
	int tid = threadIdx.x;
	if (tid <= maxid) {
		int maxstep = unsize * (int)(powf(2, idx - 1));
		for(int j = 0; j < maxstep; j++) {
			int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
			in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
		}		
	}
	
	
}

void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
	int *array_d;
	int *tmp_one;
	int unsize = size/(blocks * threads);
	
	
	dim3 dim_grid(blocks, 1, 1);
	dim3 dim_block(threads, 1, 1);

	// allocate tmp_d
	hipMalloc((void **)&tmp_one, size * sizeof(int));
	//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
	hipMalloc((void **)&array_d, size * sizeof(int));
	//copy data from host to device
	hipMemcpy(array_d, array_h, size * sizeof(int),
		   hipMemcpyHostToDevice);
	
	hipMemset(tmp_one, 0, size * sizeof(int));
	//do stage 1
	prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
	
	if (steps !=0) {
		int maxtid = 0;
		//do stage 2
		for (int i = 1; i <= steps; i++) {
			maxtid = (int)pow(2, steps-i) - 1;
			prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
		}
	}
	
		hipMemcpy(array_h, tmp_one, size * sizeof(int), hipMemcpyDeviceToHost);
	
	hipFree(array_d);
	hipFree(tmp_one);
}



void prepare_numbers(int **array, int count)
{
	int *numbers = (int *)malloc(count * sizeof(int));

	// load array
	for (int i = 0; i < count; i++) {
		numbers[i] = 1;
	}

	*array = numbers;
}

void print_array(int *array, int count)
{
	for (int i = 0; i < count; i++) {
		printf("%d\t", array[i]);
	}
	printf("\n");
}

int main()
{
	int blocks, threads, max, stepTwo;
	int *array;
    float calTime;
	hipEvent_t start, end;
	hipEventCreate(&start);
	hipEventCreate(&end);

	blocks = NUM_BLOCKS;
	threads = BLOCK_SIZE;
	stepTwo = 8;
	max = NUM_MEM;

	// pre-init numbers
	array = NULL;
	prepare_numbers(&array, max);

	hipEventRecord(start, 0);
	prefixsum(blocks, threads, stepTwo, array, max);
	hipEventRecord(end, 0);
	hipEventSynchronize(end);
	hipEventElapsedTime(&calTime, start, end);

	// print array
//	print_array(array, max);
	printf("the elapsed time with %d threads is %.10f\n", threads, calTime);

	free(array);

	return 0;
}

	.text
	.file	"prefix.hip"
	.globl	_Z24__device_stub__prefixOnePiS_ii # -- Begin function _Z24__device_stub__prefixOnePiS_ii
	.type	_Z24__device_stub__prefixOnePiS_ii,@function
_Z24__device_stub__prefixOnePiS_ii:     # @_Z24__device_stub__prefixOnePiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9prefixOnePiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__prefixOnePiS_ii, .Lfunc_end0-_Z24__device_stub__prefixOnePiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__prefixTwoPiiii # -- Begin function _Z24__device_stub__prefixTwoPiiii
	.type	_Z24__device_stub__prefixTwoPiiii,@function
_Z24__device_stub__prefixTwoPiiii:      # @_Z24__device_stub__prefixTwoPiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9prefixTwoPiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__prefixTwoPiiii, .Lfunc_end1-_Z24__device_stub__prefixTwoPiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9prefixsumiiiPii
.LCPI2_0:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z9prefixsumiiiPii
	.type	_Z9prefixsumiiiPii,@function
_Z9prefixsumiiiPii:                     # @_Z9prefixsumiiiPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movl	%edx, %ebp
	movl	%esi, %r14d
	imull	%edi, %esi
	movl	%r8d, %eax
	cltd
	idivl	%esi
	movl	%eax, %r15d
	movl	%edi, %r13d
	btsq	$32, %r13
	btsq	$32, %r14
	movl	%r8d, 16(%rsp)                  # 4-byte Spill
	movslq	%r8d, %r12
	shlq	$2, %r12
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	hipMemset
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	32(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	16(%rsp), %ecx                  # 4-byte Reload
	callq	_Z24__device_stub__prefixOnePiS_ii
.LBB2_2:
	testl	%ebp, %ebp
	jle	.LBB2_7
# %bb.3:                                # %.lr.ph.preheader
	decl	%ebp
	movl	$1, %ebx
.LBB2_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movsd	.LCPI2_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movl	%ebp, %edi
	callq	ldexp@PLT
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_6
# %bb.5:                                #   in Loop: Header=BB2_4 Depth=1
	cvttsd2si	16(%rsp), %edx          # 8-byte Folded Reload
	decl	%edx
	movq	8(%rsp), %rdi
	movl	%r15d, %esi
	movl	%ebx, %ecx
	callq	_Z24__device_stub__prefixTwoPiiii
.LBB2_6:                                #   in Loop: Header=BB2_4 Depth=1
	incl	%ebx
	addl	$-1, %ebp
	jb	.LBB2_4
.LBB2_7:                                # %.loopexit
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z9prefixsumiiiPii, .Lfunc_end2-_Z9prefixsumiiiPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15prepare_numbersPPii         # -- Begin function _Z15prepare_numbersPPii
	.type	_Z15prepare_numbersPPii,@function
_Z15prepare_numbersPPii:                # @_Z15prepare_numbersPPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movslq	%esi, %r14
	leaq	(,%r14,4), %rdi
	callq	malloc
	testl	%r14d, %r14d
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %ecx
	xorl	%edx, %edx
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, (%rax,%rdx,4)
	incq	%rdx
	cmpq	%rdx, %rcx
	jne	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movq	%rax, (%rbx)
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z15prepare_numbersPPii, .Lfunc_end3-_Z15prepare_numbersPPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11print_arrayPii              # -- Begin function _Z11print_arrayPii
	.type	_Z11print_arrayPii,@function
_Z11print_arrayPii:                     # @_Z11print_arrayPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB4_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	%esi, %r14d
	xorl	%r15d, %r15d
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB4_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB4_4:                                # %._crit_edge
	movl	$10, %edi
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end4:
	.size	_Z11print_arrayPii, .Lfunc_end4-_Z11print_arrayPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movl	$131072, %edi                   # imm = 0x20000
	callq	malloc
	movq	%rax, %rbx
	xorl	%eax, %eax
.LBB5_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, (%rbx,%rax,4)
	incq	%rax
	cmpq	$32768, %rax                    # imm = 0x8000
	jne	.LBB5_1
# %bb.2:                                # %_Z15prepare_numbersPPii.exit
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$1, %edi
	movl	$256, %esi                      # imm = 0x100
	movl	$8, %edx
	movq	%rbx, %rcx
	movl	$32768, %r8d                    # imm = 0x8000
	callq	_Z9prefixsumiiiPii
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	20(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r14), %xmm0
	movl	$.L.str.2, %edi
	movl	$256, %esi                      # imm = 0x100
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9prefixOnePiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9prefixTwoPiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9prefixOnePiS_ii,@object      # @_Z9prefixOnePiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9prefixOnePiS_ii
	.p2align	3, 0x0
_Z9prefixOnePiS_ii:
	.quad	_Z24__device_stub__prefixOnePiS_ii
	.size	_Z9prefixOnePiS_ii, 8

	.type	_Z9prefixTwoPiiii,@object       # @_Z9prefixTwoPiiii
	.globl	_Z9prefixTwoPiiii
	.p2align	3, 0x0
_Z9prefixTwoPiiii:
	.quad	_Z24__device_stub__prefixTwoPiiii
	.size	_Z9prefixTwoPiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d\t"
	.size	.L.str, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"the elapsed time with %d threads is %.10f\n"
	.size	.L.str.2, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9prefixOnePiS_ii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9prefixTwoPiiii"
	.size	.L__unnamed_2, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__prefixOnePiS_ii
	.addrsig_sym _Z24__device_stub__prefixTwoPiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9prefixOnePiS_ii
	.addrsig_sym _Z9prefixTwoPiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9prefixOnePiS_ii      ; -- Begin function _Z9prefixOnePiS_ii
	.globl	_Z9prefixOnePiS_ii
	.p2align	8
	.type	_Z9prefixOnePiS_ii,@function
_Z9prefixOnePiS_ii:                     ; @_Z9prefixOnePiS_ii
; %bb.0:
	s_load_b32 s4, s[0:1], 0x10
	s_mov_b32 s5, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, 1
	s_cbranch_scc1 .LBB0_9
; %bb.1:                                ; %.lr.ph
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v2, v0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v3, v1
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_mov_b32 s0, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_mov_b32 s1, -1
	s_cbranch_scc1 .LBB0_6
; %bb.3:                                ; %.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v0, s0, v2
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
	s_mov_b32 s1, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[0:1]
	v_add_co_u32 v7, vcc_lo, s2, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b32 v0, v[7:8], off
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v11, v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v0, v11
	global_store_b32 v[7:8], v0, off
	s_cbranch_scc1 .LBB0_4
; %bb.5:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s1, 0
.LBB0_6:                                ; %Flow36
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v0, off
.LBB0_8:                                ; %.loopexit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s0, s0, 1
	s_add_i32 s5, s5, 1
	s_cmp_eq_u32 s0, s4
	s_cbranch_scc0 .LBB0_2
.LBB0_9:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9prefixOnePiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 6
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9prefixOnePiS_ii, .Lfunc_end0-_Z9prefixOnePiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 8
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9prefixTwoPiiii       ; -- Begin function _Z9prefixTwoPiiii
	.globl	_Z9prefixTwoPiiii
	.p2align	8
	.type	_Z9prefixTwoPiiii,@function
_Z9prefixTwoPiiii:                      ; @_Z9prefixTwoPiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_ge_i32_e64 s5, v0
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_add_i32 s2, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s3, -1, 0
	v_cndmask_b32_e64 v1, 2.0, 1.0, s3
	s_mov_b32 s3, 0x3e76c4e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v1, v1
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_ldexp_f32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v1, v1
	v_add_f32_e32 v5, -1.0, v2
	v_add_f32_e32 v3, 1.0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v6, v5, v4 :: v_dual_add_f32 v7, -1.0, v3
	v_mul_f32_e32 v8, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, v2, v7
	v_fma_f32 v3, v6, v3, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v6, v2
	v_add_f32_e32 v2, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v8, v2, v8
	v_sub_f32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v7
	v_sub_f32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v2
	v_add_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v4, v2
	v_add_f32_e32 v3, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v3, v3
	v_sub_f32_e32 v4, v3, v6
	v_sub_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v3, v3, -v5
	v_add_f32_e32 v6, v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v3, v6
	v_add_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v7, s3, v6, 0x3e91f4c4
	v_sub_f32_e32 v5, v6, v5
	v_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_sub_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v6, v7
	v_fma_f32 v5, v6, v7, -v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v5, v4, v7 :: v_dual_mul_f32 v10, v3, v6
	v_add_f32_e32 v7, v8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v6, v3, -v10
	v_dual_sub_f32 v8, v7, v8 :: v_dual_fmac_f32 v11, v6, v2
	v_add_f32_e32 v9, 0x3f2aaaaa, v7
	v_ldexp_f32 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v5, v5, v8
	v_fmac_f32_e32 v11, v4, v3
	v_ldexp_f32 v3, v3, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 0x31739010, v5
	v_add_f32_e32 v8, 0xbf2aaaaa, v9
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v7
	v_add_f32_e32 v4, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v10, v11 :: v_dual_sub_f32 v7, v9, v4
	v_mul_f32_e32 v8, v6, v4
	v_sub_f32_e32 v9, v6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, v5, v7
	v_fma_f32 v7, v6, v4, -v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v11, v9
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v9, v4
	v_add_f32_e32 v4, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v6, v4, v8
	v_mul_f32_e32 v8, 0x3f317218, v1
	v_sub_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3f317218, v1, -v8
	v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v5, v3
	v_sub_f32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, v2, v3
	v_add_f32_e32 v4, v5, v2
	v_fmamk_f32 v1, v1, 0xb102e308, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v4, v5
	v_sub_f32_e32 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v1
	v_add_f32_e32 v6, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v3, v8 :: v_dual_sub_f32 v7, v6, v3
	v_dual_sub_f32 v1, v1, v8 :: v_dual_sub_f32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v1, v2
	v_sub_f32_e32 v9, v6, v7
	v_sub_f32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v3, v4, v3 :: v_dual_sub_f32 v4, v5, v1
	v_add_f32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v5, v4
	v_sub_f32_e32 v2, v2, v4
	v_add_f32_e32 v7, v6, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v4, v7, v6
	v_dual_add_f32 v1, v2, v1 :: v_dual_sub_f32 v2, v3, v4
	v_cvt_f32_i32_e32 v3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_add_f32_e32 v2, v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v2, v7
	v_mul_f32_e32 v5, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v1, v4
	v_fma_f32 v2, v3, v2, -v5
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v1
	v_add_f32_e32 v1, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v1, v5, vcc_lo
	v_sub_f32_e32 v1, v1, v5
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v1, v2, v1
	v_cndmask_b32_e64 v4, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_dual_sub_f32 v6, v3, v4 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v7, 0x3fb8aa3b, v6
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v6
	v_add_f32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v8, 0x3fb8aa3b, v6, -v7
	v_rndne_f32_e32 v9, v7
	v_dual_fmamk_f32 v8, v6, 0x32a5705f, v8 :: v_dual_sub_f32 v7, v7, v9
	v_cvt_i32_f32_e32 v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v7, v8
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v2, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v6
	v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, v2, v1, v2
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e64 v1, |v1|
	v_readfirstlane_b32 s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s2, s4
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshl_or_b32 v0, v0, 1, 1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, s2, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[0:1], off offset:-4
	global_load_b32 v5, v[2:3], off
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, v5, v4
	global_store_b32 v[2:3], v4, off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc1 .LBB1_3
.LBB1_4:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9prefixTwoPiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 8
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9prefixTwoPiiii, .Lfunc_end1-_Z9prefixTwoPiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1104
; NumSgprs: 10
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9prefixOnePiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     8
    .sgpr_spill_count: 0
    .symbol:         _Z9prefixOnePiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9prefixTwoPiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     10
    .sgpr_spill_count: 0
    .symbol:         _Z9prefixTwoPiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
