#include<cstdio>
#define S 64
#define ZERO 0
#define PI 3.14159265
#define LOW 9
#define HIGH 18
#define QUEUE_SIZE 128
#define KERNEL_RADIUS 8

extern "C" {
__device__
bool btwn(int a, int x, int y){
	return (a>=x && a<y);
}

__device__
void load_to_shared(int* src, int cache[][S], int th_x, int th_y, int n, int m){
	int val, pos, ind_x, ind_y;
	if(threadIdx.x==0 && threadIdx.y==0){
		ind_x = th_x-1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x] = val;
	}
	
	if(threadIdx.x==0 && threadIdx.y==31){
		ind_x = th_x-1; ind_y = th_y+1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x] = val;
	}
	
	if(threadIdx.x==31 && threadIdx.y==0){
		ind_x = th_x+1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x+2] = val;
	}
	
	if(threadIdx.x==31 && threadIdx.y==31){
		ind_x = th_x+1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x+2] = val;
	}

	if(threadIdx.y==0){
		ind_x = th_x; ind_y = th_y-1; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x+1] = val;
	}

	if(threadIdx.y==31){
		ind_x = th_x; ind_y = th_y+1; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x+1] = val;
	}
	
	if(threadIdx.x==0){
		ind_x = th_x-1; ind_y = th_y; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
	 	cache[threadIdx.y+1][threadIdx.x] = val;
	}

	if(threadIdx.x==31){
		ind_x = th_x+1; ind_y = th_y; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
	 	cache[threadIdx.y+1][threadIdx.x+2] = val;
	}
}

__global__
void sobel(int* src, int* dstMagni, float * arcTangensOut){
	__shared__ int cache[34][S];
	int m = gridDim.x*32, n = gridDim.y*32, 
	th_x = blockIdx.x * 32 + threadIdx.x, 
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x, ind_x, ind_y,
	magn_x, magn_y, magnAbs_x, magnAbs_y;

	/*now we load to shared with a frame of thickness eq 1*/
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	load_to_shared(src, cache, th_x, th_y, n, m);

	ind_y = threadIdx.y+1; 
	ind_x = threadIdx.x+1; 
	__syncthreads();
	magn_x = cache[ind_y][ind_x-1] - cache[ind_y][ind_x+1];
	magnAbs_x = ((magn_x>0) ? magn_x : -magn_x);
	magn_y = cache[ind_y+1][ind_x] - cache[ind_y-1][ind_x];
	magnAbs_y = ((magn_y>0) ? magn_y : -magn_y);
	dstMagni[i_src] = magnAbs_x + magnAbs_y;
	arcTangensOut[i_src] = atan2((float) magn_y,(float) magn_x)
										* 180 / PI;
}

__global__
void nonMaximalSupression(int * magn, float * arcTangens, int * dest) {
	__shared__ int cacheMagn[34][S];
	int m = gridDim.x*32, n = gridDim.y*32,
	th_x = blockIdx.x * 32 + threadIdx.x, 
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x, ind_x, ind_y;
	float angle;

	cacheMagn[threadIdx.y+1][threadIdx.x+1] = magn[i_src];
	load_to_shared(magn, cacheMagn, th_x, th_y, n, m);

	ind_y = threadIdx.y+1; ind_x = threadIdx.x+1; 
	__syncthreads();
   angle = arcTangens[i_src];
    if (angle < 0) angle = 360 + angle;
    
    //north && south
    int centerCell = cacheMagn[ind_y][ind_x];
    dest[i_src] = centerCell;
    if ((337.5 <= angle || angle < 22.5) || 
            (157.25 <= angle && angle < 202.5)) {
        if (cacheMagn[ind_y][ind_x+1] > centerCell ||
                cacheMagn[ind_y][ind_x-1] > centerCell) 
                    dest[i_src] = 0;
    } // north-east && south-west 
    else if ((22.5 <= angle && angle < 67.5) ||
            (202.5 <= angle && angle < 247.5)) {
        if (cacheMagn[ind_y-1][ind_x+1] > centerCell || 
                cacheMagn[ind_y+1][ind_x-1] > centerCell) 
                    dest[i_src] = 0;
    } // west && east
    else if ((67.5 <= angle && angle < 112.5) ||
                (247.5 <= angle && angle < 292.5)) {
        if (cacheMagn[ind_y+1][ind_x] > centerCell ||
                cacheMagn[ind_y-1][ind_x] > centerCell) 
                    dest[i_src] = 0;
    } // west-north && east-south
    else if ((112.5 <= angle && angle < 157.5) ||
        (292.5 <= angle || angle < 337.5)) {
        if (cacheMagn[ind_y-1][ind_x-1] > centerCell || 
                cacheMagn[ind_y+1][ind_x+1] > centerCell) 
                    dest[i_src] = 0;
    }

}	

__global__
void prepareBfs(int* src){
	int m = gridDim.x*32;
	int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int val = src[i_src];
	if(val < LOW){
		src[i_src] = 0;
	}
	else if(val >= HIGH){
		src[i_src] = -2;
	}
	else{
		src[i_src] = -1;
	}

}
__global__
void oneBfs(int* src, int* dst, int* changed){
	__shared__ int cache[34][S];
	int m = gridDim.x*32, n = gridDim.y*32,
	th_x = blockIdx.x * 32 + threadIdx.x,
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x,
	ind_y = threadIdx.y+1, ind_x = threadIdx.x+1,
	queue[QUEUE_SIZE],
	beg=0, end=0, val,
	procInd_x, procInd_y, x_new, y_new;
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	val = cache[ind_y][ind_x];
	load_to_shared(src, cache, th_x, th_y, n, m);
	__syncthreads();
	
	if(val==-1){
		for(int i=-1; i<2; ++i){
			for(int j=-1; j<2; ++j){
				procInd_x = ind_x+i;
				procInd_y = ind_y+j;
				if(cache[procInd_y][procInd_x]==-2){
					queue[end++] = ind_y;
					queue[end++] = ind_x;
					cache[ind_y][ind_x]=-2;
					*changed=1;
					i=2;
					j=2;
				}
			}
		}
	}
	

	while(beg!=end){
		procInd_y = queue[beg++];
		procInd_x = queue[beg++];
		for(int i=-1; i<2; ++i){
			for(int j=-1; j<2; ++j){
				x_new = procInd_x+i;
				y_new = procInd_y+j;
				if(cache[y_new][x_new]==-1 && btwn(y_new, 1, 33) 
											&& btwn(x_new, 1, 33)){
					queue[end++] = y_new;
					queue[end++] = x_new;
					cache[y_new][x_new]=-2;
				}
			}
		}
	}
	__syncthreads();
	dst[i_src] = cache[ind_y][ind_x];
	
}
__global__ 
void final_battle(int* src){
	int m = gridDim.x*32;
    int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int val = src[i_src];
	if(val==-2){
		src[i_src] = 255;
	}
	else{
		src[i_src] = 0;
	}
}

__global__
void gaussianFilter(int * src, int * dest) {
    __shared__ int cache[34][S];
    int n = gridDim.y*32;
    int m = gridDim.x*32;
    int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int ind_y, ind_x;
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	load_to_shared(src, cache, th_x, th_y, n, m);

    ind_y = threadIdx.y+1+KERNEL_RADIUS; ind_x = threadIdx.x+1+KERNEL_RADIUS;
	__syncthreads();

    int sum = 0;
    for (int i = -KERNEL_RADIUS; i <= KERNEL_RADIUS; i++) {
        for (int j = -KERNEL_RADIUS; j <= KERNEL_RADIUS; j++) {
            sum += cache[ind_y+i][ind_x+j]; //d_kernel[KERNEL_RADIUS + j]
        }
    }
    dest[i_src] = (int) sum;
}

}

	.file	"tmpxft_0039e950_00000000-6_cudaStaff.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	btwn
	.type	btwn, @function
btwn:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	btwn, .-btwn
	.globl	load_to_shared
	.type	load_to_shared, @function
load_to_shared:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	load_to_shared, .-load_to_shared
	.globl	_Z28__device_stub__Z5sobelPiS_PfPiS_Pf
	.type	_Z28__device_stub__Z5sobelPiS_PfPiS_Pf, @function
_Z28__device_stub__Z5sobelPiS_PfPiS_Pf:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	sobel(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z28__device_stub__Z5sobelPiS_PfPiS_Pf, .-_Z28__device_stub__Z5sobelPiS_PfPiS_Pf
	.globl	sobel
	.type	sobel, @function
sobel:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5sobelPiS_PfPiS_Pf
	.cfi_endproc
.LFE2054:
	.size	sobel, .-sobel
	.globl	_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_
	.type	_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_, @function
_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	nonMaximalSupression(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L12:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_, .-_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_
	.globl	nonMaximalSupression
	.type	nonMaximalSupression, @function
nonMaximalSupression:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z20nonMaximalSupressionPiPfS_PiPfS_
	.cfi_endproc
.LFE2056:
	.size	nonMaximalSupression, .-nonMaximalSupression
	.globl	_Z30__device_stub__Z10prepareBfsPiPi
	.type	_Z30__device_stub__Z10prepareBfsPiPi, @function
_Z30__device_stub__Z10prepareBfsPiPi:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	prepareBfs(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L17:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z30__device_stub__Z10prepareBfsPiPi, .-_Z30__device_stub__Z10prepareBfsPiPi
	.globl	prepareBfs
	.type	prepareBfs, @function
prepareBfs:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10prepareBfsPiPi
	.cfi_endproc
.LFE2058:
	.size	prepareBfs, .-prepareBfs
	.globl	_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_
	.type	_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_, @function
_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	oneBfs(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L22:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_, .-_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_
	.globl	oneBfs
	.type	oneBfs, @function
oneBfs:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z6oneBfsPiS_S_PiS_S_
	.cfi_endproc
.LFE2060:
	.size	oneBfs, .-oneBfs
	.globl	_Z32__device_stub__Z12final_battlePiPi
	.type	_Z32__device_stub__Z12final_battlePiPi, @function
_Z32__device_stub__Z12final_battlePiPi:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	final_battle(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L27:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z32__device_stub__Z12final_battlePiPi, .-_Z32__device_stub__Z12final_battlePiPi
	.globl	final_battle
	.type	final_battle, @function
final_battle:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z12final_battlePiPi
	.cfi_endproc
.LFE2062:
	.size	final_battle, .-final_battle
	.globl	_Z36__device_stub__Z14gaussianFilterPiS_PiS_
	.type	_Z36__device_stub__Z14gaussianFilterPiS_PiS_, @function
_Z36__device_stub__Z14gaussianFilterPiS_PiS_:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	gaussianFilter(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L32:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z36__device_stub__Z14gaussianFilterPiS_PiS_, .-_Z36__device_stub__Z14gaussianFilterPiS_PiS_
	.globl	gaussianFilter
	.type	gaussianFilter, @function
gaussianFilter:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z14gaussianFilterPiS_PiS_
	.cfi_endproc
.LFE2064:
	.size	gaussianFilter, .-gaussianFilter
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"gaussianFilter"
.LC1:
	.string	"final_battle"
.LC2:
	.string	"oneBfs"
.LC3:
	.string	"prepareBfs"
.LC4:
	.string	"nonMaximalSupression"
.LC5:
	.string	"sobel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	gaussianFilter(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	final_battle(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	oneBfs(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	prepareBfs(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	nonMaximalSupression(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	sobel(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2066:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<cstdio>
#define S 64
#define ZERO 0
#define PI 3.14159265
#define LOW 9
#define HIGH 18
#define QUEUE_SIZE 128
#define KERNEL_RADIUS 8

extern "C" {
__device__
bool btwn(int a, int x, int y){
	return (a>=x && a<y);
}

__device__
void load_to_shared(int* src, int cache[][S], int th_x, int th_y, int n, int m){
	int val, pos, ind_x, ind_y;
	if(threadIdx.x==0 && threadIdx.y==0){
		ind_x = th_x-1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x] = val;
	}
	
	if(threadIdx.x==0 && threadIdx.y==31){
		ind_x = th_x-1; ind_y = th_y+1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x] = val;
	}
	
	if(threadIdx.x==31 && threadIdx.y==0){
		ind_x = th_x+1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x+2] = val;
	}
	
	if(threadIdx.x==31 && threadIdx.y==31){
		ind_x = th_x+1; ind_y = th_y-1;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x+2] = val;
	}

	if(threadIdx.y==0){
		ind_x = th_x; ind_y = th_y-1; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y][threadIdx.x+1] = val;
	}

	if(threadIdx.y==31){
		ind_x = th_x; ind_y = th_y+1; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
		cache[threadIdx.y+2][threadIdx.x+1] = val;
	}
	
	if(threadIdx.x==0){
		ind_x = th_x-1; ind_y = th_y; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
	 	cache[threadIdx.y+1][threadIdx.x] = val;
	}

	if(threadIdx.x==31){
		ind_x = th_x+1; ind_y = th_y; val=ZERO;
		if(btwn(ind_x, 0, m) && btwn(ind_y, 0, n)){
			pos = ind_y*m + ind_x;
			val = src[pos];
		}
	 	cache[threadIdx.y+1][threadIdx.x+2] = val;
	}
}

__global__
void sobel(int* src, int* dstMagni, float * arcTangensOut){
	__shared__ int cache[34][S];
	int m = gridDim.x*32, n = gridDim.y*32, 
	th_x = blockIdx.x * 32 + threadIdx.x, 
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x, ind_x, ind_y,
	magn_x, magn_y, magnAbs_x, magnAbs_y;

	/*now we load to shared with a frame of thickness eq 1*/
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	load_to_shared(src, cache, th_x, th_y, n, m);

	ind_y = threadIdx.y+1; 
	ind_x = threadIdx.x+1; 
	__syncthreads();
	magn_x = cache[ind_y][ind_x-1] - cache[ind_y][ind_x+1];
	magnAbs_x = ((magn_x>0) ? magn_x : -magn_x);
	magn_y = cache[ind_y+1][ind_x] - cache[ind_y-1][ind_x];
	magnAbs_y = ((magn_y>0) ? magn_y : -magn_y);
	dstMagni[i_src] = magnAbs_x + magnAbs_y;
	arcTangensOut[i_src] = atan2((float) magn_y,(float) magn_x)
										* 180 / PI;
}

__global__
void nonMaximalSupression(int * magn, float * arcTangens, int * dest) {
	__shared__ int cacheMagn[34][S];
	int m = gridDim.x*32, n = gridDim.y*32,
	th_x = blockIdx.x * 32 + threadIdx.x, 
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x, ind_x, ind_y;
	float angle;

	cacheMagn[threadIdx.y+1][threadIdx.x+1] = magn[i_src];
	load_to_shared(magn, cacheMagn, th_x, th_y, n, m);

	ind_y = threadIdx.y+1; ind_x = threadIdx.x+1; 
	__syncthreads();
   angle = arcTangens[i_src];
    if (angle < 0) angle = 360 + angle;
    
    //north && south
    int centerCell = cacheMagn[ind_y][ind_x];
    dest[i_src] = centerCell;
    if ((337.5 <= angle || angle < 22.5) || 
            (157.25 <= angle && angle < 202.5)) {
        if (cacheMagn[ind_y][ind_x+1] > centerCell ||
                cacheMagn[ind_y][ind_x-1] > centerCell) 
                    dest[i_src] = 0;
    } // north-east && south-west 
    else if ((22.5 <= angle && angle < 67.5) ||
            (202.5 <= angle && angle < 247.5)) {
        if (cacheMagn[ind_y-1][ind_x+1] > centerCell || 
                cacheMagn[ind_y+1][ind_x-1] > centerCell) 
                    dest[i_src] = 0;
    } // west && east
    else if ((67.5 <= angle && angle < 112.5) ||
                (247.5 <= angle && angle < 292.5)) {
        if (cacheMagn[ind_y+1][ind_x] > centerCell ||
                cacheMagn[ind_y-1][ind_x] > centerCell) 
                    dest[i_src] = 0;
    } // west-north && east-south
    else if ((112.5 <= angle && angle < 157.5) ||
        (292.5 <= angle || angle < 337.5)) {
        if (cacheMagn[ind_y-1][ind_x-1] > centerCell || 
                cacheMagn[ind_y+1][ind_x+1] > centerCell) 
                    dest[i_src] = 0;
    }

}	

__global__
void prepareBfs(int* src){
	int m = gridDim.x*32;
	int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int val = src[i_src];
	if(val < LOW){
		src[i_src] = 0;
	}
	else if(val >= HIGH){
		src[i_src] = -2;
	}
	else{
		src[i_src] = -1;
	}

}
__global__
void oneBfs(int* src, int* dst, int* changed){
	__shared__ int cache[34][S];
	int m = gridDim.x*32, n = gridDim.y*32,
	th_x = blockIdx.x * 32 + threadIdx.x,
	th_y = blockIdx.y * 32 + threadIdx.y,
	i_src = th_y*m + th_x,
	ind_y = threadIdx.y+1, ind_x = threadIdx.x+1,
	queue[QUEUE_SIZE],
	beg=0, end=0, val,
	procInd_x, procInd_y, x_new, y_new;
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	val = cache[ind_y][ind_x];
	load_to_shared(src, cache, th_x, th_y, n, m);
	__syncthreads();
	
	if(val==-1){
		for(int i=-1; i<2; ++i){
			for(int j=-1; j<2; ++j){
				procInd_x = ind_x+i;
				procInd_y = ind_y+j;
				if(cache[procInd_y][procInd_x]==-2){
					queue[end++] = ind_y;
					queue[end++] = ind_x;
					cache[ind_y][ind_x]=-2;
					*changed=1;
					i=2;
					j=2;
				}
			}
		}
	}
	

	while(beg!=end){
		procInd_y = queue[beg++];
		procInd_x = queue[beg++];
		for(int i=-1; i<2; ++i){
			for(int j=-1; j<2; ++j){
				x_new = procInd_x+i;
				y_new = procInd_y+j;
				if(cache[y_new][x_new]==-1 && btwn(y_new, 1, 33) 
											&& btwn(x_new, 1, 33)){
					queue[end++] = y_new;
					queue[end++] = x_new;
					cache[y_new][x_new]=-2;
				}
			}
		}
	}
	__syncthreads();
	dst[i_src] = cache[ind_y][ind_x];
	
}
__global__ 
void final_battle(int* src){
	int m = gridDim.x*32;
    int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int val = src[i_src];
	if(val==-2){
		src[i_src] = 255;
	}
	else{
		src[i_src] = 0;
	}
}

__global__
void gaussianFilter(int * src, int * dest) {
    __shared__ int cache[34][S];
    int n = gridDim.y*32;
    int m = gridDim.x*32;
    int th_x = blockIdx.x * 32 + threadIdx.x;
	int th_y = blockIdx.y * 32 + threadIdx.y;
	int i_src = th_y*m + th_x;
	int ind_y, ind_x;
	cache[threadIdx.y+1][threadIdx.x+1] = src[i_src];
	load_to_shared(src, cache, th_x, th_y, n, m);

    ind_y = threadIdx.y+1+KERNEL_RADIUS; ind_x = threadIdx.x+1+KERNEL_RADIUS;
	__syncthreads();

    int sum = 0;
    for (int i = -KERNEL_RADIUS; i <= KERNEL_RADIUS; i++) {
        for (int j = -KERNEL_RADIUS; j <= KERNEL_RADIUS; j++) {
            sum += cache[ind_y+i][ind_x+j]; //d_kernel[KERNEL_RADIUS + j]
        }
    }
    dest[i_src] = (int) sum;
}

}

	.text
	.file	"cudaStaff.hip"
	.globl	__device_stub__sobel            # -- Begin function __device_stub__sobel
	.type	__device_stub__sobel,@function
__device_stub__sobel:                   # @__device_stub__sobel
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sobel, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__sobel, .Lfunc_end0-__device_stub__sobel
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__nonMaximalSupression # -- Begin function __device_stub__nonMaximalSupression
	.type	__device_stub__nonMaximalSupression,@function
__device_stub__nonMaximalSupression:    # @__device_stub__nonMaximalSupression
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$nonMaximalSupression, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__nonMaximalSupression, .Lfunc_end1-__device_stub__nonMaximalSupression
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__prepareBfs       # -- Begin function __device_stub__prepareBfs
	.type	__device_stub__prepareBfs,@function
__device_stub__prepareBfs:              # @__device_stub__prepareBfs
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$prepareBfs, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__prepareBfs, .Lfunc_end2-__device_stub__prepareBfs
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__oneBfs           # -- Begin function __device_stub__oneBfs
	.type	__device_stub__oneBfs,@function
__device_stub__oneBfs:                  # @__device_stub__oneBfs
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$oneBfs, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__oneBfs, .Lfunc_end3-__device_stub__oneBfs
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__final_battle     # -- Begin function __device_stub__final_battle
	.type	__device_stub__final_battle,@function
__device_stub__final_battle:            # @__device_stub__final_battle
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$final_battle, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__final_battle, .Lfunc_end4-__device_stub__final_battle
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__gaussianFilter   # -- Begin function __device_stub__gaussianFilter
	.type	__device_stub__gaussianFilter,@function
__device_stub__gaussianFilter:          # @__device_stub__gaussianFilter
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$gaussianFilter, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__gaussianFilter, .Lfunc_end5-__device_stub__gaussianFilter
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sobel, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$nonMaximalSupression, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$prepareBfs, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$oneBfs, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$final_battle, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$gaussianFilter, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	sobel,@object                   # @sobel
	.section	.rodata,"a",@progbits
	.globl	sobel
	.p2align	3, 0x0
sobel:
	.quad	__device_stub__sobel
	.size	sobel, 8

	.type	nonMaximalSupression,@object    # @nonMaximalSupression
	.globl	nonMaximalSupression
	.p2align	3, 0x0
nonMaximalSupression:
	.quad	__device_stub__nonMaximalSupression
	.size	nonMaximalSupression, 8

	.type	prepareBfs,@object              # @prepareBfs
	.globl	prepareBfs
	.p2align	3, 0x0
prepareBfs:
	.quad	__device_stub__prepareBfs
	.size	prepareBfs, 8

	.type	oneBfs,@object                  # @oneBfs
	.globl	oneBfs
	.p2align	3, 0x0
oneBfs:
	.quad	__device_stub__oneBfs
	.size	oneBfs, 8

	.type	final_battle,@object            # @final_battle
	.globl	final_battle
	.p2align	3, 0x0
final_battle:
	.quad	__device_stub__final_battle
	.size	final_battle, 8

	.type	gaussianFilter,@object          # @gaussianFilter
	.globl	gaussianFilter
	.p2align	3, 0x0
gaussianFilter:
	.quad	__device_stub__gaussianFilter
	.size	gaussianFilter, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"sobel"
	.size	.L__unnamed_1, 6

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"nonMaximalSupression"
	.size	.L__unnamed_2, 21

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"prepareBfs"
	.size	.L__unnamed_3, 11

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"oneBfs"
	.size	.L__unnamed_4, 7

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"final_battle"
	.size	.L__unnamed_5, 13

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"gaussianFilter"
	.size	.L__unnamed_6, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__sobel
	.addrsig_sym __device_stub__nonMaximalSupression
	.addrsig_sym __device_stub__prepareBfs
	.addrsig_sym __device_stub__oneBfs
	.addrsig_sym __device_stub__final_battle
	.addrsig_sym __device_stub__gaussianFilter
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym sobel
	.addrsig_sym nonMaximalSupression
	.addrsig_sym prepareBfs
	.addrsig_sym oneBfs
	.addrsig_sym final_battle
	.addrsig_sym gaussianFilter
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function load_to_shared
	.type	load_to_shared,@function
load_to_shared:                         ; @load_to_shared
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_and_b32_e32 v13, 0x3ff, v31
	v_bfe_u32 v12, v31, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	v_or_b32_e32 v8, v13, v12
	v_cmp_eq_u32_e64 s1, 0, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v8
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_6
; %bb.1:
	v_cmp_lt_i32_e64 s0, 0, v4
	v_cmp_le_i32_e64 s2, v4, v7
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s2
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_5
; %bb.2:
	v_cmp_lt_i32_e64 s0, 0, v5
	v_cmp_le_i32_e64 s2, v5, v6
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s2
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add_nc_u32_e32 v8, -1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v8, v7
	v_add3_u32 v8, v4, v8, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, v0, v8
	v_add_co_ci_u32_e64 v9, s0, v1, v9, s0
	flat_load_b32 v8, v[8:9]
.LBB0_4:                                ; %Flow133
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[2:3], v8
.LBB0_6:                                ; %Flow134
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e64 s0, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_12
; %bb.7:
	v_cmp_lt_i32_e64 s0, 0, v4
	v_cmp_le_i32_e64 s2, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, s2
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_11
; %bb.8:
	v_add_nc_u32_e32 v9, 1, v5
	v_cmp_lt_i32_e64 s0, -2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s2, v9, v6
	s_and_b32 s0, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_mul_lo_u32 v8, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v4, v8, -1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, s0, v0, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, v1, v9, s0
	flat_load_b32 v8, v[8:9]
.LBB0_10:                               ; %Flow131
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_11:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_add_co_u32 v9, s0, 0x2000, v2
	v_add_co_ci_u32_e64 v10, s0, 0, v3, s0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[9:10], v8 offset:256
.LBB0_12:                               ; %Flow132
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e64 s0, 31, v13
	v_add_nc_u32_e32 v14, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_18
; %bb.13:
	v_cmp_lt_i32_e64 s1, -2, v4
	v_cmp_lt_i32_e64 s2, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s4, s1
	s_cbranch_execz .LBB0_17
; %bb.14:
	v_cmp_lt_i32_e64 s1, 0, v5
	v_cmp_le_i32_e64 s2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_add_nc_u32_e32 v8, -1, v5
	v_ashrrev_i32_e32 v9, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v8, v7
	v_ashrrev_i32_e32 v10, 31, v8
	v_add_co_u32 v8, s1, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, v10, v9, s1
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, v0, v8
	v_add_co_ci_u32_e64 v9, s1, v1, v9, s1
	flat_load_b32 v8, v[8:9] offset:4
.LBB0_16:                               ; %Flow129
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_17:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[2:3], v8 offset:132
.LBB0_18:                               ; %Flow130
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e64 s1, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_24
; %bb.19:
	v_cmp_lt_i32_e64 s1, -2, v4
	v_cmp_lt_i32_e64 s2, v14, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s4, s1
	s_cbranch_execz .LBB0_23
; %bb.20:
	v_cmp_lt_i32_e64 s1, 0, v5
	v_cmp_le_i32_e64 s2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, s2
	s_and_saveexec_b32 s2, s1
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_add_nc_u32_e32 v8, -1, v5
	v_ashrrev_i32_e32 v9, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v8, v7
	v_ashrrev_i32_e32 v10, 31, v8
	v_add_co_u32 v8, s1, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, v10, v9, s1
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, v0, v8
	v_add_co_ci_u32_e64 v9, s1, v1, v9, s1
	flat_load_b32 v8, v[8:9] offset:4
.LBB0_22:                               ; %Flow127
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_23:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_add_co_u32 v9, s1, 0x2000, v2
	v_add_co_ci_u32_e64 v10, s1, 0, v3, s1
	v_mov_b32_e32 v12, 31
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[9:10], v8 offset:388
.LBB0_24:                               ; %Flow128
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s7, 0
	s_mov_b32 s6, 0
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr4_sgpr5
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $vgpr15
	v_cmpx_lt_i32_e32 30, v12
	s_xor_b32 s8, exec_lo, s8
	s_cbranch_execz .LBB0_30
; %bb.25:                               ; %LeafBlock113
	s_mov_b32 s10, 0
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr9
                                        ; implicit-def: $sgpr4_sgpr5
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $vgpr15
	v_cmpx_eq_u32_e32 31, v12
	s_cbranch_execz .LBB0_29
; %bb.26:
	v_cmp_lt_i32_e64 s1, -1, v4
	v_cmp_lt_i32_e64 s2, v4, v7
	s_mov_b32 s7, -1
	s_mov_b32 s9, 0
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s1, s2
	s_mov_b32 s1, 0
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s5, s4
	s_xor_b32 s4, exec_lo, s5
; %bb.27:
	v_add_nc_u32_e32 v15, 1, v5
	v_cmp_lt_i32_e64 s1, -2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s2, v15, v6
	s_and_b32 s1, s1, s2
	s_mov_b64 s[2:3], 33
	s_xor_b32 s5, s1, -1
	s_and_b32 s1, s1, exec_lo
	s_or_not1_b32 s7, s5, exec_lo
; %bb.28:                               ; %Flow121
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b64 s[4:5], 33
	s_and_b32 s10, s7, exec_lo
	s_and_b32 s7, s1, exec_lo
.LBB0_29:                               ; %Flow120
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s6, s10, exec_lo
	s_and_b32 s7, s7, exec_lo
.LBB0_30:                               ; %Flow119
	s_or_saveexec_b32 s8, s8
	v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v9, s5
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v11, s3
	v_mov_b32_e32 v10, s2
	s_xor_b32 exec_lo, exec_lo, s8
	s_cbranch_execz .LBB0_38
; %bb.31:                               ; %LeafBlock
	s_mov_b32 s10, s7
	s_mov_b32 s12, s6
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $sgpr11
                                        ; implicit-def: $sgpr4_sgpr5
                                        ; implicit-def: $sgpr2_sgpr3
                                        ; implicit-def: $vgpr15
	v_cmpx_eq_u32_e32 0, v12
	s_cbranch_execz .LBB0_37
; %bb.32:
	v_cmp_lt_i32_e64 s1, -1, v4
	v_cmp_lt_i32_e64 s2, v4, v7
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s5, s1, s2
	s_mov_b32 s1, s7
                                        ; implicit-def: $sgpr2_sgpr3
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB0_36
; %bb.33:
	v_cmp_lt_i32_e64 s1, 0, v5
	v_cmp_le_i32_e64 s2, v5, v6
	s_mov_b32 s5, s7
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, s1, s2
                                        ; implicit-def: $sgpr2_sgpr3
	s_xor_b32 s1, s11, -1
	s_and_saveexec_b32 s10, s11
; %bb.34:
	v_add_nc_u32_e32 v15, -1, v5
	s_mov_b64 s[2:3], 0
	s_or_b32 s5, s7, exec_lo
; %bb.35:                               ; %Flow125
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s11, s7, exec_lo
	s_and_b32 s5, s5, exec_lo
	s_or_not1_b32 s10, s1, exec_lo
	s_or_b32 s1, s11, s5
.LBB0_36:                               ; %Flow124
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s12, s6, exec_lo
	s_and_b32 s10, s10, exec_lo
	s_and_not1_b32 s13, s7, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_mov_b64 s[4:5], 0
	s_mov_b32 s11, 0
	s_or_b32 s12, s12, s10
	s_or_b32 s10, s13, s1
.LBB0_37:                               ; %Flow123
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v16, s11 :: v_dual_mov_b32 v9, s5
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v11, s3
	v_mov_b32_e32 v10, s2
	s_and_not1_b32 s1, s6, exec_lo
	s_and_b32 s2, s12, exec_lo
	s_and_not1_b32 s3, s7, exec_lo
	s_and_b32 s4, s10, exec_lo
	s_or_b32 s6, s1, s2
	s_or_b32 s7, s3, s4
.LBB0_38:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s8
	s_and_saveexec_b32 s2, s7
	s_cbranch_execz .LBB0_40
; %bb.39:                               ; %.sink.split.sink.split
	v_mad_u64_u32 v[8:9], null, v15, v7, v[4:5]
	s_or_b32 s6, s6, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s1, v0, v8
	v_add_co_ci_u32_e64 v9, s1, v1, v9, s1
	flat_load_b32 v16, v[8:9]
	v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
.LBB0_40:                               ; %Flow126
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, s6
	s_cbranch_execz .LBB0_42
; %bb.41:                               ; %.sink.split
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 8, v[8:9]
	v_lshlrev_b32_e32 v10, 2, v13
	v_add_co_u32 v8, s1, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v9, s1, v3, v9, s1
	v_add_co_u32 v8, s1, v8, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s1, 0, v9, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[8:9], v16 offset:4
.LBB0_42:
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_48
; %bb.43:
	v_cmp_lt_i32_e32 vcc_lo, 0, v4
	v_cmp_le_i32_e64 s1, v4, v7
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_47
; %bb.44:
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	v_cmp_lt_i32_e64 s1, v5, v6
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, vcc_lo, s1
	s_and_saveexec_b32 s1, s4
	s_cbranch_execz .LBB0_46
; %bb.45:
	v_mul_lo_u32 v8, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v4, v8, -1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_u32 v8, vcc_lo, v0, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
	flat_load_b32 v8, v[8:9]
.LBB0_46:                               ; %Flow116
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_47:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v9, 8, v12
	v_add_co_u32 v9, vcc_lo, v2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[9:10], v8 offset:256
.LBB0_48:                               ; %Flow117
	s_or_b32 exec_lo, exec_lo, s2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_54
; %bb.49:
	v_cmp_lt_i32_e32 vcc_lo, -2, v4
	v_cmp_lt_i32_e64 s0, v14, v7
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s2, s0
	s_cbranch_execz .LBB0_53
; %bb.50:
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	v_cmp_lt_i32_e64 s0, v5, v6
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s0
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_52
; %bb.51:
	v_mul_lo_u32 v5, v7, v5
	v_ashrrev_i32_e32 v6, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v0, vcc_lo, v0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
	flat_load_b32 v8, v[0:1] offset:4
.LBB0_52:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_53:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b32_e32 v0, 8, v12
	v_add_co_u32 v0, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	flat_store_b32 v[0:1], v8 offset:388
.LBB0_54:                               ; %Flow115
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	load_to_shared, .Lfunc_end0-load_to_shared
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 1788
; NumSgprs: 34
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	sobel                   ; -- Begin function sobel
	.globl	sobel
	.p2align	8
	.type	sobel,@function
sobel:                                  ; @sobel
; %bb.0:
	s_load_b256 s[16:23], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_mov_b64 s[0:1], src_shared_base
	v_mov_b32_e32 v31, v0
	s_mov_b32 s32, 0
	v_lshl_add_u32 v4, s14, 5, v3
	v_lshl_add_u32 v5, s15, 5, v6
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v0, s16
	s_lshl_b32 s4, s22, 5
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, load_to_shared@rel32@lo+4
	s_addc_u32 s3, s3, load_to_shared@rel32@hi+12
	v_mad_u64_u32 v[1:2], null, s4, v5, v[4:5]
	s_lshl_b32 s0, s23, 5
	v_mov_b32_e32 v7, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[17:18], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v18, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_dual_mov_b32 v3, s1 :: v_dual_lshlrev_b32 v2, 2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v19, v6, 8, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v6, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v1 offset:260
	v_mov_b32_e32 v1, s17
	s_swappc_b64 s[30:31], s[2:3]
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[0:1], v19 offset0:1 offset1:64
	ds_load_2addr_b32 v[2:3], v19 offset0:66 offset1:129
	s_mov_b32 s0, 0x3b2d2a58
	s_waitcnt lgkmcnt(0)
	v_sub_nc_u32_e32 v10, v3, v0
	v_sub_nc_u32_e32 v11, v1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v1, v10
	v_cvt_f32_i32_e32 v2, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_max_f32_e64 v4, |v2|, |v1|
	v_min_f32_e64 v6, |v2|, |v1|
	v_cmp_gt_f32_e64 vcc_lo, |v1|, |v2|
	v_frexp_mant_f32_e32 v5, v4
	v_frexp_exp_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_exp_i32_f32_e32 v7, v6
	v_frexp_mant_f32_e32 v6, v6
	v_rcp_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v7, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, v6, v5
	v_ldexp_f32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v4, v4
	v_fmaak_f32 v6, s0, v5, 0xbc7a590c
	s_mov_b32 s0, 0x53c8d4f1
	s_mov_b32 s1, 0x400921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, v5, v6, 0x3d29fb3f
	v_fmaak_f32 v6, v5, v6, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, v5, v6, 0x3dd931b2
	v_fmaak_f32 v6, v5, v6, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v6, v5, v6, 0x3e4cb8bf
	v_fmaak_f32 v6, v5, v6, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v6
	v_fmac_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, 0x3fc90fdb, v4
	v_cndmask_b32_e32 v2, v4, v5, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, 0x40490fdb, v2
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v2, v4, vcc_lo
	v_bfi_b32 v0, 0x7fffffff, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x43340000, v0
	v_cvt_f64_f32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[2:3], null, s[0:1], s[0:1], v[0:1]
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_div_scale_f64 v[6:7], vcc_lo, v[0:1], s[0:1], v[0:1]
	v_mul_f64 v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], s[0:1], v[0:1]
	v_cvt_f32_f64_e32 v4, v[0:1]
	v_sub_nc_u32_e32 v0, 0, v11
	v_sub_nc_u32_e32 v1, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_i32_e32 v0, v11, v0
	v_max_i32_e32 v1, v10, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v5, v1, v0
	v_add_co_u32 v0, vcc_lo, s18, v17
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v18, vcc_lo
	v_add_co_u32 v2, vcc_lo, s20, v17
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v18, vcc_lo
	global_store_b32 v[0:1], v5, off
	global_store_b32 v[2:3], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sobel
		.amdhsa_group_segment_fixed_size 8704
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	sobel, .Lfunc_end1-sobel
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 712
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8704 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	nonMaximalSupression    ; -- Begin function nonMaximalSupression
	.globl	nonMaximalSupression
	.p2align	8
	.type	nonMaximalSupression,@function
nonMaximalSupression:                   ; @nonMaximalSupression
; %bb.0:
	s_load_b256 s[16:23], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_mov_b64 s[0:1], src_shared_base
	v_mov_b32_e32 v31, v0
	s_mov_b32 s32, 0
	v_lshl_add_u32 v4, s14, 5, v3
	v_lshl_add_u32 v5, s15, 5, v6
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v0, s16
	s_lshl_b32 s4, s22, 5
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, load_to_shared@rel32@lo+4
	s_addc_u32 s3, s3, load_to_shared@rel32@hi+12
	v_mad_u64_u32 v[1:2], null, s4, v5, v[4:5]
	s_lshl_b32 s0, s23, 5
	v_mov_b32_e32 v7, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[18:19], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s16, v18
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v19, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_dual_mov_b32 v3, s1 :: v_dual_lshlrev_b32 v2, 2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v17, v6, 8, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v6, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v17, v1 offset:260
	v_mov_b32_e32 v1, s17
	s_swappc_b64 s[30:31], s[2:3]
	v_add_co_u32 v0, vcc_lo, s18, v18
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v19, vcc_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v0, v[0:1], off
	ds_load_b32 v2, v17 offset:260
	s_mov_b32 s2, -1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v1, 0x43b40000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v0, v1, vcc_lo
	v_add_co_u32 v0, s1, s20, v18
	v_add_co_ci_u32_e64 v1, s1, s21, v19, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_f32_e32 vcc_lo, 0x43a8c000, v3
	v_cmp_gt_f32_e64 s0, 0x41b40000, v3
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_or_b32 s3, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s3, -1
	s_and_saveexec_b32 s4, s0
	s_cbranch_execz .LBB2_24
; %bb.1:
	v_cmp_nle_f32_e32 vcc_lo, 0x431d4000, v3
	v_cmp_ngt_f32_e64 s0, 0x434a8000, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s1, vcc_lo, s0
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s5, s1
	s_cbranch_execz .LBB2_23
; %bb.2:
	v_cmp_le_f32_e32 vcc_lo, 0x41b40000, v3
	v_cmp_gt_f32_e64 s0, 0x42870000, v3
	s_mov_b32 s1, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, vcc_lo, s0
	s_mov_b32 s0, 0
	s_xor_b32 s2, s6, -1
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB2_18
; %bb.3:
	v_cmp_nle_f32_e32 vcc_lo, 0x434a8000, v3
	v_cmp_ngt_f32_e64 s0, 0x43778000, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s2, vcc_lo, s0
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s8, s2
	s_cbranch_execz .LBB2_17
; %bb.4:
	v_cmp_le_f32_e32 vcc_lo, 0x42870000, v3
	v_cmp_gt_f32_e64 s0, 0x42e10000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s0
	s_mov_b32 s0, 0
	s_xor_b32 s2, s9, -1
	s_and_saveexec_b32 s10, s2
	s_cbranch_execz .LBB2_12
; %bb.5:
	v_cmp_nle_f32_e32 vcc_lo, 0x43778000, v3
	v_cmp_ngt_f32_e64 s0, 0x43924000, v3
	s_delay_alu instid0(VALU_DEP_1)
	s_or_b32 s2, vcc_lo, s0
	s_mov_b32 s0, 0
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB2_11
; %bb.6:
	v_cmp_le_f32_e32 vcc_lo, 0x42e10000, v3
	v_cmp_gt_f32_e64 s0, 0x431d8000, v3
	v_cmp_le_f32_e64 s1, 0x43924000, v3
	v_cmp_gt_f32_e64 s2, 0x43a8c000, v3
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s0
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB2_10
; %bb.7:
	ds_load_b32 v3, v17
	s_mov_b32 s1, -1
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_le_i32_e64 v3, v2
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB2_9
; %bb.8:
	ds_load_b32 v3, v17 offset:520
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v2
	s_or_not1_b32 s1, vcc_lo, exec_lo
.LBB2_9:                                ; %Flow102
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s1, s1, exec_lo
.LBB2_10:                               ; %Flow101
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s1, exec_lo
	s_xor_b32 s1, exec_lo, -1
.LBB2_11:                               ; %Flow100
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s9, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s9, s2, s1
.LBB2_12:                               ; %Flow99
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s1, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB2_16
; %bb.13:
	ds_load_b32 v3, v17 offset:516
	s_mov_b32 s2, -1
	s_mov_b32 s9, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_le_i32_e64 v3, v2
	s_xor_b32 s9, exec_lo, s9
	s_cbranch_execz .LBB2_15
; %bb.14:
	ds_load_b32 v3, v17 offset:4
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v2
	s_or_not1_b32 s2, vcc_lo, exec_lo
.LBB2_15:                               ; %Flow104
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s0, s0, s2
.LBB2_16:                               ; %Flow103
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_xor_b32 s1, exec_lo, -1
.LBB2_17:                               ; %Flow98
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s6, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s6, s2, s1
.LBB2_18:                               ; %Flow97
	s_or_b32 exec_lo, exec_lo, s7
	s_and_saveexec_b32 s1, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB2_22
; %bb.19:
	ds_load_b32 v3, v17 offset:8
	s_mov_b32 s2, -1
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_le_i32_e64 v3, v2
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB2_21
; %bb.20:
	ds_load_b32 v3, v17 offset:512
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v2
	s_or_not1_b32 s2, vcc_lo, exec_lo
.LBB2_21:                               ; %Flow106
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s0, s0, s2
.LBB2_22:                               ; %Flow105
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_xor_b32 s2, exec_lo, -1
.LBB2_23:                               ; %Flow96
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_and_b32 s1, s0, exec_lo
	s_or_b32 s3, s3, s2
.LBB2_24:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s4
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB2_28
; %bb.25:
	ds_load_b32 v3, v17 offset:264
	s_mov_b32 s2, -1
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_le_i32_e64 v3, v2
	s_cbranch_execz .LBB2_27
; %bb.26:
	ds_load_b32 v3, v17 offset:256
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v3, v2
	s_or_not1_b32 s2, vcc_lo, exec_lo
.LBB2_27:                               ; %Flow108
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s1, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s1, s1, s2
.LBB2_28:                               ; %Flow107
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB2_30
; %bb.29:                               ; %.sink.split
	v_mov_b32_e32 v2, 0
	global_store_b32 v[0:1], v2, off
.LBB2_30:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel nonMaximalSupression
		.amdhsa_group_segment_fixed_size 8704
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	nonMaximalSupression, .Lfunc_end2-nonMaximalSupression
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1136
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8704 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	prepareBfs              ; -- Begin function prepareBfs
	.globl	prepareBfs
	.p2align	8
	.type	prepareBfs,@function
prepareBfs:                             ; @prepareBfs
; %bb.0:
	s_load_b32 s2, s[0:1], 0x8
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, s15, 5, v1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s2, v3, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, v1, 5, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, 17, v2
	v_cndmask_b32_e64 v3, -1, -2, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 8, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v3, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel prepareBfs
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	prepareBfs, .Lfunc_end3-prepareBfs
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	oneBfs                  ; -- Begin function oneBfs
	.globl	oneBfs
	.p2align	8
	.type	oneBfs,@function
oneBfs:                                 ; @oneBfs
; %bb.0:
	s_load_b256 s[16:23], s[0:1], 0x0
	v_dual_mov_b32 v20, 0 :: v_dual_and_b32 v21, 0x3ff, v0
	v_bfe_u32 v22, v0, 10, 10
	s_mov_b64 s[0:1], src_shared_base
	s_movk_i32 s32, 0x210
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v4, s14, 5, v21
	v_mov_b32_e32 v3, s1
	v_lshl_add_u32 v5, s15, 5, v22
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s4, s22, 5
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, load_to_shared@rel32@lo+4
	s_addc_u32 s3, s3, load_to_shared@rel32@hi+12
	v_mad_u64_u32 v[1:2], null, s4, v5, v[4:5]
	s_lshl_b32 s0, s23, 5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v6, s0
	v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v7, s4
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v18, vcc_lo
	global_load_b32 v23, v[1:2], off
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v21
	v_lshl_add_u32 v19, v22, 8, v1
	v_mov_b32_e32 v1, s17
	s_waitcnt vmcnt(0)
	ds_store_b32 v19, v23 offset:260
	s_swappc_b64 s[30:31], s[2:3]
	s_mov_b32 s0, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_eq_u32_e32 -1, v23
	s_cbranch_execz .LBB4_7
; %bb.1:                                ; %.preheader71.preheader
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, 1, v22
	v_dual_mov_b32 v6, -1 :: v_dual_add_nc_u32 v1, 1, v21
	v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v5, -1
	v_mov_b32_e32 v2, -2
	v_mov_b32_e32 v4, 1
	s_mov_b32 s1, 0
	s_mov_b32 s2, 0
.LBB4_2:                                ; %.preheader71
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v6, v22
	v_add_lshl_u32 v8, v5, v21, 2
	s_mov_b32 s3, exec_lo
	v_lshl_add_u32 v7, v7, 8, v8
	ds_load_b32 v7, v7 offset:260
	s_waitcnt lgkmcnt(0)
	v_cmpx_eq_u32_e32 -2, v7
	s_cbranch_execz .LBB4_4
; %bb.3:                                ;   in Loop: Header=BB4_2 Depth=1
	v_lshl_add_u32 v7, v20, 2, 16
	v_dual_mov_b32 v5, 2 :: v_dual_add_nc_u32 v20, 2, v20
	v_mov_b32_e32 v6, 2
	ds_store_b32 v19, v2 offset:260
	scratch_store_b64 v7, v[0:1], off
	global_store_b32 v3, v4, s[20:21]
.LBB4_4:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v7, 1, v6
	v_cmp_lt_i32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v6, v7
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_2
; %bb.5:                                ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mov_b32 v6, -1 :: v_dual_add_nc_u32 v7, 1, v5
	v_cmp_lt_i32_e32 vcc_lo, 0, v5
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v5, v7
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB4_2
; %bb.6:                                ; %Flow103
	s_or_b32 exec_lo, exec_lo, s1
.LBB4_7:                                ; %Flow104
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s2, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_ne_u32_e32 0, v20
	s_cbranch_execz .LBB4_16
; %bb.8:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v4, -2
	s_mov_b32 s3, 0
.LBB4_9:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_10 Depth 2
                                        ;       Child Loop BB4_11 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s0, s3, 2
	s_mov_b32 s4, -1
	s_add_i32 s0, s0, 16
	scratch_load_b64 v[0:1], off, s0
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v2, 8, v0
	v_lshlrev_b32_e32 v3, 2, v1
	v_add_nc_u32_e32 v0, -2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v2, v3, 0xfffffefc
.LBB4_10:                               ; %.preheader
                                        ;   Parent Loop BB4_9 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB4_11 Depth 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v0 :: v_dual_add_nc_u32 v3, s4, v1
	s_mov_b32 s5, 0
	v_add_nc_u32_e32 v6, -1, v3
.LBB4_11:                               ;   Parent Loop BB4_9 Depth=1
                                        ;     Parent Loop BB4_10 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, s5, v5
	v_or_b32_e32 v9, v6, v2
	v_add_nc_u32_e32 v2, 1, v2
	ds_load_b32 v8, v7
	v_cmp_gt_u32_e64 s0, 32, v9
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, s0, vcc_lo
	s_and_saveexec_b32 s0, s6
	s_cbranch_execz .LBB4_13
; %bb.12:                               ;   in Loop: Header=BB4_11 Depth=3
	v_lshl_add_u32 v8, v20, 2, 16
	v_add_nc_u32_e32 v20, 2, v20
	ds_store_b32 v7, v4
	scratch_store_b64 v8, v[2:3], off
.LBB4_13:                               ;   in Loop: Header=BB4_11 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	s_addk_i32 s5, 0x100
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s5, 0x300
	s_cbranch_scc0 .LBB4_11
; %bb.14:                               ;   in Loop: Header=BB4_10 Depth=2
	v_add_nc_u32_e32 v5, 4, v5
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 2
	s_cbranch_scc0 .LBB4_10
; %bb.15:                               ; %.loopexit
                                        ;   in Loop: Header=BB4_9 Depth=1
	s_add_i32 s3, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s3, v20
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB4_9
.LBB4_16:                               ; %Flow102
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v19 offset:260
	v_add_co_u32 v0, vcc_lo, s18, v17
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v18, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel oneBfs
		.amdhsa_group_segment_fixed_size 8704
		.amdhsa_private_segment_fixed_size 528
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	oneBfs, .Lfunc_end4-oneBfs
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 756
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 528
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8704 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	final_battle            ; -- Begin function final_battle
	.globl	final_battle
	.p2align	8
	.type	final_battle,@function
final_battle:                           ; @final_battle
; %bb.0:
	s_load_b32 s2, s[0:1], 0x8
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, s15, 5, v1
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[1:2], null, s2, v3, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, v1, 5, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, -2, v2
	v_cndmask_b32_e64 v2, 0, 0xff, vcc_lo
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel final_battle
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	final_battle, .Lfunc_end5-final_battle
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	gaussianFilter          ; -- Begin function gaussianFilter
	.globl	gaussianFilter
	.p2align	8
	.type	gaussianFilter,@function
gaussianFilter:                         ; @gaussianFilter
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[16:19], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	s_mov_b64 s[0:1], src_shared_base
	s_mov_b32 s32, 0
	v_mov_b32_e32 v19, 0
	v_lshl_add_u32 v4, s14, 5, v3
	v_lshl_add_u32 v5, s15, 5, v6
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s2, s2, 5
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, load_to_shared@rel32@lo+4
	s_addc_u32 s5, s5, load_to_shared@rel32@hi+12
	v_mad_u64_u32 v[1:2], null, s2, v5, v[4:5]
	s_lshl_b32 s0, s3, 5
	v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, s16
	v_mov_b32_e32 v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[17:18], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s16, v17
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v18, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_dual_mov_b32 v3, s1 :: v_dual_lshlrev_b32 v2, 2, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v20, v6, 8, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v6, s0
	s_waitcnt vmcnt(0)
	ds_store_b32 v20, v1 offset:260
	v_mov_b32_e32 v1, s17
	s_swappc_b64 s[30:31], s[4:5]
	v_add_nc_u32_e32 v0, 0x104, v20
	s_mov_b32 s0, -8
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB6_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB6_2 Depth 2
	s_movk_i32 s1, 0xffbc
.LBB6_2:                                ;   Parent Loop BB6_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s1, v0
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v1, v1 offset:68
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v19, v1, v19
	s_cbranch_scc0 .LBB6_2
; %bb.3:                                ;   in Loop: Header=BB6_1 Depth=1
	v_add_nc_u32_e32 v0, 0x100, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 9
	s_cbranch_scc0 .LBB6_1
; %bb.4:
	v_add_co_u32 v0, vcc_lo, s18, v17
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v18, vcc_lo
	global_store_b32 v[0:1], v19, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel gaussianFilter
		.amdhsa_group_segment_fixed_size 8704
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	gaussianFilter, .Lfunc_end6-gaussianFilter
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8704 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8704
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sobel
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         sobel.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8704
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           nonMaximalSupression
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         nonMaximalSupression.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           prepareBfs
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         prepareBfs.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8704
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           oneBfs
    .private_segment_fixed_size: 528
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         oneBfs.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           final_battle
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         final_battle.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8704
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           gaussianFilter
    .private_segment_fixed_size: 0
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         gaussianFilter.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
