__global__ void tsort1(int *input0,int *result0){
  unsigned int tid = threadIdx.x;
  unsigned int bid = blockIdx.x;
  extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
  (( int *)sbase)[tid] = ((tid&1)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^1))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^1))]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^7)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^7)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^15)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^15)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^127)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^127)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^255)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^255)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^128)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^128)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^64)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^64)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  result0[((bid*512)+tid)] = (( int *)sbase)[tid];
  
}

	.file	"tmpxft_003818d3_00000000-6_tsort1Kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z6tsort1PiS_PiS_
	.type	_Z27__device_stub__Z6tsort1PiS_PiS_, @function
_Z27__device_stub__Z6tsort1PiS_PiS_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z6tsort1PiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z27__device_stub__Z6tsort1PiS_PiS_, .-_Z27__device_stub__Z6tsort1PiS_PiS_
	.globl	_Z6tsort1PiS_
	.type	_Z6tsort1PiS_, @function
_Z6tsort1PiS_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z6tsort1PiS_PiS_
	.cfi_endproc
.LFE2033:
	.size	_Z6tsort1PiS_, .-_Z6tsort1PiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6tsort1PiS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6tsort1PiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void tsort1(int *input0,int *result0){
  unsigned int tid = threadIdx.x;
  unsigned int bid = blockIdx.x;
  extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
  (( int *)sbase)[tid] = ((tid&1)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^1))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^1))]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^7)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^7)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^15)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^15)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^127)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^127)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^255)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^255)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^32)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^16)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&2)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^2)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&1)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^1)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^128)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^128)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^64)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^64)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^8)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^4)]);
  __syncthreads();
  (( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
  __syncthreads();
  (( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
  __syncthreads();
  result0[((bid*512)+tid)] = (( int *)sbase)[tid];
  
}

	.text
	.file	"tsort1Kernel.hip"
	.globl	_Z21__device_stub__tsort1PiS_   # -- Begin function _Z21__device_stub__tsort1PiS_
	.type	_Z21__device_stub__tsort1PiS_,@function
_Z21__device_stub__tsort1PiS_:          # @_Z21__device_stub__tsort1PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6tsort1PiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__tsort1PiS_, .Lfunc_end0-_Z21__device_stub__tsort1PiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6tsort1PiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6tsort1PiS_,@object           # @_Z6tsort1PiS_
	.section	.rodata,"a",@progbits
	.globl	_Z6tsort1PiS_
	.p2align	3, 0x0
_Z6tsort1PiS_:
	.quad	_Z21__device_stub__tsort1PiS_
	.size	_Z6tsort1PiS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6tsort1PiS_"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__tsort1PiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6tsort1PiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6tsort1PiS_           ; -- Begin function _Z6tsort1PiS_
	.globl	_Z6tsort1PiS_
	.p2align	8
	.type	_Z6tsort1PiS_,@function
_Z6tsort1PiS_:                          ; @_Z6tsort1PiS_
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x0
	s_lshl_b32 s1, s15, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s1, v0
                                        ; implicit-def: $vgpr7
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	v_and_b32_e32 v3, 1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
	global_load_b32 v6, v[5:6], off
	v_and_b32_e32 v5, 0x3fe, v0
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s1, v5
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s0, s8, v3
	v_add_co_ci_u32_e64 v4, s0, s9, v4, s0
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_max_i32_e32 v7, v6, v3
                                        ; implicit-def: $vgpr6
.LBB0_2:                                ; %Flow350
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add3_u32 v3, s1, v0, 1
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, s0, s8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s9, v4, s0
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v7, v6, v3
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s2
	v_xor_b32_e32 v4, 3, v0
	v_lshl_add_u32 v3, v0, 2, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v4, v4, 2, 0
	ds_store_b32 v3, v7
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v3
	ds_load_b32 v4, v4
	v_and_b32_e32 v7, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0, v7
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v6, v4
	v_max_i32_e32 v4, v6, v4
	v_cndmask_b32_e64 v4, v4, v8, s0
	v_cmp_ne_u32_e64 s0, 0, v7
	ds_store_b32 v3, v4 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v3 offset:2048
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshl_add_u32 v4, v5, 2, 0
	ds_load_b32 v4, v4 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v4, v6, v4
                                        ; implicit-def: $vgpr6
.LBB0_6:                                ; %Flow349
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_8
; %bb.7:
	ds_load_b32 v4, v3 offset:2052
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v4, v6, v4
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v6, 7, v0
	ds_store_b32 v3, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v4, v6, 2, 0
	v_and_b32_e32 v7, 4, v0
	ds_load_b32 v6, v3
	ds_load_b32 v4, v4
	v_cmp_eq_u32_e64 s1, 0, v7
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v6, v4
	v_max_i32_e32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v8, s1
	v_cmp_ne_u32_e64 s1, 0, v7
                                        ; implicit-def: $vgpr7
	ds_store_b32 v3, v4 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v3 offset:2048
	v_and_b32_e32 v4, 0x3fd, v0
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_10
; %bb.9:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v7, v4, 2, 0
	ds_load_b32 v7, v7 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v7, v6, v7
                                        ; implicit-def: $vgpr6
.LBB0_10:                               ; %Flow348
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_12
; %bb.11:
	ds_load_b32 v7, v3 offset:2056
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v7, v6, v7
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s2
	ds_store_b32 v3, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v7, v3
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_14
; %bb.13:
	v_lshl_add_u32 v6, v5, 2, 0
	ds_load_b32 v6, v6
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v6, v7, v6
                                        ; implicit-def: $vgpr7
.LBB0_14:                               ; %Flow347
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_16
; %bb.15:
	ds_load_b32 v6, v3 offset:4
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v6, v7, v6
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v7, 15, v0
	ds_store_b32 v3, v6 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v6, v7, 2, 0
	v_and_b32_e32 v8, 8, v0
	ds_load_b32 v7, v3 offset:2048
	ds_load_b32 v6, v6 offset:2048
	v_cmp_eq_u32_e64 s2, 0, v8
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v7, v6
	v_max_i32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v6, v6, v9, s2
	v_cmp_ne_u32_e64 s2, 0, v8
                                        ; implicit-def: $vgpr8
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v7, v3
	v_and_b32_e32 v6, 0x3fb, v0
	s_and_saveexec_b32 s3, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_18
; %bb.17:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v8, v6, 2, 0
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v8, v7, v8
                                        ; implicit-def: $vgpr7
.LBB0_18:                               ; %Flow346
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_20
; %bb.19:
	ds_load_b32 v8, v3 offset:16
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v7, v8
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v3, v8 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v8, v3 offset:2048
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_lshl_add_u32 v7, v4, 2, 0
	ds_load_b32 v7, v7 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v7, v8, v7
                                        ; implicit-def: $vgpr8
.LBB0_22:                               ; %Flow345
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_24
; %bb.23:
	ds_load_b32 v7, v3 offset:2056
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v7, v8, v7
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v3, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v8, v3
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_lshl_add_u32 v7, v5, 2, 0
	ds_load_b32 v7, v7
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v7, v8, v7
                                        ; implicit-def: $vgpr8
.LBB0_26:                               ; %Flow344
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_28
; %bb.27:
	ds_load_b32 v7, v3 offset:4
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v7, v8, v7
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v8, 31, v0
	ds_store_b32 v3, v7 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v7, v8, 2, 0
	v_and_b32_e32 v9, 16, v0
	ds_load_b32 v8, v3 offset:2048
	ds_load_b32 v7, v7 offset:2048
	v_cmp_eq_u32_e64 s3, 0, v9
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v8, v7
	v_max_i32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v7, v10, s3
	v_cmp_ne_u32_e64 s3, 0, v9
                                        ; implicit-def: $vgpr9
	ds_store_b32 v3, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v8, v3
	v_and_b32_e32 v7, 0x3f7, v0
	s_and_saveexec_b32 s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_30
; %bb.29:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v9, v7, 2, 0
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v9, v8, v9
                                        ; implicit-def: $vgpr8
.LBB0_30:                               ; %Flow343
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_32
; %bb.31:
	ds_load_b32 v9, v3 offset:32
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v8, v9
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s4
	ds_store_b32 v3, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v3 offset:2048
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s4, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_34
; %bb.33:
	v_lshl_add_u32 v8, v6, 2, 0
	ds_load_b32 v8, v8 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v8, v9, v8
                                        ; implicit-def: $vgpr9
.LBB0_34:                               ; %Flow342
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_36
; %bb.35:
	ds_load_b32 v8, v3 offset:2064
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v9, v8
.LBB0_36:
	s_or_b32 exec_lo, exec_lo, s4
	ds_store_b32 v3, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v3
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s4, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_38
; %bb.37:
	v_lshl_add_u32 v8, v4, 2, 0
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v8, v9, v8
                                        ; implicit-def: $vgpr9
.LBB0_38:                               ; %Flow341
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_40
; %bb.39:
	ds_load_b32 v8, v3 offset:8
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v9, v8
.LBB0_40:
	s_or_b32 exec_lo, exec_lo, s4
	ds_store_b32 v3, v8 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v3 offset:2048
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s4, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_42
; %bb.41:
	v_lshl_add_u32 v8, v5, 2, 0
	ds_load_b32 v8, v8 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v8, v9, v8
                                        ; implicit-def: $vgpr9
.LBB0_42:                               ; %Flow340
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_44
; %bb.43:
	ds_load_b32 v8, v3 offset:2052
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v8, v9, v8
.LBB0_44:
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v9, 63, v0
	ds_store_b32 v3, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v8, v9, 2, 0
	v_and_b32_e32 v10, 32, v0
	ds_load_b32 v9, v3
	ds_load_b32 v8, v8
	v_cmp_eq_u32_e64 s4, 0, v10
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v9, v8
	v_max_i32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v8, v8, v11, s4
	v_cmp_ne_u32_e64 s4, 0, v10
                                        ; implicit-def: $vgpr10
	ds_store_b32 v3, v8 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v3 offset:2048
	v_and_b32_e32 v8, 0x3ef, v0
	s_and_saveexec_b32 s5, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_46
; %bb.45:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v10, v8, 2, 0
	ds_load_b32 v10, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v9, v10
                                        ; implicit-def: $vgpr9
.LBB0_46:                               ; %Flow339
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_48
; %bb.47:
	ds_load_b32 v10, v3 offset:2112
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v9, v10
.LBB0_48:
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b32 v3, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s5, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_50
; %bb.49:
	v_lshl_add_u32 v9, v7, 2, 0
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v9, v10, v9
                                        ; implicit-def: $vgpr10
.LBB0_50:                               ; %Flow338
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_52
; %bb.51:
	ds_load_b32 v9, v3 offset:32
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v10, v9
.LBB0_52:
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b32 v3, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3 offset:2048
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s5, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_54
; %bb.53:
	v_lshl_add_u32 v9, v6, 2, 0
	ds_load_b32 v9, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v9, v10, v9
                                        ; implicit-def: $vgpr10
.LBB0_54:                               ; %Flow337
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_56
; %bb.55:
	ds_load_b32 v9, v3 offset:2064
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v10, v9
.LBB0_56:
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b32 v3, v9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s5, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_58
; %bb.57:
	v_lshl_add_u32 v9, v4, 2, 0
	ds_load_b32 v9, v9
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v9, v10, v9
                                        ; implicit-def: $vgpr10
.LBB0_58:                               ; %Flow336
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_60
; %bb.59:
	ds_load_b32 v9, v3 offset:8
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v10, v9
.LBB0_60:
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b32 v3, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3 offset:2048
                                        ; implicit-def: $vgpr9
	s_and_saveexec_b32 s5, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_62
; %bb.61:
	v_lshl_add_u32 v9, v5, 2, 0
	ds_load_b32 v9, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v9, v10, v9
                                        ; implicit-def: $vgpr10
.LBB0_62:                               ; %Flow335
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_64
; %bb.63:
	ds_load_b32 v9, v3 offset:2052
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v9, v10, v9
.LBB0_64:
	s_or_b32 exec_lo, exec_lo, s5
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v10, 0x7f, v0
	ds_store_b32 v3, v9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v9, v10, 2, 0
	v_and_b32_e32 v11, 64, v0
	ds_load_b32 v10, v3
	ds_load_b32 v9, v9
	v_cmp_eq_u32_e64 s5, 0, v11
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v12, v10, v9
	v_max_i32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v9, v9, v12, s5
	v_cmp_ne_u32_e64 s5, 0, v11
                                        ; implicit-def: $vgpr11
	ds_store_b32 v3, v9 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3 offset:2048
	v_and_b32_e32 v9, 0x3df, v0
	s_and_saveexec_b32 s6, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_66
; %bb.65:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v11, v9, 2, 0
	ds_load_b32 v11, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v10, v11
                                        ; implicit-def: $vgpr10
.LBB0_66:                               ; %Flow334
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_68
; %bb.67:
	ds_load_b32 v11, v3 offset:2176
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v10, v11
.LBB0_68:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s6, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_70
; %bb.69:
	v_lshl_add_u32 v10, v8, 2, 0
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v11, v10
                                        ; implicit-def: $vgpr11
.LBB0_70:                               ; %Flow333
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_72
; %bb.71:
	ds_load_b32 v10, v3 offset:64
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v11, v10
.LBB0_72:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3 offset:2048
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s6, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_74
; %bb.73:
	v_lshl_add_u32 v10, v7, 2, 0
	ds_load_b32 v10, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v11, v10
                                        ; implicit-def: $vgpr11
.LBB0_74:                               ; %Flow332
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_76
; %bb.75:
	ds_load_b32 v10, v3 offset:2080
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v11, v10
.LBB0_76:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s6, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_78
; %bb.77:
	v_lshl_add_u32 v10, v6, 2, 0
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v11, v10
                                        ; implicit-def: $vgpr11
.LBB0_78:                               ; %Flow331
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_80
; %bb.79:
	ds_load_b32 v10, v3 offset:16
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v11, v10
.LBB0_80:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3 offset:2048
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s6, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_82
; %bb.81:
	v_lshl_add_u32 v10, v4, 2, 0
	ds_load_b32 v10, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v11, v10
                                        ; implicit-def: $vgpr11
.LBB0_82:                               ; %Flow330
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_84
; %bb.83:
	ds_load_b32 v10, v3 offset:2056
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v11, v10
.LBB0_84:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s6, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_86
; %bb.85:
	v_lshl_add_u32 v10, v5, 2, 0
	ds_load_b32 v10, v10
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v10, v11, v10
                                        ; implicit-def: $vgpr11
.LBB0_86:                               ; %Flow329
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_88
; %bb.87:
	ds_load_b32 v10, v3 offset:4
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v10, v11, v10
.LBB0_88:
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v11, 0xff, v0
	ds_store_b32 v3, v10 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v10, v11, 2, 0
	v_and_b32_e32 v12, 0x80, v0
	ds_load_b32 v11, v3 offset:2048
	ds_load_b32 v10, v10 offset:2048
	v_cmp_eq_u32_e64 s6, 0, v12
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v13, v11, v10
	v_max_i32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v10, v13, s6
	v_cmp_ne_u32_e64 s6, 0, v12
                                        ; implicit-def: $vgpr12
	ds_store_b32 v3, v10
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3
	v_and_b32_e32 v10, 0x3bf, v0
	s_and_saveexec_b32 s7, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_90
; %bb.89:
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v12, v10, 2, 0
	ds_load_b32 v12, v12
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v12, v11, v12
                                        ; implicit-def: $vgpr11
.LBB0_90:                               ; %Flow328
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_92
; %bb.91:
	ds_load_b32 v12, v3 offset:256
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v12, v11, v12
.LBB0_92:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v12 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3 offset:2048
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_94
; %bb.93:
	v_lshl_add_u32 v11, v9, 2, 0
	ds_load_b32 v11, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_94:                               ; %Flow327
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_96
; %bb.95:
	ds_load_b32 v11, v3 offset:2176
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_98
; %bb.97:
	v_lshl_add_u32 v11, v8, 2, 0
	ds_load_b32 v11, v11
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_98:                               ; %Flow326
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_100
; %bb.99:
	ds_load_b32 v11, v3 offset:64
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_100:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3 offset:2048
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_102
; %bb.101:
	v_lshl_add_u32 v11, v7, 2, 0
	ds_load_b32 v11, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_102:                              ; %Flow325
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_104
; %bb.103:
	ds_load_b32 v11, v3 offset:2080
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_104:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_106
; %bb.105:
	v_lshl_add_u32 v11, v6, 2, 0
	ds_load_b32 v11, v11
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_106:                              ; %Flow324
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_108
; %bb.107:
	ds_load_b32 v11, v3 offset:16
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_108:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3 offset:2048
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_110
; %bb.109:
	v_lshl_add_u32 v11, v4, 2, 0
	ds_load_b32 v11, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_110:                              ; %Flow323
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_112
; %bb.111:
	ds_load_b32 v11, v3 offset:2056
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_112:
	s_or_b32 exec_lo, exec_lo, s7
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s7
	s_cbranch_execz .LBB0_114
; %bb.113:
	v_lshl_add_u32 v11, v5, 2, 0
	ds_load_b32 v11, v11
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v11
                                        ; implicit-def: $vgpr12
.LBB0_114:                              ; %Flow322
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_116
; %bb.115:
	ds_load_b32 v11, v3 offset:4
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v11
.LBB0_116:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt lgkmcnt(0)
	v_xor_b32_e32 v12, 0x1ff, v0
	ds_store_b32 v3, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v11, v12, 2, 0
	v_and_b32_e32 v13, 0x100, v0
	ds_load_b32 v12, v3 offset:2048
	ds_load_b32 v11, v11 offset:2048
	v_cmp_eq_u32_e64 s7, 0, v13
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v14, v12, v11
	v_max_i32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v11, v11, v14, s7
	ds_store_b32 v3, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v3
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s7, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s7
	s_cbranch_execz .LBB0_118
; %bb.117:
	v_and_b32_e32 v0, 0x37f, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v0, 2, 0
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v11, v12, v0
                                        ; implicit-def: $vgpr12
.LBB0_118:                              ; %Flow321
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_120
; %bb.119:
	ds_load_b32 v0, v3 offset:512
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v11, v12, v0
.LBB0_120:
	s_or_b32 exec_lo, exec_lo, s6
	ds_store_b32 v3, v11 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v11, v3 offset:2048
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s6, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s5, exec_lo, s6
	s_cbranch_execz .LBB0_122
; %bb.121:
	v_lshl_add_u32 v0, v10, 2, 0
	ds_load_b32 v0, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v11, v0
                                        ; implicit-def: $vgpr11
.LBB0_122:                              ; %Flow319
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_124
; %bb.123:
	ds_load_b32 v0, v3 offset:2304
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v11, v0
.LBB0_124:
	s_or_b32 exec_lo, exec_lo, s5
	ds_store_b32 v3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v10, v3
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s5
	s_cbranch_execz .LBB0_126
; %bb.125:
	v_lshl_add_u32 v0, v9, 2, 0
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v10, v0
                                        ; implicit-def: $vgpr10
.LBB0_126:                              ; %Flow317
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_128
; %bb.127:
	ds_load_b32 v0, v3 offset:128
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v10, v0
.LBB0_128:
	s_or_b32 exec_lo, exec_lo, s4
	ds_store_b32 v3, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v9, v3 offset:2048
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s4
	s_cbranch_execz .LBB0_130
; %bb.129:
	v_lshl_add_u32 v0, v8, 2, 0
	ds_load_b32 v0, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v9, v0
                                        ; implicit-def: $vgpr9
.LBB0_130:                              ; %Flow315
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_132
; %bb.131:
	ds_load_b32 v0, v3 offset:2112
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v9, v0
.LBB0_132:
	s_or_b32 exec_lo, exec_lo, s3
	ds_store_b32 v3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v8, v3
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s3
	s_cbranch_execz .LBB0_134
; %bb.133:
	v_lshl_add_u32 v0, v7, 2, 0
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v8, v0
                                        ; implicit-def: $vgpr8
.LBB0_134:                              ; %Flow313
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_136
; %bb.135:
	ds_load_b32 v0, v3 offset:32
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v8, v0
.LBB0_136:
	s_or_b32 exec_lo, exec_lo, s2
	ds_store_b32 v3, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v7, v3 offset:2048
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s2, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s2
	s_cbranch_execz .LBB0_138
; %bb.137:
	v_lshl_add_u32 v0, v6, 2, 0
	ds_load_b32 v0, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v7, v0
                                        ; implicit-def: $vgpr7
.LBB0_138:                              ; %Flow311
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_140
; %bb.139:
	ds_load_b32 v0, v3 offset:2064
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v7, v0
.LBB0_140:
	s_or_b32 exec_lo, exec_lo, s1
	ds_store_b32 v3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v6, v3
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_142
; %bb.141:
	v_lshl_add_u32 v0, v4, 2, 0
	ds_load_b32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v6, v0
                                        ; implicit-def: $vgpr6
.LBB0_142:                              ; %Flow309
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_144
; %bb.143:
	ds_load_b32 v0, v3 offset:8
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v6, v0
.LBB0_144:
	s_or_b32 exec_lo, exec_lo, s0
	ds_store_b32 v3, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v3 offset:2048
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_146
; %bb.145:
	v_lshl_add_u32 v0, v5, 2, 0
	ds_load_b32 v0, v0 offset:2048
	s_waitcnt lgkmcnt(0)
	v_max_i32_e32 v0, v4, v0
                                        ; implicit-def: $vgpr4
.LBB0_146:                              ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_148
; %bb.147:
	ds_load_b32 v0, v3 offset:2052
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v0, v4, v0
.LBB0_148:
	s_or_b32 exec_lo, exec_lo, s0
	ds_store_b32 v3, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v3, v3
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6tsort1PiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6tsort1PiS_, .Lfunc_end0-_Z6tsort1PiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4788
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6tsort1PiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6tsort1PiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
