__global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
    //Have circularly rotating system of 3 buffers
    extern __shared__ float x[]; //Circular buffer
    int off = 0;
    int upoff = 0;

    //Other local variables
    int i, k;
    int i1, i2, j1, j2;
    int thisi, thisj;
    int idx;
    float val, score;
    int ci = blockIdx.x;
    int cj = blockIdx.y;

    //Figure out K (number of batches)
    int K = diagLenPow2 >> 9;
    if (K == 0) {
        K = 1;
    }

    //Initialize all buffer elements to -1
    for (k = 0; k < K; k++) {
        for (off = 0; off < 3; off++) {
            if (512*k + threadIdx.x < diagLen) {
                x[512*k + threadIdx.x + off*diagLen] = -1;
            }
        }
    }
    off = 0;

    //Process each diagonal
    for (i = 0; i < N + M - 1; i++) {
        //Figure out the bounds of this diagonal
        i1 = i;
        j1 = 0;
        upoff = -1;
        if (i1 >= M) {
            i1 = M-1;
            j1 = i - (M-1);
            upoff = 0;
        }
        j2 = i;
        i2 = 0;
        if (j2 >= N) {
            j2 = N-1;
            i2 = i - (N-1);
        }
        //Update each batch
        for (k = 0; k < K; k++) {
            idx = k*512 + threadIdx.x;
            if (idx >= diagLen) {
                break;
            }
            thisi = i1 - idx;
            thisj = j1 + idx;
            if (thisi < i2 || thisj > j2) {
                x[off*diagLen + idx] = -1;
                continue;
            }
            if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
                x[off*diagLen + idx] = -1;
                continue;
            }
            val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
            if (val < 0) {
                val *= -1;
            }
            score = -1;
            //Above
            if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
                if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
                    score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
                }
            }
            if (idx + upoff >= 0 && thisj > 0) {
                //Left
                if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
                    if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
                        score = x[((off+1)%3)*diagLen + idx + upoff] + val;
                    }
                }
            }
            if (i1 == M-1 && j1 > 1) {
                upoff = 1;
            }
            if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
                if (idx + upoff >= 0 && thisi > 0) {
                    //Diagonal
                    if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
                        if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
                            score = x[((off+2)%3)*diagLen + idx + upoff] + val;
                        }
                    }
                }
            }
            if (score == -1) {
                score = val;
            }
            x[off*diagLen + idx] = score;
            if (i == N + M - 2) {
                CSM[ci*N + cj] = score;
            }
        }
        off = (off + 2) % 3; //Cycle buffers
        __syncthreads();
    }
}

	.file	"tmpxft_0033e576_00000000-6_DTWSSMGPU.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
	.type	_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, @function
_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z6DTWSSMPfS_S_iiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, .-_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
	.globl	_Z6DTWSSMPfS_S_iiii
	.type	_Z6DTWSSMPfS_S_iiii, @function
_Z6DTWSSMPfS_S_iiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
	.cfi_endproc
.LFE2033:
	.size	_Z6DTWSSMPfS_S_iiii, .-_Z6DTWSSMPfS_S_iiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6DTWSSMPfS_S_iiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6DTWSSMPfS_S_iiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
    //Have circularly rotating system of 3 buffers
    extern __shared__ float x[]; //Circular buffer
    int off = 0;
    int upoff = 0;

    //Other local variables
    int i, k;
    int i1, i2, j1, j2;
    int thisi, thisj;
    int idx;
    float val, score;
    int ci = blockIdx.x;
    int cj = blockIdx.y;

    //Figure out K (number of batches)
    int K = diagLenPow2 >> 9;
    if (K == 0) {
        K = 1;
    }

    //Initialize all buffer elements to -1
    for (k = 0; k < K; k++) {
        for (off = 0; off < 3; off++) {
            if (512*k + threadIdx.x < diagLen) {
                x[512*k + threadIdx.x + off*diagLen] = -1;
            }
        }
    }
    off = 0;

    //Process each diagonal
    for (i = 0; i < N + M - 1; i++) {
        //Figure out the bounds of this diagonal
        i1 = i;
        j1 = 0;
        upoff = -1;
        if (i1 >= M) {
            i1 = M-1;
            j1 = i - (M-1);
            upoff = 0;
        }
        j2 = i;
        i2 = 0;
        if (j2 >= N) {
            j2 = N-1;
            i2 = i - (N-1);
        }
        //Update each batch
        for (k = 0; k < K; k++) {
            idx = k*512 + threadIdx.x;
            if (idx >= diagLen) {
                break;
            }
            thisi = i1 - idx;
            thisj = j1 + idx;
            if (thisi < i2 || thisj > j2) {
                x[off*diagLen + idx] = -1;
                continue;
            }
            if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
                x[off*diagLen + idx] = -1;
                continue;
            }
            val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
            if (val < 0) {
                val *= -1;
            }
            score = -1;
            //Above
            if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
                if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
                    score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
                }
            }
            if (idx + upoff >= 0 && thisj > 0) {
                //Left
                if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
                    if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
                        score = x[((off+1)%3)*diagLen + idx + upoff] + val;
                    }
                }
            }
            if (i1 == M-1 && j1 > 1) {
                upoff = 1;
            }
            if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
                if (idx + upoff >= 0 && thisi > 0) {
                    //Diagonal
                    if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
                        if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
                            score = x[((off+2)%3)*diagLen + idx + upoff] + val;
                        }
                    }
                }
            }
            if (score == -1) {
                score = val;
            }
            x[off*diagLen + idx] = score;
            if (i == N + M - 2) {
                CSM[ci*N + cj] = score;
            }
        }
        off = (off + 2) % 3; //Cycle buffers
        __syncthreads();
    }
}

	.text
	.file	"DTWSSMGPU.hip"
	.globl	_Z21__device_stub__DTWSSMPfS_S_iiii # -- Begin function _Z21__device_stub__DTWSSMPfS_S_iiii
	.type	_Z21__device_stub__DTWSSMPfS_S_iiii,@function
_Z21__device_stub__DTWSSMPfS_S_iiii:    # @_Z21__device_stub__DTWSSMPfS_S_iiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6DTWSSMPfS_S_iiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__DTWSSMPfS_S_iiii, .Lfunc_end0-_Z21__device_stub__DTWSSMPfS_S_iiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6DTWSSMPfS_S_iiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6DTWSSMPfS_S_iiii,@object     # @_Z6DTWSSMPfS_S_iiii
	.section	.rodata,"a",@progbits
	.globl	_Z6DTWSSMPfS_S_iiii
	.p2align	3, 0x0
_Z6DTWSSMPfS_S_iiii:
	.quad	_Z21__device_stub__DTWSSMPfS_S_iiii
	.size	_Z6DTWSSMPfS_S_iiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6DTWSSMPfS_S_iiii"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__DTWSSMPfS_S_iiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6DTWSSMPfS_S_iiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6DTWSSMPfS_S_iiii     ; -- Begin function _Z6DTWSSMPfS_S_iiii
	.globl	_Z6DTWSSMPfS_S_iiii
	.p2align	8
	.type	_Z6DTWSSMPfS_S_iiii,@function
_Z6DTWSSMPfS_S_iiii:                    ; @_Z6DTWSSMPfS_S_iiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s7, 9
	s_cmpk_gt_u32 s7, 0x1ff
	s_cselect_b32 s7, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s7, 1
	s_cselect_b32 s12, -1, 0
	s_and_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_7
; %bb.1:                                ; %.preheader198.lr.ph
	v_lshl_add_u32 v1, v0, 2, 0
	v_mov_b32_e32 v2, -1.0
	s_mov_b32 s2, 0
	s_lshl_b32 s3, s6, 2
.LBB0_2:                                ; %.preheader198
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_lshl_add_u32 v3, s2, 9, v0
	s_mov_b32 s8, 3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s6, v3
	v_mov_b32_e32 v3, v1
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	ds_store_b32 v3, v2
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v3, s3, v3
	s_add_i32 s8, s8, -1
	s_cmp_lg_u32 s8, 0
	s_cbranch_scc1 .LBB0_3
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, 0x800, v1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s7
	s_cbranch_scc0 .LBB0_2
.LBB0_7:                                ; %.preheader
	s_add_i32 s20, s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_i32 s20, 2
	s_cbranch_scc1 .LBB0_46
; %bb.8:                                ; %.lr.ph206
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	s_mul_i32 s1, s14, s5
	v_sub_nc_u32_e32 v1, 0, v0
	s_add_i32 s22, s1, s15
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, -1.0
	s_ashr_i32 s23, s22, 31
	s_add_i32 s13, s20, -1
	s_lshl_b64 s[22:23], s[22:23], 2
	s_add_i32 s16, s4, -1
	s_add_i32 s17, s5, -1
	s_add_i32 s20, s20, -2
	s_mul_i32 s18, s14, s4
	s_mul_i32 s19, s15, s5
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s22
	s_addc_u32 s3, s3, s23
	s_sub_i32 s21, 0, s14
	s_mov_b32 s22, 0
.LBB0_9:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr23
	s_cbranch_vccnz .LBB0_11
; %bb.10:                               ; %.._crit_edge_crit_edge
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_add_i32 s1, s0, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s23, s1, 0xaaaaaaab
	s_lshr_b32 s23, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s23, s23, 3
	s_sub_i32 s23, s1, s23
	s_mov_b32 s1, 0
.LBB0_11:                               ; %Flow257
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_45
; %bb.12:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_sub_i32 s1, s22, s16
	s_cmp_lt_i32 s22, s4
	v_mad_u64_u32 v[6:7], null, s0, s6, v[0:1]
	s_cselect_b32 s23, -1, 0
	v_mov_b32_e32 v7, v0
	v_cndmask_b32_e64 v4, 0, -1, s23
	s_and_b32 s23, s23, exec_lo
	s_cselect_b32 s24, 0, s1
	s_cselect_b32 s1, s22, s16
	s_sub_i32 s23, s22, s17
	s_cmp_lt_i32 s22, s5
	v_add_nc_u32_e32 v5, s1, v1
	s_cselect_b32 s25, 0, s23
	s_cselect_b32 s26, s22, s17
	s_add_i32 s23, s0, 1
	v_lshl_add_u32 v6, v6, 2, 0
	s_cmp_lg_u32 s23, 3
	s_mov_b32 s27, 0
	s_cselect_b32 s28, s23, 0
	s_cmp_eq_u32 s1, s16
	s_mul_i32 s28, s28, s6
	s_cselect_b32 s23, -1, 0
	s_cmp_gt_i32 s24, 1
	s_mov_b32 s38, s7
	s_cselect_b32 s29, -1, 0
	s_add_i32 s30, s0, 2
	s_and_b32 s29, s23, s29
	s_mul_hi_u32 s31, s30, 0xaaaaaaab
                                        ; implicit-def: $sgpr39
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s31, s31, 1
	s_mul_i32 s31, s31, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s23, s30, s31
	s_cmp_eq_u32 s22, s20
	s_mul_i32 s30, s23, s6
	s_cselect_b32 s31, -1, 0
	s_add_i32 s33, s21, s1
	s_sub_i32 s35, s15, s24
	s_add_i32 s34, s33, -1
	s_add_i32 s36, s35, 1
	s_add_i32 s37, s19, s24
.LBB0_13:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_or_b32 s39, s39, exec_lo
	s_mov_b32 s40, exec_lo
	v_cmpx_gt_i32_e64 s6, v7
	s_cbranch_execz .LBB0_43
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_nc_u32_e32 v11, s24, v7
	v_cmp_le_i32_e32 vcc_lo, s25, v5
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s26, v11
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s41, exec_lo, s1
	s_cbranch_execz .LBB0_40
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=2
	v_cmp_lt_i32_e32 vcc_lo, s14, v5
	v_cmp_lt_i32_e64 s0, s15, v11
	s_mov_b32 s42, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s1, s0, -1
	s_and_saveexec_b32 s43, s0
; %bb.16:                               ;   in Loop: Header=BB0_13 Depth=2
	v_cmp_le_i32_e32 vcc_lo, s14, v5
	v_cmp_le_i32_e64 s0, s15, v11
	s_and_not1_b32 s1, s1, exec_lo
	s_mov_b32 s42, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s1, s1, s0
; %bb.17:                               ; %Flow251
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s43
                                        ; implicit-def: $vgpr8
	s_and_saveexec_b32 s43, s1
	s_cbranch_execz .LBB0_37
; %bb.18:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_nc_u32_e32 v8, s18, v5
	v_add_nc_u32_e32 v12, s37, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v9, 31, v8
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, 0, v5
	global_load_b32 v9, v[8:9], off
	global_load_b32 v10, v[12:13], off
	v_add_nc_u32_e32 v8, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v12, 1, v8
	v_cmp_gt_i32_e64 s0, s13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_and_b32 s0, vcc_lo, s0
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v9, v9, v10 :: v_dual_mov_b32 v10, -1.0
	v_cmp_gt_f32_e64 s1, 0, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v9, v9, -v9, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_22
; %bb.19:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add3_u32 v10, s28, v7, v4
	s_mov_b32 s44, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v10, v10, 2, 0
	ds_load_b32 v12, v10 offset:4
	v_mov_b32_e32 v10, -1.0
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_f32_e32 -1.0, v12
; %bb.20:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_f32_e32 v10, v9, v12
; %bb.21:                               ; %Flow250
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s44
.LBB0_22:                               ;   in Loop: Header=BB0_13 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_lt_i32_e64 s0, -1, v8
	v_cmp_lt_i32_e64 s1, 0, v11
	s_and_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s44, s0
	s_cbranch_execz .LBB0_26
; %bb.23:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add3_u32 v8, s28, v7, v4
	s_mov_b32 s45, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v8, v8, 2, 0
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_f32_e32 -1.0, v8
; %bb.24:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_f32_e32 v8, v9, v8
	v_cmp_eq_f32_e64 s0, -1.0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s1, v8, v10
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cndmask_b32_e64 v10, v10, v8, s0
; %bb.25:                               ; %Flow249
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s45
.LBB0_26:                               ;   in Loop: Header=BB0_13 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s44
	v_cmp_ne_u32_e64 s0, s33, v7
	v_cmp_ne_u32_e64 s1, s36, v7
	v_cndmask_b32_e64 v8, v4, 1, s29
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s44, s0
	s_cbranch_execz .LBB0_34
; %bb.27:                               ;   in Loop: Header=BB0_13 Depth=2
	v_cmp_ne_u32_e64 s0, s34, v7
	v_cmp_ne_u32_e64 s1, s35, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_33
; %bb.28:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_nc_u32_e32 v11, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s0, -1, v11
	s_and_b32 s0, s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s45, s0
	s_cbranch_execz .LBB0_32
; %bb.29:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add3_u32 v11, s30, v8, v7
	s_mov_b32 s46, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v11, v11, 2, 0
	ds_load_b32 v11, v11
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_f32_e32 -1.0, v11
; %bb.30:                               ;   in Loop: Header=BB0_13 Depth=2
	v_add_f32_e32 v11, v9, v11
	v_cmp_eq_f32_e32 vcc_lo, -1.0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, v11, v10
	s_or_b32 vcc_lo, vcc_lo, s0
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
; %bb.31:                               ; %Flow246
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s46
.LBB0_32:                               ; %Flow247
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s45
.LBB0_33:                               ; %Flow248
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_34:                               ;   in Loop: Header=BB0_13 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s44
	v_cmp_eq_f32_e32 vcc_lo, -1.0, v10
	v_cndmask_b32_e32 v9, v10, v9, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s31
	ds_store_b32 v6, v9
	s_cbranch_vccnz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_13 Depth=2
	global_store_b32 v2, v9, s[2:3]
.LBB0_36:                               ; %Flow
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_and_not1_b32 s42, s42, exec_lo
.LBB0_37:                               ; %Flow252
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s43
	s_and_saveexec_b32 s0, s42
	s_cbranch_execz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_13 Depth=2
	v_mov_b32_e32 v8, v4
	ds_store_b32 v6, v3
.LBB0_39:                               ; %Flow253
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr4
.LBB0_40:                               ; %Flow254
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_and_not1_saveexec_b32 s0, s41
	s_cbranch_execz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_13 Depth=2
	v_mov_b32_e32 v8, v4
	ds_store_b32 v6, v3
.LBB0_42:                               ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s38, s38, -1
	v_dual_mov_b32 v4, v8 :: v_dual_add_nc_u32 v5, 0xfffffe00, v5
	s_cmp_eq_u32 s38, 0
	v_add_nc_u32_e32 v7, 0x200, v7
	s_cselect_b32 s0, -1, 0
	v_add_nc_u32_e32 v6, 0x800, v6
	s_and_not1_b32 s1, s39, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s39, s1, s0
.LBB0_43:                               ; %Flow255
                                        ;   in Loop: Header=BB0_13 Depth=2
	s_or_b32 exec_lo, exec_lo, s40
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s39
	s_or_b32 s27, s0, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_13
; %bb.44:                               ; %Flow256
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
.LBB0_45:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_add_i32 s22, s22, 1
	s_mov_b32 s0, s23
	s_cmp_lg_u32 s22, s13
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_9
.LBB0_46:                               ; %._crit_edge207
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6DTWSSMPfS_S_iiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 47
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6DTWSSMPfS_S_iiii, .Lfunc_end0-_Z6DTWSSMPfS_S_iiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1408
; NumSgprs: 49
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 49
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 40
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6DTWSSMPfS_S_iiii
    .private_segment_fixed_size: 0
    .sgpr_count:     49
    .sgpr_spill_count: 0
    .symbol:         _Z6DTWSSMPfS_S_iiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
