#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <complex.h>
#include <cuda_runtime.h>
#include <utility>
#include <sys/time.h>
#define K 3
#define BLCH 8
#define BLCW 32

int compute(float *img, float *f, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW) {

    int inm1, inm2, inm3, inm4, inf, ind1, ind2, ind3;
    inm1 = 0;
    inf = 0;
    ind1 = 0;

    for (int mi = 0; mi < imgN; mi++){
        ind1 += convW * convH;
        inm1 += imgW * imgH;
        for (int mj = 0; mj < convH; mj++){
            ind2 = ind1 + convW * mj;
            inm2 = inm1 + imgW * mj;
            for (int mk = 0; mk < convW; mk++){
                ind3 = ind2 + mk;
                inm3 = inm2 + mk;
                for (int fi = 0; fi < nF; fi++){
                    inm4 = inm3 + imgW * fi;
                    inf = ind3*nF*nF + fi*nF;
                    for (int fj = 0; fj < nF; fj++){
                        out[ind3] += img[inm4+fj] * f[inf+fj];
                    }
                }
            }
        }
    }
    return 0;
}

int compute_csr(float *img, float *f_csr, int *pos, int *coor, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW) {

    int inm1, inm2, inm3, inm4, inf, inf1, inf2, ind1, ind2, ind3;

    for (int mi = 0; mi < imgN; mi++){
        ind1 = mi * convW * convH;
        inm1 = mi * imgW * imgH;
        for (int mj = 0; mj < convH; mj++){
            ind2 = ind1 + convW * mj;
            inm2 = inm1 + imgW * mj;
            for (int mk = 0; mk < convW; mk++){
                ind3 = ind2 + mk;
                inm3 = inm2 + mk;
                inf = nF*nF*ind3;
                for (int fi = 0; fi < nF; fi++){
                    inf1 = pos[fi+inf];
                    inf2 = pos[fi+1+inf];
                    inm4 = inm3 + fi*imgW;
                    for (int fj = inf1; fj < inf2; fj++){
                        out[ind3] += img[inm4+coor[fj]] * f_csr[fj+inf];
                    }

                }
            }
        }
    }
    return 0;
}

__global__ void compute_gpu(float *img, float *f, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW){
    int idY = blockDim.y * blockIdx.y + threadIdx.y;
    int idX = blockDim.x * blockIdx.x + threadIdx.x;
    
    int inm1, inm2, inm3, inm4, inf, ind1, ind2, ind3;
    inm1 = 0;
    inf = 0;
    ind1 = 0;

    for (int mi = 0; mi < imgN; mi++){
        ind1 += convW * convH;
        inm1 += imgW * imgH;
        if (idX < convH && idY < convW){
            ind2 = ind1 + convW * idX;
            inm2 = inm1 + imgW * idX;
            ind3 = ind2 + idY;
            inm3 = inm2 + idY;
            for (int fi = 0; fi < nF; fi++){
               inm4 = inm3 + imgW * fi;
               inf = ind3*nF*nF + fi*nF;
               for (int fj = 0; fj < nF; fj++){
                  out[ind3] += img[inm4+fj] * f[inf+fj];
               }
             }
         }
    }
}

__global__ void compute_gpu_csr(float *img, float *f_csr, int *pos, int *coor, float *out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW){
    
    int idX = blockDim.x * blockIdx.x + threadIdx.x;
    int idY = blockDim.y * blockIdx.y + threadIdx.y;
    
    int con, imgg, inm1, inm2, inm3, inm4, inf, inf1, inf2, ind1, ind2, ind3;

    for (int mi = 0; mi < imgN; mi++){
        ind1 = mi * convW * convH;
        inm1 = mi * imgW * imgH;
        if (idX < convH && idY < convW){
            ind2 = ind1 + convW * idX;
            inm2 = inm1 + imgW * idX;
            ind3 = ind2 + idY;
            inm3 = inm2 + idY;
            inf = nF*nF*ind3;
            for (int fi = 0; fi < nF; fi++){
                inf1 = pos[fi+inf];
                inf2 = pos[fi+1+inf];
                inm4 = inm3 + fi*imgW;
                for (int fj = inf1; fj < inf2; fj++){
                    out[ind3] += img[inm4+coor[fj]] * f_csr[fj+inf];
                }

            }
            
        }
    }
}



int main(int argc, char **argv){

    //create parameters
    int imgH = 2048;
    int imgW = 2048;
    int imgN = 10;
    int blcH = BLCH;
    int blcW = BLCW;
    int k    = K;
    int s    = 1;
    int nB   = (imgH * imgW) / (blcH * blcW);
    //int nT   = (blcW+k) * (blcH+k);
    int nT   = blcW * blcH;
    int imgDims = imgH * imgW * imgN;
    int imgSize = imgDims * sizeof(float);
    
    int num=0;
    srand (time(NULL));
    // create host array that can hold pixel intensity values
    float *h_img = new float[imgDims];
    for(int i=0; i<imgDims; i++){
        h_img[i] = (float)(rand()%10485)/10485;
    }
    
    
    // create host and device array that holds the convoluted matrix
    int convH = ( (imgH - k) / s ) + 1;
    int convW = ( (imgW - k) / s ) + 1;
    int convDims = convH * convW;
    int convSize = convDims * sizeof(float);
    float *h_convolved = new float[convDims];
    for(int i=0; i<convDims; i++){
        h_convolved[i] = 0.0;
    }

    // create filter and copy to constant memory
    int filterDims = k * k * convDims;
    int filterSize = filterDims * sizeof(float);
    float *filter = new float[filterDims];
    num = 0;
    for(int i=0; i<filterDims; i++){
        if(rand()/40 == 0){
            num++;
            filter[i] = (float)(rand()%10485)/10485;
        }
        else{
            filter[i] = 0;
        }   
    }
    
    //create index arrays of CSR
    int *pos = new int[(k+1)*convDims];
    int *coor = new int[num];
    float *h_fcsr = new float[num];
    int csrposSize = (k+1)*convDims*sizeof(int);
    int csrcooSize = num*sizeof(int);
    int fSize = num*sizeof(float);
    for(int ki=0; ki<convDims; ki++){
        pos[0+ki*(k+1)] = 0;
        int index_p=0;
        int z = ki*k*k;
        for(int i=0; i<k; i++){
            for (int j=0; j<k; j++){
                if (filter[i*k+j+z] != 0){
                    coor[index_p] = j;
                    h_fcsr[index_p] = filter[i*k+j+z];
                    index_p++;
                }
            }
        pos[i+1+ki*(k+1)] = index_p;
        }
    }


    // create device array that can hold pixel intensity values in GPU GM
    float *d_img;
    float *d_convolved;
    float *d_filter;
    int *d_pos;
    int *d_coor;
    cudaMalloc((void **) &d_filter, fSize);
    cudaMemcpyToSymbol(d_filter, h_fcsr, fSize, cudaMemcpyHostToDevice);
    cudaMalloc((void **) &d_convolved, convSize);
    cudaMemcpy(d_convolved, h_convolved, convSize, cudaMemcpyHostToDevice);
    cudaMalloc((void **) &d_img, imgSize);
    cudaMemcpy(d_img, h_img, imgSize, cudaMemcpyHostToDevice);
    cudaMalloc((void **) &d_pos, csrposSize);
    cudaMemcpy(d_pos, pos, csrposSize, cudaMemcpyHostToDevice);
    cudaMalloc((void **) &d_coor, csrcooSize);
    cudaMemcpy(d_coor, coor, csrcooSize, cudaMemcpyHostToDevice);
    
    struct timeval starttime, endtime;
    double elapsed = 0.0;
    for (int i = 0; i<10000; i++){
        gettimeofday(&starttime,NULL);
        // call the kernel
        //compute_gpu<<<nB, nT>>>(d_img, d_convolved, blcH, blcW, imgH, imgW, imgN, k, convH, convW);
        compute_gpu_csr<<<nB, nT>>>(d_img, d_filter, d_pos, d_coor, d_convolved, blcH, blcW, imgH, imgW, imgN, k, convH, convW);
        gettimeofday(&endtime,NULL);
        elapsed += ((endtime.tv_sec-starttime.tv_sec)*1000000 + endtime.tv_usec-starttime.tv_usec)/1000000.0;
    }
    
    cudaMemcpy(h_convolved, d_convolved, convSize, cudaMemcpyDeviceToHost);
    cudaDeviceReset();
    printf("Input imgH: %d imgW: %d imgN: %d\n", imgH, imgW, imgN);
    printf("Tile width: %d height: %d\n", blcW, blcH);
    printf("Block number: %d, block size: %d \n", nB, nT);
    printf("time: %f \n", elapsed);
    delete h_img;
    delete h_convolved;
    delete pos;
    delete h_fcsr;
    delete coor;
    return 0;
}

	.file	"tmpxft_003baa34_00000000-6_con_filter_spa.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3941:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3941:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7computePfS_S_iiiiiiii
	.type	_Z7computePfS_S_iiiiiiii, @function
_Z7computePfS_S_iiiiiiii:
.LFB3936:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r8
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	56(%rsp), %rcx
	movl	80(%rsp), %eax
	imull	88(%rsp), %eax
	imull	%ecx, %r9d
	movl	72(%rsp), %edx
	movslq	%r9d, %r9
	salq	$2, %r9
	leaq	(%rdi,%r9), %rbx
	movq	%rbx, -48(%rsp)
	movl	%eax, %ebx
	cltq
	imull	%edx, %ebx
	salq	$2, %rax
	leaq	(%r8,%rax), %rdi
	movq	%rdi, -32(%rsp)
	movl	%ebx, -16(%rsp)
	leaq	0(,%rcx,4), %rbx
	movslq	88(%rsp), %rcx
	movq	%rbx, -56(%rsp)
	movl	88(%rsp), %ebx
	leaq	0(,%rcx,4), %rdi
	movslq	%edx, %rcx
	imull	%edx, %ebx
	movq	%rdi, -8(%rsp)
	movl	-16(%rsp), %edi
	movl	%edi, -36(%rsp)
	movl	%ebx, -12(%rsp)
	leaq	0(,%rcx,4), %rbx
	xorl	%ecx, %ecx
	movq	%rbx, -24(%rsp)
	movl	%ecx, -40(%rsp)
.L3:
	movl	-40(%rsp), %ebx
	cmpl	64(%rsp), %ebx
	jge	.L15
	movq	-48(%rsp), %rdi
	movq	-32(%rsp), %r11
	xorl	%r8d, %r8d
	movl	-36(%rsp), %r10d
	movq	%rdi, -64(%rsp)
.L8:
	cmpl	80(%rsp), %r8d
	jge	.L16
	movq	-64(%rsp), %rbp
	movq	%r11, %rdi
	movl	%r10d, %r12d
	xorl	%ebx, %ebx
.L7:
	cmpl	88(%rsp), %ebx
	jge	.L17
	movl	%r12d, %ecx
	movq	%rbp, %r14
	xorl	%r13d, %r13d
	imull	%edx, %ecx
	movslq	%ecx, %rcx
	leaq	(%rsi,%rcx,4), %r15
.L4:
	cmpl	%edx, %r13d
	jge	.L18
	xorl	%ecx, %ecx
.L5:
	movss	(%r14,%rcx,4), %xmm0
	mulss	(%r15,%rcx,4), %xmm0
	incq	%rcx
	addss	(%rdi), %xmm0
	movss	%xmm0, (%rdi)
	cmpl	%ecx, %edx
	jg	.L5
	movq	-56(%rsp), %rcx
	incl	%r13d
	addq	%rcx, %r14
	movq	-24(%rsp), %rcx
	addq	%rcx, %r15
	jmp	.L4
.L18:
	incl	%ebx
	addq	$4, %rbp
	addl	%edx, %r12d
	addq	$4, %rdi
	jmp	.L7
.L17:
	movq	-56(%rsp), %rbx
	movl	-12(%rsp), %edi
	incl	%r8d
	addq	%rbx, -64(%rsp)
	movq	-8(%rsp), %rbx
	addl	%edi, %r10d
	addq	%rbx, %r11
	jmp	.L8
.L16:
	movl	-16(%rsp), %ecx
	incl	-40(%rsp)
	addq	%r9, -48(%rsp)
	addl	%ecx, -36(%rsp)
	addq	%rax, -32(%rsp)
	jmp	.L3
.L15:
	popq	%rbx
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3936:
	.size	_Z7computePfS_S_iiiiiiii, .-_Z7computePfS_S_iiiiiiii
	.globl	_Z11compute_csrPfS_PiS0_S_iiiiiiii
	.type	_Z11compute_csrPfS_PiS0_S_iiiiiiii, @function
_Z11compute_csrPfS_PiS0_S_iiiiiiii:
.LFB3937:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	88(%rsp), %eax
	imull	%eax, %eax
	movq	%rdx, -24(%rsp)
	movl	104(%rsp), %edx
	imull	96(%rsp), %edx
	movq	%rcx, -16(%rsp)
	movq	%rsi, -32(%rsp)
	movq	%rdi, -40(%rsp)
	movslq	%edx, %rcx
	imull	%eax, %edx
	movq	%r8, -104(%rsp)
	leaq	0(,%rcx,4), %rbx
	movq	%rbx, -64(%rsp)
	movl	72(%rsp), %ebx
	movslq	%edx, %rdx
	imull	64(%rsp), %ebx
	leaq	0(,%rdx,4), %rsi
	movslq	104(%rsp), %rdx
	movq	%rsi, -56(%rsp)
	leaq	0(,%rdx,4), %rdi
	movl	104(%rsp), %edx
	movl	%ebx, -44(%rsp)
	movq	%rdi, -80(%rsp)
	imull	%eax, %edx
	cltq
	salq	$2, %rax
	movq	%rax, -88(%rsp)
	xorl	%eax, %eax
	movslq	%edx, %rdx
	movl	%eax, -92(%rsp)
	leaq	0(,%rdx,4), %rbx
	movq	%rbx, -72(%rsp)
.L20:
	cmpl	80(%rsp), %r15d
	jge	.L31
	movl	-92(%rsp), %ebx
	movq	-104(%rsp), %r10
	movq	%r14, %r11
	xorl	%r9d, %r9d
.L21:
	cmpl	96(%rsp), %r9d
	jge	.L32
	movq	%r11, %rsi
	movq	%r10, %rcx
	xorl	%edx, %edx
.L27:
	cmpl	104(%rsp), %edx
	jge	.L33
	movq	-24(%rsp), %rax
	leal	(%rdx,%rbx), %r12d
	xorl	%ebp, %ebp
	leaq	(%rax,%rsi), %rdi
	movq	-32(%rsp), %rax
	addq	%rsi, %rax
	movq	%rax, -8(%rsp)
.L22:
	cmpl	88(%rsp), %ebp
	jge	.L34
	movl	4(%rdi), %eax
	incl	%ebp
	movl	%eax, -48(%rsp)
	movslq	(%rdi), %rax
.L23:
	cmpl	%eax, -48(%rsp)
	jle	.L35
	movq	-16(%rsp), %r8
	movl	(%r8,%rax,4), %r13d
	movq	-40(%rsp), %r8
	addl	%r12d, %r13d
	movslq	%r13d, %r13
	movss	(%r8,%r13,4), %xmm0
	movq	-8(%rsp), %r8
	mulss	(%r8,%rax,4), %xmm0
	incq	%rax
	addss	(%rcx), %xmm0
	movss	%xmm0, (%rcx)
	jmp	.L23
.L35:
	addq	$4, %rdi
	addl	72(%rsp), %r12d
	jmp	.L22
.L34:
	movq	-88(%rsp), %rax
	incl	%edx
	addq	$4, %rcx
	addq	%rax, %rsi
	jmp	.L27
.L33:
	movq	-80(%rsp), %rax
	incl	%r9d
	addl	72(%rsp), %ebx
	addq	%rax, %r10
	movq	-72(%rsp), %rax
	addq	%rax, %r11
	jmp	.L21
.L32:
	movq	-64(%rsp), %rax
	addq	%rax, -104(%rsp)
	incl	%r15d
	movq	-56(%rsp), %rax
	movl	-44(%rsp), %ecx
	addl	%ecx, -92(%rsp)
	addq	%rax, %r14
	jmp	.L20
.L31:
	popq	%rbx
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3937:
	.size	_Z11compute_csrPfS_PiS0_S_iiiiiiii, .-_Z11compute_csrPfS_PiS0_S_iiiiiiii
	.globl	_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii
	.type	_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii, @function
_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii:
.LFB3963:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z11compute_gpuPfS_S_iiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L36:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3963:
	.size	_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii, .-_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii
	.globl	_Z11compute_gpuPfS_S_iiiiiiii
	.type	_Z11compute_gpuPfS_S_iiiiiiii, @function
_Z11compute_gpuPfS_S_iiiiiiii:
.LFB3964:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z11compute_gpuPfS_S_iiiiiiiiPfS_S_iiiiiiii
	.cfi_endproc
.LFE3964:
	.size	_Z11compute_gpuPfS_S_iiiiiiii, .-_Z11compute_gpuPfS_S_iiiiiiii
	.globl	_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii
	.type	_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii, @function
_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii:
.LFB3965:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	56(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 256
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L41:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3965:
	.size	_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii, .-_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii
	.globl	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.type	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, @function
_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii:
.LFB3966:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii
	.cfi_endproc
.LFE3966:
	.size	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, .-_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC4:
	.string	"Input imgH: %d imgW: %d imgN: %d\n"
.LC5:
	.string	"Tile width: %d height: %d\n"
.LC6:
	.string	"Block number: %d, block size: %d \n"
.LC7:
	.string	"time: %f \n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3938:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%edi, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movl	$167772160, %edi
	call	_Znam@PLT
	movq	%rax, %r14
.L47:
	call	rand@PLT
	movl	$10485, %ecx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	divss	.LC2(%rip), %xmm0
	movss	%xmm0, (%r14,%rbx,4)
	incq	%rbx
	cmpq	$41943040, %rbx
	jne	.L47
	movl	$16744464, %edi
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	call	_Znam@PLT
	movl	$4186116, %ecx
	movq	%rax, (%rsp)
	movq	(%rsp), %rdi
	xorl	%eax, %eax
	rep stosl
	movl	$150700176, %edi
	call	_Znam@PLT
	movq	%rax, %r15
.L49:
	call	rand@PLT
	xorps	%xmm0, %xmm0
	addl	$39, %eax
	cmpl	$78, %eax
	ja	.L48
	call	rand@PLT
	movl	$10485, %ecx
	incl	%ebx
	cltd
	idivl	%ecx
	cvtsi2ssl	%edx, %xmm0
	divss	.LC2(%rip), %xmm0
.L48:
	movss	%xmm0, (%r15,%rbp,4)
	incq	%rbp
	cmpq	$37675044, %rbp
	jne	.L49
	movl	$66977856, %edi
	movslq	%ebx, %r12
	call	_Znam@PLT
	movq	%rax, %r13
	movabsq	$2305843009213693950, %rax
	cmpq	%r12, %rax
	jb	.L50
	salq	$2, %r12
	sall	$2, %ebx
	movq	%r12, %rdi
	call	_Znam@PLT
	movq	%r12, %rdi
	movq	%rax, %rbp
	call	_Znam@PLT
	movq	%r13, %rdx
	xorl	%r8d, %r8d
	xorl	%edi, %edi
	movq	%rax, %r12
	xorps	%xmm1, %xmm1
	jmp	.L51
.L50:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L69
	call	__cxa_throw_bad_array_new_length@PLT
.L51:
	xorl	%ecx, %ecx
	leaq	(%r15,%r8), %r9
	xorl	%esi, %esi
	movl	%ecx, (%rdx)
	xorl	%ecx, %ecx
.L53:
	xorl	%eax, %eax
.L56:
	movss	(%r9,%rax,4), %xmm0
	ucomiss	%xmm1, %xmm0
	jp	.L62
	je	.L54
.L62:
	movslq	%ecx, %r10
	incl	%ecx
	movl	%eax, 0(%rbp,%r10,4)
	movss	%xmm0, (%r12,%r10,4)
.L54:
	incq	%rax
	cmpq	$3, %rax
	jne	.L56
	movl	%ecx, 4(%rdx,%rsi,4)
	incq	%rsi
	addq	$12, %r9
	cmpq	$3, %rsi
	jne	.L53
	incl	%edi
	addq	$16, %rdx
	addq	$36, %r8
	cmpl	$4186116, %edi
	jne	.L51
	movslq	%ebx, %rbx
	leaq	40(%rsp), %r15
	movq	%rbx, %rsi
	movq	%r15, %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r15, %rdi
	movl	$1, %r8d
	movq	%r12, %rsi
	movabsq	$4294967552, %r15
	call	cudaMemcpyToSymbol@PLT
	leaq	32(%rsp), %rdi
	movl	$16744464, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movl	$16744464, %edx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movl	$167772160, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$167772160, %edx
	call	cudaMemcpy@PLT
	leaq	48(%rsp), %rdi
	movl	$66977856, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$66977856, %edx
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$10000, %ebx
	call	cudaMemcpy@PLT
	movq	$0x000000000, 8(%rsp)
.L59:
	xorl	%esi, %esi
	leaq	88(%rsp), %rdi
	call	gettimeofday@PLT
	movl	$262145, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$14, %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L58
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	$8, %r9d
	pushq	$2046
	.cfi_def_cfa_offset 208
	pushq	$2046
	.cfi_def_cfa_offset 216
	pushq	$3
	.cfi_def_cfa_offset 224
	pushq	$10
	.cfi_def_cfa_offset 232
	pushq	$2048
	.cfi_def_cfa_offset 240
	pushq	$2048
	.cfi_def_cfa_offset 248
	pushq	$32
	.cfi_def_cfa_offset 256
	movq	96(%rsp), %r8
	movq	120(%rsp), %rcx
	movq	112(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z52__device_stub__Z15compute_gpu_csrPfS_PiS0_S_iiiiiiiiPfS_PiS0_S_iiiiiiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 192
.L58:
	leaq	104(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	104(%rsp), %rax
	subq	88(%rsp), %rax
	imulq	$1000000, %rax, %rax
	addq	112(%rsp), %rax
	subq	96(%rsp), %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC3(%rip), %xmm0
	addsd	8(%rsp), %xmm0
	movsd	%xmm0, 8(%rsp)
	decl	%ebx
	jne	.L59
	movq	32(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$16744464, %edx
	call	cudaMemcpy@PLT
	call	cudaDeviceReset@PLT
	movl	$10, %r8d
	xorl	%eax, %eax
	movl	$2048, %ecx
	movl	$2048, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$8, %ecx
	movl	$32, %edx
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$256, %ecx
	movl	$16384, %edx
	xorl	%eax, %eax
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	8(%rsp), %xmm0
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$4, %esi
	movq	%r14, %rdi
	call	_ZdlPvm@PLT
	movq	(%rsp), %rdi
	movl	$4, %esi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%r13, %rdi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%r12, %rdi
	call	_ZdlPvm@PLT
	movl	$4, %esi
	movq	%rbp, %rdi
	call	_ZdlPvm@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L60
.L69:
	call	__stack_chk_fail@PLT
.L60:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3938:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii"
.LC9:
	.string	"_Z11compute_gpuPfS_S_iiiiiiii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3968:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11compute_gpuPfS_S_iiiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3968:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	1176753152
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <complex.h>
#include <hip/hip_runtime.h>
#include <utility>
#include <sys/time.h>
#define K 3
#define BLCH 8
#define BLCW 32

int compute(float *img, float *f, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW) {

    int inm1, inm2, inm3, inm4, inf, ind1, ind2, ind3;
    inm1 = 0;
    inf = 0;
    ind1 = 0;

    for (int mi = 0; mi < imgN; mi++){
        ind1 += convW * convH;
        inm1 += imgW * imgH;
        for (int mj = 0; mj < convH; mj++){
            ind2 = ind1 + convW * mj;
            inm2 = inm1 + imgW * mj;
            for (int mk = 0; mk < convW; mk++){
                ind3 = ind2 + mk;
                inm3 = inm2 + mk;
                for (int fi = 0; fi < nF; fi++){
                    inm4 = inm3 + imgW * fi;
                    inf = ind3*nF*nF + fi*nF;
                    for (int fj = 0; fj < nF; fj++){
                        out[ind3] += img[inm4+fj] * f[inf+fj];
                    }
                }
            }
        }
    }
    return 0;
}

int compute_csr(float *img, float *f_csr, int *pos, int *coor, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW) {

    int inm1, inm2, inm3, inm4, inf, inf1, inf2, ind1, ind2, ind3;

    for (int mi = 0; mi < imgN; mi++){
        ind1 = mi * convW * convH;
        inm1 = mi * imgW * imgH;
        for (int mj = 0; mj < convH; mj++){
            ind2 = ind1 + convW * mj;
            inm2 = inm1 + imgW * mj;
            for (int mk = 0; mk < convW; mk++){
                ind3 = ind2 + mk;
                inm3 = inm2 + mk;
                inf = nF*nF*ind3;
                for (int fi = 0; fi < nF; fi++){
                    inf1 = pos[fi+inf];
                    inf2 = pos[fi+1+inf];
                    inm4 = inm3 + fi*imgW;
                    for (int fj = inf1; fj < inf2; fj++){
                        out[ind3] += img[inm4+coor[fj]] * f_csr[fj+inf];
                    }

                }
            }
        }
    }
    return 0;
}

__global__ void compute_gpu(float *img, float *f, float * out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW){
    int idY = blockDim.y * blockIdx.y + threadIdx.y;
    int idX = blockDim.x * blockIdx.x + threadIdx.x;
    
    int inm1, inm2, inm3, inm4, inf, ind1, ind2, ind3;
    inm1 = 0;
    inf = 0;
    ind1 = 0;

    for (int mi = 0; mi < imgN; mi++){
        ind1 += convW * convH;
        inm1 += imgW * imgH;
        if (idX < convH && idY < convW){
            ind2 = ind1 + convW * idX;
            inm2 = inm1 + imgW * idX;
            ind3 = ind2 + idY;
            inm3 = inm2 + idY;
            for (int fi = 0; fi < nF; fi++){
               inm4 = inm3 + imgW * fi;
               inf = ind3*nF*nF + fi*nF;
               for (int fj = 0; fj < nF; fj++){
                  out[ind3] += img[inm4+fj] * f[inf+fj];
               }
             }
         }
    }
}

__global__ void compute_gpu_csr(float *img, float *f_csr, int *pos, int *coor, float *out, int bh, int bw, int imgH, int imgW, int imgN, int nF, int convH, int convW){
    
    int idX = blockDim.x * blockIdx.x + threadIdx.x;
    int idY = blockDim.y * blockIdx.y + threadIdx.y;
    
    int con, imgg, inm1, inm2, inm3, inm4, inf, inf1, inf2, ind1, ind2, ind3;

    for (int mi = 0; mi < imgN; mi++){
        ind1 = mi * convW * convH;
        inm1 = mi * imgW * imgH;
        if (idX < convH && idY < convW){
            ind2 = ind1 + convW * idX;
            inm2 = inm1 + imgW * idX;
            ind3 = ind2 + idY;
            inm3 = inm2 + idY;
            inf = nF*nF*ind3;
            for (int fi = 0; fi < nF; fi++){
                inf1 = pos[fi+inf];
                inf2 = pos[fi+1+inf];
                inm4 = inm3 + fi*imgW;
                for (int fj = inf1; fj < inf2; fj++){
                    out[ind3] += img[inm4+coor[fj]] * f_csr[fj+inf];
                }

            }
            
        }
    }
}



int main(int argc, char **argv){

    //create parameters
    int imgH = 2048;
    int imgW = 2048;
    int imgN = 10;
    int blcH = BLCH;
    int blcW = BLCW;
    int k    = K;
    int s    = 1;
    int nB   = (imgH * imgW) / (blcH * blcW);
    //int nT   = (blcW+k) * (blcH+k);
    int nT   = blcW * blcH;
    int imgDims = imgH * imgW * imgN;
    int imgSize = imgDims * sizeof(float);
    
    int num=0;
    srand (time(NULL));
    // create host array that can hold pixel intensity values
    float *h_img = new float[imgDims];
    for(int i=0; i<imgDims; i++){
        h_img[i] = (float)(rand()%10485)/10485;
    }
    
    
    // create host and device array that holds the convoluted matrix
    int convH = ( (imgH - k) / s ) + 1;
    int convW = ( (imgW - k) / s ) + 1;
    int convDims = convH * convW;
    int convSize = convDims * sizeof(float);
    float *h_convolved = new float[convDims];
    for(int i=0; i<convDims; i++){
        h_convolved[i] = 0.0;
    }

    // create filter and copy to constant memory
    int filterDims = k * k * convDims;
    int filterSize = filterDims * sizeof(float);
    float *filter = new float[filterDims];
    num = 0;
    for(int i=0; i<filterDims; i++){
        if(rand()/40 == 0){
            num++;
            filter[i] = (float)(rand()%10485)/10485;
        }
        else{
            filter[i] = 0;
        }   
    }
    
    //create index arrays of CSR
    int *pos = new int[(k+1)*convDims];
    int *coor = new int[num];
    float *h_fcsr = new float[num];
    int csrposSize = (k+1)*convDims*sizeof(int);
    int csrcooSize = num*sizeof(int);
    int fSize = num*sizeof(float);
    for(int ki=0; ki<convDims; ki++){
        pos[0+ki*(k+1)] = 0;
        int index_p=0;
        int z = ki*k*k;
        for(int i=0; i<k; i++){
            for (int j=0; j<k; j++){
                if (filter[i*k+j+z] != 0){
                    coor[index_p] = j;
                    h_fcsr[index_p] = filter[i*k+j+z];
                    index_p++;
                }
            }
        pos[i+1+ki*(k+1)] = index_p;
        }
    }


    // create device array that can hold pixel intensity values in GPU GM
    float *d_img;
    float *d_convolved;
    float *d_filter;
    int *d_pos;
    int *d_coor;
    hipMalloc((void **) &d_filter, fSize);
    hipMemcpyToSymbol(HIP_SYMBOL(d_filter), h_fcsr, fSize, hipMemcpyHostToDevice);
    hipMalloc((void **) &d_convolved, convSize);
    hipMemcpy(d_convolved, h_convolved, convSize, hipMemcpyHostToDevice);
    hipMalloc((void **) &d_img, imgSize);
    hipMemcpy(d_img, h_img, imgSize, hipMemcpyHostToDevice);
    hipMalloc((void **) &d_pos, csrposSize);
    hipMemcpy(d_pos, pos, csrposSize, hipMemcpyHostToDevice);
    hipMalloc((void **) &d_coor, csrcooSize);
    hipMemcpy(d_coor, coor, csrcooSize, hipMemcpyHostToDevice);
    
    struct timeval starttime, endtime;
    double elapsed = 0.0;
    for (int i = 0; i<10000; i++){
        gettimeofday(&starttime,NULL);
        // call the kernel
        //compute_gpu<<<nB, nT>>>(d_img, d_convolved, blcH, blcW, imgH, imgW, imgN, k, convH, convW);
        compute_gpu_csr<<<nB, nT>>>(d_img, d_filter, d_pos, d_coor, d_convolved, blcH, blcW, imgH, imgW, imgN, k, convH, convW);
        gettimeofday(&endtime,NULL);
        elapsed += ((endtime.tv_sec-starttime.tv_sec)*1000000 + endtime.tv_usec-starttime.tv_usec)/1000000.0;
    }
    
    hipMemcpy(h_convolved, d_convolved, convSize, hipMemcpyDeviceToHost);
    hipDeviceReset();
    printf("Input imgH: %d imgW: %d imgN: %d\n", imgH, imgW, imgN);
    printf("Tile width: %d height: %d\n", blcW, blcH);
    printf("Block number: %d, block size: %d \n", nB, nT);
    printf("time: %f \n", elapsed);
    delete h_img;
    delete h_convolved;
    delete pos;
    delete h_fcsr;
    delete coor;
    return 0;
}

	.text
	.file	"con_filter_spa.hip"
	.globl	_Z7computePfS_S_iiiiiiii        # -- Begin function _Z7computePfS_S_iiiiiiii
	.type	_Z7computePfS_S_iiiiiiii,@function
_Z7computePfS_S_iiiiiiii:               # @_Z7computePfS_S_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
	cmpl	$0, 64(%rsp)
	jle	.LBB0_14
# %bb.1:                                # %.lr.ph70
	movl	88(%rsp), %r8d
	movl	80(%rsp), %r10d
	movl	72(%rsp), %r11d
	movl	56(%rsp), %eax
	movl	%r8d, %ecx
	imull	%r10d, %ecx
	imull	%eax, %r9d
	movslq	%r8d, %rbx
	movslq	%ecx, %rcx
	movl	%r10d, %r10d
	movq	%r10, -24(%rsp)                 # 8-byte Spill
	movq	%rbx, -32(%rsp)                 # 8-byte Spill
	movl	%ebx, %r10d
	movq	%r10, -8(%rsp)                  # 8-byte Spill
	movl	%r11d, %r12d
	imull	%r11d, %r11d
	movq	%rcx, -48(%rsp)                 # 8-byte Spill
                                        # kill: def $ecx killed $ecx killed $rcx
	imull	%r11d, %ecx
	movl	%r11d, -60(%rsp)                # 4-byte Spill
	imull	%r11d, %r8d
	movl	%r8d, -64(%rsp)                 # 4-byte Spill
	movl	%eax, %r8d
	xorl	%eax, %eax
	movq	%rax, -88(%rsp)                 # 8-byte Spill
	movq	%r9, -40(%rsp)                  # 8-byte Spill
	movq	%r9, -96(%rsp)                  # 8-byte Spill
	movl	%ecx, -72(%rsp)                 # 4-byte Spill
	movl	%ecx, -104(%rsp)                # 4-byte Spill
	xorl	%ecx, %ecx
.LBB0_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
                                        #       Child Loop BB0_6 Depth 3
                                        #         Child Loop BB0_8 Depth 4
                                        #           Child Loop BB0_9 Depth 5
	movl	%ecx, -68(%rsp)                 # 4-byte Spill
	movq	-88(%rsp), %rax                 # 8-byte Reload
	addq	-48(%rsp), %rax                 # 8-byte Folded Reload
	movq	%rax, -88(%rsp)                 # 8-byte Spill
	cmpl	$0, 80(%rsp)
	jle	.LBB0_13
# %bb.3:                                # %.lr.ph64.preheader
                                        #   in Loop: Header=BB0_2 Depth=1
	movq	-96(%rsp), %rax                 # 8-byte Reload
	movq	%rax, -56(%rsp)                 # 8-byte Spill
	movl	-104(%rsp), %eax                # 4-byte Reload
	movl	%eax, -100(%rsp)                # 4-byte Spill
	xorl	%eax, %eax
	movq	%rax, -80(%rsp)                 # 8-byte Spill
.LBB0_4:                                # %.lr.ph64
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_6 Depth 3
                                        #         Child Loop BB0_8 Depth 4
                                        #           Child Loop BB0_9 Depth 5
	cmpl	$0, 88(%rsp)
	jle	.LBB0_12
# %bb.5:                                # %.lr.ph60.preheader
                                        #   in Loop: Header=BB0_4 Depth=2
	movq	-80(%rsp), %rax                 # 8-byte Reload
	imulq	-32(%rsp), %rax                 # 8-byte Folded Reload
	addq	-88(%rsp), %rax                 # 8-byte Folded Reload
	movq	%rax, -16(%rsp)                 # 8-byte Spill
	movq	-56(%rsp), %r14                 # 8-byte Reload
	movl	-100(%rsp), %r11d               # 4-byte Reload
	xorl	%ecx, %ecx
.LBB0_6:                                # %.lr.ph60
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB0_8 Depth 4
                                        #           Child Loop BB0_9 Depth 5
	cmpl	$0, 72(%rsp)
	jle	.LBB0_11
# %bb.7:                                # %.lr.ph56
                                        #   in Loop: Header=BB0_6 Depth=3
	movq	-16(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rcx), %rbx
	movss	(%rdx,%rbx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %r13
	movl	%r11d, %r9d
	xorl	%r15d, %r15d
.LBB0_8:                                # %.lr.ph
                                        #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        #       Parent Loop BB0_6 Depth=3
                                        # =>      This Loop Header: Depth=4
                                        #           Child Loop BB0_9 Depth 5
	movslq	%r9d, %rax
	leaq	(%rsi,%rax,4), %rbp
	xorl	%eax, %eax
.LBB0_9:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_4 Depth=2
                                        #       Parent Loop BB0_6 Depth=3
                                        #         Parent Loop BB0_8 Depth=4
                                        # =>        This Inner Loop Header: Depth=5
	leal	(%rax,%r13), %r10d
	movslq	%r10d, %r10
	movss	(%rdi,%r10,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rbp,%rax,4), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%rdx,%rbx,4)
	incq	%rax
	cmpq	%rax, %r12
	jne	.LBB0_9
# %bb.10:                               # %._crit_edge
                                        #   in Loop: Header=BB0_8 Depth=4
	incq	%r15
	addl	72(%rsp), %r9d
	addq	%r8, %r13
	cmpq	%r12, %r15
	jne	.LBB0_8
.LBB0_11:                               # %._crit_edge57
                                        #   in Loop: Header=BB0_6 Depth=3
	incq	%rcx
	addl	-60(%rsp), %r11d                # 4-byte Folded Reload
	incq	%r14
	cmpq	-8(%rsp), %rcx                  # 8-byte Folded Reload
	jne	.LBB0_6
.LBB0_12:                               # %._crit_edge61
                                        #   in Loop: Header=BB0_4 Depth=2
	movq	-80(%rsp), %rcx                 # 8-byte Reload
	incq	%rcx
	movl	-100(%rsp), %eax                # 4-byte Reload
	addl	-64(%rsp), %eax                 # 4-byte Folded Reload
	movl	%eax, -100(%rsp)                # 4-byte Spill
	addq	%r8, -56(%rsp)                  # 8-byte Folded Spill
	movq	%rcx, %rax
	movq	%rcx, -80(%rsp)                 # 8-byte Spill
	cmpq	-24(%rsp), %rcx                 # 8-byte Folded Reload
	jne	.LBB0_4
.LBB0_13:                               # %._crit_edge65
                                        #   in Loop: Header=BB0_2 Depth=1
	movl	-68(%rsp), %ecx                 # 4-byte Reload
	incl	%ecx
	movl	-104(%rsp), %eax                # 4-byte Reload
	addl	-72(%rsp), %eax                 # 4-byte Folded Reload
	movl	%eax, -104(%rsp)                # 4-byte Spill
	movq	-96(%rsp), %rax                 # 8-byte Reload
	addq	-40(%rsp), %rax                 # 8-byte Folded Reload
	movq	%rax, -96(%rsp)                 # 8-byte Spill
	cmpl	64(%rsp), %ecx
	jne	.LBB0_2
.LBB0_14:                               # %._crit_edge71
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z7computePfS_S_iiiiiiii, .Lfunc_end0-_Z7computePfS_S_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11compute_csrPfS_PiS0_S_iiiiiiii # -- Begin function _Z11compute_csrPfS_PiS0_S_iiiiiiii
	.type	_Z11compute_csrPfS_PiS0_S_iiiiiiii,@function
_Z11compute_csrPfS_PiS0_S_iiiiiiii:     # @_Z11compute_csrPfS_PiS0_S_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, -24(%rsp)                 # 8-byte Spill
	movq	%rsi, -32(%rsp)                 # 8-byte Spill
	cmpl	$0, 80(%rsp)
	jle	.LBB1_15
# %bb.1:                                # %.lr.ph72
	movl	104(%rsp), %eax
	movl	88(%rsp), %edx
	movl	%edx, %esi
	imull	%edx, %esi
	movl	%eax, %r9d
	movq	%r9, -8(%rsp)                   # 8-byte Spill
	movl	%edx, %r12d
	movl	%esi, -76(%rsp)                 # 4-byte Spill
	imull	%esi, %eax
	movl	%eax, -52(%rsp)                 # 4-byte Spill
	imull	96(%rsp), %eax
	movl	%eax, -56(%rsp)                 # 4-byte Spill
	xorl	%eax, %eax
	movq	%rax, -72(%rsp)                 # 8-byte Spill
	movl	$0, -84(%rsp)                   # 4-byte Folded Spill
.LBB1_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
                                        #       Child Loop BB1_6 Depth 3
                                        #         Child Loop BB1_8 Depth 4
                                        #           Child Loop BB1_10 Depth 5
	cmpl	$0, 96(%rsp)
	jle	.LBB1_14
# %bb.3:                                # %.lr.ph68.preheader
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	-84(%rsp), %eax                 # 4-byte Reload
	movl	%eax, %edx
	imull	96(%rsp), %edx
	movq	%rdx, -40(%rsp)                 # 8-byte Spill
                                        # kill: def $eax killed $eax def $rax
	imull	64(%rsp), %eax
	movq	%rax, -48(%rsp)                 # 8-byte Spill
	xorl	%eax, %eax
	movq	%rax, -64(%rsp)                 # 8-byte Spill
	movq	-72(%rsp), %rax                 # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax
	movl	%eax, -80(%rsp)                 # 4-byte Spill
.LBB1_4:                                # %.lr.ph68
                                        #   Parent Loop BB1_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_6 Depth 3
                                        #         Child Loop BB1_8 Depth 4
                                        #           Child Loop BB1_10 Depth 5
	cmpl	$0, 104(%rsp)
	jle	.LBB1_13
# %bb.5:                                # %.lr.ph64
                                        #   in Loop: Header=BB1_4 Depth=2
	movq	-40(%rsp), %rax                 # 8-byte Reload
	movq	-64(%rsp), %rdx                 # 8-byte Reload
	addl	%edx, %eax
	imull	104(%rsp), %eax
	movq	%rax, -16(%rsp)                 # 8-byte Spill
	movq	-48(%rsp), %rax                 # 8-byte Reload
	leal	(%rdx,%rax), %ebp
	movl	-80(%rsp), %r9d                 # 4-byte Reload
	xorl	%r13d, %r13d
.LBB1_6:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB1_8 Depth 4
                                        #           Child Loop BB1_10 Depth 5
	cmpl	$0, 88(%rsp)
	jle	.LBB1_12
# %bb.7:                                # %.lr.ph61
                                        #   in Loop: Header=BB1_6 Depth=3
	movslq	%r9d, %rax
	movq	-32(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r11
	movq	-16(%rsp), %rax                 # 8-byte Reload
	addl	%r13d, %eax
	movl	-76(%rsp), %edx                 # 4-byte Reload
	imull	%eax, %edx
	movslq	%eax, %r10
	movslq	%edx, %rax
	movq	-24(%rsp), %rdx                 # 8-byte Reload
	leaq	(%rdx,%rax,4), %r15
	xorl	%edx, %edx
.LBB1_8:                                #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        #       Parent Loop BB1_6 Depth=3
                                        # =>      This Loop Header: Depth=4
                                        #           Child Loop BB1_10 Depth 5
	movslq	(%r15,%rdx,4), %rsi
	movslq	4(%r15,%rdx,4), %rax
	cmpl	%eax, %esi
	jge	.LBB1_11
# %bb.9:                                # %.lr.ph
                                        #   in Loop: Header=BB1_8 Depth=4
	leal	(%rdx,%rbp), %r14d
	imull	72(%rsp), %r14d
	movss	(%r8,%r10,4), %xmm0             # xmm0 = mem[0],zero,zero,zero
.LBB1_10:                               #   Parent Loop BB1_2 Depth=1
                                        #     Parent Loop BB1_4 Depth=2
                                        #       Parent Loop BB1_6 Depth=3
                                        #         Parent Loop BB1_8 Depth=4
                                        # =>        This Inner Loop Header: Depth=5
	movl	(%rcx,%rsi,4), %ebx
	addl	%r13d, %ebx
	addl	%r14d, %ebx
	movslq	%ebx, %rbx
	movss	(%rdi,%rbx,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r11,%rsi,4), %xmm1
	addss	%xmm1, %xmm0
	movss	%xmm0, (%r8,%r10,4)
	incq	%rsi
	cmpq	%rsi, %rax
	jne	.LBB1_10
.LBB1_11:                               # %.loopexit
                                        #   in Loop: Header=BB1_8 Depth=4
	incq	%rdx
	cmpq	%r12, %rdx
	jne	.LBB1_8
.LBB1_12:                               # %._crit_edge
                                        #   in Loop: Header=BB1_6 Depth=3
	incq	%r13
	addl	-76(%rsp), %r9d                 # 4-byte Folded Reload
	cmpq	-8(%rsp), %r13                  # 8-byte Folded Reload
	jne	.LBB1_6
.LBB1_13:                               # %._crit_edge65
                                        #   in Loop: Header=BB1_4 Depth=2
	movq	-64(%rsp), %rax                 # 8-byte Reload
	incl	%eax
	movl	-80(%rsp), %edx                 # 4-byte Reload
	addl	-52(%rsp), %edx                 # 4-byte Folded Reload
	movl	%edx, -80(%rsp)                 # 4-byte Spill
	movq	%rax, -64(%rsp)                 # 8-byte Spill
	cmpl	96(%rsp), %eax
	jne	.LBB1_4
.LBB1_14:                               # %._crit_edge69
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	-84(%rsp), %edx                 # 4-byte Reload
	incl	%edx
	movq	-72(%rsp), %rax                 # 8-byte Reload
	addl	-56(%rsp), %eax                 # 4-byte Folded Reload
	movq	%rax, -72(%rsp)                 # 8-byte Spill
	movl	%edx, -84(%rsp)                 # 4-byte Spill
	cmpl	80(%rsp), %edx
	jne	.LBB1_2
.LBB1_15:                               # %._crit_edge73
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z11compute_csrPfS_PiS0_S_iiiiiiii, .Lfunc_end1-_Z11compute_csrPfS_PiS0_S_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__compute_gpuPfS_S_iiiiiiii # -- Begin function _Z26__device_stub__compute_gpuPfS_S_iiiiiiii
	.type	_Z26__device_stub__compute_gpuPfS_S_iiiiiiii,@function
_Z26__device_stub__compute_gpuPfS_S_iiiiiiii: # @_Z26__device_stub__compute_gpuPfS_S_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11compute_gpuPfS_S_iiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__compute_gpuPfS_S_iiiiiiii, .Lfunc_end2-_Z26__device_stub__compute_gpuPfS_S_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii # -- Begin function _Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.type	_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii,@function
_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii: # @_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii, .Lfunc_end3-_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI4_0:
	.long	0x4623d400                      # float 10485
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI4_1:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$167772160, %edi                # imm = 0xA000000
	callq	_Znam
	movq	%rax, %r14
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1677843209, %rax, %rcx         # imm = 0x6401DB09
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$44, %rcx
	addl	%edx, %ecx
	imull	$10485, %ecx, %ecx              # imm = 0x28F5
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI4_0(%rip), %xmm0
	movss	%xmm0, (%r14,%rbx,4)
	incq	%rbx
	cmpq	$41943040, %rbx                 # imm = 0x2800000
	jne	.LBB4_1
# %bb.2:
	movq	%r14, 24(%rsp)                  # 8-byte Spill
	movl	$16744464, %edi                 # imm = 0xFF8010
	callq	_Znam
	xorl	%ebx, %ebx
	movl	$16744464, %edx                 # imm = 0xFF8010
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$150700176, %edi                # imm = 0x8FB8090
	callq	_Znam
	movq	%rax, %rbp
	xorl	%r14d, %r14d
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	addl	$39, %eax
	xorps	%xmm0, %xmm0
	cmpl	$78, %eax
	ja	.LBB4_5
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=1
	incl	%r14d
	callq	rand
	cltq
	imulq	$1677843209, %rax, %rcx         # imm = 0x6401DB09
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$44, %rcx
	addl	%edx, %ecx
	imull	$10485, %ecx, %ecx              # imm = 0x28F5
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	divss	.LCPI4_0(%rip), %xmm0
.LBB4_5:                                #   in Loop: Header=BB4_3 Depth=1
	movss	%xmm0, (%rbp,%rbx,4)
	incq	%rbx
	cmpq	$37675044, %rbx                 # imm = 0x23EE024
	jne	.LBB4_3
# %bb.6:
	movl	$66977856, %edi                 # imm = 0x3FE0040
	callq	_Znam
	movq	%rax, %r15
	movslq	%r14d, %rax
	leaq	(,%rax,4), %rcx
	testl	%eax, %eax
	movq	$-1, %rbx
	cmovnsq	%rcx, %rbx
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %r12
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %r13
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.LBB4_7:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_8 Depth 2
                                        #       Child Loop BB4_9 Depth 3
	movq	%rax, %rdx
	shlq	$4, %rdx
	leaq	(%r15,%rdx), %rcx
	movl	$0, (%r15,%rdx)
	movq	%rbp, %rdx
	xorl	%esi, %esi
	xorl	%edi, %edi
.LBB4_8:                                # %.preheader
                                        #   Parent Loop BB4_7 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB4_9 Depth 3
	xorl	%r8d, %r8d
.LBB4_9:                                #   Parent Loop BB4_7 Depth=1
                                        #     Parent Loop BB4_8 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdx,%r8,4), %xmm1             # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm0, %xmm1
	jne	.LBB4_10
	jnp	.LBB4_11
.LBB4_10:                               #   in Loop: Header=BB4_9 Depth=3
	movslq	%edi, %rdi
	movl	%r8d, (%r12,%rdi,4)
	movss	%xmm1, (%r13,%rdi,4)
	incl	%edi
.LBB4_11:                               #   in Loop: Header=BB4_9 Depth=3
	incq	%r8
	cmpq	$3, %r8
	jne	.LBB4_9
# %bb.12:                               #   in Loop: Header=BB4_8 Depth=2
	movl	%edi, 4(%rcx,%rsi,4)
	incq	%rsi
	addq	$12, %rdx
	cmpq	$3, %rsi
	jne	.LBB4_8
# %bb.13:                               #   in Loop: Header=BB4_7 Depth=1
	incq	%rax
	addq	$36, %rbp
	cmpq	$4186116, %rax                  # imm = 0x3FE004
	jne	.LBB4_7
# %bb.14:
	movabsq	$4294967552, %rbp               # imm = 0x100000100
	shll	$2, %r14d
	movslq	%r14d, %rbx
	leaq	56(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$1, %ecx
	movq	%r14, %rdi
	movq	%r13, %rsi
	movq	%rbx, %rdx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	leaq	32(%rsp), %r14
	movl	$16744464, %esi                 # imm = 0xFF8010
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$16744464, %edx                 # imm = 0xFF8010
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %r14
	movl	$167772160, %esi                # imm = 0xA000000
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$167772160, %edx                # imm = 0xA000000
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %r14
	movl	$66977856, %esi                 # imm = 0x3FE0040
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$66977856, %edx                 # imm = 0x3FE0040
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	40(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	%r12, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$10000, %r14d                   # imm = 0x2710
	leaq	16128(%rbp), %rbx
	leaq	72(%rsp), %rbp
.LBB4_15:                               # =>This Inner Loop Header: Depth=1
	leaq	88(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%rbx, %rdi
	movl	$1, %esi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_17
# %bb.16:                               #   in Loop: Header=BB4_15 Depth=1
	movq	64(%rsp), %rdi
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	32(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$8, %r9d
	movl	$2046, %eax                     # imm = 0x7FE
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	$3
	.cfi_adjust_cfa_offset 8
	pushq	$10
	.cfi_adjust_cfa_offset 8
	movl	$2048, %eax                     # imm = 0x800
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	$32
	.cfi_adjust_cfa_offset 8
	callq	_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB4_17:                               #   in Loop: Header=BB4_15 Depth=1
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	72(%rsp), %rax
	subq	88(%rsp), %rax
	imulq	$1000000, %rax, %rax            # imm = 0xF4240
	addq	80(%rsp), %rax
	subq	96(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI4_1(%rip), %xmm0
	movsd	8(%rsp), %xmm1                  # 8-byte Reload
                                        # xmm1 = mem[0],zero
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 8(%rsp)                  # 8-byte Spill
	decl	%r14d
	jne	.LBB4_15
# %bb.18:
	movq	32(%rsp), %rsi
	movl	$16744464, %edx                 # imm = 0xFF8010
	movq	16(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceReset
	movl	$.L.str, %edi
	movl	$2048, %esi                     # imm = 0x800
	movl	$2048, %edx                     # imm = 0x800
	movl	$10, %ecx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	$32, %esi
	movl	$8, %edx
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %edi
	movl	$16384, %esi                    # imm = 0x4000
	movl	$256, %edx                      # imm = 0x100
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.3, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	_ZdlPv
	movq	%rbx, %rdi
	callq	_ZdlPv
	movq	%r15, %rdi
	callq	_ZdlPv
	movq	%r13, %rdi
	callq	_ZdlPv
	movq	%r12, %rdi
	callq	_ZdlPv
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11compute_gpuPfS_S_iiiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11compute_gpuPfS_S_iiiiiiii,@object # @_Z11compute_gpuPfS_S_iiiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z11compute_gpuPfS_S_iiiiiiii
	.p2align	3, 0x0
_Z11compute_gpuPfS_S_iiiiiiii:
	.quad	_Z26__device_stub__compute_gpuPfS_S_iiiiiiii
	.size	_Z11compute_gpuPfS_S_iiiiiiii, 8

	.type	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii,@object # @_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.globl	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.p2align	3, 0x0
_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii:
	.quad	_Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.size	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Input imgH: %d imgW: %d imgN: %d\n"
	.size	.L.str, 34

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Tile width: %d height: %d\n"
	.size	.L.str.1, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Block number: %d, block size: %d \n"
	.size	.L.str.2, 35

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"time: %f \n"
	.size	.L.str.3, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11compute_gpuPfS_S_iiiiiiii"
	.size	.L__unnamed_1, 30

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii"
	.size	.L__unnamed_2, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__compute_gpuPfS_S_iiiiiiii
	.addrsig_sym _Z30__device_stub__compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11compute_gpuPfS_S_iiiiiiii
	.addrsig_sym _Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11compute_gpuPfS_S_iiiiiiii ; -- Begin function _Z11compute_gpuPfS_S_iiiiiiii
	.globl	_Z11compute_gpuPfS_S_iiiiiiii
	.p2align	8
	.type	_Z11compute_gpuPfS_S_iiiiiiii,@function
_Z11compute_gpuPfS_S_iiiiiiii:          ; @_Z11compute_gpuPfS_S_iiiiiiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_8
; %bb.1:                                ; %.lr.ph64
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[12:13], s[0:1], 0x30
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s3
	s_mul_i32 s15, s15, s2
	v_add3_u32 v1, s14, s12, v0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_add_nc_u32_e32 v4, s14, v0
	v_add3_u32 v0, s14, s4, v0
	v_add_nc_u32_e32 v2, s15, v3
	v_mul_lo_u32 v1, s13, v1
	s_mul_i32 s1, s5, s4
	v_cmp_gt_i32_e32 vcc_lo, s12, v4
	v_mul_lo_u32 v7, s5, v0
	v_cmp_gt_i32_e64 s0, s13, v2
	s_mul_i32 s4, s13, s12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add3_u32 v5, v3, v1, s15
	v_mad_u64_u32 v[0:1], null, v4, s13, v[2:3]
	s_mul_i32 s13, s7, s7
	s_and_b32 s12, s0, vcc_lo
	v_mul_lo_u32 v6, s13, v5
	s_cmp_gt_i32 s7, 0
	v_add3_u32 v7, v3, v7, s15
	s_cselect_b32 s14, -1, 0
	s_mov_b32 s0, 0
	s_and_b32 s12, s12, s14
	s_mul_i32 s13, s4, s13
	s_mov_b32 s14, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s14, s14, s4
	s_and_saveexec_b32 s15, s12
	s_cbranch_execz .LBB0_7
; %bb.3:                                ; %.lr.ph59
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v1, s14, v0
	v_mov_b32_e32 v9, v7
	v_mov_b32_e32 v3, v6
	s_mov_b32 s16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s2, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b32 v8, v[1:2], off
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b32 s17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
.LBB0_5:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v10, s17, v9
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s7, s17
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	v_add_co_u32 v10, vcc_lo, s8, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	global_load_b32 v12, v[4:5], off
	global_load_b32 v10, v[10:11], off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v10, v12
	global_store_b32 v[1:2], v8, off
	s_cbranch_scc0 .LBB0_5
; %bb.6:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v3, s7, v3
	v_add_nc_u32_e32 v9, s5, v9
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s16, s7
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %Flow108
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v6, s13, v6
	v_add_nc_u32_e32 v7, s1, v7
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, s6
	s_cbranch_scc0 .LBB0_2
.LBB0_8:                                ; %._crit_edge65
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11compute_gpuPfS_S_iiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11compute_gpuPfS_S_iiiiiiii, .Lfunc_end0-_Z11compute_gpuPfS_S_iiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 20
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii ; -- Begin function _Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.globl	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
	.p2align	8
	.type	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii,@function
_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii: ; @_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
; %bb.0:
	s_load_b128 s[16:19], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB1_11
; %bb.1:                                ; %.lr.ph69
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x54
	s_load_b64 s[2:3], s[0:1], 0x40
	v_and_b32_e32 v3, 0x3ff, v0
	s_load_b64 s[12:13], s[0:1], 0x20
	s_mov_b32 s20, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s4, 0xffff
	s_lshr_b32 s4, s4, 16
	v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
	v_bfe_u32 v2, v0, 10, 10
	s_mul_i32 s15, s15, s4
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mul_i32 s14, s19, s19
	s_mul_i32 s21, s3, s2
	v_add_nc_u32_e32 v0, s15, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v3, s3, v1
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_mul_i32 s21, s21, s14
	v_cmp_gt_i32_e64 s0, s3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v2, v3, s15
	s_and_b32 s1, vcc_lo, s0
	s_cmp_gt_i32 s19, 0
	s_cselect_b32 s15, -1, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v11, s14, v2
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
                                        ;       Child Loop BB1_7 Depth 3
	s_and_saveexec_b32 s22, s1
	s_cbranch_execz .LBB1_10
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s15
	s_cbranch_vccnz .LBB1_10
; %bb.4:                                ; %.lr.ph67
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[2:3], null, s20, s2, v[1:2]
	s_mov_b32 s23, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, v2, s3, v[0:1]
	v_mad_u64_u32 v[2:3], null, s20, s16, v[1:2]
	v_ashrrev_i32_e32 v5, 31, v4
	v_mul_lo_u32 v12, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v6, vcc_lo
.LBB1_5:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_7 Depth 3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s23, v12
	s_mov_b32 s24, exec_lo
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s8, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v5, v6
	s_cbranch_execz .LBB1_8
; %bb.6:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_5 Depth=2
	global_load_b32 v13, v[3:4], off
	v_add_nc_u32_e32 v7, v11, v5
	v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v14, s23, v2
	v_ashrrev_i32_e32 v10, 31, v5
	s_mov_b32 s25, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v8, 31, v7
	v_mul_lo_u32 v14, v14, s17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v15, v[9:10], off
	v_add_nc_u32_e32 v5, 1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, v5, v6
	s_or_b32 s25, s0, s25
	s_waitcnt vmcnt(0)
	v_add3_u32 v15, v15, v0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s4, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
	global_load_b32 v17, v[7:8], off
	global_load_b32 v15, v[15:16], off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, v9, 4
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v13, v15, v17
	global_store_b32 v[3:4], v13, off
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB1_7
.LBB1_8:                                ; %Flow110
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
; %bb.9:                                ; %.loopexit
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_add_i32 s23, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s23, s19
	s_cbranch_scc0 .LBB1_5
.LBB1_10:                               ; %.loopexit64
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v11, s21, v11
	s_add_i32 s20, s20, 1
	s_cmp_eq_u32 s20, s18
	s_cbranch_scc0 .LBB1_2
.LBB1_11:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii, .Lfunc_end1-_Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 628
; NumSgprs: 28
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11compute_gpuPfS_S_iiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z11compute_gpuPfS_S_iiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z15compute_gpu_csrPfS_PiS0_S_iiiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
