 #define Index3D(_nx,_ny,_i,_j,_k) ((_i)+_nx*((_j)+_ny*(_k)))
 __global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
 const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
 const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
 extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
 const bool w_region = i>0 && j>0 &&(i<(nx-1)) &&(j<(ny-1)) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
 float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
 if((i<nx) &&(j<ny))
{
 bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
 __syncthreads();
 for(int k=1;k<nz-1;k++)
{
 float a_left_right,a_up,a_down;
 if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
 if(w_region)
{
a_up =y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
 a_down =y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
 Anext[Index3D (nx, ny, i, j, k)] = (top + bottom + a_up + a_down + sh_A0[sh_id+1] +a_left_right)*c1
 - sh_A0[sh_id]*c0;
 }
 if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
 if(w_region2)
{
 a_up =y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
 a_down =y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
 Anext[Index3D (nx, ny, i2, j, k)] = (top2 + bottom2 + a_up + a_down + a_left_right +sh_A0[sh_id2-1])*c1
 - sh_A0[sh_id2]*c0;
}
 __syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
 }

	.file	"tmpxft_0025d264_00000000-6_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
	.type	_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, @function
_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 32(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 24(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii, .-_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
	.globl	_Z24block2D_hybrid_coarsen_xffPfS_iii
	.type	_Z24block2D_hybrid_coarsen_xffPfS_iii, @function
_Z24block2D_hybrid_coarsen_xffPfS_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z24block2D_hybrid_coarsen_xffPfS_iiiffPfS_iii
	.cfi_endproc
.LFE2033:
	.size	_Z24block2D_hybrid_coarsen_xffPfS_iii, .-_Z24block2D_hybrid_coarsen_xffPfS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24block2D_hybrid_coarsen_xffPfS_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24block2D_hybrid_coarsen_xffPfS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
 #define Index3D(_nx,_ny,_i,_j,_k) ((_i)+_nx*((_j)+_ny*(_k)))
 __global__ void block2D_hybrid_coarsen_x(float c0,float c1,float *A0,float *Anext, int nx, int ny, int nz)
{
 const int i = blockIdx.x*blockDim.x*2+threadIdx.x;
const int i2= blockIdx.x*blockDim.x*2+threadIdx.x+blockDim.x;
 const int j = blockIdx.y*blockDim.y+threadIdx.y;
const int sh_id=threadIdx.x + threadIdx.y*blockDim.x*2;
const int sh_id2=threadIdx.x +blockDim.x+ threadIdx.y*blockDim.x*2;
 extern __shared__ float sh_A0[];
sh_A0[sh_id]=0.0f;
sh_A0[sh_id2]=0.0f;
__syncthreads();
 const bool w_region = i>0 && j>0 &&(i<(nx-1)) &&(j<(ny-1)) ;
const bool w_region2 = j>0 &&(i2<nx-1) &&(j<ny-1) ;
const bool x_l_bound = (threadIdx.x==0);
const bool x_h_bound = ((threadIdx.x+blockDim.x)==(blockDim.x*2-1));
const bool y_l_bound = (threadIdx.y==0);
const bool y_h_bound = (threadIdx.y==(blockDim.y-1));
 float bottom=0.0f,bottom2=0.0f,top=0.0f,top2=0.0f;
 if((i<nx) &&(j<ny))
{
 bottom=A0[Index3D (nx, ny, i, j, 0)];
sh_A0[sh_id]=A0[Index3D (nx, ny, i, j, 1)];
}
if((i2<nx) &&(j<ny))
{
bottom2=A0[Index3D (nx, ny, i2, j, 0)];
sh_A0[sh_id2]=A0[Index3D (nx, ny, i2, j, 1)];
}
 __syncthreads();
 for(int k=1;k<nz-1;k++)
{
 float a_left_right,a_up,a_down;
 if((i<nx) &&(j<ny))
top=A0[Index3D (nx, ny, i, j, k+1)];
 if(w_region)
{
a_up =y_h_bound?A0[Index3D (nx, ny, i, j+1, k )]:sh_A0[sh_id+2*blockDim.x];
 a_down =y_l_bound?A0[Index3D (nx, ny, i, j-1, k )]:sh_A0[sh_id-2*blockDim.x];
a_left_right=x_l_bound?A0[Index3D (nx, ny, i-1, j, k )]:sh_A0[sh_id-1];
 Anext[Index3D (nx, ny, i, j, k)] = (top + bottom + a_up + a_down + sh_A0[sh_id+1] +a_left_right)*c1
 - sh_A0[sh_id]*c0;
 }
 if((i2<nx) &&(j<ny))
top2=A0[Index3D (nx, ny, i2, j, k+1)];
 if(w_region2)
{
 a_up =y_h_bound?A0[Index3D (nx, ny, i2, j+1, k )]:sh_A0[sh_id2+2*blockDim.x];
 a_down =y_l_bound?A0[Index3D (nx, ny, i2, j-1, k )]:sh_A0[sh_id2-2*blockDim.x];
a_left_right=x_h_bound?A0[Index3D (nx, ny, i2+1, j, k )]:sh_A0[sh_id2+1];
 Anext[Index3D (nx, ny, i2, j, k)] = (top2 + bottom2 + a_up + a_down + a_left_right +sh_A0[sh_id2-1])*c1
 - sh_A0[sh_id2]*c0;
}
 __syncthreads();
bottom=sh_A0[sh_id];
sh_A0[sh_id]=top;
bottom2=sh_A0[sh_id2];
sh_A0[sh_id2]=top2;
__syncthreads();
}
 }

	.text
	.file	"kernels.hip"
	.globl	_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii # -- Begin function _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
	.type	_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii,@function
_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii: # @_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movss	%xmm0, (%rax)
	leaq	24(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r9, 8(%rbx)
	movq	%r10, 16(%rbx)
	movq	%rdi, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%rdx, 40(%rbx)
	movq	%rcx, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24block2D_hybrid_coarsen_xffPfS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24block2D_hybrid_coarsen_xffPfS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24block2D_hybrid_coarsen_xffPfS_iii,@object # @_Z24block2D_hybrid_coarsen_xffPfS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z24block2D_hybrid_coarsen_xffPfS_iii
	.p2align	3, 0x0
_Z24block2D_hybrid_coarsen_xffPfS_iii:
	.quad	_Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
	.size	_Z24block2D_hybrid_coarsen_xffPfS_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24block2D_hybrid_coarsen_xffPfS_iii"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__block2D_hybrid_coarsen_xffPfS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24block2D_hybrid_coarsen_xffPfS_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24block2D_hybrid_coarsen_xffPfS_iii ; -- Begin function _Z24block2D_hybrid_coarsen_xffPfS_iii
	.globl	_Z24block2D_hybrid_coarsen_xffPfS_iii
	.p2align	8
	.type	_Z24block2D_hybrid_coarsen_xffPfS_iii,@function
_Z24block2D_hybrid_coarsen_xffPfS_iii:  ; @_Z24block2D_hybrid_coarsen_xffPfS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b256 s[16:23], s[0:1], 0x8
	v_bfe_u32 v20, v0, 10, 10
	v_dual_mov_b32 v15, 0 :: v_dual_and_b32 v10, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s23, s14, 1
	v_mov_b32_e32 v14, 0
	v_lshlrev_b32_e32 v4, 1, v20
	s_and_b32 s24, s2, 0xffff
	s_lshr_b32 s12, s2, 16
	v_mad_u64_u32 v[0:1], null, s23, s24, v[10:11]
	v_add_nc_u32_e32 v2, s24, v10
	s_mul_i32 s15, s15, s12
	v_mad_u32_u24 v3, v4, s24, v10
	v_add_nc_u32_e32 v11, s15, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u32_u24 v4, v4, s24, v2
	v_cmp_gt_i32_e64 s2, s20, v0
	v_lshl_add_u32 v12, v3, 2, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_i32_e32 vcc_lo, s21, v11
	v_add_nc_u32_e32 v5, s21, v11
	v_lshl_add_u32 v13, v4, 2, 0
	ds_store_b32 v12, v14
	s_and_b32 s8, s2, vcc_lo
	ds_store_b32 v13, v14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s8
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[6:7], null, v5, s20, v[0:1]
	v_mad_u64_u32 v[8:9], null, v11, s20, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s2, s16, v6
	v_add_co_ci_u32_e64 v7, s2, s17, v7, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, s16, v8
	v_add_co_ci_u32_e64 v9, s2, s17, v9, s2
	s_clause 0x1
	global_load_b32 v1, v[6:7], off
	global_load_b32 v15, v[8:9], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v12, v1
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_add_nc_u32_e32 v1, s24, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s20, v1
	s_and_b32 s9, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s9
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_mad_u64_u32 v[6:7], null, v5, s20, v[1:2]
	v_mad_u64_u32 v[8:9], null, v11, s20, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	v_lshlrev_b64 v[7:8], 2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s16, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off
	global_load_b32 v14, v[7:8], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v13, v5
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_i32 s22, 3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_23
; %bb.5:                                ; %.lr.ph
	s_add_i32 s5, s20, -1
	s_add_i32 s4, s21, -1
	v_cmp_gt_i32_e64 s3, s5, v0
	v_cmp_gt_i32_e64 s4, s4, v11
	v_cmp_gt_i32_e64 s5, s5, v1
	s_load_b64 s[6:7], s[0:1], 0x0
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	v_cmp_lt_i32_e64 s2, 0, v11
	s_lshl_b32 s14, s24, 3
	s_and_b32 s1, s5, s4
	s_lshl_b32 s5, s24, 1
	v_dual_mov_b32 v32, 0 :: v_dual_add_nc_u32 v5, s14, v12
	v_subrev_nc_u32_e32 v3, s5, v3
	s_and_b32 s10, vcc_lo, s2
	v_add_nc_u32_e32 v7, -4, v12
	s_and_b32 s0, s10, s3
	v_cmp_ne_u32_e64 s3, -1, v5
	v_lshl_add_u32 v6, v3, 2, 0
	s_and_b32 s10, s0, s4
	v_subrev_nc_u32_e32 v8, s5, v4
	s_add_i32 s12, s12, -1
	v_add3_u32 v22, s15, s21, v20
	v_cmp_ne_u32_e64 s4, -1, v6
	s_and_b32 s11, s1, s2
	s_add_i32 s0, s5, -1
	v_cmp_eq_u32_e64 s2, s12, v20
	s_mov_b64 s[12:13], src_shared_base
	v_cndmask_b32_e64 v4, 0, v6, s4
	v_dual_mov_b32 v33, 0 :: v_dual_add_nc_u32 v6, s14, v13
	v_add_nc_u32_e32 v18, 4, v13
	v_cmp_eq_u32_e64 s0, s0, v2
	v_cndmask_b32_e64 v2, 0, v5, s3
	v_cndmask_b32_e64 v3, 0, s13, s3
	v_cmp_ne_u32_e64 s3, -1, v7
	v_lshl_add_u32 v8, v8, 2, 0
	v_cndmask_b32_e64 v5, 0, s13, s4
	v_cmp_ne_u32_e64 s4, -1, v6
	v_add_nc_u32_e32 v23, -1, v22
	v_mul_lo_u32 v22, s20, v22
	v_lshl_add_u32 v11, s21, 1, v11
	v_cmp_ne_u32_e64 s5, -1, v18
	v_cndmask_b32_e64 v16, 0, v7, s3
	v_cndmask_b32_e64 v17, 0, s13, s3
	v_cmp_ne_u32_e64 s3, -1, v8
	v_cndmask_b32_e64 v6, 0, v6, s4
	v_cndmask_b32_e64 v7, 0, s13, s4
	s_add_i32 s4, s22, -2
	v_mul_lo_u32 v29, s20, v23
	v_mul_lo_u32 v11, s20, v11
	v_cndmask_b32_e64 v18, 0, v18, s5
	v_cndmask_b32_e64 v19, 0, s13, s5
	s_add_u32 s5, s16, -4
	s_addc_u32 s12, s17, -1
	v_cndmask_b32_e64 v9, 0, s13, s3
	s_add_u32 s13, s16, 4
	v_add_nc_u32_e32 v30, s20, v22
	v_cndmask_b32_e64 v8, 0, v8, s3
	s_addc_u32 s14, s17, 0
	s_add_i32 s3, s23, 1
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_mul_i32 s3, s3, s24
	v_cmp_eq_u32_e64 s1, 0, v20
	v_add_nc_u32_e32 v20, -4, v13
	v_ashrrev_i32_e32 v21, 31, v0
	v_ashrrev_i32_e32 v23, 31, v1
	v_add3_u32 v24, v10, v22, s3
	v_add3_u32 v25, v10, v29, s3
	v_add3_u32 v26, v10, v30, s3
	v_add3_u32 v27, v10, v11, s3
	v_add_nc_u32_e32 v28, v0, v22
	v_add_nc_u32_e32 v29, v0, v29
	v_add_nc_u32_e32 v30, v0, v30
	v_add_nc_u32_e32 v31, v0, v11
	s_mov_b32 s15, 0
	s_mul_i32 s20, s21, s20
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	s_and_saveexec_b32 s21, s8
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
	global_load_b32 v33, v[10:11], off
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_and_saveexec_b32 s21, s10
	s_cbranch_execz .LBB0_14
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=1
	v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
	s_and_saveexec_b32 s22, s2
; %bb.10:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
; %bb.11:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	flat_load_b32 v34, v[10:11]
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	s_and_saveexec_b32 s22, s1
; %bb.12:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
; %bb.13:                               ; %._crit_edge209
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_add_nc_u32_e32 v35, s15, v22
	flat_load_b32 v37, v[10:11]
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v15, v15, v33
	v_ashrrev_i32_e32 v36, 31, v35
	v_add_co_u32 v35, s3, v0, v35
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v15, v15, v34 :: v_dual_add_nc_u32 v34, s15, v28
	v_add_co_ci_u32_e64 v36, s3, v21, v36, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[35:36], 2, v[35:36]
	v_add_co_u32 v35, s3, s5, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v36, s3, s12, v36, s3
	v_cndmask_b32_e32 v10, v16, v35, vcc_lo
	v_ashrrev_i32_e32 v35, 31, v34
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v17, v36, vcc_lo
	flat_load_b32 v36, v[10:11]
	ds_load_2addr_b32 v[10:11], v12 offset1:1
	s_waitcnt vmcnt(1)
	v_add_f32_e32 v15, v15, v37
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v15, v11
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v15, s6, v10 :: v_dual_add_f32 v36, v36, v11
	v_lshlrev_b64 v[10:11], 2, v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, v36, s7, -v15
	v_add_co_u32 v10, s3, s18, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s19, v11, s3
	global_store_b32 v[10:11], v15, off
.LBB0_14:                               ; %Flow246
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_and_saveexec_b32 s21, s9
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
	global_load_b32 v32, v[10:11], off
.LBB0_16:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_and_saveexec_b32 s21, s11
	s_cbranch_execz .LBB0_22
; %bb.17:                               ;   in Loop: Header=BB0_6 Depth=1
	v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
	s_and_saveexec_b32 s22, s2
; %bb.18:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
; %bb.19:                               ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	flat_load_b32 v15, v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_and_saveexec_b32 s22, s1
; %bb.20:                               ;   in Loop: Header=BB0_6 Depth=1
	v_add_nc_u32_e32 v10, s15, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s3, s16, v10
	v_add_co_ci_u32_e64 v11, s3, s17, v11, s3
; %bb.21:                               ; %._crit_edge208
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	flat_load_b32 v36, v[10:11]
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v14, v14, v32
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v14, v15
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v15, v14, v36 :: v_dual_add_nc_u32 v34, s15, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v35, 31, v34
	v_add_co_u32 v34, s3, v1, v34
	v_add_nc_u32_e32 v14, s15, v24
	v_add_co_ci_u32_e64 v35, s3, v23, v35, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[34:35], 2, v[34:35]
	v_add_co_u32 v34, s3, s13, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v35, s3, s14, v35, s3
	v_cndmask_b32_e64 v10, v18, v34, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v11, v19, v35, s0
	flat_load_b32 v34, v[10:11]
	ds_load_2addr_b32 v[10:11], v20 offset1:1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mul_f32 v35, s6, v11 :: v_dual_add_f32 v34, v15, v34
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v34, v34, v10
	v_lshlrev_b64 v[10:11], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, v34, s7, -v35
	v_add_co_u32 v10, s3, s18, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s19, v11, s3
	global_store_b32 v[10:11], v14, off
.LBB0_22:                               ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v15, v12
	ds_store_b32 v12, v33
	ds_load_b32 v14, v13
	s_add_i32 s4, s4, -1
	s_add_i32 s15, s15, s20
	s_cmp_eq_u32 s4, 0
	ds_store_b32 v13, v32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_6
.LBB0_23:                               ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24block2D_hybrid_coarsen_xffPfS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24block2D_hybrid_coarsen_xffPfS_iii, .Lfunc_end0-_Z24block2D_hybrid_coarsen_xffPfS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1820
; NumSgprs: 27
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         160
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24block2D_hybrid_coarsen_xffPfS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z24block2D_hybrid_coarsen_xffPfS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
